Back etching method of polycrystalline silicon and semiconductor process equipment

Abstract

The invention discloses a back etching method of polycrystalline silicon and semiconductor process equipment. The method comprises the following steps: introducing mixed gas into a chamber, so that the sensitivity coefficient of the etching amount to the temperature is within a set range; obtaining the target etching amount of each sub-region of the electrostatic chuck and the sensitive coefficient of the etching amount to the temperature; performing temperature control on the sub-regions according to the target etching amount of the sub-regions and the sensitivity coefficient of the etching amount corresponding to the mixed gas to the temperature; and starting the power of the upper radio frequency power supply to carry out plasma glow starting so as to carry out back etching on the polycrystalline silicon on the surface of the wafer placed on the electrostatic chuck. According to the invention, it is ensured that the average value and range of the thickness of the film layer are stable, the number of strip-shaped defects after etching is reduced, and the yield of wafers is improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a polysilicon etching back method and semiconductor process equipment. Background Art

[0002] The Poly Etch Back (Poly EB) process is to form a film thickness range of about 50-100 angstroms (Å) after chemical mechanical polishing of Poly in the Poly process loop. By plasma etching poly, within the range of about 200-250Å, the film thickness range after Poly EB reaches 30±5Å in the entire wafer. Because the in-wafer uniformity of the film thickness after Poly EB directly affects the uniformity of the in-wafer morphology and key dimensions after etching, the control of the film thickness of Poly is very critical for processes of 14 nanometers and below. After polysilicon etching, strip-shaped incomplete etch defects (partial etch defects) will also be formed, which will cause the connection of the pattern at the defective position, resulting in a loss of yield, so the number of strip-shaped defects must be controlled within the set number.

[0003] In the related technology, the inductively coupled plasma (ICP) etching scheme is generally used. The electrostatic chuck (ESC) uses the conventional four-zone annular ESC in the industry. The gases introduced are mainly tetrafluoromethane (CF4) / trifluoromethane (CHF3) / helium (He). The chamber is controlled to be low-pressure 3~10 mTorr. The RF power supply is controlled to generate plasma at a power of 300-600 watts (W), and a certain RF bias is added to make the plasma bombard the wafer surface. The uniformity of the film thickness is achieved by adjusting the temperature of the four-zone ESC and the current ratio and air intake method of the inner and outer coils of the RF power supply, ranging from 50~100A. However, when the above scheme uses the same recipe, the etching amount is fixed. In the actual mass production process, there are often differences in the chemical mechanical polishing of the front-end machine (chemical mechanical polishing is a rough physical polishing that will thin the film layer, but cannot accurately control the range of the surface film thickness). Therefore, the mean and range of the film thickness after etching each wafer cannot be guaranteed to be stable. In addition, the polymer corresponding to the above gas components CF4 / CHF3 / He is relatively light, making the etching amount insensitive to temperature. Therefore, the uniformity of the film thickness within the wafer cannot be controlled by temperature, and there is a problem of a large number of strip defects after etching, the number of which is generally in the range of 200-300 (each, abbreviated as ea), which reduces the yield of the wafer. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a polysilicon back-etching method and semiconductor process equipment to solve the problem in the related art that the mean and range of the film thickness after etching each wafer cannot be guaranteed to be stable, and the polymer corresponding to the gas components CF4 / CHF3 / He is relatively light, making the etching amount insensitive to temperature. Therefore, the uniformity of the film thickness within the wafer cannot be controlled by temperature, and there are a large number of strip-shaped defects after etching, which reduces the wafer yield.

[0005] To achieve the above objectives, the present application embodiment adopts the following technical solutions: In a first aspect, an embodiment of the present application provides a method for back-etching polysilicon, comprising: an etching step, wherein the etching step comprises: introducing a mixed gas into a chamber so that the temperature sensitivity coefficient of the etching amount is within a set range; obtaining a target etching amount of each sub-area of ​​an electrostatic chuck and a temperature sensitivity coefficient of the etching amount corresponding to the mixed gas; temperature-controlling the sub-area according to the target etching amount of the sub-area and the temperature sensitivity coefficient of the etching amount; and turning on the upper RF power supply power to perform plasma ignition to back-etch the polysilicon on the surface of a wafer placed on the electrostatic chuck.

[0006] In a second aspect, an embodiment of the present application provides a semiconductor process equipment, comprising: a chamber, an upper RF power supply and a controller, the controller comprising at least one processor and at least one memory, the memory storing a computer program, and when the computer program is executed by the processor, the steps of the polysilicon back etching method as described in the embodiment of the first aspect of the present application are implemented.

[0007] At least one of the above technical solutions adopted in the embodiments of the present application can achieve the following beneficial effects: In the embodiment of the present application, when back-etching the polysilicon on the surface of the wafer, in the etching step, a mixed gas is introduced into the chamber to make the temperature sensitivity coefficient of the etching amount within a set range, and the target etching amount of each sub-area of ​​the electrostatic chuck and the temperature sensitivity coefficient of the etching amount corresponding to the mixed gas are obtained. According to the target etching amount of the sub-area and the temperature sensitivity coefficient of the etching amount, the temperature of the sub-area is controlled, and the upper RF power supply is turned on to start the plasma to back-etch the polysilicon on the surface of the wafer placed on the electrostatic chuck. The mixed gas used in the embodiment of the present application makes the sensitivity coefficient of the etching amount to temperature within a relatively high set range. Therefore, by controlling the temperature of each sub-area of ​​the electrostatic chuck, the etching amount and film thickness of different sub-areas of the Poly can be accurately controlled to ensure that the mean and range of the film thickness after etching each wafer are stable. Since the number of strip-shaped defects increases with the increase in the sensitivity coefficient of the etching amount to temperature, the sensitivity coefficient of the etching amount to temperature is limited within the set range, so that the number of strip-shaped defects is also limited within the set number, thereby reducing the number of strip-shaped defects after etching and improving the yield of the wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 It is a schematic diagram of the structure of the wafer before and after etching; Figure 2It is the top view of the strip defect; Figure 3 is a schematic diagram of a four-zone electrostatic chuck; Figure 4 This is a schematic diagram of the defect number obtained by the method used in the background technology when the number of defects is 200-300ea; Figure 5 It is a schematic diagram of the structure of a plasma etching device; Figure 6 A schematic flow chart of a polysilicon etching back method provided for one embodiment of the present application; Figure 7 A schematic structural diagram of a multi-zone electrostatic chuck provided for one embodiment of the present application; Figure 8 A schematic diagram of the correlation between the number of defects and the sensitivity coefficient of the etching amount to the temperature provided in one embodiment of the present application; Fig. 9 This is a schematic diagram of a polysilicon etching back method according to an embodiment of the present application when the number of defects is 100-200 ea; Fig.10 This is a schematic diagram of the case where the number of defects obtained by the multiple-cycle etching method of the present application is less than 40 ea; Fig.11 A schematic diagram of the overall process of a polysilicon etching back method provided in another embodiment of the present application; Fig.12 A schematic diagram of a film layer of a wafer before and after each step of a polysilicon etch-back method provided in another embodiment of the present application is cyclically executed; Fig.13 A schematic diagram comparing the uniformity of the film thickness after wafer etching between the related technical solution and the embodiment of the present application; Fig.14 A schematic structural diagram of a semiconductor process equipment provided for one embodiment of the present application. DETAILED DESCRIPTION

[0009] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0010] The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here. In addition, the "and / or" in this application represents at least one of the connected objects, and the character " / " generally represents that the front and back associated objects are in an "or" relationship. It should be noted that the data involved in this application are all obtained on the premise of obtaining user authorization.

[0011] With the continuous development of semiconductor process technology, in integrated circuits with a process of 14 nanometers (nm) and below, in order to solve the leakage problem caused by the short channel effect, the transistor structure has changed from a planar junction field effect transistor to a fin field effect transistor (Fin Field Effective Transistor, Fin-FET) with a three-dimensional gate structure. In one process route, the Poly EB process is to form a film thickness range of about 50-100Å after chemical mechanical polishing (CMP) of Poly in a Poly loop, and then etch the poly through plasma, so that the film thickness range of the entire wafer after Poly EB reaches 30±5Å within the range of about 200-250Å. Because the in-chip uniformity of the film thickness after Poly EB directly affects the uniformity of the in-chip morphology and critical dimension (CD) after etching, the film thickness control of Poly is very critical for processes of 14 nm and below. Figure 1 This is the wafer structure diagram before and after Poly EB etching. The wafer includes poly101, Fin102 and silicon dioxide (SiO2) 103. Poly101 is the main etched material in this process, and the material of Fin102 is Si.

[0012] After polysilicon etching, a partial etch defect with a length of 10-20 microns (μm) and a width of 0.1-0.2μm will be formed. Figure 2 The figure shows a top view of a strip defect. When placed at the second (i.e., P2) site, a connection of the pattern will be formed at the location with the defect, resulting in a loss of yield. Assuming that the yield loss at each site is 2%, and the entire semiconductor preparation process has 100 sites, only 13% of the entire wafer can be used in the end. Therefore, the number of strip defects must be controlled within the set number.

[0013] The related technology generally adopts the ICP etching solution, and the ESC adopts the conventional four-zone annular ESC in the industry (such as Figure 3 As shown in the figure, the gas introduced is mainly CF4 / CHF3 / He, the pressure in the chamber is controlled to be low 3~10mTorr, the RF power is controlled to generate plasma with a power of 300-600 W, and a certain RF bias is added to make the plasma bombard the wafer surface. The uniformity of the film thickness is achieved by adjusting the temperature of the four-zone ESC and the current ratio and gas intake method of the inner and outer coils of the RF power supply, with a range of 50~100Å. However, when the above scheme uses the same recipe, the etching amount is fixed. In the actual mass production process, there are often differences in the chemical mechanical polishing of the front-end machine (chemical mechanical polishing is a rough physical polishing that will thin the film layer, but cannot accurately control the range of the surface film thickness). Therefore, the mean and range of the film thickness after etching each wafer cannot be guaranteed to be stable. In addition, the polymer corresponding to the above gas components CF4 / CHF3 / He is relatively light, making the etching amount insensitive to temperature. For example, the etching amount of this component is 450Å per minute at 55°C, and the etching amount per minute is basically 450Å at 65°C. The etching amount does not change with the change of temperature. Therefore, the uniformity of the film thickness within the wafer cannot be controlled by temperature. After etching, there is a problem of a large number of strip defects, and the number of particles is generally in the range of 200-300ea (such as Figure 4 As shown in the figure), the yield of the wafer is reduced.

[0014] Figure 5 is a schematic diagram of the structure of the ICP etching device, such as Figure 5 As shown, it includes a chamber 501, an ESC502 arranged in the chamber 501, a wafer 503 placed on the ESC502, an upper RF power supply 504 and an upper electrode coil 505, a nozzle 506 and a bias power supply 507. The process gas is introduced into the chamber 501 through the nozzle 506, and plasma is generated under the action of the upper RF power supply 504.

[0015] In order to achieve the required mean and range of film thickness and controllable number of strip defects, the present application proposes a polysilicon back-etching method, semiconductor process equipment and storage medium to solve the problem that the mean and range of the film thickness after etching of each wafer cannot be guaranteed to be stable in the related technology, and the polymer corresponding to the gas component CF4 / CHF3 / He is relatively light, making the etching amount insensitive to temperature. Therefore, the uniformity of the film thickness within the wafer cannot be controlled by temperature. After etching, there are a large number of strip defects, which reduces the wafer yield.

[0016] The technical solutions provided by various embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0017] Figure 6 A schematic diagram of a polysilicon etching back method provided in accordance with an embodiment of the present application. Figure 6 As shown, the polysilicon etching back method of the embodiment of the present application may specifically include: an etching step. The etching step may specifically include the following steps: S601, introducing a mixed gas into the chamber so that the sensitivity coefficient of the etching amount to the temperature is within a set range.

[0018] In the embodiment of the present application, the executor of the polysilicon back etching method of the embodiment of the present application is a controller, which can be set in the host computer and / or the slave computer of the semiconductor process equipment (such as plasma etching equipment, etc.).

[0019] Before the etching step, the polysilicon back-etching method of the embodiment of the present application may further include a natural oxide layer treatment step: using a gas including a fluorocarbon to remove the natural oxide layer on the surface of the Poly, and etching may be performed using a CF4-based gas.

[0020] In order to achieve the mean stability of the film thickness and the required range (for example, 30±5 Å), due to the uncertainty of the front-end process and the unevenness of the film thickness on the whole wafer caused by the front-end process, it is necessary to use a multi-zone electrostatic chuck and combine the sensitivity of the etching amount to temperature. The parameter of the sensitivity of the etching amount to temperature (that is, the sensitivity coefficient of the etching amount to temperature) is very critical. The sensitivity coefficient of the etching amount to temperature refers to the change of the etching amount per unit temperature when the etching time remains unchanged, and the unit is angstrom / degree Celsius (Å / ℃). The multi-zone electrostatic chuck utilizes the sensitivity of the etching amount to temperature and divides the electrostatic chuck into multiple sub-areas. Multiple sub-areas can accurately achieve temperature control to achieve the regulation of film thickness. When the sensitivity coefficient of the etching amount to temperature is low, the change of the etching amount per unit temperature is small, and the temperature rise and fall capability of the multi-zone electrostatic chuck is also limited, so the ability to regulate the film thickness is weak. Therefore, if you want to improve the ability of the multi-zone electrostatic chuck to control the film thickness, you need to make the etching amount as sensitive to temperature as possible, and the process gas needs to use a gas with a heavier polymer.

[0021] Among them, the multi-zone electrostatic chuck of the embodiment of the present application can be used Figure 3 The four-zone annular electrostatic chuck shown corresponds to four annular sub-areas, which can also be used Figure 7 More zones of electrostatic chucks are shown, such as Figure 7 As shown, the electrostatic chuck includes multiple annular areas, each of which includes multiple sub-areas. Compared with the four-area annular electrostatic chuck, only radial etching adjustment can be achieved in circles, and angular etching adjustment cannot be achieved. Figure 7 The electrostatic chuck with more zones shown can better achieve etching adjustment in different directions and positions.

[0022] The number of stripe defects is strongly correlated with the etching amount. As the etching amount increases, the amount of byproducts also increases. The double bonds formed by the byproducts are connected and polymerized to form stripe defects. When etching continues downward, poly partial etch is formed. Therefore, the lighter the polymer, the more conducive it is to reducing the number of defects. However, considering the application mechanism of the multi-zone electrostatic chuck, reducing the generation of polymer will lose temperature sensitivity, thereby weakening the control of the multi-zone electrostatic chuck on the film thickness. Therefore, it is necessary to find a balance between temperature sensitivity and the number of defects. The correlation is as follows: Figure 8 As shown, the weight of the polymer is quantified by the etching rate (corresponding to the etching rate on the horizontal axis, in Å / s), and the number of defects (corresponding to the number of defects on the vertical axis, in ea) is positively correlated with the sensitivity coefficient of the etching amount to temperature (corresponding to the sensitivity coefficient on the vertical axis, in Å / ℃), and both are related to the weight of the polymer. The heavier the polymer, the slower the etching rate, the more defects there are, and the higher the sensitivity coefficient of the etching amount to temperature used to control the multi-zone calculation. Therefore, it is necessary to find a balance between the number of defects and the sensitivity coefficient of the etching amount to temperature, so that the multi-zone electrostatic chuck can use temperature sensitivity to realize the calculation function and control the number of defects at a certain level. Figure 8 The circles in the figure can be regarded as the process in which the proportion of the first gas and the second gas in the mixed gas gradually decreases (accounting for 5%~25%). In the box (accounting for 13%~18%), the sensitivity coefficients of the number of defects and the etching amount to temperature both drop to a lower level for the first time and do not show a significant increase within a certain range.

[0023] In the etching step, a mixed gas is introduced into the chamber so that the sensitivity coefficient of the etching amount to the temperature is within a set range, such as 2~10Å / ℃. The mixed gas includes at least a first type of reaction gas, a second type of reaction gas and an auxiliary gas. The first type of reaction gas includes a carbon fluoride compound gas, and the number of carbon atoms in the first type of reaction gas accounts for greater than or equal to 20%. The second type of reaction gas is a fluorine-containing gas whose byproduct is a gas, such as nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), etc., which provides more F ions and increases the etching rate. At the same time, the byproducts nitric oxide (NO) and sulfur dioxide (SO2) are gases that are easily pumped away. The auxiliary gas can be oxygen (O2). The volume ratio of the first type of reaction gas to the sum of the second type of reaction gas and the auxiliary gas in the mixed gas can range from 3:2 to 2:1.

[0024] The first type of reaction gas may further include a first gas and a second gas. The first gas is a carbon-based polymer gas whose carbon-based atomic number ratio is higher than a first set value. The first set value may be 30%, for example, C x1 F z1 , where x1 / (x1+z1) is greater than or equal to 30%, and may specifically be hexafluorobutadiene (C4F6), octafluorocyclobutane (C4F8), etc. The second gas is a hydrocarbon-based polymer gas in which the proportion of hydrocarbon-based atoms is higher than the second set value, and the second set value may specifically be 40%, for example, C x2 H y2 F z2 , where (x2+y2) / (x2+y2+z2) is greater than or equal to 40%, which can be difluoromethane (CH2F2), fluoromethane (CH3F), etc. This step selects C4F6, CH2F2 (or C4F8, CH3F, etc.) for etching poly mainly because C or CH x The content of is high, and the by-products formed by its reaction with Poly are highly sensitive to temperature, resulting in a high sensitivity coefficient of etching amount to temperature.

[0025] The mixed gas may also include a diluent gas. The diluent gas is a rare gas, such as helium (He). The volume ratio of the first gas to the second gas, the second type of reaction gas and the auxiliary gas in the mixed gas may be controlled to be in the range of 2:3 to 1:1.

[0026] Taking the mixed gas C4F6 / CH2F2 / NF3 / O2 / He as an example, the basic chemical reaction equation with polymer is: Si+C4F6+CH2F2+NF3+O2→Si-CF(s)+CHF(s)+SiF4↑+CO2↑+NO↑+H2O.

[0027] The chamber pressure can be controlled within the range of 5~30mTorr, and the flow of the mixed gas can be controlled within the range of 200~500 volume flow units (standard cubic centimeter per minute, referred to as sccm). The volume ratio of the first gas, the second gas, the second type of reaction gas, the auxiliary gas and the dilution gas in the mixed gas can be controlled within the range of (2~3):1:1:1:(20~30). The dilution gas such as helium (He) should have a higher ratio as a dilution gas. The first gas such as C4F6 as the main control gas for the polymer can be set to the sum of the flow rates of other gases except He. The temperature range of the electrostatic chuck can be set to 50-70℃, and the current ratio Ir of the outer coil of the upper electrode inductor double spiral coil to the sum of the inner and outer coils can be set to 0.2~0.8.

[0028] S602, obtaining a target etching amount of each sub-region of the electrostatic chuck and a sensitivity coefficient of the etching amount corresponding to the mixed gas to temperature.

[0029] In an embodiment of the present application, the target etching amount, that is, the etching amount required for each sub-region of the electrostatic chuck, can be obtained by the following steps: obtaining the film thickness value of the sub-region before etching, obtaining the target film thickness value of the sub-region, calculating the difference between the initial film thickness value and the target film thickness value, and obtaining the target etching amount.

[0030] Specifically, the film thickness value before etching of the sub-region can be obtained by measuring the film thickness value of each sub-region before etching. The target film thickness value of the sub-region is the film thickness value of the sub-region after etching required by the customer. Assuming that the film thickness value of a sub-region before etching is 1200Å, and the target film thickness value required by the customer is 950Å, it can be calculated that the etching amount required for the sub-region, i.e., the target etching amount, is 1200Å-950Å=250Å.

[0031] Since the gas types and gas volume ratios in the mixed gas are determined, the temperature sensitivity coefficient of the etching amount corresponding to the mixed gas is also determined. Therefore, the temperature sensitivity coefficient of the etching amount corresponding to the mixed gas can be predetermined and stored in a set position, and can be directly obtained from the set position each time it is used. Correspondingly, before the above step of "obtaining the temperature sensitivity coefficient of the etching amount corresponding to the mixed gas", the following steps can also be included: determining the temperature sensitivity coefficient of the etching amount corresponding to the mixed gas.

[0032] Among them, the sensitivity coefficient of the etching amount corresponding to the mixed gas to temperature can be determined by the following steps: when the mixed gas is introduced into the chamber, the etching amount corresponding to different temperatures of the electrostatic chuck under the set etching time is obtained; based on the etching amount corresponding to different temperatures, the sensitivity coefficient of the etching amount to temperature is calculated.

[0033] Specifically, the calculation formula of the sensitivity coefficient of etching amount to temperature is as follows: (A T1 -A T2 ) / (T1-T2) Among them, A T1 is the etching amount at temperature T1, A T2 is the etching amount at temperature T2. For example, at the same etching time, the Poly etching amount is 280 Å at 60°C and 200 Å at 50°C. However, due to the hardware temperature control limit, the maximum temperature control range of the sub-region is less than 10°C, and the maximum film thickness range that can be adjusted by the multi-zone electrostatic chuck is 80 Å.

[0034] For example, the specific process of determining the sensitivity coefficient of etching amount to temperature can be as follows: first, run 3 wafers and enable multi-zone to collect film thickness data before and after etching. The operating conditions of the 3 wafers are base temperature, high temperature (A T1 ), low temperature (A T2 ), as a known data template for the machine, the definition of high and low temperature is generally set to cover the highest and lowest film thickness differences of the entire wafer, generally set to ±5°C. In this case, the sensitivity coefficient of etching amount to temperature can be calculated as follows: for example, when the etching time remains unchanged, the etching amount at the base temperature of 60°C is 240A, the etching amount at 55°C is 200A, and the etching amount at 65°C is 280A. The sensitivity coefficient of etching amount to temperature is (280-200) / (65-55)=8 Å / °C.

[0035] S603, controlling the temperature of the sub-region according to the target etching amount of the sub-region and the sensitivity coefficient of the etching amount to temperature.

[0036] In the embodiment of the present application, based on the target etching amount of each sub-region and the temperature sensitivity coefficient of the etching amount obtained in step S602, each sub-region is temperature controlled. Specifically, it can be achieved by the following steps: according to the target etching amount of the sub-region and the temperature sensitivity coefficient of the etching amount, the target temperature of the sub-region is determined; and the temperature of the sub-region is controlled according to the target temperature.

[0037] Specifically, the target temperature of the sub-region is the temperature that needs to be controlled in the sub-region. Taking the target etching amount of a sub-region as 250 Å and the etching amount sensitivity coefficient to temperature as 8 Å / ℃ as an example, it is known that the etching amount is 240Å when the base temperature is 60℃, then the target temperature of the sub-region is 60+(250-240) / 8=61.25℃, and the temperature of the sub-region is controlled to be 61.25℃.

[0038] S604, turning on the upper RF power supply to start the plasma, so as to etch back the polysilicon on the surface of the wafer placed on the electrostatic chuck.

[0039] In the embodiment of the present application, the upper RF power supply is turned on and the power is set to 500-1000W to generate plasma to etch back the polysilicon on the surface of the wafer placed on the electrostatic chuck. The lower RF power supply is turned on and the power is set to 50-200 volts (V).

[0040] When the sensitivity coefficient of etching amount to temperature is in the range of 3~10Å / ℃, the number of defects has dropped to about 100~200ea. Fig. 9 shown.

[0041] After the etching step, the polysilicon etching back method of the embodiment of the present application may further include: a stripe defect repairing step. The stripe defect repairing step includes: introducing oxygen into the chamber to first clean the byproducts on the surface of the wafer.

[0042] Specifically, the strip defect repair step is mainly used to remove the polymer byproducts produced in the previous step. The specific process parameters are as follows: the upper RF power supply power is set to 500~1500W to generate plasma, the lower RF power supply power is set to 0V, the chamber pressure is controlled in the range of 5~30mTorr, the etching gas is selected as O2, the total gas flow is set to 50~300sccm, the temperature range of the electrostatic chuck is set to 50~70℃, and the current ratio Ir of the outer coil of the upper electrode inductor double spiral coil and the sum of the inner and outer coils is set to 0.2~0.7. Since C4F6 / CH2F2 / NF3 is used as the main etching gas in the previous step, in the process of etching Poly, in addition to the generation of gas byproducts such as silicon tetrafluoride (SiF4) and NO, since C4F6 / CH2F2 will decompose CHx groups in the plasma etcher, after reacting with Poly, polymer byproducts such as Si-CF and CHF will be generated. Therefore, the strip defect repair step chooses to introduce oxygen into the chamber. The oxygen ions react with the above-mentioned solid by-products to form gaseous substances such as carbon dioxide (CO2) and water vapor (H2O), which are finally pumped away as waste gas by the molecular pump.

[0043] Furthermore, after the strip defect repair step, the polysilicon back etching method of the embodiment of the present application may also include the following steps: determining whether the number of cycles reaches a preset cycle number threshold; if not, returning to execute the natural oxide layer treatment step; if reached, executing the remaining by-product removal step: introducing argon gas into the chamber, and applying a bias voltage to the wafer surface to perform a second cleaning of the remaining by-products on the wafer surface.

[0044] Specifically, the cycle number threshold can be set according to the severity of the strip defect, for example, it can be set to 3 times. After the strip defect repair step, the cycle number is increased by 1. If the cycle number does not reach 3 times, it returns to the natural oxide layer processing step. The first three steps (natural oxide layer processing step, etching step and strip defect repair step) are repeated so that the by-products are processed before they are connected into long chains of μm level and fall onto the wafer surface. At this time, the number of defects can be reduced to within 40ea, such as Fig.10 shown.

[0045] If the number of cycles reaches 3, the residual byproduct removal step is performed. In the residual byproduct removal step, argon (Ar) is introduced into the chamber to maintain the chamber at a relatively high pressure (100~500mTorr) to enhance the probability of collision between different particles in the chamber and between particles and the wafer, and a suitable bias voltage (0~500V) is applied to the wafer surface. Ar dissociates into Ar+ ions under the action of the RF power supply. The Ar+ ions bombard the surface of the wafer under the action of the electric field on the wafer surface. After the byproducts are sputtered off the Poly surface, they are extracted by the vacuum system in the chamber to complete the cleaning process of the wafer surface.

[0046] Fig.11 The overall flow chart of the polysilicon etching back method of the embodiment of the present application is as follows: Fig.11 As shown, including: S1101, natural oxide layer treatment step.

[0047] S1102, etching step.

[0048] S1103, strip defect repair step.

[0049] S1104, determine whether the cycle number threshold is reached. If yes, execute step S1105. If no, return to step S1101.

[0050] S1105, residual by-product removal step.

[0051] Fig.12 The schematic diagram of the film layer of the wafer before and after the steps of the polysilicon back etching method of the embodiment of the present application are cyclically executed, wherein the wafer includes poly 101, Fin 102 and silicon dioxide (SiO2) 103.

[0052] Fig.13 The figure is a schematic diagram comparing the uniformity of the film thickness after the wafer is etched in the related technical solution and the embodiment of the present application, wherein the ordinate is the thickness uniformity, in Å, and the abscissa is the number of wafers, in pieces. Fig.13 It can be seen that the above line graph corresponds to the relevant technical solution, and the corresponding film thickness uniformity amplitude varies greatly, so the uniformity of the film thickness is relatively unstable; the following line graph corresponds to the embodiment solution of the present application, and the corresponding film thickness uniformity amplitude varies less, so the uniformity of the film thickness is relatively stable.

[0053] In summary, in the polysilicon back-etching method of the embodiment of the present application, when back-etching the polysilicon on the surface of the wafer, in the etching step, a mixed gas is introduced into the chamber to make the sensitivity coefficient of the etching amount to the temperature within a set range, and the target etching amount and the sensitivity coefficient of the etching amount to the temperature of each sub-area of ​​the electrostatic chuck are obtained. According to the target etching amount and the sensitivity coefficient of the etching amount to the temperature of the sub-area, the temperature of the sub-area is controlled, and the upper RF power supply is turned on for plasma ignition to back-etch the polysilicon on the surface of the wafer placed on the electrostatic chuck. The mixed gas used in the embodiment of the present application makes the sensitivity coefficient of the etching amount to temperature within a relatively high set range. Therefore, by controlling the temperature of each sub-area of ​​the electrostatic chuck, the etching amount and film thickness of different sub-areas of the Poly can be accurately controlled to ensure that the mean or range of the film thickness after each wafer is etched is stable. Since the number of strip defects increases with the increase of the sensitivity coefficient of the etching amount to temperature, the sensitivity coefficient of the etching amount to temperature is limited within the set range, so that the number of strip defects is also limited to the set number, reducing the number of strip defects after etching and improving the yield of the wafer. The mixed gas also includes fluorine-containing gases whose by-products are gases, which can provide more F ions to increase the etching rate. At the same time, the by-products NO and SO2 are gases that are easily extracted. The electrostatic chuck includes multiple annular areas, each of which includes multiple sub-areas, which can achieve etching adjustment in different directions and positions. The natural oxide layer processing step, etching step and strip defect repair step are executed cyclically, so that the by-products can be processed before they are connected into long chains at the μm level and fall onto the wafer surface, further reducing the number of defects.

[0054] The present application also provides a semiconductor process equipment. Fig.14 As shown, the semiconductor process equipment 1300 includes: a chamber 501, an upper RF power supply 504 and a controller 1301, the controller 1301 includes at least one processor and at least one memory, the memory stores a computer program, and when the computer program is executed by the processor, the steps of any of the above-mentioned polysilicon back-etching method embodiments are implemented to back-etch the polysilicon on the surface of the wafer placed on the electrostatic chuck 502 of the chamber 501.

[0055] The semiconductor process equipment of the embodiment of the present application adopts a mixed gas so that the sensitivity coefficient of the etching amount to temperature is within a relatively high set range. Therefore, the etching amount and film thickness of different sub-regions of the Poly can be accurately controlled by controlling the temperature of each sub-region of the electrostatic chuck, ensuring that the mean or range of the film thickness after each wafer is etched is stable. Since the number of strip defects increases with the increase of the sensitivity coefficient of the etching amount to temperature, the sensitivity coefficient of the etching amount to temperature is limited within the set range, so that the number of strip defects is also limited to the set number, reducing the number of strip defects after etching and improving the yield of the wafer. The mixed gas also includes fluorine-containing gas whose by-product is gas, which can provide more F ions to increase the etching rate, and the by-products NO and SO2 are gases that are easily extracted. The electrostatic chuck includes multiple annular areas, each of which includes multiple sub-areas, which can achieve etching adjustment in different directions and positions. The natural oxide layer processing step, etching step and strip defect repair step are executed cyclically, so that the by-products can be processed before they are connected into long chains at the μm level and fall onto the wafer surface, further reducing the number of defects.

[0056] An embodiment of the present application also proposes a readable storage medium, on which one or more computer programs are stored. The one or more computer programs include instructions. When the program or instructions are executed by a processor in a semiconductor process equipment including multiple application programs, the processor in the semiconductor process equipment can execute the various processes of the above-mentioned polysilicon back-etching method embodiment, and is specifically used to execute the steps of any of the above-mentioned polysilicon back-etching method embodiments.

[0057] The readable storage medium of the embodiment of the present application adopts a mixed gas so that the sensitivity coefficient of the etching amount to temperature is within a relatively high set range. Therefore, the etching amount and film thickness of different sub-regions of the Poly can be accurately controlled by controlling the temperature of each sub-region of the electrostatic chuck, ensuring that the mean or range of the film thickness after each wafer is etched is stable. Since the number of strip defects increases with the increase of the sensitivity coefficient of the etching amount to temperature, the sensitivity coefficient of the etching amount to temperature is limited within the set range, so that the number of strip defects is also limited to the set number, reducing the number of strip defects after etching and improving the yield of the wafer. The mixed gas also includes fluorine-containing gas whose by-product is gas, which can provide more F ions to increase the etching rate, and the by-products NO and SO2 are gases that are easily extracted. The electrostatic chuck includes multiple annular areas, each of which includes multiple sub-areas, which can achieve etching adjustment in different directions and positions. The natural oxide layer processing step, etching step and strip defect repair step are executed cyclically, so that the by-products can be processed before they are connected into long chains at the μm level and fall onto the wafer surface, further reducing the number of defects.

[0058] The systems, devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0059] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0060] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0061] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0062] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0063] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0064] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0065] Memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0066] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined in this article, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0067] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0068] The present application may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0069] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0070] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A polysilicon etching back method, characterized in that: include: An etching step, the etching step comprising: A mixed gas is introduced into the chamber so that the sensitivity coefficient of the etching amount to the temperature is within a set range; Obtaining a target etching amount of each sub-region of the electrostatic chuck and a sensitivity coefficient of the etching amount corresponding to the mixed gas to temperature; Controlling the temperature of the sub-region according to the target etching amount of the sub-region and a sensitivity coefficient of the etching amount to temperature; The upper radio frequency power supply is turned on to start the plasma so as to etch back the polysilicon on the surface of the wafer placed on the electrostatic chuck.

2. The method according to claim 1, characterized in that The setting range is 2 angstroms / degree Celsius to 10 angstroms / degree Celsius.

3. The method according to claim 1, characterized in that The mixed gas includes a first type of reaction gas, a second type of reaction gas and an auxiliary gas. The first type of reaction gas includes a fluorocarbon compound gas, and the second type of reaction gas is a fluorine-containing gas whose byproduct is gas.

4. The method according to claim 3, characterized in that The proportion of carbon atoms in the first type of reaction gas in the mixed gas is greater than or equal to 20%; and / or, The volume ratio of the first type of reaction gas to the sum of the second type of reaction gas and the auxiliary gas in the mixed gas is in a range of 3:2 to 2:

1.

5. The method according to claim 4, characterized in that The first type of reaction gas further includes a first gas and a second gas, wherein the first gas is C x1 F z1 , the second gas is C x2 H y2 F z2 ; x1 / (x1+z1) is greater than or equal to 30%, (x2+y2) / (x2+y2+z2) is greater than or equal to 40%.

6. The method according to claim 5, characterized in that The first gas is hexafluorobutadiene C4F6 and / or octafluorocyclobutane C4F8; the second gas is difluoromethane CH2F2 and / or fluoromethane CH3F.

7. The method according to claim 5, characterized in that The volume ratio of the first gas to the second gas, the second type of reaction gas and the auxiliary gas in the mixed gas is in a range of 2:3 to 1:

1.

8. The method according to any one of claims 5 to 7, characterized in that: The mixed gas further includes a dilution gas, and the dilution gas is a rare gas; and / or, The auxiliary gas is oxygen.

9. The method according to claim 8, characterized in that The volume ratio range of the first gas, the second gas, the second type of reaction gas, the auxiliary gas and the dilution gas in the mixed gas is: (2~3): 1: 1: 1: (20~30).

10. The method according to claim 1, characterized in that The electrostatic chuck includes a plurality of annular regions, each of which includes a plurality of sub-regions.

11. The method according to claim 1, characterized in that: The step of obtaining a target etching amount of each sub-region of the electrostatic chuck comprises: Obtaining a film thickness value of the sub-region before etching; Obtaining a target film thickness value of the sub-region; The difference between the initial film thickness value and the target film thickness value is calculated to obtain the target etching amount.

12. The method according to claim 1, characterized in that Before obtaining the temperature sensitivity coefficient of the etching amount corresponding to the mixed gas, the method further includes determining the temperature sensitivity coefficient of the etching amount corresponding to the mixed gas, which specifically includes: When the mixed gas is introduced into the chamber, obtaining the etching amount corresponding to different temperatures of the electrostatic chuck under a set etching time; According to the etching amounts corresponding to the different temperatures, a sensitivity coefficient of the etching amount to temperature is calculated.

13. The method according to claim 1, characterized in that The step of controlling the temperature of the sub-region according to the target etching amount of the sub-region and the sensitivity coefficient of the etching amount to temperature comprises: Determining a target temperature of the sub-region according to the target etching amount of the sub-region and a sensitivity coefficient of the etching amount to temperature; The temperature of the sub-area is controlled according to the target temperature.

14. The method according to claim 1, characterized in that Before the etching step, a natural oxide layer processing step is also included: A gas including fluorocarbons is used to remove the native oxide layer on the surface of the polysilicon.

15. The method according to claim 14, characterized in that After the etching step, the method further comprises: a strip defect repairing step, wherein the strip defect repairing step comprises: Oxygen is introduced into the chamber to perform a first cleaning of byproducts on the surface of the wafer.

16. The method according to claim 15, characterized in that After the strip defect repairing step, the method further comprises: Determine whether the number of cycles reaches a preset cycle number threshold; If not reached, return to execute the natural oxide layer treatment step; If the condition is reached, a residual by-product removal step is performed: argon gas is introduced into the chamber, and a bias voltage is applied to the surface of the wafer to perform a second cleaning on the residual by-products on the surface of the wafer.

17. A semiconductor process equipment, characterized in that: include: A chamber, an upper radio frequency power supply and a controller, wherein the controller includes at least one processor and at least one memory, wherein the memory stores a computer program, and when the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 16 are implemented.

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