Failure analysis method of storage structure, failure analysis device of storage structure, computer readable storage medium and terminal

Abstract

The invention discloses a failure analysis method of a storage structure, a failure analysis device of the storage structure, a computer readable storage medium and a terminal. The method comprises the following steps: acquiring a test structure data graph; comparing the plurality of test structure data graphs with the yield data graph of the wafer to be analyzed one by one, and judging whether the test structures corresponding to the test structure data graphs are abnormal or not; when the test structure corresponding to the test structure data graph is judged to be abnormal, obtaining wafer test data of a hierarchical structure in the test structure; obtaining a hierarchical structure data graph; comparing the hierarchical structure data graph with the yield data graph one by one; and when the hierarchical structure corresponding to the hierarchical structure data graph is abnormal, acquiring defect scanning data related to the abnormal hierarchical structure so as to analyze the failure reason of the failure position in the yield data graph. According to the method, the degree of dependence on experience of analysts is reduced, the burdensome labor of data processing is reduced, and the failure position of the storage structure is positioned more quickly.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a failure analysis method for a storage structure, a failure analysis device for a storage structure, a computer-readable storage medium, and a terminal. Background Art

[0002] As chip integration continues to increase, the feature size of integrated circuits continues to shrink at an exponential rate. Static Random Access Memory (SRAM) testing and failure analysis are becoming increasingly important.

[0003] Static random access memory is widely used in wafer foundries. By utilizing the addressability of static random access memory, the failure point can be located relatively easily, and confirmed through physical failure analysis methods such as atomic force microscope probe (Atomic Force Microscope, referred to as AFP), scanning electron microscope (Scanning Electron Microscope, referred to as SEM), and the cause of failure can be analyzed, and the process step that causes the failure can be located and improved.

[0004] However, the current failure analysis method of static random access memory needs to be improved. Summary of the invention

[0005] The problem solved by the present invention is how to perform failure analysis on a storage structure to reduce reliance on the experience of analysts, alleviate the cumbersome labor of data processing, and locate the failure position more quickly.

[0006] In order to solve the above problems, the present invention provides a failure analysis method for a storage structure, comprising: obtaining multiple test structures of each chip in a wafer to be analyzed, wafer test data of each test structure, and wafer test data of each hierarchical structure in each test structure; displaying and processing the wafer test data of a test structure to obtain a test structure data graph, wherein the test structure data graph corresponds to a test structure; comparing the multiple test structure data graphs with the yield data graph of the wafer to be analyzed one by one, and judging whether the test structure corresponding to the test structure data graph is abnormal; judging whether the test structure corresponding to the test structure data graph is abnormal When the test data of the wafer of the hierarchical structure in the test structure is obtained according to the type of the test structure with the abnormality, the wafer test data of the hierarchical structure in the test structure is displayed and processed to obtain a hierarchical structure data graph, and the hierarchical structure data graph corresponds to a hierarchical structure in the test structure; the hierarchical structure data graph is compared with the yield data graph one by one to determine whether the hierarchical structure corresponding to the hierarchical structure data graph has an abnormality; when the hierarchical structure corresponding to the hierarchical structure data graph has an abnormality, the defect scanning data involved in the hierarchical structure with the abnormality is obtained to analyze the failure cause of the failure position in the yield data graph.

[0007] Optionally, the method further includes: setting display processing rules; and in the step of performing display processing, performing display processing based on the display processing rules.

[0008] Optionally, the step of setting display processing rules includes: obtaining wafer test data of each test structure based on probe-contact wafer-level test results of multiple test structures of the same type; obtaining a threshold order of magnitude of wafer test data of the test structure based on the wafer test data of multiple test structures of the same type; and setting color display rules based on the threshold order of magnitude of wafer test data of the test structure.

[0009] Optionally, the method also includes: obtaining a yield data graph.

[0010] Optionally, the step of obtaining a yield data graph includes: performing a probe-contact wafer-level test on the wafer to be analyzed; and obtaining a yield data graph based on a result of the probe-contact wafer-level test.

[0011] Optionally, the display processing step includes: obtaining an initial data graph based on wafer test data; overlaying the initial data graphs of the same structure to obtain a structure data graph, wherein the structure data graph is the test structure data graph or the hierarchical structure data graph.

[0012] Optionally, the comparing step includes: comparing the structure data map with the yield data map respectively, the structure data map being one of a test structure data map and a hierarchical structure data map; when the failure position in the structure data map is consistent with that in the yield data map, determining that there is an abnormality in the structure corresponding to the structure data map.

[0013] Optionally, the step of analyzing the failure cause of the failure position in the yield data graph includes: when there is an abnormal defect in the defect scanning data involved in the abnormal hierarchical structure, judging that the abnormal hierarchical structure is the failure cause of the failure position; when there is no abnormal defect in the defect scanning data involved in the abnormal hierarchical structure, performing physical fault analysis.

[0014] Optionally, the method further includes: comparing the hierarchical structure data graph with the yield data graph one by one, and performing physical fault analysis when it is determined that there is no abnormality in the hierarchical structure corresponding to the hierarchical structure data graph.

[0015] Optionally, the step of physical fault analysis includes: slicing the test structure with the abnormality to obtain a slice structure; performing a characterization test on the slice structure to analyze whether there is an abnormality in the hierarchical structure of the abnormal test structure.

[0016] Optionally, the method further includes: before obtaining multiple test structures of each chip in a wafer to be analyzed, wafer test data of each test structure, and wafer test data of each hierarchical structure in each test structure, classifying the test structures in the wafer to be analyzed.

[0017] Correspondingly, the present invention also provides a failure analysis device of a storage structure, comprising: an acquisition module, adapted to acquire multiple test structures of each chip in a wafer to be analyzed, wafer test data of each test structure, and wafer test data of each hierarchical structure in each test structure; a storage module, adapted to pre-store a yield data graph of the wafer to be analyzed; a first processing module, adapted to display and process wafer test data of a test structure, and acquire a test structure data graph, wherein the test structure data graph corresponds to a test structure; compare the multiple test structure data graphs with the yield data graph of the wafer to be analyzed one by one, and determine whether the test structure corresponding to the test structure data graph is abnormal; and determine whether the test structure data graph corresponds to the test structure data graph. When there is an abnormality in the test structure corresponding to the graph, wafer test data of the hierarchical structure in the test structure is obtained according to the type of the test structure with the abnormality; a second processing module is suitable for displaying and processing the wafer test data of the hierarchical structure in the test structure, and obtaining a hierarchical structure data graph, wherein the hierarchical structure data graph corresponds to a hierarchical structure in the test structure; the hierarchical structure data graph is compared with the yield data graph one by one to determine whether there is an abnormality in the hierarchical structure corresponding to the hierarchical structure data graph; when there is an abnormality in the hierarchical structure corresponding to the hierarchical structure data graph, defect scanning data involved in the hierarchical structure with the abnormality is obtained to analyze the failure cause of the failure position in the yield data graph.

[0018] Accordingly, the present invention also provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor to implement the steps of any one of the methods for failure analysis of a storage structure.

[0019] Correspondingly, the present invention also provides a terminal, including a memory and a processor, wherein the memory stores computer instructions that can be run on the processor, and when the processor runs the computer instructions, the steps of any one of the methods for failure analysis of storage structures are executed.

[0020] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0021] The failure analysis method of the storage structure of the technical solution of the present invention first compares multiple test structure data graphs one by one with the yield data graph of the wafer to be analyzed, and determines whether the test structure corresponding to the test structure data graph has an abnormality, and then compares the hierarchical structure data graphs of various hierarchical structures in the test structure with the abnormality with the yield data graph of the wafer to be analyzed, and determines whether the hierarchical structure corresponding to the hierarchical structure data graph has an abnormality, and analyzes the failure cause of the failure position in the yield data graph based on the defect scanning data involved in the hierarchical structure with the abnormality. The failure analysis method of the storage structure reduces the degree of dependence on the experience of analysts, reduces the tedious labor of data processing, and locates the failure position of the storage structure more quickly. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a flow chart of various steps of a failure analysis method for a storage structure according to an embodiment of the present invention;

[0023] Figure 2 is a flowchart of various steps of setting display processing rules according to an embodiment of the present invention;

[0024] Figure 3 is a flow chart of various steps of display processing of a test structure according to an embodiment of the present invention;

[0025] Figure 4 is a schematic diagram of a superposition processing process of an initial data graph according to an embodiment of the present invention;

[0026] Figure 5 It is a flow chart of various steps of comparing the test structure data graph and the yield data graph of the wafer to be analyzed according to an embodiment of the present invention;

[0027] Figure 6 is a schematic diagram of comparison between a yield data diagram and a test structure data diagram of an embodiment of the present invention;

[0028] Figure 7 is a flowchart of various steps of a display process of a hierarchical structure according to an embodiment of the present invention;

[0029] Figure 8 It is a flow chart of various steps of comparing the hierarchical structure data graph and the yield data graph of the wafer to be analyzed according to an embodiment of the present invention;

[0030] Fig. 9 is a flow chart of various steps of analyzing failure causes of failure locations in a yield data graph according to an embodiment of the present invention;

[0031] Fig.10 is a flow chart of various steps of physical fault analysis according to an embodiment of the present invention;

[0032] Fig.11The invention relates to a failure analysis device for a storage structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] As can be seen from the background technology, there are many problems in the prior art. The causes of these problems are analyzed below:

[0034] In the prior art, the yield monitoring system or yield management system generally pulls offline data to analyze the yield, and the yield engineer imports the relevant data into the data drawing software for data analysis. An experienced case manager may find inspiration for solving the case after careful research and judgment. However, in this solution, the entire process is highly dependent on the experience of the case manager, and the case manager's patience, sensitivity, analysis and judgment and other abilities determine the progress of the case. The entire research and judgment process takes time and brainpower, and whether the case manager can get inspiration from the vast amount of data is still unknown, so this approach is highly uncertain. Especially for engineers who are new to the workplace and have no experience to follow, the challenges are huge and the return on investment is very low.

[0035] In order to solve the technical problem, the present invention provides a failure analysis method for a storage structure, comprising: obtaining multiple test structures of each chip in a wafer to be analyzed, wafer test data of each test structure, and wafer test data of each hierarchical structure in each test structure; displaying and processing the wafer test data of a test structure to obtain a test structure data graph, wherein the test structure data graph corresponds to a test structure; comparing the multiple test structure data graphs with the yield data graph of the wafer to be analyzed one by one, and judging whether the test structure corresponding to the test structure data graph is abnormal; judging whether the test structure corresponding to the test structure data graph is abnormal Normally, according to the type of test structure with an abnormality, wafer test data of the hierarchical structure in the test structure is obtained; the wafer test data of the hierarchical structure in the test structure is displayed and processed to obtain a hierarchical structure data graph, which corresponds to a hierarchical structure in the test structure; the hierarchical structure data graph is compared with the yield data graph one by one to determine whether the hierarchical structure corresponding to the hierarchical structure data graph has an abnormality; when the hierarchical structure corresponding to the hierarchical structure data graph has an abnormality, the defect scanning data involved in the hierarchical structure with the abnormality is obtained to analyze the failure cause of the failure position in the yield data graph.

[0036] The technical solution of the present invention first compares multiple test structure data graphs one by one with the yield data graph of the wafer to be analyzed, and determines whether the test structure corresponding to the test structure data graph has an abnormality, and then compares the hierarchical structure data graphs of various hierarchical structures in the test structure with the abnormality with the yield data graph of the wafer to be analyzed, and determines whether the hierarchical structure corresponding to the hierarchical structure data graph has an abnormality, and analyzes the failure cause of the failure position in the yield data graph based on the defect scanning data involved in the hierarchical structure with the abnormality. The failure analysis method of the storage structure reduces the degree of dependence on the experience of the analyst, reduces the tedious labor of data processing, and locates the failure position of the storage structure more quickly.

[0037] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0038] Please refer to Figure 1 The steps of the failure analysis method of the storage structure of the embodiment of the present invention include:

[0039] Step S11, obtaining a plurality of test structures of each chip in a wafer to be analyzed, wafer test data of each test structure, and wafer test data of each hierarchical structure in each test structure;

[0040] Step S12, setting display processing rules;

[0041] Step S13, displaying and processing wafer test data of a test structure to obtain a test structure data graph, wherein the test structure data graph corresponds to a test structure;

[0042] Step S14, comparing the multiple test structure data graphs with the yield data graph of the wafer to be analyzed one by one, and determining whether the test structure corresponding to the test structure data graph has an abnormality;

[0043] Step S15, when it is determined that the test structure corresponding to the test structure data graph has an abnormality, obtaining wafer test data of the hierarchical structure in the test structure according to the type of the test structure with the abnormality;

[0044] Step S16, displaying the wafer test data of the hierarchical structure in the test structure to obtain a hierarchical structure data graph, wherein the hierarchical structure data graph corresponds to a hierarchical structure in the test structure;

[0045] Step S17, comparing the hierarchical structure data graph with the yield data graph one by one, and determining whether the hierarchical structure corresponding to the hierarchical structure data graph has an abnormality;

[0046] Step S18, when there is an abnormality in the hierarchical structure corresponding to the hierarchical structure data graph, defect scanning data involved in the abnormal hierarchical structure is obtained to analyze the failure cause of the failure position in the yield data graph. The following will describe in detail the various steps of the failure analysis method of the storage structure.

[0047] In step S11 , according to different types of structures, multiple test structures, wafer test data of each test structure, and wafer test data of each hierarchical structure in each test structure are obtained.

[0048] Specifically, in some embodiments of the present invention, the wafer test data of the test structure is test data of a wafer acceptance test (WAT) of the test structure.

[0049] Specifically, in some embodiments of the present invention, the wafer test data of the hierarchical structure is test data of a wafer acceptance test (WAT) of the hierarchical structure.

[0050] In some embodiments of the present invention, before executing step S11, the method further includes: executing step S10.

[0051] Step S10, classifying the test structures in the wafer to be analyzed.

[0052] In step S10 , the test structure of the wafer to be analyzed is classified, including: classifying the test structure (SRAM health of line, SRAMHOL for short) and the hierarchical structure (Ground-Rule Verification, GRV for short) of the wafer to be analyzed.

[0053] By way of example, the test structure includes: PD-PD, WL-WL, BL-WL, ND-VDD, GND-ND, PO-BL stack chain, etc.; the hierarchical structure includes AA-AA, PO-PO, CT-CT, CT-PO, CT-M1, M1-M1, etc.

[0054] In step S12, please refer to Figure 1 Please refer to Figure 2 , the steps to set display processing rules include:

[0055] Step S120, obtaining wafer test data of each test structure according to wafer-level test results of probe contact of multiple test structures of the same type;

[0056] Step S121, obtaining a threshold magnitude of wafer test data of the same type of test structure according to wafer test data of a plurality of the test structures;

[0057] Step S122, setting a color rendering rule according to a threshold level of the test structure wafer test data.

[0058] In step S120, according to the result of wafer-level test (Chip Probing, referred to as CP) by probe contact, wafer test data of the test structure that passed the wafer-level test by probe contact is obtained. That is, when the result of wafer-level test by probe contact meets the requirements of wafer-level test by probe contact, the wafer test data of the test structure, that is, the test data of wafer acceptance test (WAT) of the test structure is obtained; when the result of wafer-level test by probe contact does not meet the requirements of wafer-level test by probe contact, the wafer test data of the test structure is not obtained.

[0059] In step S121, a threshold order of magnitude of wafer test data of the test structure is obtained according to the wafer test data of the test structure.

[0060] For example: according to the wafer test data of the test structure BL-WL, the leakage threshold magnitude of the test structure BL-WL is obtained in the range of 10 5 ~10 6 According to the wafer test data of the plurality of said hierarchical structures CT-PO, the leakage threshold magnitude of the hierarchical structure CT-PO is obtained in 10 6 .

[0061] In step S122, a color rendering rule is set according to a threshold level of the test structure wafer test data.

[0062] For example: When the leakage threshold of the test structure BL-WL is on the order of 10 5 ~10 6 When the order of magnitude is set to 10 5 ~10 6 The die on the data graph within the interval is displayed in green, and the set order of magnitude is less than 10 5 The die is displayed in yellow, and the set magnitude is greater than 10 6 The die is displayed in red.

[0063] In step S13, the display processing step performs display processing based on the display processing rule in step S12.

[0064] Specifically, in step S13, please refer to Figure 1Please refer to Figure 3 The steps of displaying and processing wafer test data of a test structure include:

[0065] Step S130, obtaining an initial data graph according to the wafer test data of the test structure;

[0066] Step S131 , performing superposition processing on initial data graphs of the same test structure to obtain a test structure data graph.

[0067] Specifically, in some embodiments of the present invention, the parameters at each position in the test structure data graph obtained by superposition processing indicate the maximum value of the parameters at the corresponding position of each initial data graph of the same structure.

[0068] In step S130, for example, please refer to Figure 4 , Figure 4 is a schematic diagram of the superposition process. In an embodiment of the present invention, the initial data diagram of the test structure is as follows Figure 4 As shown in A and B.

[0069] In step S131, for example, please continue to refer to Figure 4 , the initial data graph A and the initial data graph B of the same test structure are superimposed to obtain the test structure data graph C.

[0070] Specifically, the parameters at each position in the test structure data graph C obtained by superposition processing correspond to the maximum value of the parameters at the corresponding position in the initial data graph A and the initial data graph B of the same test structure.

[0071] For example, Figure 4 As shown, the parameter of the 1st row and 1st column in the initial data graph A is 1, and the parameter of the 1st row and 1st column in the initial data graph B is 3. In the test structure data graph C obtained after the superposition processing, the parameter of the 1st row and 1st column takes the maximum value of the parameters of the initial data graph A and the initial data graph B at the corresponding positions, that is, the maximum value 3 between 1 and 3; the parameter of the 2nd row and 3rd column in the initial data graph A is 9, and the parameter of the 2nd row and 3rd column in the initial data graph B is 6. In the test structure data graph C obtained after the superposition processing, the parameter of the 2nd row and 3rd column takes the maximum value of the parameters of the initial data graph A and the initial data graph B at the corresponding positions, that is, the maximum value 9 between 6 and 9.

[0072] The failure analysis method of the storage structure further includes: obtaining a yield data graph.

[0073] The steps to obtain the yield data map include:

[0074] Performing a probe contact wafer-level test on the wafer to be analyzed;

[0075] A yield data graph is obtained according to the result of the wafer-level test of the probe contact type.

[0076] In step S14, please refer to Figure 1 Please refer to Figure 5 , the comparison step comprises:

[0077] Step S140, comparing the test structure data graph with the yield data graph respectively;

[0078] Step S141 , when the failure positions in the test structure data graph and the yield data graph are consistent, it is determined that an abnormality exists in the test structure corresponding to the test structure data graph.

[0079] In step S141, the failure position in the test structure data map is consistent with that in the yield data map, that is, the failure position in the test structure data map is the same as that in the yield data map, or the overlap rate between the distribution area of ​​the failure position in the test structure data map and the distribution area of ​​the failure position in the yield data map is greater than a preset value. In some embodiments, the preset value is 60%, that is, when the overlap rate between the distribution area of ​​the failure position in the test structure data map and the distribution area of ​​the failure position in the yield data map is greater than 60%, it is determined that the test structure corresponding to the test structure data map is abnormal. In other embodiments, the preset value may be other values.

[0080] Please refer to Figure 6 , Figure 6 It is a comparison diagram of the yield data graph and the test structure data graph. Among them, D is the yield data graph, E is the test structure data graph corresponding to the normal test structure, and F is the test structure data graph corresponding to the abnormal test structure.

[0081] For example, the yield data graph D is compared with the test structure data graphs: such as Figure E and Figure F. When the failure positions in the test structure data graph F and the yield data graph D are consistent,

[0082] That is, when the failure position in the test structure data graph F is the same as that in the yield data graph D, or the overlap rate between the distribution area of ​​the failure position in the test structure data graph F and the distribution area of ​​the failure position in the yield data graph D is greater than a preset value, it is determined that the test structure corresponding to the test structure data graph F has an abnormality;

[0083] When the failure positions in the test structure data graph E and the yield data graph D are inconsistent,

[0084] That is, when the failure positions in the test structure data graph E are different from those in the yield data graph D, and the overlap rate between the distribution area of ​​the failure positions in the test structure data graph E and the distribution area of ​​the failure positions in the yield data graph D is not greater than a preset value, it is determined that there is no abnormality in the test structure corresponding to the test structure data graph E.

[0085] In step S15, when the test structure corresponding to the test structure data graph has an abnormality, wafer test data of a hierarchical structure of the test structure having the abnormality is obtained.

[0086] For example, when an abnormality exists in the WL-BL test structure, wafer test data of hierarchical structures involved in the WL-BL test structure, such as CT-PO, CT-M1, and M1-M1, are analyzed.

[0087] In step S16, please refer to Figure 1 Please refer to Figure 7 The step of displaying and processing the wafer test data of the hierarchical structure in the test structure includes:

[0088] Step S160, obtaining an initial data graph of the hierarchical structure according to wafer test data of the hierarchical structure;

[0089] Step S161 , performing superposition processing on initial data graphs of the same hierarchical structure to obtain the hierarchical structure data graph.

[0090] For example, in the step of obtaining the initial data graph of the hierarchical structure according to the wafer test data of the hierarchical structure, a plurality of initial data graphs G, H... of the hierarchical structure are obtained; the plurality of initial data graphs G, H... are superimposed to obtain the hierarchical structure data Figure X .

[0091] The hierarchical structure data obtained by superposition processing Figure X The parameters at each position in the diagram illustrate the maximum values ​​of the parameters at the corresponding positions of multiple initial data graphs G, initial data graphs H, etc. of the same hierarchical structure.

[0092] Specifically, in some embodiments of the present invention, the overlay processing process in the step of displaying the wafer test data of the hierarchical structure in the test structure is the same as the overlay processing process in the step of displaying the wafer test data of a test structure in the aforementioned step S13.

[0093] In step S17, the hierarchical structure data map is compared with the yield data map; when the failure positions in the hierarchical structure data map and the yield data map are consistent, step S18 is performed.

[0094] In some embodiments of the present invention, when the failure positions in the hierarchical structure data map and the yield data map are inconsistent, step S19 is performed.

[0095] In step S18, the failure position in the hierarchical structure data map is consistent with that in the yield data map.

[0096] That is, the failure position in the hierarchical structure data map is the same as that in the yield data map, or the overlap rate between the distribution area of ​​the failure position in the hierarchical structure data map and the distribution area of ​​the failure position in the yield data map is greater than a preset value. In some embodiments, the preset value is 60%, that is, when the overlap rate between the distribution area of ​​the failure position in the hierarchical structure data map and the distribution area of ​​the failure position in the yield data map is greater than 60%, it is determined that the hierarchical structure corresponding to the hierarchical structure data map is abnormal. In other embodiments, the preset value may be other values.

[0097] In step S19, the failure positions in the hierarchical structure data map and the yield data map are inconsistent.

[0098] That is, the failure positions in the hierarchical structure data map and the yield data map are different, and the overlap rate between the distribution area of ​​the failure positions in the hierarchical structure data map and the distribution area of ​​the failure positions in the yield data map is not greater than a preset value. It is determined that there is no abnormality in the hierarchical structure corresponding to the hierarchical structure data map, and a physical fault analysis is performed.

[0099] In step S18, please refer to Figure 1 Please refer to Fig. 9 , the steps of analyzing the failure causes of the failure locations in the yield data graph include:

[0100] Step S180, when there is an abnormal defect in the defect scanning data involved in the abnormal hierarchical structure, it is determined that the abnormal hierarchical structure is the failure cause of the failure position;

[0101] Step S181 , when the defect scanning data involved in the abnormal hierarchical structure does not have abnormal defects, physical fault analysis is performed.

[0102] In step S180, when the hierarchical structure data graph is consistent with the failure position in the yield data graph, a defect scan record is searched in a yield management system (YMS), and it is determined whether the hierarchical structure has an abnormal defect according to the defect scan record. When it is determined that the hierarchical structure has an abnormal defect according to the defect scan record, the abnormal hierarchical structure is determined to be the failure cause of the failure position.

[0103] In step S181, the physical fault analysis step includes:

[0104] Slice the test structure with the exception to obtain the slice structure;

[0105] A characterization test is performed on the slice structure to analyze whether there is an abnormality in the hierarchical structure of the abnormal test structure.

[0106] The characterization test includes: Scanning Electron Microscope (SEM) test.

[0107] The scanning electron microscope test image of the cross section of the slice structure is observed to analyze whether the hierarchical structure of the abnormal test structure has an abnormality.

[0108] Step S19, comparing the hierarchical structure data graph with the yield data graph one by one, and performing physical fault analysis when it is determined that there is no abnormality in the hierarchical structure corresponding to the hierarchical structure data graph.

[0109] In step S19, please refer to Figure 1 Please refer to Fig.10 , the steps of physical fault analysis include:

[0110] Step S190, slicing the test structure with the abnormality to obtain a slice structure;

[0111] Step S191, performing a characterization test on the slice structure to analyze whether there is an abnormality in the hierarchical structure of the abnormal test structure.

[0112] That is, when the failure positions in the hierarchical structure data map and the yield data map are inconsistent, the test structure is directly sliced ​​to obtain a slice structure; a scanning electron microscope (SEM) test is performed on the slice structure to analyze whether there is an abnormality in the hierarchical structure of the abnormal test structure.

[0113] Accordingly, an embodiment of the present invention further provides a failure analysis device for a storage structure, comprising:

[0114] An acquisition module 20, adapted to acquire multiple test structures of each chip in a wafer to be analyzed, wafer test data of each test structure, and wafer test data of each hierarchical structure in each test structure;

[0115] A storage module 21, adapted to pre-store the yield data graph of the wafer to be analyzed;

[0116] The first detection module 22 is suitable for displaying and processing wafer test data of a test structure, obtaining a test structure data graph, and the test structure data graph corresponds to a test structure; comparing multiple test structure data graphs with the yield data graph of the wafer to be analyzed one by one, and judging whether the test structure corresponding to the test structure data graph has an abnormality; when judging that the test structure corresponding to the test structure data graph has an abnormality, obtaining wafer test data of a hierarchical structure in the test structure according to the type of the test structure with the abnormality;

[0117] The second detection module 23 is suitable for displaying and processing the wafer test data of the hierarchical structure in the test structure, obtaining a hierarchical structure data graph, and the hierarchical structure data graph corresponds to a hierarchical structure in the test structure; comparing the hierarchical structure data graph with the yield data graph one by one to determine whether the hierarchical structure corresponding to the hierarchical structure data graph has an abnormality; when the hierarchical structure corresponding to the hierarchical structure data graph has an abnormality, obtaining the defect scanning data involved in the hierarchical structure with the abnormality to analyze the failure cause of the failure position in the yield data graph.

[0118] The failure analysis device of the storage structure of the present invention is suitable for executing the steps of the failure analysis method of the storage structure of the present invention. The technical solutions of the acquisition module 20, the storage module 21, the first detection module 22 and the second detection module 23 can be specifically referred to the embodiment of the failure analysis method of the storage structure, which will not be repeated here.

[0119] Correspondingly, an embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. The computer program is executed by a processor to implement the steps of any one of the test probe multiplexing analysis methods.

[0120] Correspondingly, an embodiment of the present invention also provides a terminal, including a memory and a processor, wherein the memory stores computer instructions that can be executed on the processor, and when the processor executes the computer instructions, the steps of any one of the test probe multiplexing analysis methods are executed.

[0121] The processor includes a general-purpose processor and a digital signal processor (DSP). The general-purpose processor includes a network processor (NP), a central processing unit (CPU), etc.; the digital signal processor includes an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.

[0122] The memory includes volatile memory and non-volatile memory. The volatile memory includes random access memory (RAM) and cache memory, etc.; the non-volatile memory includes read-only memory (ROM), erasable programmable read-only memory (EPROM), hard disk, universal serial bus (USB) memory, flash memory, etc.

[0123] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A failure analysis method for a storage structure, characterized in that: include: Acquire multiple test structures of each chip in a wafer to be analyzed, wafer test data of each test structure, and wafer test data of each hierarchical structure in each test structure; Displaying and processing wafer test data of a test structure to obtain a test structure data graph, wherein the test structure data graph corresponds to a test structure; Compare the multiple test structure data graphs with the yield data graph of the wafer to be analyzed one by one, and determine whether the test structure corresponding to the test structure data graph has an abnormality; When it is determined that the test structure corresponding to the test structure data graph has an abnormality, obtaining wafer test data of a hierarchical structure in the test structure according to the type of the test structure having the abnormality; Displaying and processing wafer test data of the hierarchical structure in the test structure to obtain a hierarchical structure data graph, wherein the hierarchical structure data graph corresponds to a hierarchical structure in the test structure; Compare the hierarchical structure data graphs with the yield data graphs one by one to determine whether there is an abnormality in the hierarchical structure corresponding to the hierarchical structure data graphs; When there is an abnormality in the hierarchical structure corresponding to the hierarchical structure data graph, defect scanning data involved in the abnormal hierarchical structure is obtained to analyze the failure cause of the failure position in the yield data graph.

2. The failure analysis method of the storage structure according to claim 1, characterized in that: Also includes: Setting display processing rules; in the step of performing display processing, performing display processing based on the display processing rules.

3. The failure analysis method of the storage structure according to claim 2, characterized in that: The steps to set up display processing rules include: According to wafer-level test results of probe contact of multiple test structures of the same type, obtaining wafer test data of each of the test structures; According to wafer test data of a plurality of the test structures of the same type, a threshold order of magnitude of wafer test data of the test structure is obtained; The color rendering rule is set according to the threshold order of magnitude of the wafer test data of the test structure.

4. The failure analysis method of a storage structure according to claim 1, characterized in that: Also includes: Get the yield data graph.

5. The failure analysis method of the storage structure according to claim 4, characterized in that: The steps to obtain the yield data map include: Performing a probe contact wafer-level test on the wafer to be analyzed; A yield data graph is obtained according to the result of the wafer-level test of the probe contact type.

6. The failure analysis method of a storage structure according to claim 1, characterized in that: The steps of display processing include: According to the wafer test data, an initial data graph is obtained; The initial data graphs of the same structure are overlaid to obtain a structure data graph, where the structure data graph is the test structure data graph or the hierarchical structure data graph.

7. The failure analysis method of a storage structure according to claim 1, characterized in that: The comparison step comprises: Comparing the structure data graph with the yield data graph respectively, the structure data graph being one of a test structure data graph and a hierarchical structure data graph; When the failure positions in the structure data graph and the yield data graph are consistent, it is determined that an abnormality exists in the structure corresponding to the structure data graph.

8. The failure analysis method of a storage structure according to claim 1, characterized in that: The steps to analyze the failure causes of failure locations in the yield data graph include: When the defect scanning data involved in the abnormal hierarchical structure has an abnormal defect, it is determined that the abnormal hierarchical structure is the failure cause of the failure position; When the defect scanning data involved in the abnormal hierarchical structure does not have abnormal defects, physical fault analysis is performed.

9. The failure analysis method of a storage structure according to claim 1, characterized in that: Also includes: The hierarchical structure data graph is compared with the yield data graph one by one, and when it is determined that there is no abnormality in the hierarchical structure corresponding to the hierarchical structure data graph, a physical fault analysis is performed.

10. The failure analysis method of a storage structure according to claim 8 or 9, characterized in that: The steps of the physical fault analysis include: Slice the test structure with the exception to obtain the slice structure; A characterization test is performed on the slice structure to analyze whether there is an abnormality in the hierarchical structure of the abnormal test structure.

11. The failure analysis method of a storage structure according to claim 1, characterized in that: Also includes: Before obtaining multiple test structures of each chip in a wafer to be analyzed, wafer test data of each test structure, and wafer test data of each hierarchical structure in each test structure, the test structures in the wafer to be analyzed are classified.

12. A failure analysis device for a storage structure, characterized in that: include: An acquisition module, adapted to acquire multiple test structures of each chip in a wafer to be analyzed, wafer test data of each test structure, and wafer test data of each hierarchical structure in each test structure; A storage module, adapted to pre-store the yield data graph of the wafer to be analyzed; A first detection module is adapted to display and process wafer test data of a test structure to obtain a test structure data graph, wherein the test structure data graph corresponds to a test structure; Compare the multiple test structure data graphs with the yield data graph of the wafer to be analyzed one by one, and determine whether the test structure corresponding to the test structure data graph has an abnormality; When it is determined that the test structure corresponding to the test structure data graph has an abnormality, obtaining wafer test data of a hierarchical structure in the test structure according to the type of the test structure having the abnormality; A second detection module is adapted to display and process wafer test data of the hierarchical structure in the test structure to obtain a hierarchical structure data graph, wherein the hierarchical structure data graph corresponds to a hierarchical structure in the test structure; Compare the hierarchical structure data graphs with the yield data graphs one by one to determine whether there is an abnormality in the hierarchical structure corresponding to the hierarchical structure data graphs; When there is an abnormality in the hierarchical structure corresponding to the hierarchical structure data graph, defect scanning data involved in the abnormal hierarchical structure is obtained to analyze the failure cause of the failure position in the yield data graph.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: The computer program is executed by a processor to implement the steps of the method according to any one of claims 1 to 11.

14. A terminal comprising a storage structure and a processor, wherein the storage structure stores computer instructions that can be executed on the processor, characterized in that: When the processor runs the computer instructions, the steps of the method according to any one of claims 1 to 11 are performed.

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