Chip packaging structure, preparation method thereof and electronic equipment

Abstract

The embodiment of the invention discloses a chip packaging structure, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. The chip packaging structure comprises a packaging substrate, a first component, a second component and an elevating assembly. The package substrate has a first surface and a second surface. The first component is connected to the first surface. The second component and the elevated assembly are connected to the second surface. The elevating assembly comprises a fixing layer and a plurality of conductive columns, and the conductive columns extend in the direction perpendicular to the second surface. The fixing layer surrounds part of the side surfaces of the conductive columns to limit the displacement of the conductive columns. The surface of one side, close to the packaging substrate, of each conductive column is connected with the second surface. The fixing layer fixes the plurality of conductive posts such that the elevated assembly can be used as a single part. In the process of connecting the conductive columns with the packaging substrate, the plurality of conductive columns can be connected to the second surface at the same time, the plurality of conductive columns do not need to be punched one by one, and the yield of the chip packaging structure can be improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a chip packaging structure and a preparation method thereof, and an electronic device. Background Art

[0002] With the development of packaging technology, the demand for miniaturization of chip packaging structure is increasing, and chip packaging technology is gradually shifting from single-sided packaging to dual-sided packaging (DSM). Double-sided packaging means that chips are mounted on two opposite surfaces of the packaging substrate. This means that double-sided packaging can carry more chips and realize more functions.

[0003] However, the chip is arranged on two surfaces of the packaging substrate at the same time, which increases the difficulty of leading out the I / O terminal on the packaging substrate and reduces the yield rate of the chip packaging structure. Summary of the invention

[0004] The embodiments of the present application provide a chip packaging structure and a preparation method thereof, and an electronic device, which are used to improve the yield of the chip packaging structure.

[0005] In order to achieve the above purpose, the embodiment of the present application adopts the following technical solution:

[0006] In a first aspect, a chip packaging structure is provided, which includes a packaging substrate, a first component, a second component and an elevated component. The packaging substrate has a first surface and a second surface opposite to each other. The first component is connected to the first surface. The second component and the elevated component are connected to the second surface. The elevated component includes a fixed layer and a plurality of conductive columns, and the conductive columns extend in a direction perpendicular to the second surface. The fixed layer surrounds part of the side surface of each conductive column to limit the displacement of the conductive column. The material of the fixed layer includes liquid crystal polymer or inorganic material. A side surface of the conductive column close to the packaging substrate is connected to the second surface. The distance between the side surface of the conductive column away from the packaging substrate and the second surface is greater than the distance between the side surface of the second component away from the packaging substrate and the second surface.

[0007] The chip packaging structure provided by some embodiments of the present application can lead out the I / O terminal of the packaging substrate by using the conductive pillars in the elevated component by arranging an elevated component on the second surface of the packaging substrate. This means that the embodiments of the present application can use the point solder between the conductive pillars and the packaging substrate to replace the solder balls, and use the conductive pillars to replace the elevated board, thereby eliminating the problems caused by the solder balls and the elevated board, improving the yield of the chip packaging structure, and making the elevated component in the embodiments of the present application applicable to both scenarios with a large elevation and scenarios with a small ball spacing (for example, a ball spacing less than 0.35 mm).

[0008] Moreover, the embodiment of the present application provides a fixing layer, and uses the fixing layer to surround part of the side surface of each conductive column to fix each conductive column, so that the elevated component composed of the fixing layer and multiple conductive columns can be used as an independent module. In this way, in the process of connecting the conductive column to the packaging substrate, the elevated component can be operated as a single part, and then the multiple conductive columns in the elevated component can be welded to the packaging substrate at one time, improving the phenomenon of the conductive column tilting, falling, bending, etc. caused by the one-by-one punching of the conductive column, avoiding damage to the conductive column, improving the yield and electrical performance of the chip packaging structure, and improving the welding yield between the chip packaging structure and the circuit board.

[0009] In addition, the fixed layer is made of liquid crystal polymer or inorganic material, which has low cost, thus avoiding a significant increase in the manufacturing cost of the chip packaging structure.

[0010] In a possible implementation of the first aspect, there are multiple elevating components, and the multiple elevating components are located on at least two sides of the second component. In this way, while the I / O terminals of the package substrate are led out by using different elevating components, a relatively balanced and stable support can be formed for the package substrate, thereby improving the structural stability between the chip package structure and the circuit board.

[0011] In a possible implementation of the first aspect, there are multiple fixed layers, and the multiple fixed layers are stacked at intervals in a direction perpendicular to the second surface. This is conducive to increasing the stability or consistency between the conductive pillars, improving the structural stability of the elevated component, and further improving the connection yield between the elevated component and the packaging substrate.

[0012] In a possible implementation of the first aspect, there is a gap between the fixed layer and the second surface of the packaging substrate. In this way, the surface of the conductive column close to the packaging substrate can be exposed, which facilitates welding between the conductive column and the packaging substrate. Moreover, when the second surface of the packaging substrate is plastic-sealed, it can be ensured that the plastic sealing material can be filled in the gap between the fixed layer and the second surface, thereby improving the yield of the chip packaging structure.

[0013] In a possible implementation of the first aspect, the distance between the side surface of the conductive column away from the packaging substrate and the second surface is greater than the distance between the side surface of the fixed layer away from the packaging substrate and the second surface. In this way, the side surface of the conductive column away from the packaging substrate can be in a bare state, which is convenient for welding between the conductive column and the circuit board. In a possible implementation of the first aspect, the chip packaging structure also includes: a first packaging layer. The first packaging layer is connected to the second surface, at least fills the gap between two adjacent conductive columns, and surrounds the side of each conductive column. The second packaging layer also wraps the fixed layer. The first packaging layer can not only provide physical protection for the second component and the elevated component, but also fix the second component and the elevated component on the packaging substrate, improve the structural stability between the second component and the packaging substrate, and improve the structural stability between the elevated component and the packaging substrate, which is beneficial to improve the quality and yield of the chip packaging structure.

[0014] In a possible implementation of the first aspect, the material of the second encapsulation layer is different from the material of the fixed layer. For example, the material of the second encapsulation layer is different from the material of the fixed layer. For another example, the material of the second encapsulation layer is the same as the material of the fixed layer, and each has a different filling material.

[0015] In a second aspect, a chip packaging structure is provided, which includes a packaging substrate, a first component, a second component, an elevated component and a first packaging layer. The packaging substrate has a first surface and a second surface opposite to each other. The first component is connected to the first surface. The second component, the elevated component and the first packaging layer are connected to the second surface. Among them, the elevated component includes a fixed layer and a plurality of conductive columns, and the conductive columns extend in a direction perpendicular to the second surface. The fixed layer surrounds part of the side surface of each conductive column to limit the displacement of the conductive column. The distance between the side surface of the conductive column away from the packaging substrate and the second surface is greater than the distance between the side surface of the second component away from the packaging substrate and the second surface. The first packaging layer fills at least in the gap between two adjacent conductive columns and surrounds each conductive column. The first packaging layer also wraps the fixed layer.

[0016] The chip packaging structure provided by some embodiments of the present application can lead out the I / O terminal of the packaging substrate by using the conductive pillars in the elevated component by arranging an elevated component on the second surface of the packaging substrate. This means that the embodiments of the present application can use the point solder between the conductive pillars and the packaging substrate to replace the solder balls, and use the conductive pillars to replace the elevated board, thereby eliminating the problems caused by the solder balls and the elevated board, improving the yield of the chip packaging structure, and making the elevated component in the embodiments of the present application applicable to both scenarios with a large elevation and scenarios with a small ball spacing (for example, a ball spacing less than 0.35 mm).

[0017] Moreover, the embodiment of the present application provides a fixing layer, and uses the fixing layer to surround part of the side surface of each conductive column to fix each conductive column, so that the elevated component composed of the fixing layer and multiple conductive columns can be used as an independent module. In this way, in the process of connecting the conductive column to the packaging substrate, the elevated component can be operated as a single part, and then the multiple conductive columns in the elevated component can be welded to the packaging substrate at one time, improving the phenomenon of the conductive column tilting, falling, bending, etc. caused by the one-by-one punching of the conductive column, avoiding damage to the conductive column, improving the yield and electrical performance of the chip packaging structure, and improving the welding yield between the chip packaging structure and the circuit board.

[0018] In addition, by providing the first packaging layer, the structural stability between the elevated component and the packaging substrate can be improved, thereby improving the reliability of the chip packaging structure.

[0019] In a possible implementation of the second aspect, there are multiple elevating components, and the multiple elevating components are located on at least two sides of the second component. In this way, while the I / O terminals of the package substrate are led out by using different elevating components, a relatively balanced and stable support can be formed for the package substrate, thereby improving the structural stability between the chip package structure and the circuit board.

[0020] In a possible implementation of the second aspect, there are multiple fixed layers, and the multiple fixed layers are stacked at intervals in a direction perpendicular to the second surface. This is conducive to increasing the stability or consistency between the conductive pillars, improving the structural stability of the elevated component, and further improving the connection yield between the elevated component and the packaging substrate.

[0021] In a possible implementation of the second aspect, there is a gap between the fixed layer and the second surface of the packaging substrate. In this way, the surface of the conductive column close to the packaging substrate can be exposed, which facilitates welding between the conductive column and the packaging substrate. Moreover, when the second surface of the packaging substrate is plastic-sealed, it can be ensured that the plastic sealing material can be filled in the gap between the fixed layer and the second surface, thereby improving the yield of the chip packaging structure.

[0022] In a possible implementation of the second aspect, the distance between the side surface of the conductive column away from the packaging substrate and the second surface is greater than the distance between the side surface of the fixed layer away from the packaging substrate and the second surface. In this way, the side surface of the conductive column away from the packaging substrate can be exposed, which facilitates welding between the conductive column and the circuit board.

[0023] In a possible implementation of the second aspect, the material of the fixed layer includes a liquid crystal polymer or a resin material. The material of the fixed layer includes an insulating material, which can avoid short circuits between different conductive pillars.

[0024] In a third aspect, a method for preparing a transistor is provided, the method comprising: providing a package body; the package body comprises a package substrate, a first component and a second component, the package substrate has a first surface and a second surface opposite to each other, the first component is connected to the first surface, and the second component is connected to the second surface. Forming an elevated component; the elevated component comprises a fixed layer and a plurality of conductive columns, the conductive columns extend in a direction perpendicular to the second surface; the fixed layer surrounds part of the side surface of each conductive column to limit the displacement of the conductive column. Connect each conductive column in the elevated component to the second surface; the distance between the side surface of the conductive column away from the package substrate and the second surface is greater than the distance between the side surface of the second component away from the package substrate and the second surface.

[0025] The preparation method provided in some embodiments of the present application forms an elevated component by connecting a conductive column and a fixed layer together. The fixed layer can be used to fix each conductive column, so that the elevated component composed of the fixed layer and multiple conductive columns acts as an independent module. In the process of connecting the conductive column to the second surface of the packaging substrate, the elevated component can be operated as a single part, and multiple conductive columns in the elevated component can be synchronously connected to the second surface, thereby improving the phenomenon of tilting, falling, bending, etc. of the conductive column caused by punching the conductive column one by one, avoiding damage to the conductive column, improving the yield of the chip packaging structure, and improving the welding yield between the chip packaging structure and the circuit board.

[0026] In a possible implementation of the third aspect, forming an elevated assembly includes: providing a plurality of conductive posts; arranging the plurality of conductive posts at intervals, each conductive post extending in the same direction; and forming a fixing layer surrounding a portion of a side surface of each conductive post.

[0027] In a possible implementation manner of the third aspect, the preparation method further includes: forming a first encapsulation layer on the second surface. The first encapsulation layer at least fills the gap between two adjacent conductive pillars and surrounds the side of each conductive pillar. The first encapsulation layer also wraps the fixed layer.

[0028] In a fourth aspect, an electronic device is provided, the electronic device comprising: a circuit board, and a chip packaging structure electrically connected to the circuit board. The chip packaging structure comprises the chip packaging structure as described in any one of the embodiments of the first aspect or the second aspect.

[0029] The technical effects brought about by the fourth aspect can refer to the technical effects brought about by the different design methods in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A structural diagram of an electronic device provided in an embodiment of the present application;

[0031] Figure 2A partial structural diagram of an electronic device provided in an embodiment of the present application;

[0032] Figure 3 A partial structural diagram of another electronic device provided in an embodiment of the present application;

[0033] Figure 4 A partial structural diagram of another electronic device provided in an embodiment of the present application;

[0034] Figure 5 A structural diagram of a chip packaging structure provided in an embodiment of the present application;

[0035] Figure 6 A bottom view of a chip packaging structure provided in an embodiment of the present application;

[0036] Figure 7 A bottom view of another chip packaging structure provided in an embodiment of the present application;

[0037] Figure 8 A structural diagram of another chip packaging structure provided in an embodiment of the present application;

[0038] Fig. 9 A structural diagram of another chip packaging structure provided in an embodiment of the present application;

[0039] Fig.10 A structural diagram of another chip packaging structure provided in an embodiment of the present application;

[0040] Fig.11 A structural diagram of another chip packaging structure provided in an embodiment of the present application;

[0041] Fig.12 A structural diagram of another chip packaging structure provided in an embodiment of the present application;

[0042] Fig.13 A partial structural diagram of another electronic device provided in an embodiment of the present application;

[0043] Fig.14 A flowchart of a method for preparing a chip packaging structure provided in an embodiment of the present application;

[0044] Fig.15 A structural diagram corresponding to each step in a method for preparing a chip packaging structure provided in an embodiment of the present application;

[0045] Fig.16 A structural diagram corresponding to each step in another method for preparing a chip packaging structure provided in an embodiment of the present application;

[0046] Fig.17A structural diagram corresponding to each step in a method for preparing another chip packaging structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] The following will describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0048] Among them, in the description of the embodiments of the present application, unless otherwise specified, "multiple" refers to two or more than two. "At least one item" or similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one item of a, b and c can be represented by: a, b, c, ab, ac, bc or abc, where a, b, c can be single or multiple. "a and / or b" includes the following three combinations: only a, only b, and a combination of a and b.

[0049] In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, the words "first", "second" and the like are used to distinguish the same items or similar items with substantially the same functions and effects. Those skilled in the art will understand that the words "first", "second" and the like do not limit the quantity and execution order, and the words "first", "second" and the like do not necessarily limit the differences. At the same time, in the embodiments of the present application, the words "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or design solutions. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete manner for ease of understanding.

[0050] When describing some embodiments, the expression "connected" and its derivatives are used. The term "connected" should be understood in a broad sense. For example, "connected" can be fixedly connected, detachably connected, or integrated; it can be directly connected or indirectly connected through an intermediate medium. In addition, the use of "based on" means openness and inclusiveness, because the process, step, calculation or other action "based on" one or more of the conditions or values ​​can be based on additional conditions or values ​​beyond the described values ​​in practice.

[0051] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within the acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.

[0052] In the embodiments of the present application, "upper" and "lower" are not limited to being defined relative to the orientation of the schematic placement of the components in the drawings. It should be understood that these directional terms can be relative concepts, which are used for description and clarification relative to the components, and can change accordingly according to the change in the orientation of the components in the drawings. In the drawings, for the sake of clarity, the thickness of the layers and regions is exaggerated, and the dimensional ratio relationship between the parts in the drawings does not reflect the actual dimensional ratio relationship. Therefore, changes in the shape relative to the drawings due to, for example, manufacturing technology and / or tolerances can be envisioned. Therefore, the exemplary embodiments should not be interpreted as being limited to the shape of the areas shown in the present application, but include shape deviations caused by, for example, manufacturing. For example, an etched area shown as a rectangle will generally have curved features. Therefore, the areas shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the areas of the device, and are not intended to limit the scope of the exemplary embodiments.

[0053] In addition, the architecture and scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of the architecture and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0054] The embodiment of the present application provides an electronic device. The electronic device may be a mobile phone, a tablet computer (pad), a television, a desktop computer, a laptop computer, a handheld computer, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a cellular phone, a personal digital assistant (PDA), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a smart wearable device (e.g., a smart watch, a smart bracelet), an in-vehicle device, a smart home device and / or a smart city device, etc. The embodiment of the present application does not impose any special restrictions on the specific type of the electronic device.

[0055] Figure 1 The following is a schematic diagram of the architecture of an electronic device provided in an embodiment of the present application. Figure 1 As shown, the electronic device 1000 includes: a memory 100, a processor 200, an input device 300, an output device 400 and other components. Those skilled in the art can understand that Figure 1 The structure of the electronic device shown in the figure does not constitute a limitation on the electronic device 1000. The electronic device 1000 may include, for example Figure 1 More or fewer components may be shown, or they may be combined as shown. Figure 1 Some of the components shown may be combined with Figure 1 The components shown are arranged differently.

[0056] The memory 100 is used to store software programs and modules. The memory 100 mainly includes a program storage area and a data storage area, wherein the program storage area can store an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the electronic device (such as audio data, image data, phone book, etc.), etc. In addition, the memory 100 includes an external memory 110 and an internal memory 120. The data stored in the external memory 110 and the internal memory 120 can be transmitted to each other. The external memory 110 includes, for example, a hard disk, a USB flash drive, a floppy disk, etc. The internal memory 120 includes, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a read-only memory, etc.

[0057] The processor 200 is the control center of the electronic device 1000. It uses various interfaces and lines to connect various parts of the entire electronic device 1000. By running or executing software programs and / or modules stored in the memory 100, and calling data stored in the memory 100, it performs various functions of the electronic device 1000 and processes data, thereby monitoring the electronic device 1000 as a whole. Optionally, the processor 200 may include one or more processing units. For example, the processor 200 may include a central processing unit (CPU), an artificial intelligence (AI) processor, a digital signal processor (DSP), and a neural network processor, and may also be other specific integrated circuits (application specific integrated circuits, ASICs), etc. Figure 1 In the example, the processor 200 is a CPU, and the CPU may include an operator 210 and a controller 220. The operator 210 obtains data stored in the internal memory 120, processes the data stored in the internal memory 120, and generally sends the processed result back to the internal memory 120. The controller 220 may control the operator 210 to process the data, and the controller 220 may also control the external memory 110 and the internal memory 120 to store data or read data. The memory 100 may store data generated by the processor 200.

[0058] The input device 300 is used to receive input digital or character information, and to generate key signal input related to the user settings and function control of the electronic device 1000. Exemplarily, the input device 300 may include a touch screen and other input devices. The touch screen, also known as a touch panel, can collect the user's touch operation on or near the touch screen (such as the user's operation on or near the touch screen using any suitable object or accessory such as a finger, a stylus, etc.), and drive the corresponding connection device according to a pre-set program. Optionally, the touch screen may include two parts: a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch direction, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into the touch point coordinates, and then sends it to the processor 200, and can receive and execute the command sent by the processor 200. In addition, the touch screen can be implemented using multiple types such as resistive, capacitive, infrared and surface acoustic waves. Other input devices may include but are not limited to one or more of a physical keyboard, function keys (such as a volume control key, a power switch key, etc.), a trackball, a mouse, a joystick, etc. The controller 220 in the processor 200 can also control the input device 300 to receive input signals or not receive input signals. In addition, the input digital or character information received by the input device 300, and the key signal input related to the user settings and function control of the electronic device can be stored in the internal memory 120.

[0059] The output device 400 is used to output a signal corresponding to the data input by the input device 300 and stored in the internal memory 120. For example, the output device 400 outputs a sound signal or a video signal. The controller 220 in the processor 200 can also control the output device 400 to output a signal or not output a signal.

[0060] It should be noted that Figure 1 The thick arrows in the figure are used to indicate data transmission, and the direction of the thick arrows indicates the direction of data transmission. For example, the one-way arrow between the input device 300 and the internal memory 120 indicates that the data received by the input device 300 is transmitted to the internal memory 120. For another example, the two-way arrow between the operator 210 and the internal memory 120 indicates that the data stored in the internal memory 120 can be transmitted to the operator 210, and the data processed by the operator 210 can be transmitted to the internal memory 120. Figure 1 The thin arrows in the figure represent components that can be controlled by the controller 220. For example, the controller 220 can control the external memory 110, the internal memory 120, the operator 210, the input device 300, the output device 400, and the like.

[0061] Alternatively, if Figure 1The electronic device 1000 shown may also include various sensors, such as a gyroscope sensor, a hygrometer sensor, an infrared sensor, a magnetometer sensor, etc., which are not described in detail here. Optionally, the electronic device 1000 may also include a wireless fidelity (WiFi) module, a Bluetooth module, etc., which are not described in detail here.

[0062] Figure 2 , Figure 3 and Figure 4 1 and 2 respectively illustrate a partial structure of the electronic device 1000. Figure 2 to Figure 4 As shown, the electronic device 1000 may further include a circuit board 500 and a chip packaging structure 600 . The chip packaging structure 600 is disposed on the circuit board 500 and is electrically connected to the circuit board 500 .

[0063] In some examples, such as Figure 2 to Figure 4 As shown, the chip packaging structure 600 includes a packaging substrate 1 , and the packaging substrate 1 has a first surface 1A and a second surface 1B opposite to each other.

[0064] Exemplarily, the package substrate 1 includes at least one dielectric layer and multiple metal layers, the dielectric layers and the metal layers are alternately stacked, and the metal layers can also be called rewiring layers. A through hole is provided in the dielectric layer, and two metal layers located on opposite sides of the dielectric layer are electrically connected through the through hole.

[0065] Optionally, the packaging substrate 1 includes but is not limited to an organic substrate, a ceramic substrate, a silicon substrate, etc.

[0066] The chip packaging structure 600 also includes components, which include chips and / or passive components. That is, the components may be only chips, only passive components, or both chips and passive components.

[0067] In conjunction with the accompanying drawings, the embodiments of the present application are schematically described below using a chip as an example of a component.

[0068] like Figure 2 to Figure 4 As shown, the chip package structure 600 further includes a chip 2. The number of the chip 2 is at least one. For example, the number of the chip 2 can be one, two, three, four or even more.

[0069] In some embodiments of the present application, the chip 2 may be a wafer with a functional layer formed thereon, or may be a bare chip (die) obtained by cutting a wafer with a functional layer formed thereon, and a bare chip may also be referred to as a grain or particle. In some cases, the chip 2 may also be a chip obtained by packaging a bare chip. Based on this, in some embodiments, the multiple chips 2 in the above-mentioned chip packaging structure 600 may all be bare chips or chips obtained by packaging bare chips. In other embodiments, the multiple chips 2 in the above-mentioned chip packaging structure 600 may all be wafers. In yet other embodiments, the multiple chips 2 in the above-mentioned chip packaging structure 600 may be some chips 2 as wafers, some chips 2 as bare chips and / or chips obtained by packaging bare chips.

[0070] For example, the above functional layer enables the chip 2 to realize a storage function, and accordingly, the chip 2 is a memory chip. For another example, the above functional layer enables the chip 2 to realize a logic calculation function, and accordingly, the chip 2 is a processor chip.

[0071] Figure 2 The chip packaging structure 600 shown in FIG. 1 is packaged using a single-sided packaging technology. Figure 3 and Figure 4 The chip packaging structure 600 shown in FIG. 1 is packaged using a double-sided packaging technology. The chip 2 is arranged in different ways in different packaging technologies, which are schematically described below in conjunction with the accompanying drawings.

[0072] exist Figure 2 In the structure shown, the chip 2 is located on the first surface 1A, and the circuit board 500 is located on the second surface 1B.

[0073] The chip packaging structure 600, for example, further includes a first connector 3 disposed between the chip 2 and the first surface 1A, and the chip 2 is connected (or welded) to the packaging substrate 1 through the first connector 3. The first connector 3 is, for example, a controlled collapse chip connection bump (C4 bump). The chip packaging structure 600 further includes a second connector 4 disposed between the circuit board 500 and the second surface 1B, and the circuit board 500 is connected (or welded) to the packaging substrate 1 through the second connector 4. The second connector 4 can be, for example, a solder ball (also called a tin ball).

[0074] In this way, the chip 2 can be electrically connected to the circuit board 500 through the first connecting member 3, the packaging substrate 1, and the second connecting member 4 in sequence.

[0075] The number of the chip 2 is at least one. Figure 2Two chips 2 are shown, and the two chips 2 are arranged side by side. Of course, when there are multiple chips 2, the multiple chips 2 can be stacked in sequence along a direction perpendicular to the first surface 1A.

[0076] like Figure 3 and Figure 4 In the structure shown, the components include a first component and a second component. For example, the first component includes a first chip 21 and the second component includes a second chip 22. The first chip 21 is located on the first surface 1A, and the second chip 22 is located on the second surface 1B.

[0077] The connection method between the first chip 21 and the first surface 1A, and the connection method between the second chip 22 and the second surface 1B are, for example, the same as the connection method between the chip 2 and the packaging substrate 1 in the above-mentioned single-sided packaging technology, and will not be repeated here.

[0078] Furthermore, the I / O terminals on the second surface 1B of the package substrate 1 are electrically connected to the circuit board 500. In this way, the first chip 21 and the second chip 22 can be electrically connected to the circuit board 500 through the package substrate 1 and the I / O terminals on the second surface 1B thereof.

[0079] The number of the first chip 21 is at least one. For example, the number of the first chip 21 may be one, two, three, four or even more. Figure 3 Two first chips 21 are shown schematically, and the two first chips 21 are arranged side by side. Figure 4 Three first chips 21 are schematically shown, among which some of the first chips 21 are arranged side by side, and some of the first chips 21 are stacked in sequence along a direction perpendicular to the first surface 1A.

[0080] The number of the second chips 22 is at least one. For example, the number of the second chips 22 may be one, two, three, four or even more. Figure 3 One second chip 22 is shown. When there are multiple second chips 22, the multiple second chips 22 can be arranged side by side or stacked in sequence along a direction perpendicular to the second surface 1B.

[0081] Compared with the above-mentioned single-sided packaging technology, the double-sided packaging technology can increase the area of ​​the packaging substrate 1 that can be connected to the chip, so that the chip packaging structure 600 can carry more chips and realize more functions.

[0082] It is understandable that in the double-sided packaging technology, the spacing between the packaging substrate 1 and the circuit board 500 increases due to the arrangement of the second chip 22. Therefore, the packaging substrate 1 needs to be elevated to facilitate the I / O terminals on the second surface 1B of the packaging substrate 1.

[0083] In a possible implementation, solder balls are used to elevate the package substrate 1 to lead out the I / O terminals on the second surface 1B of the package substrate 1. That is, solder balls are used to electrically connect the I / O terminals on the second surface 1B of the package substrate 1 and the circuit board 500. However, when the thickness of the device (including but not limited to the second chip 22, passive devices, etc.) arranged on the second surface 1B (that is, the size of the device in a direction perpendicular to the second surface 1B) is large, it is necessary to increase the ball diameter (ball diemater) of the solder ball. However, due to the ball pitch between different solder balls, if the ball diameter of the solder ball is relatively large, short circuits between different solder balls will easily occur, thereby reducing the yield of the chip packaging structure.

[0084] Therefore, in the embodiments of the present application, Figure 3 and Figure 4 A method of raising the packaging substrate 1 is schematically shown respectively.

[0085] exist Figure 3 In the embodiment, the chip packaging structure 600 further includes a frame board 5 disposed on the second surface 1B of the packaging substrate 1. A plurality of solder balls are disposed on the upper surface of the frame board 5, and the frame board 5 is electrically connected to the second surface 1B of the packaging substrate 1 through the plurality of solder balls. A plurality of solder balls are disposed on the lower surface of the frame board 5, and the frame board 5 is electrically connected to the circuit board 500 through the plurality of solder balls.

[0086] The chip packaging structure 600 is elevated by using the elevated plate 5 and solder balls, which can reduce the ball diameters of the solder balls arranged on the upper and lower surfaces of the elevated plate 5, reduce the risk of short circuits between different solder balls, and help improve the yield of the chip packaging structure.

[0087] However, as the thickness of the device disposed on the second surface 1B increases, the diameter of the solder balls still needs to be increased, which means that short circuits between different solder balls are still likely to occur. Limited by the diameter of the solder balls and the ball spacing, when the height is large (for example, the height is greater than 0.5 mm) or the ball spacing is small (for example, the ball spacing is less than 0.35 mm), the process difficulty will be greatly increased, limiting the scenarios where the height plate 5 and the solder balls are used for heightening.

[0088] Moreover, when the solder ball is large in size, it is easy to block the cleaning process (deflux) of the flux, resulting in incomplete water washing.

[0089] In addition, when the elevated board 5 and the solder balls are molded, on the one hand, the solder balls between the elevated board 5 and the packaging substrate 1 are prone to tin overflow, causing failure of the chip packaging structure 600; on the other hand, the elevated board 5 or the solder balls are prone to affect the molding flow, resulting in voids or filling problems.

[0090] exist Figure 4 In the embodiment, the chip package structure 600 further includes a plurality of conductive pillars 6 disposed between the package substrate 1 and the circuit board 500. One end of the conductive pillar 6 is electrically connected to the second surface 1B of the package substrate 1, for example, by a spot solder; and the other end of the conductive pillar 6 is electrically connected to the circuit board 500, for example, by a spot solder.

[0091] The chip packaging structure 600 is elevated by using the conductive pillars 6, and point solder can be used instead of solder balls, and the conductive pillars 6 can be used instead of the elevated plate 5, thereby eliminating the problems caused by the solder balls and the elevated plate 5, and improving the yield and electrical performance of the chip packaging structure 600. Moreover, the use of the conductive pillars 6 for elevation can be applied to scenarios with a large elevation and scenarios with a ball pitch less than 0.35 mm.

[0092] However, due to the limitation of processing equipment, it is necessary to use surface mount technology (SMT) to place the conductive pillars 6 one by one on the package substrate 1 to complete the welding. In this process, the conductive pillars 6 are prone to tilt, fall down, bend, etc., causing the conductive pillars 6 to be damaged, which will reduce the yield rate of the chip packaging structure 600 and the welding yield rate between the chip packaging structure 600 and the circuit board 500.

[0093] Based on this, the embodiment of the present application also provides a method for elevating the packaging substrate 1. Figure 5 As shown, the chip packaging structure 600 further includes a stand-up component 7 . The stand-up component 7 is connected to the second surface 1B of the packaging substrate 1 .

[0094] Continue reading Figure 5 The elevated assembly 7 includes a plurality of conductive pillars 72. The conductive pillars 72 are made of metal material, such as copper. In this case, the conductive pillars 72 can also be called copper pillars.

[0095] Among the above-mentioned multiple conductive pillars 72, the extension direction of each conductive pillar 72 is the same, and the extension direction of each conductive pillar 72 is perpendicular to the second surface 1B. Among them, the side surface of the conductive pillar 72 close to the packaging substrate 1 is connected to the second surface 1B, for example, the conductive pillar 72 and the second surface 1B of the packaging substrate 1 are electrically connected through point solder.

[0096] Further, the distance between the side surface of the conductive column 72 away from the package substrate 1 and the second surface 1B is greater than the distance between the side surface of the second chip 22 away from the package substrate 1 and the second surface 1B. That is, relative to the second surface 1B, the side surface of the conductive column 72 away from the package substrate 1 protrudes from the side surface of the second chip 22 away from the package substrate 1. In the case where the thickness of the passive component connected to the second surface 1B is greater than the thickness of the second chip 22, the distance between the side surface of the conductive column 72 away from the package substrate 1 and the second surface 1B is greater than the distance between the side surface of the passive component away from the package substrate 1 and the second surface 1B. That is, relative to the second surface 1B, the side surface of the conductive column 72 away from the package substrate 1 protrudes from the side surface of the passive component away from the package substrate 1. This makes it easy to electrically connect the conductive column 72 to the circuit board 500.

[0097] Optionally, in the above-mentioned elevated component 7, the arrangement of the multiple conductive columns 72 can be set according to actual product requirements, and the embodiment of the present application is not limited to this.

[0098] Combination Figure 5 , Figure 6 and Figure 7 The elevated component 7 further includes a fixed layer 71. The material of the fixed layer 71 includes an insulating material. Optionally, the material of the fixed layer 71 includes but is not limited to a liquid crystal polymer (LCP), an inorganic material (such as a ceramic material), and the like.

[0099] The fixing layer 71 is, for example, in the form of a thin film and extends in a direction parallel to the second surface 1B. In a direction perpendicular to the second surface 1B, the thickness of the fixing layer 71 is smaller than the height of the conductive pillar 72 .

[0100] The fixing layer 71 surrounds part of the side surface of each conductive column 72. It can also be considered that each conductive column 72 passes through the fixing layer 71. The fixing layer 71 only contacts part of the side surface of the conductive column 72 and fixes the conductive column 72, but does not completely contact the side surface of the conductive column 72, nor does it wrap the conductive column 72. Among them, the fixing layer 71 fixes different conductive columns 72 together, and can use itself to limit the displacement of different conductive columns 72, so that the fixing layer 71 and the multiple conductive columns 72 fixed thereto constitute a module.

[0101] Therefore, the chip packaging structure 600 provided in some embodiments of the present application can lead out the I / O terminal of the packaging substrate 1 by using the conductive pillars 72 in the elevated component 7, and electrically connect it to the circuit board 500 by setting the elevated component 7 on the second surface 1B of the packaging substrate 1. This means that the embodiments of the present application can use the point solder between the conductive pillars 72 and the packaging substrate 1 instead of the solder balls, and use the conductive pillars 72 instead of the elevated board, thereby eliminating the problems caused by the solder balls and the elevated board, improving the yield of the chip packaging structure 600, and making the elevated component 7 in the embodiments of the present application applicable to both scenarios with a large elevation and scenarios with a small ball spacing (for example, a ball spacing less than 0.35 mm).

[0102] Moreover, the embodiment of the present application provides a fixing layer 71, and uses the fixing layer 71 to surround part of the side surface of each conductive column 72 to fix each conductive column 72, so that the elevated component 7 composed of the fixing layer 71 and multiple conductive columns 72 can be used as an independent module. In this way, in the process of electrically connecting the conductive column 72 to the packaging substrate 1, the elevated component 7 can be operated as a single part, and then the multiple conductive columns 72 in the elevated component 7 can be welded to the packaging substrate 1 at one time, thereby improving the phenomenon of the conductive column 72 tilting, falling, bending, etc. caused by punching the conductive column 72 one by one, avoiding damage to the conductive column 72, improving the yield rate of the chip packaging structure 600, and improving the welding yield rate between the chip packaging structure 600 and the circuit board 500.

[0103] In addition, the volume of the conductive pillar 72 is relatively small, and the conductive pillar 72 has little effect on water washing, which can avoid the risk of solder balls in design and process. The fixed layer 71 is made of liquid crystal polymer or inorganic materials, which is low in cost. This can avoid a significant increase in the preparation cost of the chip packaging structure 600.

[0104] In some embodiments, the number of the elevated components 7 can be one or more (eg, two, three, four or even more).

[0105] In the case where there is one elevated component 7 , the elevated component 7 is block-shaped and located at one side of the second chip 22 . Alternatively, the elevated component 7 is a hollow frame structure surrounding the second chip 22 .

[0106] Combination Figure 5 , Figure 6 and Figure 7 When there are multiple elevated components 7, the number of conductive posts 72 in different elevated components 7 may be the same or different; the arrangement of the conductive posts 72 in different elevated components 7 may be the same or different.

[0107] In addition, the plurality of elevated components 7 are located on at least two sides of the second component (e.g., the second chip 2 shown in the figure) 2. That is, the plurality of elevated components 7 can be located on two opposite sides, three sides, or around the second chip 22. Different elevated components 7 are arranged at intervals.

[0108] For example, in Figure 6 In the embodiment, the number of the elevated components 7 is two, and the two elevated components 7 are arranged on opposite sides of the second chip 22. Of course, the two elevated components 7 can also be arranged on adjacent two sides of the second chip 22.

[0109] For example, in Figure 7 In the embodiment, the number of the elevated components 7 is five, and the five elevated components 7 are arranged around the periphery of the second chip 22 .

[0110] It is understandable that, when there are multiple elevating components 7, the multiple elevating components 7 can respectively provide support for the package substrate 1. By arranging multiple elevating components 7 on at least two sides of the second component, while using different elevating components 7 to lead out the I / O terminal of the package substrate 1, a more balanced and stable support can be formed for the package substrate 1, thereby improving the structural stability between the chip package structure 600 and the circuit board 500.

[0111] In some embodiments, in the above-mentioned elevated component 7, the number of the fixed layers 71 can be one or more (for example, two, three, four or even more). Figure 5 It is shown that each elevated component 7 includes a fixed layer 71, Figure 8 It is schematically shown that the partial elevated component 7 includes two fixed layers 71.

[0112] Continue reading Figure 8 In the case where there are multiple fixed layers 71, the multiple fixed layers 71 can be stacked at intervals in a direction perpendicular to the second surface 1B. The thicknesses of different fixed layers 71 can be equal or unequal. The orthographic projection areas of different fixed layers 71 on the second surface 1B can be equal or unequal.

[0113] Optionally, each fixing layer 71 surrounds a plurality of conductive posts 72 in the elevated component 7 and fixes the plurality of conductive posts 72 .

[0114] This is beneficial to increasing the stability or consistency between the conductive pillars 72 , improving the structural stability of the elevated component 7 , and further improving the connection yield between the elevated component 7 and the packaging substrate 1 .

[0115] Furthermore, among the above-mentioned multiple fixed layers 71, the spacing between any two adjacent fixed layers 71 can be set according to actual needs. In the case where the second surface 1B of the packaging substrate 1 is plastic-sealed, the spacing between two adjacent fixed layers 71 should ensure that the plastic sealing material can be filled between the two adjacent fixed layers 71 to avoid affecting the yield of the chip packaging structure 600.

[0116] In some embodiments, Fig. 9 and Fig.11 As shown, there is a gap between the fixing layer 71 and the second surface 1B of the package substrate 1. That is, after the package substrate 1 of the elevated component 7 is welded, the fixing layer 71 is not in contact with the second surface 1B of the package substrate 1. On the side of the fixing layer 71 close to the package substrate 1, the conductive column 72 protrudes from the fixing layer 71. The conductive column 72 is close to the side surface of the package substrate 1 and is not wrapped by the fixing layer 71.

[0117] In this way, the surface of the conductive pillar 72 on one side close to the package substrate 1 can be exposed, which facilitates the welding between the conductive pillar 72 and the package substrate 1. Fig.11 As shown, when the second surface 1B of the packaging substrate 1 is plastic-sealed, since the fixing layer 71 has been solidified in advance, it can be ensured that the plastic-sealing material can flow and fill the gap between the fixing layer 71 and the second surface 1B of the packaging substrate 1, thereby improving the yield of the chip packaging structure 600.

[0118] Optionally, the distance between the fixing layer 71 and the second surface 1B of the packaging substrate 1 can be set according to actual needs.

[0119] In some embodiments, Fig. 9 and Fig.13 As shown, the distance between the side surface of the conductive pillar 72 away from the package substrate 1 and the second surface 1B is greater than the distance between the side surface of the fixed layer 71 away from the package substrate 1 and the second surface 1B. That is, on the side of the fixed layer 71 away from the package substrate 1, the conductive pillar 72 protrudes from the fixed layer 71. The side surface of the conductive pillar 72 away from the package substrate 1 is not wrapped by the fixed layer 71.

[0120] like Fig.13 As shown, in this way, the surface of the conductive pillar 72 on one side away from the packaging substrate 1 can be exposed, which facilitates welding between the conductive pillar 72 and the circuit board 500 .

[0121] In some embodiments, Figures 9 to 12As shown, the chip packaging structure 600 further includes: a second packaging layer 8 and / or a first packaging layer 9. That is, the chip packaging structure 600 may include only the second packaging layer 8, or only the first packaging layer 9, or both the second packaging layer 8 and the first packaging layer 9. The second packaging layer 8 is located on the first surface 1A of the packaging substrate 1, and the first packaging layer 9 is located on the second surface 1B of the packaging substrate 1.

[0122] The second packaging layer 8 at least surrounds the first component (for example, the first chip 21 shown in the figure). Fig.10 As shown, when the first chip 21 is laid flat on the package substrate 1, the second package layer 8 can surround the side wall of the first chip 21 to expose the side surface of the first chip 21 away from the package substrate 1. Fig.12 and Fig.13 As shown, when multiple first chips 21 are stacked and electrically connected to the packaging substrate 1 using leads, the second packaging layer 8 surrounds the side walls of the first chip 21 and covers the side surface of the first chip 21 away from the packaging substrate 1.

[0123] In this way, the second packaging layer 8 can be used to package the first component to provide physical protection for the first component, and the first component can be fixed on the packaging substrate 1, thereby improving the structural stability between the first component and the packaging substrate 1 and improving the reliability of the chip packaging structure 600.

[0124] The first packaging layer 9 at least fills the gap between two adjacent conductive pillars 72 and surrounds the side surfaces of each conductive pillar 72. Fig.11 As shown, the first encapsulation layer 9 wraps the side of each conductive column 72. In the direction perpendicular to the second surface 1B, the thickness of the first encapsulation layer 9 is, for example, the same as the height of the conductive column 72. Further, in the direction perpendicular to the second surface 1B, the thickness of the fixed layer 71 is less than the thickness of the first encapsulation layer 9. In the orthographic projection onto the second surface 1B, the area of ​​the fixed layer 71 is less than the area of ​​the first encapsulation layer 9. The first encapsulation layer 9 wraps the fixed layer 71 to cover the side of the fixed layer 71, and the first encapsulation layer 9 is also filled between the fixed layer 71 and the second surface 1B of the encapsulation substrate 1. In the case where the number of fixed layers 71 is multiple, the first encapsulation layer 9 is also filled in the gap between two adjacent fixed layers 71. Among them, the first encapsulation layer 9 exposes the side surface of the conductive column 72 away from the encapsulation substrate 1.

[0125] Alternatively, if Fig. 9 , Fig.12 and Fig.13 As shown, the first packaging layer 9 also surrounds the second component (eg, the second chip 22 shown in the figure) and covers a side surface of the second component (eg, the second chip 22 shown in the figure) away from the packaging substrate 1.

[0126] In this way, the first packaging layer 9 can be used to package the second component and the elevated component 7, which can not only provide physical protection for the second component and the elevated component 7, but also fix the second component and the elevated component 7 on the packaging substrate 1, thereby improving the structural stability between the second component and the packaging substrate 1, and improving the structural stability between the elevated component 7 and the packaging substrate 1, which is beneficial to improving the quality and yield of the chip packaging structure 600.

[0127] Optionally, any one of the second encapsulation layer 8 and the first encapsulation layer 9 can be formed by compression molding, transfer molding, liquid sealing molding, vacuum lamination or spin coating. The material of any one of the second encapsulation layer 8 and the first encapsulation layer 9 includes but is not limited to polyimide, silicone, epoxy resin, etc.

[0128] In some examples, the material of the first encapsulation layer 9 is different from the material of the fixing layer 71. In this case, there is a relatively obvious interface between the first encapsulation layer 9 and the fixing layer 71.

[0129] Optionally, the material of the first encapsulation layer 9 and the material of the fixed layer 71 are different types of materials. For example, the material of the first encapsulation layer 9 is an organic insulating material, and the material of the fixed layer 71 is an inorganic insulating material. Alternatively, the material of the first encapsulation layer 9 is an organic insulating material, and the material of the fixed layer 71 is LCP.

[0130] Optionally, the material of the first encapsulation layer 9 and the material of the fixing layer 71 are both resin materials, but the material of the first encapsulation layer 9 and the material of the fixing layer 71 contain different filling materials respectively.

[0131] The embodiment of the present application also provides a method for elevating the packaging substrate 1. Fig. 9 and Fig.11 As shown, the chip packaging structure 600 further includes a raised component 7 and a first packaging layer 9. The raised component 7 and the first packaging layer 9 are both connected to the second surface 1B of the packaging substrate 1.

[0132] The above-mentioned elevated component 7 includes a fixed layer 71 and a plurality of conductive pillars 72. The number and setting positions of the elevated components 7, the number and setting method of the fixed layers 71, the positional relationship between the fixed layers 71 and the second surface 1B of the package substrate 1, the connection method and arrangement method of the conductive pillars 72, and the positional relationship between the side surface of the conductive pillars 72 away from the package substrate 1 and the second surface 1B are the same as the relevant descriptions in some of the above-mentioned embodiments, and will not be repeated here.

[0133] Continue reading Fig. 9 and Fig.11The first encapsulation layer 9 at least fills the gap between two adjacent conductive pillars 72 and surrounds the side surfaces of each conductive pillar 72. Fig.11 As shown, the first encapsulation layer 9 wraps the side of each conductive column 72. In the direction perpendicular to the second surface 1B, the thickness of the first encapsulation layer 9 is, for example, the same as the height of the conductive column 72. Further, in the direction perpendicular to the second surface 1B, the thickness of the fixed layer 71 is less than the thickness of the first encapsulation layer 9. In the orthographic projection onto the second surface 1B, the area of ​​the fixed layer 71 is less than the area of ​​the first encapsulation layer 9. The first encapsulation layer 9 wraps the fixed layer 71 to cover the side of the fixed layer 71, and the first encapsulation layer 9 is also filled between the fixed layer 71 and the second surface 1B of the encapsulation substrate 1. In the case where the number of fixed layers 71 is multiple, the first encapsulation layer 9 is also filled in the gap between two adjacent fixed layers 71. Among them, the first encapsulation layer 9 exposes the side surface of the conductive column 72 away from the encapsulation substrate 1.

[0134] Alternatively, if Fig. 9 , Fig.12 and Fig.13 As shown, the first packaging layer 9 also surrounds the second component (eg, the second chip 22 shown in the figure) and covers a side surface of the second component (eg, the second chip 22 shown in the figure) away from the packaging substrate 1.

[0135] In this way, the chip packaging structure 600 provided in the embodiment of the present application can use the conductive pillars 72 in the elevated component 7 to lead out the I / O terminal of the package substrate 1 and electrically connect it to the circuit board 500. This means that the embodiment of the present application can use the point solder between the conductive pillars 72 and the package substrate 1 instead of the solder balls, and use the conductive pillars 72 instead of the elevated board, so as to eliminate the problems caused by the solder balls and the elevated board, improve the yield of the chip packaging structure 600, and make the elevated component 7 in the embodiment of the present application applicable to both the scene with a large elevation and the scene with a small ball spacing (for example, the ball spacing is less than 0.35mm).

[0136] Moreover, the embodiment of the present application can treat the elevated component 7 composed of the fixed layer 71 and multiple conductive pillars 72 as an independent module. In this way, in the process of electrically connecting the conductive pillars 72 to the packaging substrate 1, the elevated component 7 can be operated as a single part, and then the multiple conductive pillars 72 in the elevated component 7 can be welded to the packaging substrate 1 at one time, thereby improving the tilting, tipping, bending and other phenomena of the conductive pillars 72 caused by punching the conductive pillars 72 one by one, and avoiding damage to the conductive pillars 72. Then, the first packaging layer 9 can be set on the second surface 1B, filling the gap between two adjacent conductive pillars 72, and wrapping the fixed layer 71, so as to improve the structural stability between the elevated component 7 and the packaging substrate 1, which is beneficial to improving the quality and yield of the chip packaging structure 600.

[0137] The fixing layer 71 may be made of a variety of materials, which may be selected according to actual requirements (such as electrical performance, moisture resistance, corrosion resistance, etc.).

[0138] Optionally, the material of the fixing layer 71 includes but is not limited to insulating materials such as liquid crystal polymer, resin material (epoxy), and inorganic material.

[0139] Of course, the material of the fixed layer 71 may also include a metal material or other supporting material. In this case, an insulating material is provided between the supporting material and the conductive pillar 72 .

[0140] Some embodiments of the present application also provide a method for preparing a chip packaging structure, which is used, for example, to prepare a chip packaging structure 600 as described in any of the above embodiments. Fig.14 A flowchart of a method for preparing a chip packaging structure provided in some embodiments of the present application; Fig.15 (a), (b), (c), (d), (e) in Fig.16 (a), (b) and Fig.17 (a) and (b) are structural diagrams corresponding to the steps in the method for preparing a chip packaging structure according to some embodiments. It should be understood that Fig.14 The steps shown are not exclusive, and other steps may be performed before, after or between any of the steps shown. In addition, some of the steps may be performed simultaneously, or may be performed in different steps. Fig.14 Executed in the order shown.

[0141] In some embodiments, Fig.14 As shown, the method for preparing the chip packaging structure includes: S100-S300.

[0142] S100, such as Fig.15 As shown in (a) of the figure, a package is provided. The package includes a package substrate 1, a first component (for example, a first chip 21 in the figure) and a second component (for example, a second chip 22 in the figure), the package substrate 1 has a first surface 1A and a second surface 1B opposite to each other, the first chip 21 is connected to the first surface 1A, and the second chip 22 is connected to the second surface 1B.

[0143] The structure or type of any one of the packaging substrate 1, the first chip 21, and the second chip 22, and the arrangement of the first chip 21 and the second chip 22 are the same as those in some of the above embodiments, and will not be repeated here.

[0144] Exemplarily, the method for forming the above package includes: firstly connecting the first chip 21 to the first surface 1A of the package substrate 1 by using the SMT process; and then connecting the second chip 22 to the second surface 1B of the package substrate 1 by using the SMT process.

[0145] like Fig.15 As shown in (b), in the case where the package body also includes a second packaging layer 8, before the second chip 22 is welded on the second surface 1B, the method for forming the package body also includes: plastic-sealing the first chip 21 to form a second packaging layer 8, the second packaging layer 8 is in contact with the first surface 1A and covers the first chip 21; then grinding the side surface of the second packaging layer 8 away from the packaging substrate 1, flattening the second packaging layer 8 or exposing the side surface of the first chip 21 away from the packaging substrate 1.

[0146] S200, such as Fig.15 As shown in (c) of FIG. 1 , an elevated component 7 is formed. The elevated component 7 includes a fixing layer 71 and a plurality of conductive pillars 72 . The conductive pillars 72 extend in a direction perpendicular to the second surface 1B. The fixing layer 71 surrounds a portion of the side surface of each conductive pillar 72 to limit the displacement of the conductive pillars 72 .

[0147] In some examples, the method of forming the elevated component 7 includes: S210 to S220.

[0148] S210, such as Fig.16 (a) and Fig.17 As shown in (a) of FIG. 1 , a plurality of conductive pillars 72 are provided. The plurality of conductive pillars 72 are arranged at intervals, and each conductive pillar 72 extends in the same direction. That is, the axes of each conductive pillar 72 are arranged parallel to each other.

[0149] The arrangement of the plurality of conductive pillars 72 can be set according to the arrangement of the I / O terminals to be soldered. The heights of different conductive pillars 72 are, for example, the same; the radial dimensions of different conductive pillars 72 can be the same or different.

[0150] S220, such as Fig.16 (b) and Fig.17 As shown in (b) of FIG. 1 , a fixed layer 71 is formed to surround a portion of the side surface of each conductive pillar 72 .

[0151] For example, before forming the fixed layer 71, the plurality of conductive pillars 72 may be arranged according to actual product requirements, and the plurality of conductive pillars 72 may be vertically connected to a film, or Fig.17 As shown in (a), the plurality of conductive posts 72 are connected to the cross beam or support plate of the frame 10, and then the plurality of conductive posts 72 are placed in a receiving cavity.

[0152] Furthermore, under the conditions of high temperature and high pressure (temperature and pressure can be set according to actual needs), the fixing material is filled into the accommodating cavity. At this time, the fixing material has a certain fluidity and can flow into the gap between any two adjacent conductive pillars 72. After the fixing material surrounds part of the side surface of each conductive pillar 72 and has a certain thickness, the film is cured to form a fixing layer 71. Moreover, the fixing layer 71 can fix each conductive pillar 72.

[0153] By adjusting the position where the fixing material is filled, the position where the fixing layer 71 is formed can be adjusted, and a plurality of fixing layers 71 can be stacked at intervals.

[0154] It is understandable that when the height of each conductive column 72 is small or the thickness of the fixed layer 71 is small, the strength of the elevated component 7 is low. By setting the frame 10 or the support plate, the crossbeam or the support plate can be used to provide support for the conductive column 72, which is conducive to enhancing the strength of the elevated component 7 and facilitating welding the conductive columns 72 in the elevated component 7 with the packaging substrate 1. The material of the frame 10 or the support plate includes but is not limited to metal material, as long as it can play a supporting role.

[0155] Of course, the method of forming the elevated component 7 is not limited thereto. For example, in the embodiment of the present application, the fixing layer 71 may be formed first, and then the conductive pillars 72 may penetrate the fixing layer 71 .

[0156] S300, such as Fig.15 As shown in (d) in the figure, each conductive column 72 in the elevated component 7 is connected to the second surface 1B. The distance between the side surface of the conductive column 72 away from the package substrate 1 and the second surface 1B is greater than the distance between the side surface of the second component (for example, the second chip 22 in the figure) away from the package substrate 1 and the second surface 1B.

[0157] Illustratively, the embodiment of the present application may use the SMT process to simultaneously connect each conductive pillar 72 in the elevated component 7 to the second surface 1B of the package substrate 1 .

[0158] Therefore, the preparation method provided by some embodiments of the present application, by connecting the conductive pillar 72 and the fixed layer 71 together to form an elevated component 7, can use the fixed layer 71 to fix the conductive pillars 72, so that the elevated component 7 composed of the fixed layer 71 and multiple conductive pillars 72 acts as an independent module, and then in the process of connecting the conductive pillar 72 to the second surface 1B of the packaging substrate 1, the elevated component 7 can be operated as a single part, and then the multiple conductive pillars 72 in the elevated component 7 can be synchronously connected to the second surface 1B, thereby improving the tilting, tipping, bending and other phenomena of the conductive pillars 72 caused by punching the conductive pillars 72 one by one, avoiding damage to the conductive pillars 72, improving the yield of the chip packaging structure 600, and improving the welding yield between the chip packaging structure 600 and the circuit board 500.

[0159] In some examples, such as Fig.15 As shown in (e) of FIG. 1 , the preparation method further includes: forming a first encapsulation layer 9 on the second surface 1B of the encapsulation substrate 1. The first encapsulation layer 9 at least fills the gap between two adjacent conductive pillars 72 and surrounds the side of each conductive pillar 72; the first encapsulation layer 9 also wraps the fixing layer 71.

[0160] It can be understood that, compared with the first packaging layer 9, the elevated component 7 is first connected to the second surface 1B. Correspondingly, compared with the first packaging layer 9, the fixed layer 71 of the elevated component 7 is first solidified. The material of the first packaging layer 9 has a certain fluidity. Therefore, in the process of forming the first packaging layer 9, the material of the first packaging layer 9 will flow to the gap between two adjacent conductive pillars 72, to the gap between the fixed layer 71 and the second surface 1B, and wrap the fixed layer 71 and the second chip 22. Then, a curing process can be performed to form the first packaging layer 9.

[0161] Continue reading Fig.15 In (e), the first encapsulation layer 9 formed after the curing treatment contacts the second surface 1B and covers the second chip 22. The first encapsulation layer 9 wraps the fixing layer 71 inside and contacts the side of the conductive column 72, while the side surface of the conductive column 72 away from the encapsulation substrate 1 is exposed outside the first encapsulation layer 9.

[0162] In which, when the first packaging layer 9 covers the side surface of the conductive column 72 away from the packaging substrate 1, the side surface of the first packaging layer 9 away from the packaging substrate 1 can also be ground, or a laser etching process can be used to remove a portion of the first packaging layer 9 covering the side surface of the conductive column 72 away from the packaging substrate 1 to expose the side surface of the conductive column 72 away from the packaging substrate 1.

[0163] It is understandable that when the frame 10 or the support plate is used in the above S220, after the first packaging layer 9 is formed, the frame 10 or the support plate can be ground away, or the frame 10 or the support plate can be removed by desoldering.

[0164] The material of the first encapsulation layer 9 and the material of the fixed layer 71 may be the same or different. When the material of the first encapsulation layer 9 and the material of the fixed layer 71 are the same, since the fixed layer 71 is solidified first and the first encapsulation layer 9 is solidified later, an interface may exist between the first encapsulation layer 9 and the fixed layer 71. When the material of the first encapsulation layer 9 and the material of the fixed layer 71 are different, please refer to the description in some of the above examples, which will not be repeated here.

[0165] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present disclosure should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure comprises: A packaging substrate having a first surface and a second surface opposite to each other; a first component connected to the first surface; a second component and an elevated assembly connected to the second surface; The elevated component includes a fixed layer and a plurality of conductive columns, wherein the conductive columns extend in a direction perpendicular to the second surface; the fixed layer surrounds a portion of the side surface of each conductive column to limit the displacement of the conductive column; the material of the fixed layer includes liquid crystal polymer or inorganic material; A side surface of the conductive column close to the packaging substrate is connected to the second surface; A distance between a side surface of the conductive column away from the packaging substrate and the second surface is greater than a distance between a side surface of the second component away from the packaging substrate and the second surface.

2. The chip packaging structure according to claim 1, characterized in that: The number of the elevated components is multiple; The plurality of elevated components are located on at least two sides of the second component.

3. The chip packaging structure according to claim 1 or 2, characterized in that: The number of the fixed layers is multiple; The plurality of fixing layers are stacked at intervals along a direction perpendicular to the second surface.

4. The chip packaging structure according to any one of claims 1 to 3, characterized in that: A gap is provided between the fixing layer and the second surface.

5. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The distance between the side surface of the conductive pillar away from the packaging substrate and the second surface is greater than the distance between the side surface of the fixed layer away from the packaging substrate and the second surface.

6. The chip packaging structure according to any one of claims 1 to 5, characterized in that: The chip packaging structure further includes: a first packaging layer; The first packaging layer is connected to the second surface, at least fills the gap between two adjacent conductive pillars, and surrounds each conductive pillar; the first packaging layer also wraps the fixed layer.

7. A chip packaging structure, characterized in that: The chip packaging structure comprises: A packaging substrate having a first surface and a second surface opposite to each other; a first component connected to the first surface; A second component, an elevated component and a first packaging layer connected to the second surface; The elevated assembly includes a fixed layer and a plurality of conductive posts, wherein the conductive posts extend in a direction perpendicular to the second surface; the fixed layer surrounds a portion of the side surface of each of the conductive posts to limit the displacement of the conductive posts; A side surface of the conductive column close to the packaging substrate is connected to the second surface; The distance between the side surface of the conductive column away from the packaging substrate and the second surface is greater than the distance between the side surface of the second component away from the packaging substrate and the second surface; The first packaging layer at least fills the gap between two adjacent conductive pillars and surrounds each conductive pillar; the first packaging layer also wraps the fixed layer.

8. The chip packaging structure according to claim 7, characterized in that: The number of the elevated components is multiple; The plurality of elevated components are located on at least two sides of the second component.

9. The chip packaging structure according to claim 7 or 8, characterized in that: The number of the fixed layers is multiple; The plurality of fixing layers are stacked at intervals along a direction perpendicular to the second surface.

10. The chip packaging structure according to any one of claims 7 to 9, characterized in that: A gap is provided between the fixing layer and the second surface.

11. The chip packaging structure according to any one of claims 7 to 10, characterized in that: The distance between the side surface of the conductive pillar away from the packaging substrate and the second surface is greater than the distance between the side surface of the fixed layer away from the packaging substrate and the second surface.

12. The chip packaging structure according to any one of claims 7 to 11, characterized in that: The material of the fixed layer includes liquid crystal polymer, resin material or inorganic material.

13. A method for preparing a chip packaging structure, characterized in that: The preparation method comprises: A package is provided; the package comprises a package substrate, a first component and a second component, the package substrate has a first surface and a second surface opposite to each other, the first component is connected to the first surface, and the second component is connected to the second surface; Forming an elevated component; the elevated component comprises a fixed layer and a plurality of conductive posts, the conductive posts extending in a direction perpendicular to the second surface; the fixed layer surrounds a portion of the side surface of each of the conductive posts to limit the displacement of the conductive posts; Each of the conductive posts in the elevated component is connected to the second surface; the distance between the side surface of the conductive post away from the packaging substrate and the second surface is greater than the distance between the side surface of the second component away from the packaging substrate and the second surface.

14. The preparation method according to claim 13, characterized in that: The formation of the elevated assembly comprises: Providing a plurality of conductive pillars; the plurality of conductive pillars are arranged at intervals, and each of the conductive pillars extends in the same direction; A fixed layer is formed surrounding a portion of the side surface of each of the conductive pillars.

15. The preparation method according to claim 13, characterized in that: The preparation method further comprises: A first packaging layer is formed on the second surface, wherein the first packaging layer at least fills the gap between two adjacent conductive pillars and surrounds the side surfaces of each conductive pillar; the first packaging layer also wraps the fixed layer.

16. An electronic device, characterized in that: The electronic device comprises: Circuit boards; and, The chip packaging structure according to any one of claims 1 to 12, wherein the chip packaging structure is connected to the circuit board.

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