Packaging substrate, crystal grain packaging body and preparation method thereof

Abstract

The invention provides a packaging substrate, a crystal grain packaging body and a preparation method of the crystal grain packaging body. The package substrate includes: a package board; and the convex block is arranged on the packaging plate and protrudes from the packaging plate, and the convex block is configured to be connected with a corresponding metal contact window of a crystal grain so as to package the crystal grain on the packaging substrate. The packaging substrate is beneficial to realizing packaging miniaturization, and the cost of forming a crystal grain packaging body and the electrical interference to crystal grains are reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a packaging substrate, a crystal chip package and a preparation method thereof. Background Art

[0002] In the packaging process, the die needs to be electrically connected to the packaging substrate and then packaged to obtain a die package. However, the current die package based on the packaging substrate is expensive and the electrical properties of the die are disturbed. Summary of the invention

[0003] The packaging substrate, the grain package and the preparation method thereof provided in the present application are intended to solve the problem that the cost of preparing the grain package based on the current packaging substrate is high and the electrical properties of the grain are disturbed.

[0004] In order to solve the above technical problems, a technical solution adopted by the present application is: to provide a packaging substrate, the packaging substrate comprising:

[0005] Package board;

[0006] The bump is disposed on the packaging board and protrudes from the packaging board, and the bump is configured to be connected with the corresponding metal contact window of the die to package the die on the packaging substrate.

[0007] In one embodiment of the present application, the package board includes at least one lead frame board; each of the lead frame boards includes a die support sheet and a plurality of pins, and each of the pins is provided with at least one bump to connect to at least one corresponding metal contact window of the die; or

[0008] The packaging board includes at least one packaging loading board, a connecting wire is arranged inside the packaging loading board, and at least one bump is arranged on a surface of the packaging loading board, each of the bumps is respectively connected to at least one corresponding connecting wire, and the bump is configured to be connected to the metal contact window of the grain.

[0009] In one embodiment of the present application, the bump includes:

[0010] The convex block comprises:

[0011] A metal layer, disposed on the packaging board and electrically connected to the packaging board;

[0012] An anti-diffusion layer is provided on a surface of the metal layer facing away from the packaging board; the anti-diffusion layer is configured to block the diffusion of particles between the metal contact window and the metal layer;

[0013] The connection layer is disposed on a surface of the anti-diffusion layer facing away from the metal layer and is configured to be in electrical contact with the metal contact window; wherein the melting point of the connection layer is lower than the melting points of the anti-diffusion layer and the metal contact window.

[0014] In one embodiment of the present application, the material of the metal layer is the same as the conductive material of the packaging board; and / or the ratio of the thickness of the metal layer to the height of the entire bump is 0.5-0.8.

[0015] In one embodiment of the present application, the material of the packaging board and the metal layer includes copper; and / or the material of the anti-diffusion layer includes nickel; and / or the material of the connecting layer includes one or more of tin, silver and tin-silver alloy.

[0016] In one embodiment of the present application, the bump and / or the connection layer are not disposed on the die.

[0017] In one embodiment of the present application, the die includes:

[0018] substrate;

[0019] A dielectric layer, disposed on the substrate and having a lead-out hole;

[0020] The metal wiring is arranged in the dielectric layer, and part of the metal wiring is exposed through the lead-out hole; wherein the part of the metal wiring exposed through the lead-out hole serves as the metal contact window.

[0021] In one embodiment of the present application, the die includes:

[0022] substrate;

[0023] A dielectric layer, disposed on the substrate and having a lead-out hole;

[0024] A metal wiring is disposed in the dielectric layer, and a portion of the metal wiring is exposed through the lead-out hole;

[0025] The soldering pad is at least partially disposed in the lead-out hole and is electrically connected to the metal wiring; wherein the portion of the soldering pad exposed through the lead-out hole serves as the metal contact window.

[0026] In order to solve the above technical problems, another technical solution adopted by the present application is: to provide a chip package, the chip package comprising:

[0027] The packaging substrate is the packaging substrate mentioned above;

[0028] A crystal grain, comprising a metal contact window, wherein the metal contact window is electrically connected to the bump contact;

[0029] The packaging layer is used to package the die and part of the packaging substrate.

[0030] In order to solve the above technical problems, another technical solution adopted by the present application is: to provide a method for preparing a chip package, the method comprising:

[0031] Providing a packaging board and a die; the die includes a metal contact window;

[0032] Arrange a bump on the packaging board;

[0033] Directing the metal contact window of the die toward the bump and electrically connecting the metal contact window with the bump;

[0034] The packaging plate and the die are packaged to form a packaging layer.

[0035] In one embodiment of the present application, the package board includes at least one lead frame board; each of the lead frame boards includes a die support sheet and a plurality of pins; the step of providing a bump on the package board includes:

[0036] Disposing a metal layer on each of the pins, wherein the metal layer is electrically connected to the pin;

[0037] Disposing an anti-diffusion layer on a surface of the metal layer on a side away from the pin;

[0038] Disposing a connection layer on a surface of the diffusion prevention layer facing away from the metal layer to form a bump;

[0039] Alternatively, the package board includes at least one package carrier, and each package carrier is provided with a connecting wire; and the step of providing a bump on the package board includes:

[0040] A metal layer is provided on a surface of the package carrier, wherein the metal layer is electrically connected to at least one corresponding connection line;

[0041] Disposing an anti-diffusion layer on a surface of the metal layer facing away from the packaging carrier;

[0042] A connection layer is arranged on a surface of the diffusion prevention layer which is away from the metal layer to form a bump.

[0043] In one embodiment of the present application, the crystal grain includes a substrate, a dielectric layer and a metal trace; the dielectric layer is disposed on the substrate and has a lead-out hole; the metal trace is disposed in the dielectric layer, and a portion of the metal trace is exposed through the lead-out hole; wherein the portion of the metal trace exposed through the lead-out hole serves as the metal contact window;

[0044] The step of directing the metal contact window of the grain toward the bump and electrically connecting the metal contact window with the bump comprises:

[0045] The connection layer of the bump is brought into contact with the metal contact window through the lead-out hole, and electrical connection between the connection layer and the metal contact window is achieved.

[0046] In one embodiment of the present application, the packaging board includes a plurality of the lead frame boards or a plurality of the packaging carrier boards, and the number of the dies is a plurality;

[0047] After the step of packaging the packaging board and the die to form a packaging layer, the method further includes:

[0048] The packaging plate and the packaging layer are cut to form a single chip package.

[0049] The beneficial effects of the embodiments of the present application are different from the prior art: the packaging substrate provided by the embodiments of the present application, by setting a bump on the packaging board and making the bump protrude from the packaging board, the bump is configured to be connected to the corresponding metal contact window of the grain, so as to package the grain on the packaging substrate. In this way, there is no need to use a wire bonding process to achieve electrical connection between the grain and the packaging substrate through metal wires, which speeds up the connection process between the grain and the packaging substrate and is conducive to miniaturization of packaging. At the same time, the bump is set on the packaging substrate, and there is no need to set a bump on the grain. In this way, the grain obtained by the front-end process (chip factory) can be directly connected to the packaging substrate, and there is no need to perform additional processing on the grain in the packaging factory. In the process of preparing the grain package, the additional redistribution layer (RDL) and bump process of the grain are omitted, so that the metal wiring of the grain is exposed through the lead-out hole to other preset positions, thereby effectively saving the cost expenditure of the RDL and bump processes, reducing the cost, and avoiding the interference of the RDL / bump process on the electrical properties of the grain, and reducing the thermal process of the grain. In addition, wiring on the packaging board is a necessary process for the packaging board. The present application chooses to set the bump on the packaging board. It only needs to use the original process for preparing the packaging board to rewire the packaging board to achieve the setting of the bump at the preset position of the packaging board. There is no need to change the preparation process of the existing packaging board. The process is simple and saves the overall preparation cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A top view of a package substrate including a plurality of lead frame plates provided in an embodiment of the present application;

[0051] Figure 2 for Figure 1 A top view of pins and bumps corresponding to a lead frame plate in the package substrate shown;

[0052] Figure 3 A schematic cross-sectional structure diagram of a package substrate including a lead frame plate provided in an embodiment of the present application;

[0053] Figure 4 A schematic diagram of a cross-sectional structure of a grain is provided for one embodiment of the present application;

[0054] Figure 5 A schematic cross-sectional structure diagram of a grain is provided for another embodiment of the present application;

[0055] Figure 6 A die and a Figure 3 A schematic diagram of the cross-sectional structure of the package substrate after connection is shown;

[0056] Figure 7 A schematic cross-sectional structure diagram of a plurality of die and a plurality of lead frame plates connected to each other according to an embodiment of the present application;

[0057] Figure 8 A top view of a packaging substrate including a plurality of packaging carriers provided in accordance with another embodiment of the present application;

[0058] Fig. 9 for Figure 8 A top view of connecting wires and bumps in a package carrier in the package substrate shown;

[0059] Fig.10 A schematic cross-sectional structure diagram of a packaging substrate including a packaging carrier provided in one embodiment of the present application;

[0060] Fig.11 A die and a Fig.10 A schematic diagram of the cross-sectional structure of the package substrate after connection is shown;

[0061] Fig.12 A schematic cross-sectional structure diagram of a plurality of dies connected to a plurality of packaging carriers according to an embodiment of the present application;

[0062] Figures 13 to 16 A schematic diagram of a cross-sectional structure of a chip package provided in different embodiments of the present application;

[0063] Fig.17 A flow chart of a method for preparing a die package provided in one embodiment of the present application;

[0064] Fig.18 It is a schematic diagram of a structure in which a metal contact window of a die is in contact with a bump on a lead frame plate but has not yet been connected;

[0065] Fig.19 It is a structural schematic diagram showing that the metal contact window of the die is in contact with the bump on the package carrier but has not yet been connected.

[0066] BRIEF DESCRIPTION OF THE DRAWINGS

[0067] 10 package substrate; 1 package board; 1A lead frame board; 11 pin; 1B package carrier; 12 connecting wire; 2 bump; 21 metal layer; 22 anti-diffusion layer; 23 connecting layer; 20 grain; 200 metal contact window; 201 substrate; 202 dielectric layer; 203 metal routing; 204 lead hole; 205 pad; 30 package layer. DETAILED DESCRIPTION

[0068] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0069] The terms "first", "second", "third" in this application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first", "second", "third" can expressly or implicitly include at least one of the features. In the description of this application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication also changes accordingly. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the steps or units listed, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or devices.

[0070] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0071] In order to achieve electrical connection between the die and the packaging substrate, the die is usually mounted on the packaging substrate, and then the electrical connection between the die and the packaging substrate is achieved by using metal wires or metal bumps / bumps. However, for metal wires, a wire bonding process is required, which is slow and not conducive to miniaturization of packaging. As for metal bumps / bumps, metal bumps / bumps are set on the die, but it is difficult to make bumps on the die, and the process is more complicated. It is necessary to do RDL and bump processes on the die. The high-end packaging machine and corresponding mask (mask) and other tools used in this process are very expensive, and the RDL / bump process may interfere with the electrical properties of the die and increase the thermal process of the die.

[0072] To this end, the embodiments of the present application provide a packaging substrate, a chip package and a preparation method thereof, which can not only realize miniaturized packaging but also have low cost, reduce electrical interference to the chip, and reduce the thermal process of the chip.

[0073] The present application is described in detail below with reference to the accompanying drawings and embodiments.

[0074] See also Figures 1 to 3 , Figure 1 A top view of a package substrate including a plurality of lead frame plates provided in an embodiment of the present application; Figure 2 for Figure 1 A top view of a plurality of pins and bumps in a lead frame plate in the package substrate shown; Figure 3 A schematic cross-sectional structure diagram of a package substrate including a lead frame plate provided in one embodiment of the present application. In this embodiment, a package substrate 10 is provided, and the package substrate 10 is used to support a die 20 and is electrically connected to the die 20. It should be noted that the die 20 is a bare die cut from a wafer. The die 20 can be a chip.

[0075] Combination Figures 1 to 4 The package substrate 10 includes a package board 1 and a bump 2. The bump 2 is disposed on the package board 1 and protrudes from the package board 1. The bump 2 is configured to be connected to a corresponding metal contact window 200 of a die 20 to package the die 20 on the package substrate 10. The bump 2 may be a regular columnar structure, or an irregular block or dot structure.

[0076] In one embodiment, see Figure 4 , Figure 4 A schematic cross-sectional structure diagram of a crystal grain 20 is provided for an embodiment of the present application. The crystal grain 20 includes a substrate 201, a dielectric layer 202, and a metal trace 203. The substrate 201 may be a semiconductor substrate, such as a silicon substrate, a germanium substrate, and the like.

[0077] The dielectric layer 202 is disposed on the substrate 201 and has a lead-out hole 204. In some embodiments, the dielectric layer 202 may be a single-layer or multi-layer structure. The dielectric layer 202 may specifically include insulating materials such as silicon dioxide, silicon nitride, and aluminum oxide.

[0078] The metal trace 203 is arranged in the dielectric layer 202, and part of the metal trace 203 is exposed through the lead-out hole 204. In this embodiment, the part of the metal trace 203 exposed through the lead-out hole 204 serves as the metal contact window 200. In this embodiment, the bump 2 and / or the connection layer 23 described below are not arranged on the die 20; that is, the die 20 is the initial structure obtained by the front-end process (chip factory), and the die 20 does not have any additional structural arrangement.

[0079] The material of the metal trace 203 may be at least one of aluminum-copper alloy, aluminum, germanium, and copper. Preferably, the material of the metal trace 203 is copper, but it may also be other metal materials.

[0080] The above-mentioned portion of the metal trace 203 exposed through the lead-out hole 204 is used as the metal contact window 200; in this way, there is no need to set the bump 2 and / or the connection layer 23 described below on the grain 20, and the grain 20 obtained by the front-end process (chip factory) can be directly used to connect with the packaging substrate 10, and there is no need to perform additional processing on the grain 20 in the packaging factory; that is, the grain 20 does not need any additional settings to be directly connected to the packaging substrate 10, eliminating the need for additional RDL and bump processes on the grain 20, so as to lead the portion of the metal trace 203 exposed through the lead-out hole 204 to other preset positions, thereby effectively saving the cost expenditure of additional RDL and bump processes for the grain 20, reducing costs, and avoiding interference with the electrical properties of the grain 20 caused by the RDL / bump process, reducing the thermal process of the grain 20. At the same time, the manufacturing process of the pad 205 (such as an aluminum pad) for leading the metal trace 203 through the lead-out hole 204 is eliminated, simplifying the process and reducing costs. The following embodiments of this application all take this as an example.

[0081] Of course, in other embodiments, see Figure 5 , Figure 5A schematic diagram of the cross-sectional structure of a crystal grain 20 is provided for another embodiment of the present application. The crystal grain 20 may further include a pad 205, at least a portion of which is disposed in the lead-out hole 204, and is in electrical contact with the metal trace 203 through the lead-out hole 204, so as to lead out the metal trace 203. Among them, the surface of the side of the pad 205 facing away from the metal trace 203 may be flush with the surface of the side of the dielectric layer 202 facing away from the substrate 201. Or the surface of the side of the pad 205 facing away from the metal trace 203 is lower than the surface of the side of the dielectric layer 202 facing away from the substrate 201. Or the surface of the side of the pad 205 facing away from the metal trace 203 is higher than the surface of the side of the dielectric layer 202 facing away from the substrate 201, and this embodiment of the present application takes this as an example.

[0082] In this embodiment, the portion of the pad 205 exposed through the lead-out hole 204 serves as the metal contact window 200. In this way, the bump 2 can be directly in contact with the pad 205 for electrical connection; Figure 4 In the solution shown, during the process of preparing the package substrate 10, the bump 2 no longer needs to extend into the lead-out hole 204. Figure 5 In the scheme shown, there is no need to consider the relationship between the aperture size of the bump 2 and the lead-out hole 204, that is, the cross-sectional area of ​​the bump 2 and the cross-sectional area of ​​the lead-out hole 204 are not limited. The scheme of this embodiment can avoid the problem that the bump 2 cannot extend into the lead-out hole 204 to contact and electrically connect with the metal trace 203; at the same time, by extending the solder pad 205 to the side surface of the dielectric layer 202 away from the substrate 201, the metal contact window 200 can be enlarged, so that the requirements for the alignment accuracy of the bump 2 and the metal contact window 200 during packaging are reduced.

[0083] In some embodiments, the orthographic projection of the metal contact window 200 on the package substrate 10 can completely overlap with the bump 2. The overlap here means that the circumferential edge of the orthographic projection of the metal contact window 200 on the package substrate 10 completely overlaps with the circumferential edge of the bump 2; that is, the shape and size of the metal contact window 200 are the same as the shape and size of the surface of the side of the bump 2 away from the package board 1. In this way, when the cross-sectional area of ​​the bump 2 and the cross-sectional area of ​​the metal contact window 200 are constant, the contact area between the bump 2 and the metal contact window 200 can be increased, and the connection strength between the die 20 and the package substrate 10 can be improved.

[0084] In the above scheme, the bump 2 is set on the packaging board 1, but the bump 2 is not set on the grain 20. The connection between the grain 20 and the packaging substrate 10 is realized through the bump 2 on the packaging substrate 10, and there is no need to use the wire bonding process to realize the electrical connection between the grain 20 and the packaging substrate 10 through the metal wire, which speeds up the connection process between the grain 20 and the packaging substrate 10 and is conducive to the miniaturization of the package. At the same time, the bump 2 is not set on the grain 20, and the grain 20 obtained by the front-end process (chip factory) can be directly connected to the packaging substrate 10, and there is no need to perform additional processing on the grain 20 in the packaging factory. In the process of preparing the grain package, the additional RDL and bump processes for the grain 20 are omitted, so that the exposed part of the metal trace 203 through the lead-out hole 204 is led out to other preset positions, thereby effectively saving the cost expenditure of the RDL and bump processes, reducing the cost, and avoiding the interference of the RDL / bump process on the electrical properties of the grain 20, reducing the thermal process of the grain 20. In addition, wiring on the packaging board 1 is a necessary process for the packaging board 1. The present application chooses to set the bump 2 on the packaging board 1. It is only necessary to rewire the packaging board 1 using the original process for preparing the packaging board 1 to achieve setting the bump 2 at a preset position of the packaging board 1. There is no need to change the preparation process of the existing packaging board. The process is simple and saves the overall preparation cost.

[0085] In one embodiment, see Figures 1 to 3 The package board 1 includes at least one lead frame board 1A. Each lead frame board 1A includes a die support sheet (not shown) and a plurality of pins 11.

[0086] The die support sheet is used to provide mechanical support for the die 20 during the packaging process. In one embodiment, a plurality of pins 11 may be arranged around the die support sheet. The die support sheet and the pins 11 may be made of an iron (Fe)-nickel (Ni) alloy or a copper-based alloy.

[0087] The multiple pins 11 of the same lead frame board 1A are respectively used to electrically connect to the same die 20. Each pin 11 is provided with at least one bump 2, which protrudes from the plane where the pin 11 is located, and the bump 2 is configured to connect to a corresponding metal contact window 200 of the die 20.

[0088] In some embodiments, a corresponding bump 2 is disposed on a portion of each lead 11 close to the die support sheet.

[0089] In one embodiment, see Figure 6 , Figure 6 A die and a Figure 3The cross-sectional structure diagram of the package substrate after connection is shown; the package board 1 includes a lead frame board 1A. In this embodiment, the die 20 is connected to the lead frame board 1A and packaged to form a single die package.

[0090] In another embodiment, in combination Figure 1 , the package board 1 includes a plurality of lead frame boards 1A. In this embodiment, see Figure 7 , Figure 7 A schematic diagram of the cross-sectional structure of multiple dies 20 connected to multiple lead frame boards 1A provided in an embodiment of the present application; the vertical dotted lines in the figures involved in the present application only represent the boundary schematic lines of the lead frame board 1A or the package carrier board 1B, and do not represent the actual structure of the package board 1. Multiple dies 20 are respectively connected to the package board 1, and one die 20 is correspondingly connected to a bump 2 on the lead frame board 1A. After the product is packaged, the product can be further cut to form a single die package. Each die package includes a lead frame board 1A.

[0091] In some embodiments, see Figures 8 to 10 , Figure 8 A top view of a packaging substrate 10 including a plurality of packaging carriers provided in another embodiment of the present application; Fig. 9 for Figure 8 A top view of the connection wires 12 and the bumps 2 in a package carrier 1B in the package substrate 10 shown; Fig.10 A schematic cross-sectional structure diagram of a packaging substrate including a packaging carrier provided in an embodiment of the present application. The packaging board 1 includes at least one packaging carrier 1B, each packaging carrier 1B having a first surface and a second surface opposite to each other. At least one connecting wire 12 is arranged in the packaging carrier 1B, and at least part of the connecting wire 12 is exposed on the first surface and / or the second surface of the packaging carrier 1B.

[0092] Among them, Fig.10 As shown, at least one bump 2 is disposed on the first surface of the package carrier 1B, and each bump 2 is respectively connected to at least one corresponding connection line 12, so that the bump 2 is led out to the second surface of the package carrier 1B through the corresponding connection line 12. Each bump 2 is configured to be connected to a corresponding metal contact window 200 of the die 20.

[0093] In a specific embodiment, each package carrier 1B may include a plurality of connection wires 12 , each or a plurality of connection wires 12 correspondingly connects to a bump 2 , and these bumps 2 are respectively in electrical contact with the metal contact window 200 of the same die 20 .

[0094] In one embodiment, Fig.10 As shown, the package board 1 includes a package carrier board 1B. Fig.11, Fig.11 A die and a Fig.10 The cross-sectional structure diagram of the package substrate after connection is shown; the die 20 is connected to the package carrier 1B, and a single die package is formed after packaging.

[0095] In another embodiment, in combination Figure 8 , the packaging board 1 includes a plurality of packaging carriers 1B. In this embodiment, see Fig.12 , Fig.12 The cross-sectional structure diagram of multiple dies 20 and multiple package carriers 1B provided in one embodiment of the present application is shown; multiple dies 20 are connected to the package board 1 respectively, and one die 20 is connected to a bump 2 on the package carrier 1B. After the product is packaged, the product can be further cut to form a single die package. Each die package includes a package carrier 1B.

[0096] See also Figure 3 or Fig.10 The bump 2 involved in any of the above embodiments includes a metal layer 21, an anti-diffusion layer 22 and a connection layer 23. The metal layer 21 is provided on the package board 1 and is electrically connected to the package board 1. In some embodiments, the material of the metal layer 21 is the same as the conductive material of the package board 1. Among them, the metal layer 21 is made of the same material as the package board 1, and the metal layer 21 of the bump 2 can be prepared with existing materials. Not only is the bonding force between the metal layer 21 and the package board 1 better, the risk of delamination is reduced, and the process is easier to implement, which can reduce costs.

[0097] In some embodiments, the material of the metal layer 21 includes copper.

[0098] The anti-diffusion layer 22 is disposed on the surface of the metal layer 21 facing away from the package board 1; the stability and density of the anti-diffusion layer 22 are better than those of the metal layer 21 and the connection layer 23; the anti-diffusion layer 22 is configured to block the diffusion of molecular particles between the metal contact window 200 and the metal layer 21. In this way, the anti-diffusion layer 22 can reduce the risk of metal particles in the metal layer 21 diffusing into the crystal grain 20 and affecting the performance of the crystal grain 20; and reduce the probability of conductive particles in the crystal grain 20 diffusing into the package board 1.

[0099] In some embodiments, the material of the anti-diffusion layer 22 includes nickel.

[0100] The connection layer 23 is disposed on the surface of the anti-diffusion layer 22 facing away from the metal layer 21, and the connection layer 23 is configured to be in contact and electrically connected with the metal contact window 200. The melting point of the connection layer 23 is lower than the melting points of the anti-diffusion layer 22 and the metal contact window 200; thus, in the process of reflow soldering to realize the connection between the bump 2 and the die 20, it is convenient to quickly realize the effective electrical connection between the bump 2 and the die 20, and the connection strength between the bump 2 and the die 20 is better.

[0101] Since copper has a lower cost and better conductivity, and the material of the packaging board 1 is also copper, in this embodiment, the ratio of the thickness of the metal layer 21 to the height of the entire bump 2 can be greater than or equal to 0.5 and less than or equal to 0.8; for example, 0.5, 0.6, 0.7 or 0.8.

[0102] In some embodiments, the material of the connection layer 23 includes one or more of tin, silver, and tin-silver alloy. Compared with the solution of directly contacting and electrically connecting with the metal contact window 200 of the die 20 through the metal layer 21 or the diffusion prevention layer 22, the connection layer 23 of the above materials has better bonding strength with the metal contact window 200 of the die 20.

[0103] In some embodiments, the metal layer 21 , the anti-diffusion layer 22 , and the connection layer 23 are all the same in shape and size.

[0104] The package substrate 10 provided in this embodiment has the bump 2 disposed on the package board 1, but not disposed on the die 20. By disposing the bump 2 on the package board 1 and making the bump 2 protrude from the package board 1, the bump 2 is configured to be connected to the corresponding metal contact window 200 of the die 20, so as to package the die 20 on the package substrate 10. In this way, there is no need to use a wire bonding process to realize the electrical connection between the die 20 and the package substrate 10 through metal wires, which speeds up the connection process between the die 20 and the package substrate 10 and is conducive to miniaturization of the package. At the same time, no bump 2 is set on the crystal grain 20, and the crystal grain 20 obtained by the front-end process (chip factory) can be directly connected to the packaging substrate 10, without the need for additional processing of the crystal grain 20 in the packaging factory. In the process of preparing the crystal grain package, the additional RDL / bump process for the crystal grain 20 is omitted, thereby effectively saving the cost expenditure of the RDL and bump processes, reducing the cost, and avoiding the interference of the RDL / bump process on the electrical properties of the crystal grain 20, reducing the thermal process of the crystal grain 20. In addition, wiring on the packaging board 1 is a necessary process for the packaging board 1. The present application chooses to set the bump 2 on the packaging board 1. It only needs to use the original process for preparing the packaging board 1 to rewire the packaging board 1, so as to achieve setting the bump 2 at the preset position of the packaging board 1, without changing the preparation process of the existing packaging board, the process is simple, and the overall preparation cost is saved.

[0105] See also Figures 13 to 16 , Figures 13 to 16 Schematic diagram of the cross-sectional structure of the grain package provided in different embodiments of the present application; in some embodiments, a grain package is provided, which includes a packaging substrate 10, a grain 20 and a packaging layer 30. Among them, the packaging substrate 10 can be the packaging substrate 10 provided in any of the above embodiments. The grain 20 includes a metal contact window 200, and the metal contact window 200 is in contact and electrically connected with the bump 2. The specific introduction of the grain 20 can be found in the above text. The packaging layer 30 encapsulates the grain 20 and part of the packaging substrate 10 therein. The material of the packaging layer 30 includes silicon dioxide or epoxy resin.

[0106] When the package substrate 10 includes a lead frame plate 1A, the specific structure of the die package can be found in Fig.13 When the package substrate 10 includes a plurality of lead frame plates 1A, the specific structure of the die package can be found in Fig.14 When the package substrate 10 includes a package carrier 1B, the specific structure of the chip package can be found in Fig.15 When the package substrate 10 includes a plurality of package carriers 1B, the specific structure of the die package can be found in Fig.16 .

[0107] In some embodiments, see Fig.17 , Fig.17 The flowchart of a method for preparing a chip package provided by an embodiment of the present application includes:

[0108] Step S1 : providing a packaging board 1 and a die 20 ; the die 20 includes a metal contact window 200 .

[0109] In one embodiment, the package board 1 includes at least one lead frame board 1A. In some implementations, the original process for preparing the lead frame board 1A can be used to first rewire at least one lead frame board 1A to set the pin 11 at a preset position of the package board 1. Among them, wiring the package board 1 is a necessary process for the package board 1. The present application uses the original process for preparing the package board 1 to rewire the package board 1, so that the pin 11 can be set at the preset position of the package board 1, so as to realize setting the bump 2 at the preset position of the package board 1. There is no need to change the preparation process of the existing package board, the process is simple, and the overall preparation cost is saved.

[0110] Each lead frame plate 1A includes a die support sheet and a plurality of leads 11. The lead frame plate 1A and the die 20 are described above.

[0111] Step S2 : providing bumps 2 on the packaging board 1 .

[0112] In one embodiment, step S2 specifically includes:

[0113] Step S21 a: a metal layer 21 is provided on each pin 11 , and the metal layer 21 is electrically connected to the pin 11 .

[0114] Specifically, a metal layer 21 may be provided on a portion of each pin 11 close to the die support sheet. In some embodiments, a metal layer 21 may be formed on each pin 11 by electroplating. Of course, the metal layer 21 may also be formed by sputtering, printing, chemical plating or electrochemical deposition (ECD). The metal layer 21 may be a copper layer.

[0115] Step S22 a: Disposing an anti-diffusion layer 22 on the surface of the metal layer 21 facing away from the lead 11 .

[0116] The size and shape of the diffusion prevention layer 22 may be the same as those of the metal layer 21. The diffusion prevention layer 22 may be a nickel layer.

[0117] Step S23 a : a connection layer 23 is disposed on a surface of the diffusion prevention layer 22 which is away from the metal layer 21 , so as to form a bump 2 .

[0118] The melting point of the connection layer 23 is lower than the melting points of the diffusion prevention layer 22 and the metal contact window 200 . Thus, in the subsequent step S3 , it is convenient to quickly realize the effective electrical connection between the bump 2 and the die 20 , and the connection strength between the bump 2 and the die 20 is better.

[0119] In some embodiments, the material of the connection layer 23 includes one or more of tin, silver, and tin-silver alloy.

[0120] The anti-diffusion layer 22 and the connection layer 23 can be formed by electroplating; of course, they can also be formed by sputtering, printing, chemical plating or electrochemical deposition (ECD).

[0121] Step S3 : the metal contact window 200 of the die 20 faces the bump 2 and is in electrical contact with the bump 2 .

[0122] In one embodiment, the portion of the metal trace 203 of the die 20 exposed through the lead-out hole 204 serves as the metal contact window 200; in this embodiment, step S3 specifically uses a flip-chip process to electrically connect the metal contact window 200 of the die 20 to the bump 2. Specifically, the connection layer 23 of the bump 2 contacts the metal contact window 200 through the lead-out hole 204, and the electrical connection between the connection layer 23 and the metal contact window 200 is achieved.

[0123] Among them, combined Figure 6 and Fig.18 , Fig.18It is a structural schematic diagram of the metal contact window 200 of the grain 20 in contact with the bump 2 but not yet connected; after the metal contact window 200 of the grain 20 is directed toward the bump 2 and in contact with the bump 2, a reflow process can be used to melt the connecting layer 23 to achieve the combination of the bump 2 and the metal contact window 200 of the grain 20.

[0124] Step S4 : packaging the packaging board 1 and the die 20 to form a packaging layer 30 .

[0125] The encapsulation layer 30 encapsulates the die 20 and a portion of the encapsulation substrate 10. The encapsulation layer 30 is made of silicon dioxide or epoxy resin.

[0126] In some embodiments, the package plate 1 includes a plurality of lead frame plates 1A. In this embodiment, the product structure after the step S4 can be seen in FIG. Fig.14 The preparation method further comprises in step S4:

[0127] Step S5: cutting the packaging board 1 and the packaging layer 30 to form a single chip package.

[0128] in, Fig.14 The product structure after the product is processed in step S5 is as follows: Fig.13 shown.

[0129] In some embodiments, another method for preparing a die package is provided. Different from the above embodiments, the package board 1 includes at least one package carrier 1B. In this embodiment, step S1 specifically utilizes the original process for preparing the package carrier 1B to first rewire at least one package carrier 1B, so as to set at least one connection line 12 at a preset position of each package carrier 1B. Similarly, in this method, wiring the package carrier 1B is a necessary process for the package carrier 1B. The present application utilizes the original process for preparing the package carrier 1B to rewire the package carrier 1B, so as to set the bump 2 at the preset position of the package carrier 1B, without changing the existing process for preparing the package carrier 1B, and the process is simple, which also saves the overall preparation cost.

[0130] In this embodiment, step S21 specifically comprises disposing at least one metal layer 21 on the first surface of the package carrier 1B, and each metal layer 21 is electrically connected to a corresponding connection line 12 .

[0131] In this embodiment, the structure corresponding to the specific process of step S3 can be found in Fig.11 , Fig.12 and Fig.19 . Fig.19 It is a structural schematic diagram showing that the metal contact window 200 of the die 20 is in contact with the bump 2 on the package carrier 1B but has not yet been connected.

[0132] In this embodiment, Fig.11 and Fig.12 The product structure after the structure shown in step S4 is processed can be seen in Fig.15 and Fig.16 .

[0133] Similarly, when the packaging board 1 includes a plurality of packaging carriers 1B, step S15 is still performed after step S4; wherein the product structure after processing in step S5 is as follows: Fig.16 shown.

[0134] The method for preparing the grain package provided in this embodiment is to arrange the bump 2 on the packaging board 1; then the metal contact window 200 of the grain 20 is oriented toward the bump 2 and is electrically connected to the bump 2. In this way, there is no need to use the wire bonding process to realize the electrical connection between the grain 20 and the packaging substrate 10 through the metal wire, which speeds up the preparation process and is conducive to the miniaturization of the grain package. At the same time, the bump 2 is arranged on the packaging board 1, and the bump 2 is not arranged on the grain 20. The grain 20 obtained by the front-end process (chip factory) can be directly connected to the packaging substrate 10, and there is no need to perform additional processing on the grain 20 in the packaging factory, eliminating the need for additional RDL and bump processes for the grain 20, thereby effectively saving the cost expenditure of the RDL and bump processes, effectively reducing the cost, and avoiding the interference of the RDL / bump process on the electrical properties of the grain 20, reducing the thermal process of the grain 20. In addition, wiring on the packaging board 1 is a necessary process for the packaging board 1. The present application chooses to set the bump 2 on the packaging board 1. It is only necessary to rewire the packaging board 1 using the original process for preparing the packaging board 1 to achieve setting the bump 2 at a preset position of the packaging board 1. There is no need to change the preparation process of the existing packaging board. The process is simple and saves the overall preparation cost.

[0135] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A packaging substrate, characterized in that: include: Package board; The bump is disposed on the packaging board and protrudes from the packaging board, and the bump is configured to be connected with the corresponding metal contact window of the die to package the die on the packaging substrate.

2. The packaging substrate according to claim 1, characterized in that: The package board includes at least one lead frame board; each of the lead frame boards includes a die support sheet and a plurality of pins, and each of the pins is provided with at least one bump to connect with at least one corresponding metal contact window of the die; or The packaging board includes at least one packaging loading board, a connecting wire is arranged inside the packaging loading board, and at least one bump is arranged on a surface of the packaging loading board, each of the bumps is respectively connected to at least one corresponding connecting wire, and the bump is configured to be connected to the metal contact window of the grain.

3. The packaging substrate according to claim 1 or 2, characterized in that: The convex block comprises: A metal layer, disposed on the packaging board and electrically connected to the packaging board; An anti-diffusion layer is provided on a surface of the metal layer facing away from the packaging board; the anti-diffusion layer is configured to block the diffusion of particles between the metal contact window and the metal layer; The connection layer is disposed on a surface of the anti-diffusion layer facing away from the metal layer and is configured to be in electrical contact with the metal contact window; wherein the melting point of the connection layer is lower than the melting points of the anti-diffusion layer and the metal contact window.

4. The packaging substrate according to claim 3, characterized in that: The material of the metal layer is the same as the conductive material of the packaging board; and / or, The ratio of the thickness of the metal layer to the height of the entire bump is 0.5-0.

8.

5. The packaging substrate according to claim 4, characterized in that: The material of the packaging board and the metal layer includes copper; and / or, The material of the anti-diffusion layer includes nickel; and / or, The material of the connection layer includes one or more of tin, silver and tin-silver alloy.

6. The packaging substrate according to claim 1, characterized in that: The bump and / or the connection layer are not arranged on the die.

7. The packaging substrate according to claim 1, characterized in that: The crystal grains include: substrate; A dielectric layer, disposed on the substrate and having a lead-out hole; The metal wiring is arranged in the dielectric layer, and part of the metal wiring is exposed through the lead-out hole; wherein the part of the metal wiring exposed through the lead-out hole serves as the metal contact window.

8. The packaging substrate according to claim 1, characterized in that: The crystal grains include: substrate; A dielectric layer, disposed on the substrate and having a lead-out hole; A metal wiring is disposed in the dielectric layer, and a portion of the metal wiring is exposed through the lead-out hole; The soldering pad is at least partially disposed in the lead-out hole and is electrically connected to the metal wiring; wherein the portion of the soldering pad exposed through the lead-out hole serves as the metal contact window.

9. A chip package, characterized in that: include: A packaging substrate, which is a packaging substrate as claimed in any one of claims 1 to 8; A crystal grain, comprising a metal contact window, wherein the metal contact window is electrically connected to the bump contact; The packaging layer is used to package the die and part of the packaging substrate.

10. A method for preparing a chip package, characterized in that: include: Provide packaging boards and dies; The die includes a metal contact window; Arrange a bump on the packaging board; Directing the metal contact window of the die toward the bump and electrically connecting the metal contact window with the bump; The packaging board and the die are packaged to form a packaging layer.

11. The method for preparing a chip package according to claim 10, characterized in that: The package board includes at least one lead frame board; each of the lead frame boards includes a die support sheet and a plurality of pins; the step of providing a bump on the package board includes: Disposing a metal layer on each of the pins, wherein the metal layer is electrically connected to the pin; Disposing an anti-diffusion layer on a surface of the metal layer on a side away from the pin; Disposing a connection layer on a surface of the anti-diffusion layer on a side away from the metal layer to form a bump; Alternatively, the package board includes at least one package carrier, and each package carrier is provided with a connecting wire; and the step of providing a bump on the package board includes: A metal layer is provided on a surface of the package carrier, wherein the metal layer is electrically connected to at least one corresponding connection line; Disposing an anti-diffusion layer on a surface of the metal layer facing away from the packaging carrier; A connection layer is arranged on a surface of the diffusion prevention layer which is away from the metal layer to form a bump.

12. The method for preparing a chip package according to claim 11, characterized in that: The crystal grain comprises a substrate, a dielectric layer and a metal trace; the dielectric layer is arranged on the substrate and has a lead-out hole; the metal trace is arranged in the dielectric layer, and a part of the metal trace is exposed through the lead-out hole; wherein the part of the metal trace exposed through the lead-out hole serves as the metal contact window; The step of directing the metal contact window of the grain toward the bump and electrically connecting the metal contact window with the bump comprises: The connection layer of the bump is brought into contact with the metal contact window through the lead-out hole, and electrical connection between the connection layer and the metal contact window is achieved.

13. The method for preparing a chip package according to claim 11, characterized in that: The packaging board includes a plurality of the lead frame boards or a plurality of the packaging carrier boards, and the number of the dies is multiple; After the step of packaging the packaging board and the die to form a packaging layer, the method further includes: The packaging plate and the packaging layer are cut to form a single chip package.

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