High-voltage driving integrated circuit for driving GaN FET (Field Effect Transistor)

Abstract

The invention relates to the technical field of driving circuits, in particular to a high-voltage driving integrated circuit for driving a GaN FET, a noise filtering module is arranged on the high-voltage side, and a bootstrap voltage pre-adjusting unit in the noise filtering module is electrically connected between a bootstrap diode DBST and a bootstrap capacitor CBST and used for clamping bootstrap voltage; the pulse unit is used for driving the level shift unit to generate a first pulse voltage and a second pulse voltage; the voltage-to-current unit is used for receiving the first pulse voltage and the second pulse voltage and converting the first pulse voltage and the second pulse voltage into first pulse current and second pulse current respectively; the current-to-voltage unit is used for receiving the first pulse current and the second pulse current and respectively converting the first pulse current and the second pulse current into a first driving voltage and a second driving voltage to drive the RS trigger; the problem that in the process of driving the GaN FET on the high-voltage side, noise filtering efficiency is low, time delay is serious, and the performance of the GaN FET is limited or damaged due to the fact that bootstrap voltage is too large is solved.

Description

Technical Field

[0001] This invention relates to the field of driving circuit technology, and in particular to a high-voltage driving integrated circuit for driving GaN FETs. Background Technology

[0002] High-voltage driver integrated circuits (HVICs or high-voltage side driver circuits) are typically used to drive semiconductor power components (such as MOSFETs and IGBTs) connected in a half-bridge configuration. These are integrated into intelligent power modules (IPMs), making them suitable for use in frequency converters driving motors and various inverter power supplies. They are ideal power electronic devices in fields such as variable frequency speed control, metallurgical machinery, electric traction, servo drives, and variable frequency home appliances. The input of an HVIC receives control signals from a microcomputer, while its output provides signals to drive the high-side and low-side power devices in the half-bridge circuit.

[0003] GaN FETs (Gallium Nitride Field-Effect Transistors) are third-generation semiconductors. They incorporate a built-in freewheeling diode (FRD), eliminating the need for an external FRD compared to silicon IGBTs. This results in higher integration density. GaN FETs also possess stronger chemical bonds, allowing them to withstand electric fields many times higher than silicon devices without collapsing. This means the distance between the transistor's terminals can be reduced by a factor of ten, resulting in shorter electron switching times and higher switching frequencies. Compared to silicon IGBTs and MOSFETs, they also exhibit superior breakdown capability, higher electron density and mobility, enabling high switching frequencies with low loss. Furthermore, low loss reduces heat generation from conduction resistance, contributing to smaller integrated modules (such as smart power modules). In summary, GaN FETs offer advantages such as fast switching, low loss, and suitability for integration, making them ideal for highly integrated modules.

[0004] For example, the intelligent power module integrates HVIC and GaN FET, with multiple GaN FETs connected to the high-voltage side output (H0) and low-voltage side output (LO) of the HVIC and driven by the HVIC. In particular, the high-voltage side of the HVIC is also equipped with a power supply circuit consisting of a bootstrap capacitor CBST and a bootstrap diode DBST to enhance the reliability of the high-voltage side power supply. However, during the high-level shifting process, when the MOSFET in the high-voltage side pulse circuit is turned on or off, dVs / dt noise is easily generated at the VS terminal. This causes a transient voltage drop due to the parasitic capacitance of the MOSFET, resulting in noise current (I = C * dVs / dt) being generated simultaneously on both sides of the SET and RESET pulse circuits. This causes both MOSFETs to go low at the same time, leading to false triggering of the RS flip-flop, failure of the HVIC, and the inability of the GaN FET to function properly. At the same time, due to the negative bias generated at the VS terminal, the voltage is conducted to the GaN FET through the power supply circuit composed of the bootstrap capacitor CBST and the bootstrap diode DBST. This can lead to an excessively high bootstrap voltage, resulting in an excessively high gate voltage for the GaN FET. This can easily cause excessive leakage current or even permanent damage (breakdown) to the GaN FET.

[0005] Currently, common methods for filtering dVs / dt noise include: First, using filters to remove noise, but this increases circuit delay, and while simple, noise residue remains and cannot suppress bootstrap voltage; second, using a pulse circuit with interlocking on both the SET and RESET sides to prevent simultaneous low or high levels, but this is complex, the interlock duration is uncertain, significantly impacting HVIC efficiency, and prolonged interlocking can lead to continuous bootstrap voltage applied to the GaN FET, causing rapid damage. More importantly, both of these methods involve excessively long or uncertain delays, which are incompatible with the high switching frequency performance of GaN FETs, easily hindering their high switching frequency capabilities due to excessively long delays.

[0006] Therefore, there is an urgent need for a high-voltage driver integrated circuit for driving GaN FETs that can efficiently filter out high-voltage side dVs / dt noise while also filtering out other types of noise, avoiding affecting the high switching frequency performance of GaN FETs, and preventing excessively high bootstrap voltage. Summary of the Invention

[0007] To address the aforementioned shortcomings, the present invention aims to provide a high-voltage driver integrated circuit for driving GaN FETs, which solves the problems of low efficiency in filtering dVs / dt noise and other types of noise, severe delay, and excessive bootstrap voltage leading to limited or damaged GaN FET performance during the high-voltage side driving process of the high-voltage driver integrated circuit for GaN FETs.

[0008] To achieve this objective, the present invention adopts the following technical solution:

[0009] A high-voltage driver integrated circuit for driving a GaN FET includes a pulse unit, a bootstrap diode DBST, a bootstrap capacitor CBST, and an output circuit, and further includes a noise filtering module. The VCC terminal of the pulse unit and the anode of the bootstrap diode DBST are both connected to the power supply VCC terminal. The COM, SET, and RESET terminals of the pulse unit are electrically connected to the COM terminal, the first input terminal, and the second input terminal of the noise filtering module, respectively. The cathode of the bootstrap diode DBST is electrically connected to the VCC terminal of the noise filtering module. The VCCA terminal of the noise filtering module and the VCC terminal of the output circuit are both electrically connected to one end of the bootstrap capacitor CBST. The output terminal of the noise filtering module is electrically connected to the input terminal of the output circuit. The VS terminal of the noise filtering module and the other end of the bootstrap capacitor CBST are both electrically connected to the source of the GaN FET. The gate of the GaN FET is electrically connected to the output terminal of the output circuit.

[0010] The noise filtering module includes a bootstrap voltage pre-adjustment unit, a level shifting unit, a voltage-to-current unit, a current-to-voltage unit, and an RS flip-flop. The input and output terminals of the bootstrap voltage pre-adjustment unit are respectively used as the VCC and VCCA terminals of the noise filtering module. The ground terminal, first input terminal, and second input terminal of the level shifting unit are respectively used as the COM terminal, first input terminal, and second input terminal of the noise filtering module. The VS terminal of the current-to-voltage unit is used as the VS terminal of the noise filtering module. The output terminal of the RS flip-flop is used as the output terminal of the noise filtering module.

[0011] The VCCA terminals of the level shifting unit, the voltage-to-current unit, and the current-to-voltage unit are all electrically connected to the output terminal of the bootstrap voltage pre-adjustment unit. The VS terminals of the bootstrap voltage pre-adjustment unit, the voltage-to-current unit, and the current-to-voltage unit are all electrically connected to the VS terminal of the current-to-voltage unit. The first and second output terminals of the level shifting unit are respectively electrically connected to the first and second input terminals of the voltage-to-current unit. The first and second output terminals of the voltage-to-current unit are respectively electrically connected to the first and second input terminals of the current-to-voltage unit. The first and second output terminals of the current-to-voltage unit are respectively electrically connected to the R and S terminals of the RS flip-flop.

[0012] The bootstrap voltage pre-adjustment unit is used to clamp the bootstrap voltage;

[0013] The pulse unit is used to drive the level shifting unit to generate a first pulse voltage and a second pulse voltage;

[0014] The voltage-to-current unit is used to receive the first pulse voltage and the second pulse voltage, and convert them into a first pulse current and a second pulse current, respectively.

[0015] The current-to-voltage unit is used to receive the first pulse current and the second pulse current, and convert them into a first driving voltage and a second driving voltage to drive the RS flip-flop, respectively.

[0016] Furthermore, the bootstrap voltage pre-regulation unit includes a Zener diode D1, a Zener diode ZD1, a resistor R1, and a transistor Q3; the anode of the Zener diode D1 serves as the input terminal of the bootstrap voltage pre-regulation unit, the emitter of the transistor Q3 serves as the output terminal of the bootstrap voltage pre-regulation unit, and the anode of the Zener diode ZD1 serves as the VS terminal of the bootstrap voltage pre-regulation unit.

[0017] The cathode of the Zener diode D1 and the collector of the transistor Q3 are both electrically connected to one end of the resistor R1, and the cathode of the Zener diode ZD1 and the base of the transistor Q3 are both electrically connected to the other end of the resistor R1.

[0018] Furthermore, the voltage-to-current unit has a current subtraction function, which is used to cancel out the noise current generated by the first pulse voltage and the noise current generated by the second pulse voltage when noise is generated.

[0019] The generation time of the first driving voltage is negatively correlated with the magnitude of the first pulse current, and the generation time of the second driving voltage is negatively correlated with the magnitude of the second pulse current.

[0020] Furthermore, the voltage-to-current conversion unit includes MOSFETs PM1, PM2, PM3, PM4, NM1, NM2, NM3, and NM4; the gate of MOSFET PM1 serves as the first input terminal of the voltage-to-current conversion unit, the gate of MOSFET PM3 serves as the second input terminal of the voltage-to-current conversion unit, the drain of MOSFET PM2 serves as the first output terminal of the voltage-to-current conversion unit, the drain of MOSFET PM3 serves as the second output terminal of the voltage-to-current conversion unit, the source of MOSFET PM1 serves as the VCCA terminal of the voltage-to-current conversion unit, and the source of MOSFET NM4 serves as the VS terminal of the voltage-to-current conversion unit.

[0021] The gate of MOS transistor PM1 is electrically connected to the gate of MOS transistor PM2, and the gate of MOS transistor PM3 is electrically connected to the gate of MOS transistor PM4. The sources of MOS transistors PM1, PM2, and PM3 are all electrically connected to the source of MOS transistor PM4. The drain of MOS transistor PM1 is electrically connected to the drain of MOS transistor NM1, and the drain of MOS transistor PM4 is electrically connected to the drain of MOS transistor NM4. The drains of MOS transistors PM2, NM4, and NM3 are all electrically connected to the gate of MOS transistor NM3. The drains of MOS transistors PM3, NM1, and NM2 are all electrically connected to the gate of MOS transistor NM2, and the sources of MOS transistors NM1, NM2, and NM3 are all electrically connected to the source of MOS transistor NM4.

[0022] Furthermore, the current-to-voltage unit 4 includes a first voltage generation control circuit, a second voltage generation control circuit, resistors R4 and R5, a MOSFET NM5, and a MOSFET NM6; the input terminal of the first voltage generation control circuit is used as the first input terminal of the current-to-voltage unit, the input terminal of the second voltage generation control circuit is used as the second input terminal of the current-to-voltage unit, the drain of the MOSFET NM5 is used as the first output terminal of the current-to-voltage unit, the drain of the MOSFET NM6 is used as the second output terminal of the current-to-voltage unit, one end of the resistor R4 is used as the VCCA terminal of the current-to-voltage unit, and the source of the MOSFET NM6 is used as the VS terminal of the current-to-voltage unit;

[0023] The output terminal of the first voltage generation control circuit is electrically connected to the gate of the MOSFET NM5, and the other end of the resistor R4 is electrically connected to the drain of the MOSFET NM5. The output terminal of the second voltage generation control circuit is electrically connected to the gate of the MOSFET NM6, and the other end of the resistor R5 is electrically connected to the drain of the MOSFET NM6. One end of the resistor R4 is electrically connected to one end of the resistor R5. The ground terminal of the first voltage generation control circuit, the ground terminal of the second voltage generation control circuit, and the source of the MOSFET NM5 are all electrically connected to the source of the MOSFET NM6.

[0024] The first voltage generation control circuit is used to receive the first pulse current and generate a first drive signal; the generation time of the first drive signal is negatively correlated with the magnitude of the first pulse current; when the MOS transistor NM5 receives the first drive signal, it generates the first drive voltage.

[0025] The second voltage generation control circuit is used to receive the second pulse current and generate a second drive signal; the generation time of the second drive signal is negatively correlated with the magnitude of the second pulse current; when the MOS transistor NM6 receives the second drive signal, it generates the second drive voltage.

[0026] Furthermore, the level shifting unit includes resistors R1 and R6, LDMOS transistors Q1 and Q2; the gate of LDMOS transistor Q1 is used as the SET terminal of the level shifting unit, the gate of LDMOS transistor Q2 is used as the RESET terminal of the level shifting unit, the drain of LDMOS transistor Q1 is used as the first output terminal of the level shifting unit, the drain of LDMOS transistor Q2 is used as the second output terminal of the level shifting unit, one end of resistor R1 is used as the VCCA terminal of the level shifting unit, and the source of LDMOS transistor Q2 is used as the ground terminal of the level shifting unit.

[0027] The drain of the LDMOS transistor Q1 is electrically connected to the other end of the resistor R1, the drain of the LDMOS transistor Q2 is electrically connected to the other end of the resistor R6, one end of the resistor R1 is electrically connected to one end of the resistor R6, and the source of the LDMOS transistor Q1 is electrically connected to the LDMOS transistor Q2.

[0028] Furthermore, the first voltage generation control circuit includes a resistor R3 and a capacitor C1; one end of the resistor R3 is used as the input terminal of the first voltage generation control circuit, the other end of the resistor R3 is used as the output terminal of the first voltage generation control circuit, and one end of the capacitor C1 is used as the ground terminal of the first voltage generation control circuit.

[0029] The other end of the resistor R3 is electrically connected to the other end of the capacitor C1.

[0030] Furthermore, the second voltage generation control circuit includes a resistor R2 and a capacitor C2; one end of the resistor R2 is used as the input terminal of the second voltage generation control circuit, the other end of the resistor R2 is used as the output terminal of the second voltage generation control circuit, and one end of the capacitor C2 is used as the ground terminal of the second voltage generation control circuit.

[0031] The other end of the resistor R2 is electrically connected to the other end of the capacitor C2.

[0032] Furthermore, the resistance values ​​of resistors R2 and R3 are 1-5KΩ, and the capacitance values ​​of capacitors C1 and C2 are 0.2-1μF.

[0033] The technical solution provided by this invention can include the following beneficial effects: before driving the GaN FET on the high-voltage side of the high-voltage drive integrated circuit, the bootstrap voltage of the power supply circuit composed of bootstrap diode DBST and bootstrap capacitor CBST is clamped by the bootstrap voltage pre-adjustment unit, and then the clamped bootstrap voltage is supplied to the subsequent circuit, output circuit and GaN FET in the noise filtering module, so as to avoid the noise causing the bootstrap voltage to be too large and damage the GaN FET, while maintaining the stability of the subsequent noise filtering operation of the noise filtering module.

[0034] In the subsequent circuit of the filtering module, if the level shifting unit generates dVs / dt noise or other noise under the drive of the pulse unit, the pulse voltage generated by the level shifting unit can be converted into current and then back into voltage. The noise energy is consumed by the conversion process. Then, the voltage is re-established to shape and filter the noise, so as to obtain a precise driving voltage to drive the RS flip-flop. This avoids the RS flip-flop from being falsely triggered, which would cause the HVIC to fail. This makes the noise cancellation circuit not only suitable for filtering dVs / dt noise, but also for filtering other noise through the conversion-reconstruction mechanism. It has a wider range of applications, and the circuit is simple with a short delay time. Attached Figure Description

[0035] Figure 1 This is a circuit schematic diagram of a high-voltage driver integrated circuit for driving GaN FETs, which is one embodiment of the present invention.

[0036] Figure 2 Is it like this? Figure 1 The circuit principle of the noise filtering module shown Figure 1 .

[0037] Figure 3 Is it like this? Figure 1 The circuit principle of the noise filtering module shown Figure 2 .

[0038] The circuit includes: pulse unit 1, bootstrap diode DBST, bootstrap capacitor CBST, output circuit 8, noise filtering module 7, level shifting unit 2, voltage to current unit 3, current to voltage unit 4, RS trigger 5, Zener diode D1, Zener diode ZD1, resistor R1, transistor Q3, MOSFET PM1, MOSFET PM2, MOSFET PM3, MOSFET PM4, MOSFET NM1, MOSFET NM2, MOSFET NM3, MOSFET NM4, first voltage generation control circuit 41, second voltage generation control circuit 42, resistor R4, resistor R5, MOSFET NM5, MOSFET NM6, resistor R1, resistor R6, LDMOS transistor Q1, LDMOS transistor Q2, resistor R3, capacitor C1, resistor R2, and capacitor C2. Detailed Implementation

[0039] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0040] In the description of embodiments of the present invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of embodiments of the present invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0041] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of the present invention according to the specific circumstances.

[0042] The following is combined Figures 1 to 3 This invention describes a high-voltage driver integrated circuit for driving GaN FETs according to an embodiment of the present invention.

[0043] A high-voltage driving integrated circuit for driving a GaN FET includes a pulse unit 1, a bootstrap diode DBST, a bootstrap capacitor CBST, and an output circuit 8, and also includes a noise filtering module 7. The VCC terminal of the pulse unit 1 and the anode of the bootstrap diode DBST are both connected to the power supply VCC terminal. The COM terminal, SET terminal, and RESET terminal of the pulse unit 1 are electrically connected to the COM terminal, the first input terminal, and the second input terminal of the noise filtering module 7, respectively. The cathode of the bootstrap diode DBST is electrically connected to the VCC terminal of the noise filtering module 7. The VCCA terminal of the noise filtering module 7 and the VCC terminal of the output circuit 8 are both electrically connected to one end of the bootstrap capacitor CBST. The output terminal of the noise filtering module 7 is electrically connected to the input terminal of the output circuit 8. The VS terminal of the noise filtering module 7 and the other end of the bootstrap capacitor CBST are both electrically connected to the source of the GaN FET. The gate of the GaN FET is electrically connected to the output terminal of the output circuit 8.

[0044] The noise filtering module 7 includes a bootstrap voltage pre-conditioning unit 6, a level shifting unit 2, a voltage-to-current unit 3, a current-to-voltage unit 4, and an RS flip-flop 5. The input and output terminals of the bootstrap voltage pre-conditioning unit 6 are used as the VCC and VCCA terminals of the noise filtering module 7, respectively. The ground terminal, first input terminal, and second input terminal of the level shifting unit 2 are used as the COM terminal, first input terminal, and second input terminal of the noise filtering module 7, respectively. The VS terminal of the current-to-voltage unit 4 is used as the VS terminal of the noise filtering module 7. The output terminal of the RS flip-flop 5 is used as the output terminal of the noise filtering module 7.

[0045] The VCCA terminals of level shifting unit 2, voltage-to-current unit 3, and current-to-voltage unit 4 are all electrically connected to the output terminal of bootstrap voltage pre-adjustment unit 6. The VS terminals of bootstrap voltage pre-adjustment unit 6, voltage-to-current unit 3, and current-to-voltage unit 4 are all electrically connected to the VS terminal of current-to-voltage unit 4. The first and second output terminals of level shifting unit 2 are electrically connected to the first and second input terminals of voltage-to-current unit 3, respectively. The first and second output terminals of voltage-to-current unit 3 are electrically connected to the first and second input terminals of current-to-voltage unit 4, respectively. The first and second output terminals of current-to-voltage unit 4 are electrically connected to the R and S terminals of RS flip-flop 5, respectively.

[0046] The bootstrap voltage pre-regulation unit 6 is used to clamp the bootstrap voltage;

[0047] Pulse unit 1 is used to drive level shift unit 2 to generate a first pulse voltage and a second pulse voltage;

[0048] The voltage-to-current unit 3 is used to receive the first pulse voltage and the second pulse voltage, and convert them into the first pulse current and the second pulse current, respectively.

[0049] The current-to-voltage unit 4 is used to receive the first pulse current and the second pulse current, and convert them into the first driving voltage and the second driving voltage respectively to drive the RS flip-flop 5.

[0050] In a preferred embodiment of the high-voltage driver integrated circuit for driving GaN FETs proposed in this invention, such as... Figures 1 to 3 As shown, before driving the GaN FET on the high-voltage side of the high-voltage drive integrated circuit, the bootstrap voltage pre-regulation unit 6 clamps the bootstrap voltage of the power supply circuit composed of bootstrap diode DBST and bootstrap capacitor CBST. Then, the clamped bootstrap voltage is supplied to the subsequent circuits, output circuit 8 and GaN FET in the noise filtering module 7. This avoids the noise causing the bootstrap voltage to be too large and damage the GaN FET, while maintaining the stability of the subsequent noise filtering operation of the noise filtering module 7.

[0051] In the subsequent circuit of the filtering module 7, if the level shifting unit 2 generates dVs / dt noise or other noise under the drive of the pulse unit 1, it can convert the pulse voltage generated by the level shifting unit 2 (i.e., the first pulse voltage and the second pulse voltage, which are SET and RESET in the figure, respectively) into current and then back into voltage. The noise energy is consumed by the conversion process. Then, the voltage is re-established to shape and filter the noise, and obtain a precise driving voltage (i.e., the first driving voltage and the second driving voltage, which are R and S in the figure, respectively) to drive the RS flip-flop 5. This avoids the RS flip-flop from being falsely triggered, which would cause the HVIC to fail. This makes the noise cancellation circuit not only suitable for filtering dVs / dt noise, but also for filtering other noise through the conversion-reconstruction mechanism. It has a wider range of applications, and the circuit is simple with a short delay time, which reduces the impact of the noise filtering process on the high switching frequency performance of the GaN FET.

[0052] Furthermore, the bootstrap voltage pre-regulation unit 6 includes a Zener diode D1, a Zener diode ZD1, a resistor R1, and a transistor Q3; the anode of the Zener diode D1 is used as the input terminal of the bootstrap voltage pre-regulation unit 6, the emitter of the transistor Q3 is used as the output terminal of the bootstrap voltage pre-regulation unit 6, and the anode of the Zener diode ZD1 is used as the VS terminal of the bootstrap voltage pre-regulation unit 6.

[0053] The cathode of Zener diode D1 and the collector of transistor Q3 are both electrically connected to one end of resistor R1, and the cathode of Zener diode ZD1 and the base of transistor Q3 are both electrically connected to the other end of resistor R1.

[0054] In this embodiment, before the bootstrap voltage pre-adjustment unit 6 is set, the bootstrap voltage is VCCA = VCC - UDBST - VS, where VCC, UDBST, and VS are the power supply voltage, the bootstrap diode DBST voltage, and the VS terminal voltage, respectively. When a negative bias voltage is generated at the VS terminal, the bootstrap voltage increases. After the bootstrap voltage pre-adjustment unit 6 is set, the bootstrap voltage is VCCA = UZ - UBE, where UZ and UBE are the Zener diode D1 voltage and the base-emitter voltage of the transistor, respectively. That is, the bootstrap voltage is determined by the Zener diode ZD1's regulated voltage and the forward voltage drop of the transistor Q3. UBE is typically around 0.7V for silicon transistors. When a negative bias is generated at the VS terminal, since UZ remains constant, according to Kirchhoff's voltage law, UBE will increase. This will further turn on transistor Q3 and provide more current to increase the load voltage. Conversely, when the load increases, the drain-emitter current of transistor Q3 will decrease to maintain the output voltage, thereby self-regulating the bootstrap voltage to a stable state and achieving a clamping effect.

[0055] Since resistor R1 provides bias current for Zener diode ZD1 and transistor Q3, when a negative bias voltage is generated at the VS terminal, the efficiency and power consumption performance of the voltage regulator composed of Zener diode ZD1 and transistor Q3 must be considered; therefore, the value of resistor R1 must satisfy the following formula:

[0056] R1=minV1 / (minID+maxIL(hFE+1));

[0057] Where: MinV1 is the minimum voltage to be maintained across resistor R1, minID is the minimum current to be maintained through Zener diode ZD1, maxIL is the maximum design load current, and hFE is the forward current gain (IC / IB) of transistor Q3.

[0058] Furthermore, the voltage-to-current unit 3 has a current subtraction function, which is used to cancel out the noise current generated by the first pulse voltage and the noise current generated by the second pulse voltage when noise is generated.

[0059] The generation time of the first driving voltage is negatively correlated with the magnitude of the first pulse current, and the generation time of the second driving voltage is negatively correlated with the magnitude of the second pulse current.

[0060] In this embodiment, to ensure effective reduction of dVs / dt noise at the power supply VS terminal during the voltage-to-current conversion process, a current subtraction function is provided in the voltage-to-current unit 3. When noise is generated, the noise current generated by the first pulse voltage and the noise current generated by the second pulse voltage cancel each other out, thereby achieving noise filtering (mainly common-mode noise caused by dVs / dt noise). It should be noted that when dVs / dt noise is present, the first and second pulse voltages will contain transient voltage drops caused by dVs / dt noise, resulting in noise current during the voltage-to-current conversion process.

[0061] The current-to-voltage unit 4 is mainly used to filter out differential-mode noise caused by dVs / dt noise (for example, due to differences in the manufacturing process of the components in the voltage-to-current unit 3, the noise current may not be completely canceled, resulting in residual differential-mode noise) and other types of noise. Since residual noise will cause fluctuations in the first pulse current or the second pulse current, the current-to-voltage unit 4, in order to ensure that the first drive voltage and the second drive voltage can still be generated normally and drive the RS flip-flop 5, negatively correlates the generation time of the first drive voltage (or the second drive voltage) with the magnitude of the first pulse current (or the second pulse current). This ensures that the fluctuations in the first pulse current or the second pulse current only affect the generation time of the drive signal and do not affect the normal drive logic. Thus, it uses different drive signal generation times to filter out residual noise and has a wide range of applicable noise. For example, if there is a certain type of noise that severely reduces the first pulse current (or the second pulse current), the drive signal generation time will be long, or even the drive may be shut down. In addition to reliably eliminating differential-mode noise caused by dVs / dt noise, it can also adaptively pair protection measures for subsequent drive circuits according to the type and severity of noise.

[0062] Furthermore, the voltage-to-current conversion unit 3 includes MOSFETs PM1, PM2, PM3, PM4, NM1, NM2, NM3, and NM4; the gate of MOSFET PM1 is used as the first input terminal of the voltage-to-current conversion unit 3, the gate of MOSFET PM3 is used as the second input terminal of the voltage-to-current conversion unit 3, the drain of MOSFET PM2 is used as the first output terminal of the voltage-to-current conversion unit 3, the drain of MOSFET PM3 is used as the second output terminal of the voltage-to-current conversion unit 3, the source of MOSFET PM1 is used as the VCCA terminal of the voltage-to-current conversion unit 3, and the source of MOSFET NM4 is used as the VS terminal of the voltage-to-current conversion unit 3.

[0063] The gates of MOSFET PM1 and PM2 are electrically connected, and the gates of MOSFET PM3 and PM4 are electrically connected. The sources of MOSFET PM1, PM2, and PM3 are all electrically connected to the source of MOSFET PM4. The drain of MOSFET PM1 is electrically connected to the drain of MOSFET NM1, and the drain of MOSFET PM4 is electrically connected to the drain of MOSFET NM4. The drains of MOSFET PM2, NM4, and NM3 are all electrically connected to the gate of MOSFET NM3. The drains of MOSFET PM3, NM1, and NM2 are all electrically connected to the gate of MOSFET NM2. The sources of MOSFET NM1, NM2, and NM3 are all electrically connected to the source of MOSFET NM4.

[0064] In this embodiment, a voltage-to-current conversion unit 3 with current subtraction function is constructed from MOSFETs PM1, PM2, PM3, PM4, NM1, NM2, NM3, and NM4. The voltage-to-current conversion of the voltage-to-current unit 3 is achieved by turning on the MOSFETs according to the first pulse voltage and the second pulse voltage. Figure 1 Points A and B in the middle generate the first pulse current and the second pulse current, respectively.

[0065] The noise filtering mechanism of voltage-to-current unit 3 for dVs / dt noise or other types of noise is as follows: Taking point A as an example, when a transient voltage drop is introduced due to noise, the voltage drop on the SET side will turn on the MOSFET PM1, and introduce a noise current I1 under the current mirror effect of the MOSFETs NM1 and NM2; the voltage drop on the RESET side will turn on the MOSFET PM3, generating a noise current I3; by utilizing the mutual cancellation of noise currents I1 and I3, i.e., the current subtraction function, when noise is generated, the noise current (I1) generated by the first pulse voltage and the noise current (I2) generated by the second pulse voltage cancel each other out, thereby filtering out the noise.

[0066] Furthermore, the current-to-voltage unit 4 includes a first voltage generation control circuit 41, a second voltage generation control circuit 42, resistors R4 and R5, MOSFET NM5 and MOSFET NM6; the input terminal of the first voltage generation control circuit 41 is used as the first input terminal of the current-to-voltage unit 4, the input terminal of the second voltage generation control circuit 42 is used as the second input terminal of the current-to-voltage unit 4, the drain of MOSFET NM5 is used as the first output terminal of the current-to-voltage unit 4, the drain of MOSFET NM6 is used as the second output terminal of the current-to-voltage unit 4, one end of resistor R4 is used as the VCCA terminal of the current-to-voltage unit 4, and the source of MOSFET NM6 is used as the VS terminal of the current-to-voltage unit 4;

[0067] The output terminal of the first voltage generation control circuit 41 is electrically connected to the gate of MOSFET NM5, and the other end of resistor R4 is electrically connected to the drain of MOSFET NM5. The output terminal of the second voltage generation control circuit 42 is electrically connected to the gate of MOSFET NM6, and the other end of resistor R5 is electrically connected to the drain of MOSFET NM6. One end of resistor R4 is electrically connected to one end of resistor R5. The ground terminal of the first voltage generation control circuit 41, the ground terminal of the second voltage generation control circuit 42, and the source of MOSFET NM5 are all electrically connected to the source of MOSFET NM6.

[0068] The first voltage generation control circuit 41 is used to receive the first pulse current and generate the first drive signal; the generation time of the first drive signal is negatively correlated with the magnitude of the first pulse current; when the MOS transistor NM5 receives the first drive signal, it generates the first drive voltage.

[0069] The second voltage generation control circuit 42 is used to receive the second pulse current and generate the second drive signal; the generation time of the second drive signal is negatively correlated with the magnitude of the second pulse current; when the MOS transistor NM6 receives the second drive signal, it generates the second drive voltage.

[0070] In this embodiment, the current-to-voltage unit 4 converts current into voltage using MOSFETs NM5 and NM6. That is, when the MOSFETs are turned on, the first driving voltage (or the second driving voltage) is at a high level, and when the MOSFETs are turned off, the first driving voltage (or the second driving voltage) is at a low level. The generation time of the first driving voltage (or the second driving voltage) is controlled by the first voltage generation control circuit 41 (or the second voltage generation control circuit 42).

[0071] Furthermore, the level shifting unit 2 includes resistors R1 and R6, LDMOS transistors Q1 and Q2; the gate of LDMOS transistor Q1 is used as the SET terminal of the level shifting unit 2, the gate of LDMOS transistor Q2 is used as the RESET terminal of the level shifting unit 2, the drain of LDMOS transistor Q1 is used as the first output terminal of the level shifting unit 2, the drain of LDMOS transistor Q2 is used as the second output terminal of the level shifting unit 2, one end of resistor R1 is used as the VCCA terminal of the level shifting unit 2, and the source of LDMOS transistor Q2 is used as the ground terminal of the level shifting unit 2.

[0072] The drain of LDMOS transistor Q1 is electrically connected to the other end of resistor R1, the drain of LDMOS transistor Q2 is electrically connected to the other end of resistor R6, one end of resistor R1 is electrically connected to one end of resistor R6, and the source of LDMOS transistor Q1 is electrically connected to LDMOS transistor Q2.

[0073] In this embodiment, the level shifting unit 2 shifts the high level by turning on or off LDMOS transistors Q1 and Q2. When there is dVs / dt noise, due to the parasitic capacitance of the LDMOS transistor, the dVs / dt noise will generate a transient voltage drop across resistors R1 and R6, thereby generating noise currents (such as I1 and I3). Therefore, LDMOS transistors are preferred as switching transistors. Compared with ordinary MOS transistors, they have lower distortion, higher efficiency, and smaller parasitic capacitance, and are less affected by dVs / dt noise, or even unaffected by dVs / dt noise.

[0074] Furthermore, the first voltage generation control circuit 41 includes a resistor R3 and a capacitor C1; one end of the resistor R3 is used as the input terminal of the first voltage generation control circuit 41, the other end of the resistor R3 is used as the output terminal of the first voltage generation control circuit 41, and one end of the capacitor C1 is used as the ground terminal of the first voltage generation control circuit 41.

[0075] The other end of resistor R3 is electrically connected to the other end of capacitor C1.

[0076] In this embodiment, the first voltage generation control circuit 41 is preferably an RC charging and discharging circuit to ensure that the generation time of the first driving signal is negatively correlated with the magnitude of the first pulse current. The charging time can be determined based on the magnitude of the first pulse current. More importantly, the input terminal of the RC charging and discharging circuit is connected to... Figure 1 At point B, when MOSFET PM1 or MOSFET PM2 is turned on, the potential at point B is about half of the power supply voltage (power supply VCCA terminal), which does not affect the turn-on or turn-off of MOSFET NM5, and thus does not affect the normal drive logic. Therefore, the first drive voltage is not affected by the noise current of voltage-to-current unit 3.

[0077] Furthermore, the second voltage generation control circuit 42 includes a resistor R2 and a capacitor C2; one end of the resistor R2 is used as the input terminal of the second voltage generation control circuit 42, the other end of the resistor R2 is used as the output terminal of the second voltage generation control circuit 42, and one end of the capacitor C2 is used as the ground terminal of the second voltage generation control circuit 42.

[0078] The other end of resistor R2 is electrically connected to the other end of capacitor C2.

[0079] In this embodiment, the second voltage generation control circuit 42 is similar to the first voltage generation control circuit 41.

[0080] Furthermore, the resistance values ​​of resistors R2 and R3 are 1-5KΩ, and the capacitance values ​​of capacitors C1 and C2 are 0.2-1μF.

[0081] In this embodiment, the charging process of the RC circuit can be described by the time constant τ = R * C, where R is the resistance value and C is the capacitance value. The charging process of the capacitor is completed within several time constants, typically 3τ to 5τ. During this time, the capacitor voltage reaches 95% to 99% of its stable value. For example, when R = 1KΩ and C = 1μF, τ = 1ms. This means that the capacitor voltage reaches 95% to 99% of its stable value in approximately 3ms to 5ms, causing MOSFET NM5 or NM6 to conduct. Therefore, in order to shorten the conduction time of the MOSFET and improve the efficiency of the noise cancellation circuit, the charging time of the RC circuit needs to be reduced as much as possible. Based on this, considering that an excessively large resistance will affect the sinking capability and pull down the voltage, the resistance is preferably 1-5KΩ, and the capacitor is preferably 0.2-1μF, ensuring that the time constant τ is around 1ms. This ensures that the charging time of the RC circuit can be shortened as much as possible regardless of whether the first pulse current or the second pulse current is large or small, adapting to various noise conditions.

[0082] Other configurations and operations of a high-voltage driver integrated circuit for driving GaN FETs according to embodiments of the present invention are known to those skilled in the art and will not be described in detail here.

[0083] In the description of this specification, references to terms such as "embodiment," "example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0084] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A high voltage driver integrated circuit for driving GaN FET, comprising a pulse unit, a bootstrap diode DBST, a bootstrap capacitor CBST and an output circuit, characterized in that: It also includes a noise filtering module; the VCC terminal of the pulse unit and the anode of the bootstrap diode DBST are connected to the power supply VCC terminal, the COM terminal, the SET terminal and the RESET terminal of the pulse unit are electrically connected to the COM terminal, the first input terminal and the second input terminal of the noise filtering module respectively, the cathode of the bootstrap diode DBST is electrically connected to the VCC terminal of the noise filtering module, the VCCA terminal of the noise filtering module and the VCC terminal of the output circuit are electrically connected to one end of the bootstrap capacitor CBST, the output end of the noise filtering module is electrically connected to the input end of the output circuit, the VS terminal of the noise filtering module and the other end of the bootstrap capacitor CBST are electrically connected to the source of the GaN FET, and the gate of the GaN FET is electrically connected to the output end of the output circuit; The noise filtering module comprises a bootstrap voltage pre-regulating unit, a level shifting unit, a voltage-to-current unit, a current-to-voltage unit and an RS trigger; the input end and the output end of the bootstrap voltage pre-regulating unit are respectively used as the VCC end and the VCCA end of the noise filtering module, the ground end, the first input end and the second input end of the level shifting unit are respectively used as the COM end, the first input end and the second input end of the noise filtering module, the VS end of the current-to-voltage unit is used as the VS end of the noise filtering module, and the output end of the RS trigger is used as the output end of the noise filtering module; The VCCA terminals of the level shift unit, the voltage-to-current unit, and the current-to-voltage unit are all electrically connected to the output terminal of the bootstrap voltage pre-regulation unit, the VS terminals of the bootstrap voltage pre-regulation unit, the voltage-to-current unit, and the current-to-voltage unit are all electrically connected to the VS terminal of the current-to-voltage unit, the first output terminal and the second output terminal of the level shift unit are respectively electrically connected to the first input terminal and the second input terminal of the voltage-to-current unit, the first output terminal and the second output terminal of the voltage-to-current unit are respectively electrically connected to the first input terminal and the second input terminal of the current-to-voltage unit, and the first output terminal and the second output terminal of the current-to-voltage unit are respectively electrically connected to the R terminal and the S terminal of the RS trigger; The bootstrap voltage pre-regulation unit is used to clamp the bootstrap voltage; The pulse unit is used to drive the level shift unit to generate a first pulse voltage and a second pulse voltage; The voltage-to-current unit is used to receive the first pulse voltage and the second pulse voltage, and convert them into a first pulse current and a second pulse current respectively; The current-to-voltage unit is used to receive the first pulse current and the second pulse current, and convert them into a first driving voltage and a second driving voltage respectively to drive the RS trigger.

2. A high voltage driver integrated circuit for driving GaN FET according to claim 1, characterized in that: The bootstrap voltage pre-regulation unit includes a Zener diode D1, a voltage regulator ZD1, a resistor R1 and a transistor Q3; the anode of the Zener diode D1 is used as the input end of the bootstrap voltage pre-regulation unit, the emitter of the transistor Q3 is used as the output end of the bootstrap voltage pre-regulation unit, and the anode of the voltage regulator ZD1 is used as the VS end of the bootstrap voltage pre-regulation unit; The cathode of the Zener diode D1 and the collector of the transistor Q3 are both electrically connected to one end of the resistor R1 , and the cathode of the voltage regulator tube ZD1 and the base of the transistor Q3 are both electrically connected to the other end of the resistor R1 .

3. The high voltage driver integrated circuit for driving GaN FET according to claim 1, characterized in that: The voltage-to-current unit has a current subtraction function, which is used to cancel out the noise current generated by the first pulse voltage and the noise current generated by the second pulse voltage when noise is generated; The generation time of the first driving voltage is negatively correlated with the magnitude of the first pulse current, and the generation time of the second driving voltage is negatively correlated with the magnitude of the second pulse current.

4. A high voltage driver integrated circuit for driving GaN FET according to claim 3, characterized in that: The voltage-to-current unit comprises a MOS transistor PM1, a MOS transistor PM2, a MOS transistor PM3, a MOS transistor PM4, a MOS transistor NM1, a MOS transistor NM2, a MOS transistor NM3 and a MOS transistor NM4; the gate of the MOS transistor PM1 is used as the first input terminal of the voltage-to-current unit, the gate of the MOS transistor PM3 is used as the second input terminal of the voltage-to-current unit, the drain of the MOS transistor PM2 is used as the first output terminal of the voltage-to-current unit, the drain of the MOS transistor PM3 is used as the second output terminal of the voltage-to-current unit, the source of the MOS transistor PM1 is used as the VCCA terminal of the voltage-to-current unit, and the source of the MOS transistor NM4 is used as the VS terminal of the voltage-to-current unit; The gate of the MOS transistor PM1 is electrically connected to the gate of the MOS transistor PM2, the gate of the MOS transistor PM3 is electrically connected to the gate of the MOS transistor PM4, the source of the MOS transistor PM1, the source of the MOS transistor PM2, and the source of the MOS transistor PM3 are all electrically connected to the source of the MOS transistor PM4, the drain of the MOS transistor PM1 is electrically connected to the drain of the MOS transistor NM1, the drain of the MOS transistor PM4 is electrically connected to the drain of the MOS transistor NM4, the drain of the MOS transistor PM2, the gate of the MOS transistor NM4, and the drain of the MOS transistor NM3 are all electrically connected to the gate of the MOS transistor NM3, the drain of the MOS transistor PM3, the gate of the MOS transistor NM1, and the drain of the MOS transistor NM2 are all electrically connected to the gate of the MOS transistor NM2, and the source of the MOS transistor NM1, the source of the MOS transistor NM2, and the source of the MOS transistor NM3 are all electrically connected to the source of the MOS transistor NM4.

5. The high voltage driver integrated circuit for driving GaN FET according to claim 3, characterized in that: The current-to-voltage unit 4 includes a first voltage generation control circuit, a second voltage generation control circuit, a resistor R4, a resistor R5, a MOS tube NM5 and a MOS tube NM6; the input end of the first voltage generation control circuit is used as the first input end of the current-to-voltage unit, the input end of the second voltage generation control circuit is used as the second input end of the current-to-voltage unit, the drain of the MOS tube NM5 is used as the first output end of the current-to-voltage unit, the drain of the MOS tube NM6 is used as the second output end of the current-to-voltage unit, one end of the resistor R4 is used as the VCCA end of the current-to-voltage unit, and the source of the MOS tube NM6 is used as the VS end of the current-to-voltage unit; The output end of the first voltage generation control circuit is electrically connected to the gate of the MOS tube NM5, the other end of the resistor R4 is electrically connected to the drain of the MOS tube NM5, the output end of the second voltage generation control circuit is electrically connected to the gate of the MOS tube NM6, the other end of the resistor R5 is electrically connected to the drain of the MOS tube NM6, one end of the resistor R4 is electrically connected to one end of the resistor R5, and the ground end of the first voltage generation control circuit, the ground end of the second voltage generation control circuit, and the source of the MOS tube NM5 are all electrically connected to the source of the MOS tube NM6; The first voltage generation control circuit is used to receive the first pulse current and generate a first drive signal; The generation time of the first driving signal is negatively correlated with the magnitude of the first pulse current; when the MOS transistor NM5 receives the first driving signal, it generates the first driving voltage; The second voltage generation control circuit is used to receive the second pulse current and generate a second drive signal; The generation time of the second driving signal is negatively correlated with the magnitude of the second pulse current; when the MOS tube NM6 receives the second driving signal, it generates the second driving voltage.

6. The high voltage driver integrated circuit for driving GaN FET according to claim 3, characterized in that: The level shift unit includes a resistor R1, a resistor R6, an LDMOS transistor Q1 and an LDMOS transistor Q2; the gate of the LDMOS transistor Q1 is used as the SET terminal of the level shift unit, the gate of the LDMOS transistor Q2 is used as the RESET terminal of the level shift unit, the drain of the LDMOS transistor Q1 is used as the first output terminal of the level shift unit, the drain of the LDMOS transistor Q2 is used as the second output terminal of the level shift unit, one end of the resistor R1 is used as the VCCA terminal of the level shift unit, and the source of the LDMOS transistor Q2 is used as the ground terminal of the level shift unit; The drain of the LDMOS tube Q1 is electrically connected to the other end of the resistor R1, the drain of the LDMOS tube Q2 is electrically connected to the other end of the resistor R6, one end of the resistor R1 is electrically connected to one end of the resistor R6, and the source of the LDMOS tube Q1 is electrically connected to the LDMOS tube Q2.

7. The high voltage driver integrated circuit for driving GaN FET according to claim 5, characterized in that: The first voltage generation control circuit includes a resistor R3 and a capacitor C1; one end of the resistor R3 is used as an input end of the first voltage generation control circuit, the other end of the resistor R3 is used as an output end of the first voltage generation control circuit, and one end of the capacitor C1 is used as a ground end of the first voltage generation control circuit; The other end of the resistor R3 is electrically connected to the other end of the capacitor C1.

8. The high voltage driver integrated circuit for driving GaN FET according to claim 7, characterized in that: The second voltage generation control circuit includes a resistor R2 and a capacitor C2; one end of the resistor R2 is used as an input end of the second voltage generation control circuit, the other end of the resistor R2 is used as an output end of the second voltage generation control circuit, and one end of the capacitor C2 is used as a ground end of the second voltage generation control circuit; The other end of the resistor R2 is electrically connected to the other end of the capacitor C2.

9. A high voltage driver integrated circuit for driving GaN FET according to claim 8, characterized in that: The resistance values ​​of the resistor R2 and the resistor R3 are 1-5KΩ, and the capacitance values ​​of the capacitor C1 and the capacitor C2 are 0.2-1μF.

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