Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and the semiconductor device comprises a plurality of transistors which are distributed in different layers and are stacked in a direction perpendicular to a substrate; the bit lines penetrate through the plurality of transistors of different layers and extend along the direction vertical to the substrate; the transistor comprises a gate electrode and a semiconductor layer, the semiconductor layer comprises a first semiconductor sub-layer extending in the direction parallel to the substrate and a second semiconductor sub-layer extending in the direction perpendicular to the substrate, the first semiconductor sub-layer comprises a strip-shaped part extending in the first direction, and the second semiconductor sub-layer comprises a strip-shaped part extending in the second direction. The second semiconductor sub-layer is connected with the bit line, and the gate electrode extends in the direction parallel to the substrate and surrounds the strip-shaped part. The embodiment of the invention provides a gate-all-around semiconductor device convenient to stack, which can simplify the process and improve the gate control capability.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] Semiconductor storage can be divided into volatile memory and non-volatile memory based on application.

[0003] In order to reduce the cost of memory products as much as possible, people hope to make as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's needs for current products. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The present application provides a semiconductor device that simplifies the process and improves gate control capability.

[0006] The present application provides a semiconductor device, comprising:

[0007] Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate;

[0008] A bit line connected to the plurality of transistors at different layers and extending in a direction perpendicular to the substrate;

[0009] The transistor includes a gate electrode and a semiconductor layer, the semiconductor layer includes a first semiconductor sublayer extending in a direction parallel to the substrate and a second semiconductor sublayer extending in a direction perpendicular to the substrate, the first semiconductor sublayer includes a strip-shaped portion extending in a first direction, the second semiconductor sublayer is connected to the bit line, and the gate electrode extends in a direction parallel to the substrate and surrounds the strip-shaped portion.

[0010] In some embodiments, the second semiconductor sublayer surrounds the bit line.

[0011] In some embodiments, on a plane perpendicular to the substrate and the first direction, the orthographic projection of the strip portion is located within the orthographic projection of the second semiconductor sublayer, and the orthographic projection of the gate electrode on the substrate is located outside the orthographic projection of the second semiconductor sublayer on the substrate.

[0012] In some embodiments, the first semiconductor sublayer also includes an end portion of the strip portion away from one end of the bit line, and on a plane perpendicular to the substrate and the first direction, the orthographic projection of the strip portion is located within the orthographic projection of the end portion, and the orthographic projection of the gate electrode on the substrate is located outside the orthographic projection of the end portion on the substrate.

[0013] In some embodiments, the end portion is provided with a first groove opening away from the bit line, and the transistor further includes: a first source / drain electrode, and the first source / drain electrode fills the first groove.

[0014] In some embodiments, the first source / drain electrode includes a first portion filling the first groove and a second portion disposed on a side of the first groove away from the bit line, and the second portion overlaps the first portion.

[0015] In some embodiments, the second portion of the first source / drain electrode is provided with a second groove opening away from the bit line, and the semiconductor device further includes: a capacitor including a second electrode insulated from the first source / drain electrode by a dielectric layer and filling the second groove.

[0016] In some embodiments, the second portion of the first source / drain electrode is a block electrode, and the semiconductor device further includes: a capacitor, the capacitor including a second pole, the second pole being provided with a third groove opening toward the bit line, the second portion of the first source / drain electrode being insulated from the second pole by a dielectric layer and filling the third groove.

[0017] In some embodiments, the semiconductor device includes a multi-layer memory cell array distributed along a direction perpendicular to the substrate, wherein each layer of the memory cell array includes a plurality of rows and columns of memory cells distributed along a first direction and a second direction, respectively, a plurality of word lines extending along the second direction and arranged at intervals along a direction perpendicular to the substrate, and a plurality of bit lines extending along a direction perpendicular to the substrate and arranged at intervals along the second direction; the memory cell includes the transistor and the capacitor, the plurality of transistors are located in different layers and arranged in an array; the same word line includes a plurality of connecting electrodes distributed along the second direction; the plurality of connecting electrodes of the same word line are connected through gate electrodes of transistors in the same column distributed along the second direction; and each bit line is connected to a transistor in at least one column of the memory cells arranged perpendicular to the substrate.

[0018] In some embodiments, the connection electrode is connected to a region of the gate electrode close to the bit line.

[0019] In some embodiments, semiconductor layers of the plurality of transistors at the same position in different layers are connected to form an integrated structure.

[0020] In some embodiments, the arrangement direction of the transistor and the capacitor of the same memory cell is parallel to the first direction, and in the memory cells of the same layer, the arrangement directions of the transistors and capacitors of the memory cells adjacent along the first direction are opposite to each other; the semiconductor layers of the memory cells adjacent along the first direction and whose transistors are close to each other are connected to form an integrated structure.

[0021] In some embodiments, the semiconductor layer of the integrated structure is connected to the same bit line and surrounds the connected bit line.

[0022] The present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device comprises: a plurality of transistors and bit lines distributed in different layers and stacked along a direction perpendicular to a substrate, wherein the transistors comprise a gate electrode and a semiconductor layer, and include:

[0023] Forming a stack structure of alternately stacked first insulating layers and sacrificial layers on a substrate;

[0024] The stack structure is patterned to form a word line region extending along a second direction and a plurality of memory cell regions extending along a first direction and spaced apart along the second direction; a groove extending along the first direction and penetrating the stack structure is provided between any two adjacent memory cell regions;

[0025] forming a first hole penetrating the stacked structure in the word line region; removing a portion of each sacrificial layer to form a plurality of first grooves communicating with the first hole;

[0026] forming a gate electrode covering the sidewall of the first groove;

[0027] Depositing a gate insulating film and a semiconductor film in the first groove and the first hole in sequence to form a gate insulating layer and a semiconductor layer of the transistor, wherein the semiconductor layer fills the first groove and covers the bottom wall and the side wall of the first hole, the gate insulating layer surrounds the semiconductor layer, and the gate electrode surrounds the gate insulating layer;

[0028] The bit line is formed by depositing a first conductive film in the first hole where the semiconductor layer is formed.

[0029] In some embodiments, the method further comprises:

[0030] Removing the sacrificial layer of the storage unit area to form a second groove connected to the first groove, wherein the second groove is arranged on a side of the first groove away from the first hole;

[0031] The step of sequentially depositing a gate insulating film and a semiconductor film in the first groove and the first hole to form a gate insulating layer and a semiconductor layer of the transistor, wherein the semiconductor layer fills the first groove and covers the bottom wall and the side wall of the first hole, the gate insulating layer surrounds the semiconductor layer, and the gate electrode surrounds the gate insulating layer; and depositing a first conductive film in the first hole where the semiconductor layer is formed to form the bit line comprises:

[0032] Depositing a gate insulating film, a semiconductor film, and a first conductive film in the second groove, the first groove, and the first hole in sequence, and the semiconductor film fills the first groove, etching the gate insulating film, the semiconductor film, and the first conductive film in the second groove to a preset length to form the gate insulating layer, the semiconductor layer, and the bit line, and the first conductive film retained in the second groove forms a first part of a first source / drain electrode of the transistor;

[0033] A second portion of the first source / drain electrode is formed in the second groove, and the second portion of the first source / drain electrode overlaps the first portion of the first source / drain electrode.

[0034] In some embodiments, the second portion of the first source / drain electrode covers the bottom wall and sidewalls of the second groove; the method further includes: forming a second pole filling the second groove, and a dielectric layer disposed between the second pole and the first source / drain electrode.

[0035] In some embodiments, the second portion of the first source / drain electrode fills the second groove; the method also includes exposing an outer side wall of the second portion of the first source / drain electrode, the outer side wall including an end surface of the second portion of the first source / drain electrode facing away from the first portion of the first source / drain electrode, and each side wall connected to the end surface; forming a second pole surrounding the outer side wall, and forming a dielectric layer disposed between the outer side wall and the second pole.

[0036] In some embodiments, removing a portion of each of the sacrificial layers to form a plurality of first grooves communicating with the first holes comprises:

[0037] Performing lateral etching through the first hole to remove a portion of each of the sacrificial layers to form a plurality of first grooves communicating with the first hole;

[0038] Alternatively, before forming the first hole, the first part of each sacrificial layer is replaced with a dummy layer, and a second part of the sacrificial layer exists between the dummy layer and the first hole; after etching away the second part of the sacrificial layer, the dummy layer is etched away to form a plurality of first grooves connected to the first hole.

[0039] In some embodiments, the method further comprises:

[0040] A second hole penetrating the stacked structure is formed in each of the grooves, the second hole exposing the side wall of the sacrificial layer in the word line region but not exposing the side wall of the sacrificial layer in the memory cell region; a plurality of third grooves are formed by transversely etching the sacrificial layer in the word line region through each of the second holes, the third grooves connecting two second holes adjacent to each other along the first direction;

[0041] Depositing a second conductive film filling the third grooves in the plurality of third grooves, forming a third hole penetrating the stacked structure in the word line region, wherein the third hole disconnects the second conductive film of each third groove to form two disconnected connection electrodes, wherein the connection electrode is connected to the gate electrode, and a plurality of connection electrodes distributed along the second direction are connected to form a word line through a plurality of gate electrodes distributed along the second direction;

[0042] Alternatively, a second hole penetrating the stacked structure is formed in each of the grooves, the second hole exposing the side wall of the sacrificial layer in the word line region and not exposing the side wall of the sacrificial layer in the memory cell region; the sacrificial layer in the word line region is laterally etched through each of the second holes to form a plurality of third grooves, the third grooves connecting two second holes adjacent to each other along the first direction; and the second hole is enlarged along the second direction to expose the side wall of the sacrificial layer in the memory cell region;

[0043] A second conductive film filling the third grooves is deposited in the plurality of third grooves, and a third hole penetrating the stacked structure is formed in the word line region. The third hole disconnects the second conductive film of each of the third grooves to form two disconnected connecting electrodes, and the connecting electrode is connected to the gate electrode. A plurality of connecting electrodes distributed along the second direction are connected through a plurality of gate electrodes distributed along the second direction to form a word line.

[0044] In some embodiments, the method further comprises:

[0045] When patterning the stack structure, a plurality of third holes penetrating the stack structure are formed in the word line region;

[0046] After the third hole and the trench are filled with the second insulating layer, a second hole penetrating the stacked structure is formed in each of the trenches, and the second insulating layer in the third hole is removed, wherein the second hole exposes the side wall of the sacrificial layer in the word line region and does not expose the side wall of the sacrificial layer in the memory cell region; the sacrificial layer in the word line region is laterally etched through each of the second hole and the third hole to form a plurality of fourth grooves, wherein the fourth grooves are arranged between the second hole and the third hole and connect the second hole and the third hole;

[0047] A second conductive film filling the fourth grooves is deposited in the plurality of fourth grooves to form a connecting electrode connected to the gate electrode. The plurality of connecting electrodes distributed along the second direction are connected through the plurality of gate electrodes distributed along the second direction to form a word line.

[0048] An embodiment of the present disclosure provides an electronic device, comprising the semiconductor device described in any of the above embodiments, or a semiconductor device formed by the semiconductor device manufacturing method described in any of the above embodiments.

[0049] The present application includes a semiconductor device and a manufacturing method thereof, and an electronic device, wherein the semiconductor device includes: a plurality of transistors distributed in different layers and stacked in a direction perpendicular to the substrate; a bit line connected to the plurality of transistors in the different layers and extending in a direction perpendicular to the substrate; the transistor includes a gate electrode and a semiconductor layer, the semiconductor layer includes a first semiconductor sublayer extending in a direction parallel to the substrate and a second semiconductor sublayer extending in a direction perpendicular to the substrate, the first semiconductor sublayer includes a strip extending in a first direction, the second semiconductor sublayer is connected to the bit line, and the gate electrode extends in a direction parallel to the substrate and surrounds the strip. This embodiment provides a ring-gate semiconductor device that is easy to stack, which can simplify the process and improve the gate control capability.

[0050] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings.

[0051] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0053] Figure 1A A plan view of a semiconductor device provided for an exemplary embodiment; Figure 1B For along Figure 1A Cross-sectional view along the aa' direction; Figure 1C For along Figure 1A Cross-sectional view along the bb' direction; Figure 1D is a cross-sectional view along the cc' direction in 1A; Figure 1E For along Figure 1A Cross-sectional view along the dd' direction;

[0054] Figure 2A and Figure 2Bare cross-sectional views of a semiconductor device along the aa' direction and the dd' direction respectively provided by another exemplary embodiment;

[0055] FIG. 3A to FIG. 3D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after a stacked structure is formed, respectively, provided by an exemplary embodiment;

[0056] 4A to 4D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the first preset pattern is formed, respectively, provided by an exemplary embodiment. Figure 4E is a schematic diagram of the plane position of the first groove;

[0057] FIG. 5A to FIG. 5D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the third insulating layer is formed, respectively, provided by an exemplary embodiment;

[0058] Figures 6A to 6D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the first hole is formed, respectively, provided by an exemplary embodiment; Fig. 6E is a schematic diagram of the plane position of the first hole;

[0059] Figures 7A to 7D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after etching the sacrificial layer in the word line region provided by an exemplary embodiment;

[0060] FIG. 8A to FIG. 8D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after a word line structure layer is formed, respectively, provided by an exemplary embodiment;

[0061] 9A to 9D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after a word line is formed, respectively, provided by an exemplary embodiment; Fig.9E is a schematic diagram of the plane position of the second hole;

[0062] FIG. 10A to FIG. 10D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the fourth insulating layer is formed, respectively, provided by an exemplary embodiment;

[0063] FIG. 11A to FIG. 11D are cross-sectional views along the aa' direction, bb' direction, cc' direction, and dd' direction after the third hole is formed, respectively, according to an exemplary embodiment. Fig.11E is a schematic diagram of the plane position of the third hole;

[0064] FIG. 12A to FIG. 12DThey are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the first groove is formed, respectively, provided by an exemplary embodiment;

[0065] FIG. 13A to FIG. 13D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after forming a gate electrode according to an exemplary embodiment;

[0066] FIG. 14A to FIG. 14D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the gate electrodes of different layers are disconnected, respectively, provided by an exemplary embodiment;

[0067] FIG. 15A to FIG. 15D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after forming the fifth insulating layer and the sixth insulating layer, respectively, provided by an exemplary embodiment;

[0068] FIG. 16A to FIG. 16D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the second trench is formed, respectively, provided by an exemplary embodiment;

[0069] FIG. 17A to FIG. 17D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the second groove is formed, respectively, according to an exemplary embodiment;

[0070] 18A to 18D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after etching the gate electrode provided by an exemplary embodiment;

[0071] 19A to 19D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the seventh insulating layer is formed, respectively, provided by an exemplary embodiment;

[0072] FIG. 20A to FIG. 20D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the fifth insulating layer, the sixth insulating layer, and the seventh insulating layer are etched away, respectively, according to an exemplary embodiment;

[0073] FIG. 21A to FIG. 21D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after forming a gate insulating layer provided by an exemplary embodiment;

[0074] FIG. 22A to FIG. 22D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after forming a semiconductor layer and a bit line according to an exemplary embodiment;

[0075] FIG. 23A to FIG. 23DThey are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after etching the first portion, respectively, provided by an exemplary embodiment;

[0076] FIG. 24A to FIG. 24D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after etching the first portion, the semiconductor layer, and the gate insulating layer, respectively, provided by an exemplary embodiment;

[0077] FIG. 25A to FIG. 25D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the second portion is formed, respectively, provided by an exemplary embodiment;

[0078] FIG. 26A to FIG. 26D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the second parts of different layers are cut off, respectively, according to an exemplary embodiment;

[0079] FIG. 27A to FIG. 27D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after a dielectric layer is formed, respectively, provided by an exemplary embodiment;

[0080] FIG. 28A to FIG. 28D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the second pole is formed, respectively, according to an exemplary embodiment;

[0081] FIG. 29A to FIG. 29D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the eighth insulating layer is removed, respectively, provided by an exemplary embodiment;

[0082] FIG. 30A to FIG. 30D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the second preset pattern is formed, respectively, provided by an exemplary embodiment;

[0083] FIG. 31A to FIG. 31D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the third insulating layer is formed, respectively, provided by an exemplary embodiment;

[0084] FIG. 32A to FIG. 32D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after forming the first hole and the second hole, respectively, provided by an exemplary embodiment;

[0085] FIG. 33A to FIG. 33D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after etching the sacrificial layer in the word line region provided by an exemplary embodiment;

[0086] FIG. 34A to FIG. 34DThey are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after a word line structure layer is formed, respectively, provided by an exemplary embodiment;

[0087] FIG. 35A to FIG. 35D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after a word line is formed, respectively, provided by an exemplary embodiment;

[0088] FIG. 36A to FIG. 36D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after etching the third insulating layer, respectively, provided by an exemplary embodiment;

[0089] Fig.37 A cross-sectional view along the cc' direction after forming a word line structure layer is provided for an exemplary embodiment.

[0090] FIG. 38A to FIG. 38D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the fourth hole is formed, respectively, provided by an exemplary embodiment; Fig.38E is a schematic diagram of the plane position of the fourth hole;

[0091] FIG. 39A to FIG. 39D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after etching the sacrificial layer according to an exemplary embodiment;

[0092] FIG. 40A to FIG. 40D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after forming a dummy layer according to an exemplary embodiment;

[0093] Fig.41 A cross-sectional view along the cc' direction after etching the dummy layer is provided for an exemplary embodiment.

[0094] Fig.42 A cross-sectional view along the cc' direction after forming a tenth insulating layer is provided for an exemplary embodiment.

[0095] FIG. 43A to FIG. 43D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the third hole is formed, respectively, provided by an exemplary embodiment;

[0096] FIG. 44A to FIG. 44D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the first sub-groove is formed, respectively, provided by an exemplary embodiment;

[0097] Fig.45 A cross-sectional view along the aa' direction after forming the second sub-groove provided for an exemplary embodiment;

[0098] FIG. 46A to FIG. 46DThey are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after forming a gate electrode according to an exemplary embodiment;

[0099] FIG. 47A to FIG. 47D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the second trench is formed, respectively, provided by an exemplary embodiment;

[0100] FIG. 48A to FIG. 48D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after etching the gate electrode provided by an exemplary embodiment;

[0101] FIG. 49A to FIG. 49D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the fifth insulating layer and the sixth insulating layer are removed by etching according to an exemplary embodiment;

[0102] FIG. 50A to FIG. 50D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the second pole is formed, respectively, according to an exemplary embodiment;

[0103] FIG. 51A to FIG. 51D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after a word line is formed, respectively, provided by an exemplary embodiment;

[0104] FIG. 52A to FIG. 52D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the fourth insulating layer is formed, respectively, provided by an exemplary embodiment;

[0105] FIG. 53A to FIG. 53D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after a word line structure layer is formed, respectively, provided by an exemplary embodiment;

[0106] FIG. 54A to FIG. 54D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after a word line structure layer is formed, respectively, provided by an exemplary embodiment;

[0107] FIG. 55A to FIG. 55D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the second portion is formed, respectively, provided by an exemplary embodiment;

[0108] FIG. 56A to FIG. 56D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the second parts of different layers are cut off, respectively, according to an exemplary embodiment;

[0109] FIG. 57A to FIG. 57DThe cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the second portion is exposed are respectively provided for an exemplary embodiment;

[0110] FIG. 58A to FIG. 58D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after the second pole is formed, respectively, according to an exemplary embodiment;

[0111] FIG. 59A to FIG. 59D They are cross-sectional views along the aa' direction, the bb' direction, the cc' direction, and the dd' direction after a word line is formed, respectively, provided by an exemplary embodiment;

[0112] FIG. 60A to FIG. 60D They are cross-sectional views along aa', bb', cc' and dd' directions after forming the fourth insulating layer, respectively, provided for an exemplary embodiment. DETAILED DESCRIPTION

[0113] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0114] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by a person having ordinary skills in the field to which the present disclosure belongs.

[0115] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0116] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0117] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0118] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a physical connection or a signal connection, a contact connection or an integral connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0119] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0120] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0121] In the present disclosure, "connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0122] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0123] The "A and B are arranged in the same layer" mentioned in the present disclosure includes film layers formed of the same material or different materials located on the same film layer. Exemplarily, A and B are formed by forming the same film layer with the same material and then undergoing the same patterning process or different patterning processes. A and B arranged in the same layer may be located on the same horizontal plane but not necessarily on the same film layer, or located in different regions of the same film layer but not necessarily on the same horizontal plane.

[0124] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0125] In the embodiments of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0126] Figure 1A A schematic plan view of a semiconductor device provided as an exemplary embodiment, Figures 1B to 1E Along Figure 1A The cross-sectional view in the aa', bb', cc' and dd' directions. Figures 1A to 1E As shown, an embodiment of the present disclosure provides a semiconductor device, which may include a multi-layer memory cell array vertically stacked on a substrate 1; the multi-layer memory cell array may be distributed along a third direction Z. The third direction Z may be perpendicular to the substrate 1.

[0127] Each layer of the memory cell array may include a plurality of bit lines 30, a plurality of word lines 40, and a plurality of memory cells. The plurality of memory cells of the memory cell array may be arrayed along a first direction X and a second direction Y. The word lines 40 may be conductive lines extending along a second direction Y parallel to the substrate 1, and the plurality of word lines 40 of the memory cell array of the same layer may be spaced apart from each other, and the plurality of word lines 40 may be spaced apart from each other along the first direction X parallel to the substrate 1. The word lines 40 of memory cell arrays of different layers may be stacked on the substrate 1, and the word lines 40 at the same position of different layers may be spaced apart from each other.

[0128] The bit lines 30 may extend along a third direction Z, and the bit lines 30 may be distributed in an array along a first direction X and a second direction Y on the substrate 1 .

[0129] The memory cell may include a transistor and a capacitor connected to the transistor, and the transistor may include a gate electrode 26, a first electrode 51, and a second electrode 52. The second electrode 52 may be a part of a bit line 30, and the second electrodes 52 of transistors at the same position in different layers may be a part of the same bit line 30. The gate electrodes 26 of the memory cells in the same column of the same memory cell array may be connected to the same word line 40. The capacitor may include a first electrode 41 and a second electrode 42, and the first electrode 41 and the second electrode 42 are insulated by a dielectric layer 43.

[0130] In some embodiments, the word line 40 may include a plurality of independent connection electrodes distributed along the second direction Y. The plurality of connection electrodes of the same word line 40 are connected through the gate electrodes 26 of transistors in the same column distributed along the second direction Y.

[0131] In some embodiments, the plurality of connection electrodes may be connected to form a linear word line 40. The solution provided in this embodiment can make the semiconductor device compact and the process simple, but the disclosed embodiment is not limited thereto, the positions of the plurality of connection electrodes may be staggered, and the word line 40 formed by the connection may not be a straight line.

[0132] In some embodiments, the connection electrode may be connected to a region of the gate electrode 26 close to the bit line 30 .

[0133] The following description will be made by taking a semiconductor device including a group of memory cells stacked vertically at the same position as an example.

[0134] like Figures 1A to 1E As shown, an embodiment of the present disclosure provides a semiconductor device, which may include:

[0135] A plurality of transistors are distributed in different layers and stacked along a direction perpendicular to the substrate 1;

[0136] A bit line 30 connected to the plurality of transistors in different layers and extending in a direction perpendicular to the substrate 1;

[0137] The transistor includes a gate electrode 26 and a semiconductor layer 23, the semiconductor layer 23 may include a first semiconductor sublayer 231 extending in a direction parallel to the substrate 1 and a second semiconductor sublayer 232 extending in a direction perpendicular to the substrate 1, the first semiconductor sublayer 231 may include a strip portion 2311 extending in a first direction X, the second semiconductor sublayer 232 is connected to the bit line 30, and the gate electrode 26 extends in a direction parallel to the substrate 1 and surrounds the strip portion.

[0138] This embodiment provides a semiconductor device including a wraparound gate electrode, which can improve gate control capability and facilitate stacking.

[0139] In some embodiments, the second semiconductor sublayer 232 may surround the bit line 30. The surrounding may be a full surround, which fully surrounds the sidewall of the bit line 30, that is, on a plane parallel to the substrate 1, the cross section of the second semiconductor sublayer 232 may be a closed loop.

[0140] In some embodiments, on a plane perpendicular to the substrate 1 and the first direction X, the orthographic projection of the strip-shaped portion is located within the orthographic projection of the second semiconductor sublayer 232; the orthographic projection of the gate electrode 26 on the substrate 1 is located outside the orthographic projection of the second semiconductor sublayer 232 on the substrate 1. In this embodiment, the orthographic projection of the second semiconductor sublayer 232 is located outside the orthographic projection of the gate electrode 26, and the second semiconductor layer 232 is the semiconductor layer 23 at the end of the transistor. The semiconductor layer 23 at the end is widened to form a structure similar to CAA, thereby improving the gate control capability.

[0141] In some embodiments, the first semiconductor sublayer 231 may further include an end portion 2312 disposed at an end of the strip portion 2311 away from the bit line 30, and on a plane perpendicular to the substrate 1 and the first direction X, the orthographic projection of the strip portion 2311 is located within the orthographic projection of the end portion 2312, and the orthographic projection of the gate electrode 26 on the substrate 1 is located outside the orthographic projection of the end portion 2312 on the substrate 1. In this embodiment, the end portion 2312 of the semiconductor layer 23 is wider than the strip portion 2311, and a structure similar to a channel all around (CAA) can be formed to improve the gate control capability.

[0142] In some embodiments, the orthographic projection of the gate electrode 26 on the substrate 1 is located outside the orthographic projection of the second semiconductor sublayer 232 on the substrate 1 .

[0143] In some embodiments, the end portion 2312 is provided with a first groove with an opening away from the bit line 30, and the transistor further includes: a first source / drain electrode 51, and the first source / drain electrode 51 fills the first groove. The solution provided in this embodiment can increase the contact area between the first source / drain electrode 51 and the semiconductor layer 23.

[0144] In some embodiments, the first source / drain electrode 51 may include a first portion 511 filling the first groove and a second portion 512 disposed on a side of the first groove away from the bit line 30, and the second portion 512 overlaps the first portion 511. In this embodiment, the first source / drain electrode 51 may be divided into two portions, the first portion 511 and the second portion 512 may be manufactured separately, and the first portion 511 may be deposited and formed in sequence with the semiconductor layer 23 without being formed after etching the semiconductor layer 23, thereby not damaging the contact surface between the first portion 511 and the semiconductor layer 23, thereby improving device performance.

[0145] In some embodiments, the semiconductor layers 23 of the multiple transistors at the same position in different layers can be connected to form an integrated structure. The solution provided in this embodiment can form a semiconductor layer 23 of multiple transistors stacked vertically at one time, simplify the process, reduce costs, and facilitate the stacking of semiconductor devices with a large number of layers. At this time, the semiconductor layer 23 may include a longitudinal extension portion extending in a direction perpendicular to the substrate 1 and a plurality of lateral extension portions extending horizontally from the longitudinal extension portion to multiple layers, and the lateral extension portion is the first semiconductor sublayer 231. The semiconductor layer 23 forms an integrated structure by connecting the second semiconductor sublayer 232 to form an integrated structure.

[0146] In some embodiments, the arrangement direction of the transistor and the capacitor of the same storage unit is parallel to the first direction X. In the storage units of the same layer, the arrangement directions of the transistors and capacitors of the storage units adjacent along the first direction are opposite to each other; the semiconductor layers 23 of the storage units adjacent along the first direction and whose transistors are close to each other are connected to form an integrated structure. That is, two storage units adjacent along the first direction are taken as a group, the transistors of the storage units of the group are close to each other, and the capacitors are away from each other. The semiconductor layers of the storage units of the group can be formed at one time, thereby simplifying the process. Since the semiconductor layers 23 of the multiple transistors (referred to as transistors in a vertical column, distinguished from a column of transistors in the same layer, in this disclosure, when it is not specified as a vertical column, they are all a column of the same layer) in the same position of different layers can be connected to form an integrated structure, then, the semiconductor layers 23 of the transistors in two vertical columns adjacent along the first direction X can form an integrated structure.

[0147] In some embodiments, the semiconductor layer 23 of the integrated structure can be connected to the same bit line 30 and surround the connected bit line 30. At this time, a semiconductor film and a conductive film can be deposited in sequence in one hole to form a semiconductor layer and a bit line 30, and the semiconductor layer 23 of multiple memory cells and the bit lines 30 connected to the multiple memory cells can be formed at one time. In this embodiment, a portion of the bit line 30 serves as the second source / drain electrode 52 of the transistor.

[0148] In some embodiments, the transistor may further include a gate insulating layer 24 , wherein the gate insulating layer 24 is disposed between the gate electrode 26 and the semiconductor layer 23 , and the gate electrode 26 and the semiconductor layer 23 are insulated by the gate insulating layer 24 .

[0149] In some embodiments, the gate insulating layers 24 of the multiple transistors at the same position in different layers can be connected to form an integrated structure. In this embodiment, the gate insulating layers 24 of the stacked multiple transistors can be formed by one manufacturing process, simplifying the manufacturing process of the device with multiple stacked transistors.

[0150] In some embodiments, the gate insulating layers 24 of transistors in two adjacent vertical columns along the first direction X may form an integrated structure. This embodiment may further simplify the manufacturing process of a device with multiple transistor stacks.

[0151] In some embodiments, the bit line 30 may extend in a direction perpendicular to the substrate 1, may extend in a straight line direction, or may extend in a curved line direction. In some embodiments, the bit line 30 may be a straight line. The cross section of the straight bit line 30 along the direction parallel to the substrate 1 may be the same everywhere, or may not be completely the same. The embodiment of the present application does not limit the cross-sectional characteristics of the straight line.

[0152] In some embodiments, the cross-section of the bit line 30 on a plane parallel to the substrate 1 may be circular, square, elliptical, etc.

[0153] In some embodiments, the second portion 512 of the first source / drain electrode 51 also serves as the first pole 41 of the capacitor. The second portion 512 of the first source / drain electrode 51 may be provided with a second groove opening away from the bit line 30. The second pole 42 is insulated from the first source / drain electrode 51 by a dielectric layer 43 and fills the second groove.

[0154] In some embodiments, the second electrodes 42 of the capacitors of multiple vertical columns of memory cells arranged along the second direction may be connected to form an integrated structure, and the second electrode 42 of the integrated structure may include a longitudinal sub-electrode filling the grooves between adjacent memory cells along the second direction and extending in a direction perpendicular to the substrate 1, and a plurality of transverse sub-electrodes extending from the longitudinal sub-electrode to the second grooves of each layer, each transverse sub-electrode corresponding to a memory cell.

[0155] In some embodiments, the second portion 512 of the first source / drain electrode 51 may not have a second groove and is a block electrode, the second electrode 42 is provided with a third groove opening toward the bit line 30, the second portion 512 of the first source / drain electrode 51 is insulated from the second electrode 42 by a dielectric layer 43 and fills the third groove. Figure 2A and 2B As shown, Figure 2A A cross-sectional view of a semiconductor device along the aa' direction provided for another exemplary embodiment, Figure 2BA cross-sectional view of a semiconductor device along the dd' direction provided for another exemplary embodiment. In this embodiment, the structure of the transistor can refer to the previous embodiment and will not be repeated. The solution provided in this embodiment can increase the electrode area of ​​the capacitor, improve the capacitance, and do not increase the area occupied by the capacitor. In this embodiment, the second pole 42 of the capacitor of a plurality of vertical columns of storage cells arranged along the second direction can be connected to form an integrated structure, and the integrated structure fills the grooves between the adjacent storage cells along the second direction to form a planar electrode, and the planar electrode has a plurality of grooves, and the second portion 512 of the first source / drain electrode 51 is arranged in the groove and is insulated from the planar electrode by the dielectric layer 43.

[0156] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0157] In an exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0158] 101) forming a stacking structure;

[0159] The forming of the stacked structure may include: alternately depositing a first insulating film and a sacrificial layer film on the substrate 1 in sequence to form a stacked structure, such as Figure 3A , Figure 3B , Figure 3C and Figure 3D As shown, Figure 3A A cross-sectional view along the aa' direction after a stacked structure is formed provided by an exemplary embodiment; Figure 3B This is a cross-sectional view along the bb' direction after the stacking structure is formed. Figure 3C This is a cross-sectional view along the cc' direction after the stacking structure is formed. Figure 3DIt is a cross-sectional view along the dd' direction after the stacking structure is formed. The stacking structure may include multiple stackings of first insulating layers 10 and sacrificial layers 11 that are alternately arranged.

[0160] In some embodiments, the substrate 1 can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate can be a conventional silicon substrate or other bulk substrate including a semiconductor material layer.

[0161] In some embodiments, the first insulating film and the sacrificial layer film may be deposited by chemical vapor deposition.

[0162] In some embodiments, the first insulating film may be a low-K dielectric layer, that is, a dielectric layer having a dielectric constant K not greater than 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2) and the like.

[0163] In some embodiments, the sacrificial layer film may be an insulating material different from the first insulating film, such as silicon nitride (SiN).

[0164] Figure 3A The stacked structure shown in the figure includes four first insulating layers 10 and three sacrificial layers 11, which is only an example. In other embodiments, the stacked structure may include more or fewer first insulating layers 10 and sacrificial layers 11 that are alternately arranged. The topmost first insulating layer 10 may use a material different from that of other first insulating layers 10 as a hard mask layer.

[0165] 102) etching the stacked structure to form a first preset pattern;

[0166] The etching of the plurality of stacked structures to form a first preset pattern may include:

[0167] Depositing a second insulating film to form a second insulating layer 13;

[0168] The stacked structure is etched using a mask whose pattern is a first preset pattern, so that the first insulating layer 10 and the sacrificial layer 11 form a first preset pattern. The first preset pattern may include a memory cell area 100 and a word line area 200; the memory cell area 100 may extend along a first direction X, and the word line area 200 may extend along a second direction Y; the memory cell area 100 may include a capacitor area 101 and a transistor area 102, the capacitor area 101 is arranged on a side of the transistor area 102 away from the word line area 200, and a capacitor is subsequently formed in the capacitor area 101, a semiconductor layer 23, a gate electrode 26, etc. are formed in the transistor area 102, and a word line 40 and a bit line 30 are formed in the word line area 200. Figure 4A , Figure 4B, Figure 4C , Figure 4D and Figure 4E As shown, Figure 4A A cross-sectional view along the aa' direction after forming a first preset pattern provided by an exemplary embodiment; Figure 4B The cross-sectional view along the bb' direction after the first preset pattern is formed, Figure 4C A cross-sectional view along the cc' direction after forming the first preset pattern, Figure 4D A cross-sectional view along the dd' direction after the first preset pattern is formed, Figure 4E FIG. 2 is a schematic diagram of the plane position of the first trench T1. Figure 4E As shown, the film layer in the first trench T1 is etched away, and the film layer in the remaining area is retained to form a first preset pattern.

[0169] In some embodiments, the second insulating film may be made of an insulating material different from the first insulating film, including but not limited to SiN.

[0170] 103) forming a third insulating layer 14;

[0171] The forming of the third insulating layer 14 may include: depositing a third insulating film on the substrate 1 forming the aforementioned structure and grinding it flat to form the third insulating layer 14 filling the first trench T1; the third insulating layer 14 may be flush with the second insulating layer 13. Figure 5A , Figure 5B , Figure 5C and Figure 5D As shown, Figure 5A A cross-sectional view along the aa' direction after forming the third insulating layer 14 is provided for an exemplary embodiment. Figure 5B is a cross-sectional view along the bb' direction after the third insulating layer 14 is formed. Figure 5C is a cross-sectional view along the cc' direction after the third insulating layer 14 is formed. Figure 5D It is a cross-sectional view along the dd' direction after forming the third insulating layer 14. The third insulating layer 14 isolates a plurality of memory cells formed subsequently.

[0172] In some embodiments, the third insulating film may be made of an insulating material different from that of the second insulating film, such as SiO 2 .

[0173] 104) forming a first hole K1;

[0174] The forming of the first hole K1 may include: forming the first hole K1 penetrating the third insulating layer 14 in a direction perpendicular to the substrate 1, wherein the sidewall of the first hole K1 exposes the sacrificial layer 11 of the word line region 200 and does not expose the sacrificial layer 11 of the memory cell region 100, such as Fig. 6A , Figure 6B , Figure 6C , Fig.6D and Fig. 6E As shown, Fig. 6A A cross-sectional view along the aa' direction after the first hole K1 is formed is provided for an exemplary embodiment. Figure 6B This is a cross-sectional view along the bb' direction after the first hole K1 is formed. Figure 6C This is a cross-sectional view along the cc' direction after the first hole K1 is formed. Fig.6D This is a cross-sectional view along the dd' direction after the first hole K1 is formed. Fig. 6E is a schematic diagram of the plane position of the first hole K1. Figure 6C As shown, it can be seen that the third insulating layer 14 is retained on both sides of the sacrificial layer 11 in the cc′ direction, and the sacrificial layer 11 is protected by the retained third insulating layer 14 to prevent the sacrificial layer 11 from being etched away when the word line region 200 is subsequently etched.

[0175] 105) etching the sacrificial layer 11 of the word line region 200;

[0176] The etching of the sacrificial layer 11 in the word line area 200 may include: introducing an etching solution into the first hole K1, and laterally etching and removing the sacrificial layer 11 in the word line area 200, while not removing all of the sacrificial layer 11 in the word line area 200, and not removing the sacrificial layer 11 in the extending direction of the memory cell area 100, and forming the sacrificial layer 11 in the word line area 200 into a plurality of segments spaced apart along the second direction Y, such as Fig. 7A , Figure 7B , Figure 7C and Fig.7D As shown, Fig. 7A A cross-sectional view along the aa' direction after etching the sacrificial layer 11 of the word line region 200 provided in an exemplary embodiment, Figure 7B is a cross-sectional view along the bb' direction after etching the sacrificial layer 11 of the word line region 200, Figure 7C is a cross-sectional view along the cc' direction after etching the sacrificial layer 11 of the word line region 200, Fig.7D It is a cross-sectional view along the dd' direction after etching the sacrificial layer 11 of the word line region 200. It can be seen that in the aa' direction, the sacrificial layer 11 of the word line region 200 is not etched away (the sacrificial layer 11 extends continuously along the first direction X).

[0177] 106) forming a word line structure layer 40';

[0178] The forming of the word line structure layer 40' may include: depositing a first conductive film on the substrate 1 forming the aforementioned structure to form the word line structure layer 40', wherein the word line structure layer 40' fills the first hole K1 and the area where the sacrificial layer 11 of the word line region 200 is laterally etched. Fig. 8A , Figure 8B , Figure 8C and Fig.8D As shown, Fig. 8AFIG. 4 is a cross-sectional view along the aa′ direction after forming a word line structure layer 40′ according to an exemplary embodiment. Figure 8B It is a cross-sectional view along the bb' direction after the word line structure layer 40' is formed. Figure 8C is a cross-sectional view along the cc' direction after the word line structure layer 40' is formed. Fig.8D It is a cross-sectional view along the dd' direction after the word line structure layer 40' is formed.

[0179] In some embodiments, the first conductive film may be one or more of the following different types of materials:

[0180] For example, it may contain metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; it may be a metal alloy containing the aforementioned metals;

[0181] Alternatively, it may be a metal oxide, a metal nitride, a metal silicide, a metal carbide, etc., such as metal oxide materials with high conductivity such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO); for example, metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN);

[0182] Alternatively, it may be polysilicon material, conductive doped semiconductor material, etc., for example, conductive doped silicon, conductive doped germanium, conductive doped silicon germanium, etc.; other materials that embody conductivity, etc.

[0183] The subsequent second to fifth conductive films are similar to the first conductive film and are not described in detail.

[0184] 107) forming a word line 40;

[0185] The forming of the word line 40 may include: etching away the word line structure layer 40' in the first hole K1, and forming a plurality of second holes K2 penetrating the word line structure layer 40' and the first insulating layer 10 in a direction perpendicular to the substrate 1, wherein the plurality of second holes K2 disconnect the word line structure layer 40' to form two independent word lines 40, such as Fig. 9A , Fig. 9B , Fig. 9C , Fig.9D and Fig.9E As shown, Fig. 9A A cross-sectional view along the aa' direction after forming a word line 40 is provided for an exemplary embodiment. Fig. 9B is a cross-sectional view along the bb' direction after the word line 40 is formed. Fig. 9C is a cross-sectional view along the cc' direction after the word line 40 is formed. Fig.9D is a cross-sectional view along the dd' direction after the word line 40 is formed. Fig.9EThe word line 40 includes multiple segments, which are distributed along the second direction Y. The multiple segments are subsequently connected by gate electrodes 26 of multiple transistors distributed along the second direction Y.

[0186] In some embodiments, on a plane parallel to the substrate 1 , a cross section of the second hole K2 is, for example, square.

[0187] 108) forming a fourth insulating layer 15;

[0188] The forming of the fourth insulating layer 15 may include: depositing a fourth insulating film on the substrate 1 forming the aforementioned structure to form the fourth insulating layer 15, wherein the fourth insulating layer 15 fills the first hole K1 and the second hole K2; Fig. 10A , Fig. 10B , Fig. 10C and Fig. 10D As shown, Fig. 10A A cross-sectional view along the aa' direction after forming the fourth insulating layer 15 is provided for an exemplary embodiment. Fig. 10B is a cross-sectional view along the bb' direction after the fourth insulating layer 15 is formed. Fig. 10C is a cross-sectional view along the cc' direction after the fourth insulating layer 15 is formed. Fig. 10D It is a cross-sectional view along the dd' direction after the fourth insulating layer 15 is formed.

[0189] In some embodiments, the fourth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as SiO 2 .

[0190] 109) forming a third hole K3;

[0191] The forming of the third hole K3 may include: forming the third hole K3 penetrating the stacked structure in a direction perpendicular to the substrate 1, such as Fig.11A , Fig. 11B , Fig. 11C , Fig.11D and Fig.11E As shown, Fig.11A A cross-sectional view along the aa' direction after the third hole K3 is formed is provided for an exemplary embodiment. Fig. 11B This is a cross-sectional view along the bb' direction after the third hole K3 is formed. Fig. 11C This is a cross-sectional view along the cc' direction after the third hole K3 is formed. Fig.11D This is a cross-sectional view along the dd' direction after the third hole K3 is formed. Fig.11E Schematic diagram of the plane position of the third hole K3. The third hole K3 may be located in the word line region 200, and the third hole K3 penetrates the first insulating layer 10 and the sacrificial layer 11. A bit line 30 may be formed in the third hole K3 later.

[0192] In some embodiments, on a plane parallel to the substrate 1 , a cross-section of the third hole K3 may be square, circular, elliptical, etc.

[0193] 110) forming a first groove A1;

[0194] The forming of the first groove A1 may include: removing the sacrificial layer 11 of the transistor region 102 by lateral etching through the third hole K3 to form the first groove A1; at this time, the sacrificial layer 11 of the capacitor region 101 is retained, such as Fig. 12A , Fig. 12B , Fig. 12C and Fig.12D As shown, Fig. 12A A cross-sectional view along the aa' direction after the first groove A1 is formed according to an exemplary embodiment. Fig. 12B This is a cross-sectional view along the bb' direction after the first groove A1 is formed. Fig. 12C This is a cross-sectional view along the cc' direction after the first groove A1 is formed. Fig.12D It is a cross-sectional view along the dd' direction after the first groove A1 is formed. Subsequently, a gate electrode 26 is formed in the first groove A1.

[0195] In some embodiments, the sacrificial layer 11 can be removed by dry lateral etching, for example, by performing lateral long-distance dry lateral etching by free radicals generated by remote plasma to remove the sacrificial layer 11 of the transistor area 102. The solution provided in this embodiment forms the area where the semiconductor layer is located at one time, reducing the steps of photolithography and etching. However, the embodiments of the present disclosure are not limited to this, and the first groove A1 can be formed by other methods. However, the embodiments of the present disclosure are not limited to this, and the sacrificial layer 11 can be removed by wet lateral etching. Compared with wet etching, dry etching is faster and has better process controllability.

[0196] 111) forming a gate electrode 26;

[0197] The gate electrode 26 may include: depositing a second conductive film on the substrate 1 forming the aforementioned structure to form a gate electrode 26 covering the inner wall of the first groove A1 and the inner wall of the third hole K3 (including the bottom wall and side wall of the third hole K3), such as Fig.13A , Fig. 13B , Fig. 13C and Fig.13D As shown, Fig.13A A cross-sectional view along the aa' direction after forming the gate electrode 26 is provided for an exemplary embodiment. Fig. 13B is a cross-sectional view along the bb' direction after the gate electrode 26 is formed. Fig. 13C is a cross-sectional view along the cc' direction after the gate electrode 26 is formed. Fig.13D It is a cross-sectional view along the dd′ direction after the gate electrode 26 is formed.

[0198] In some embodiments, a high temperature process may be selected to form the gate electrode 26 to improve the electron mobility of the gate electrode 26. In the solution provided in this embodiment, the gate electrode 26 is formed before the semiconductor layer 23 is formed. Compared with the solution of forming the gate electrode 26 after the semiconductor layer 23 is formed, since there is no need to consider the damage of the semiconductor layer 23 caused by the high temperature process, the gate electrode 26 has a wider range of optional materials and optional processes, and a material with better conductive properties can be selected, and a better crystal phase can be obtained by manufacturing through a high temperature process, thereby improving the conductivity of the gate electrode 26.

[0199] 112) disconnecting the gate electrodes 26 of different layers;

[0200] The disconnecting of the gate electrodes 26 of different layers may include: etching and removing the gate electrodes 26 located in the third hole K3 to disconnect the gate electrodes 26 of different layers, such as Fig.14A , Fig. 14B , Fig. 14C and Fig.14D As shown, Fig.14A A cross-sectional view along the aa' direction after disconnecting the gate electrodes 26 of different layers provided by an exemplary embodiment, Fig. 14B is a cross-sectional view along the bb' direction after disconnecting the gate electrodes 26 of different layers. Fig. 14C is a cross-sectional view along the cc' direction after disconnecting the gate electrodes 26 of different layers, Fig.14D It is a cross-sectional view along the dd' direction after the gate electrodes 26 of different layers are disconnected. At this time, the gate electrodes 26 are only distributed in the first groove A1.

[0201] In some embodiments, the gate electrode 26 in the third hole K3 may be removed by etching using a dry etching method.

[0202] 113) forming a fifth insulating layer 16 and a sixth insulating layer 17;

[0203] A fifth insulating film is deposited on the substrate 1 having the aforementioned structure and then ground to form a fifth insulating layer 16 filling the first groove A1 and the third hole K3;

[0204] Depositing a sixth insulating film to form a sixth insulating layer 17, such as Fig.15A , Fig. 15B , Fig. 15C and Fig.15D As shown, Fig.15A A cross-sectional view along the aa' direction after forming the fifth insulating layer 16 and the sixth insulating layer 17 is provided for an exemplary embodiment. Fig. 15B is a cross-sectional view along the bb' direction after the fifth insulating layer 16 and the sixth insulating layer 17 are formed. Fig. 15C is a cross-sectional view along the cc' direction after the fifth insulating layer 16 and the sixth insulating layer 17 are formed, Fig.15DIt is a cross-sectional view along the dd′ direction after the fifth insulating layer 16 and the sixth insulating layer 17 are formed.

[0205] In some embodiments, the fifth insulating film may be a film layer having a higher etching selectivity ratio with the first insulating film, such as SiN.

[0206] In some embodiments, the sixth insulating film may be a low-K dielectric layer, including but not limited to silicon oxide, such as SiO 2 .

[0207] 114) forming a second trench T2;

[0208] The forming of the second trench T2 may include: forming a second trench T2 penetrating the stacked structure along a direction perpendicular to the substrate 1 at an end of the capacitor region 101 away from the bit line 30, wherein the sidewall of the second trench T2 exposes the sacrificial layer 11 so as to subsequently remove the sacrificial layer 11 of the capacitor region 101, such as Fig.16A , Fig. 16B , Fig. 16C and Fig.16D As shown, Fig.16A A cross-sectional view along the aa' direction after forming the second trench T2 is provided for an exemplary embodiment. Fig. 16B is a cross-sectional view along the bb' direction after the second trench T2 is formed. Fig. 16C This is a cross-sectional view along the cc' direction after the second trench T2 is formed. Fig.16D It is a cross-sectional view along the dd' direction after the second trench T2 is formed.

[0209] 115) forming a second groove A2;

[0210] The forming of the second groove A2 may include: removing the sacrificial layer 11 of the capacitor region 101 by lateral etching through the second trench T2 to form the second groove A2. Fig.17A , Fig. 17B , Fig. 17C and Fig.17D As shown, Fig.17A A cross-sectional view along the aa' direction after the second groove A2 is formed is provided for an exemplary embodiment. Fig. 17B This is a cross-sectional view along the bb' direction after the second groove A2 is formed. Fig. 17C This is a cross-sectional view along the cc' direction after the second groove A2 is formed. Fig.17D It is a cross-sectional view along the dd' direction after the second groove A2 is formed.

[0211] 116) etching the gate electrode 26;

[0212] The etching of the gate electrode 26 may include: etching and removing the side wall of the gate electrode 26 extending in a direction perpendicular to the substrate 1 (i.e., the bottom wall of the first groove A1), so that the gate electrode 26 forms a ring-shaped membrane layer with double-side openings (previously, a ring-shaped membrane layer with single-side openings), such as Fig.18A , Fig.18B , Fig.18C and Fig.18D As shown, Fig.18A A cross-sectional view along the aa' direction after etching the gate electrode 26 provided in an exemplary embodiment. Fig.18B is a cross-sectional view along the bb' direction after etching the gate electrode 26, Fig.18C is a cross-sectional view along the cc' direction after etching the gate electrode 26, Fig.18D It is a cross-sectional view along the dd' direction after etching the gate electrode 26.

[0213] In some embodiments, the sidewalls of the gate electrode 26 extending in a direction perpendicular to the substrate 1 may be removed by wet etching.

[0214] 117) forming a seventh insulating layer 18;

[0215] The forming of the seventh insulating layer 18 may include: depositing a seventh insulating film on the substrate 1 forming the aforementioned structure to form the seventh insulating layer 18, wherein the seventh insulating layer 18 fills the second trench T2 and the second groove A2, such as Fig.19A , Fig.19B , Fig.19C and Fig.19D As shown, Fig.19A A cross-sectional view along the aa' direction after the seventh insulating layer 18 is formed is provided for an exemplary embodiment. Fig.19B is a cross-sectional view along the bb' direction after the seventh insulating layer 18 is formed. Fig.19C is a cross-sectional view along the cc' direction after the seventh insulating layer 18 is formed. Fig.19D It is a cross-sectional view along the dd′ direction after the seventh insulating layer 18 is formed.

[0216] In some embodiments, the seventh insulating film may be made of a material having a higher etching selectivity ratio with the gate electrode 26 , such as SiN, carbon, aluminum oxide (Al 2 O 3 ), etc.

[0217] 118) etching and removing the fifth insulating layer 16, the sixth insulating layer 17 and the seventh insulating layer 18;

[0218] The etching and removing the fifth insulating layer 16, the sixth insulating layer 17 and the seventh insulating layer 18 may include: grinding or dry etching and removing the sixth insulating layer 17 to expose the fifth insulating layer 16;

[0219] The fifth insulating layer 16 (ie, the fifth insulating layer 16 filled in the first groove A1 and the third hole K3) and the seventh insulating layer 18 are removed by etching. Fig. 20A , Fig. 20B , Fig. 20C and Fig.20D As shown, Fig. 20A A cross-sectional view along the aa' direction after the fifth insulating layer 16, the sixth insulating layer 17 and the seventh insulating layer 18 are removed by etching according to an exemplary embodiment. Fig. 20B It is a cross-sectional view along the bb' direction after the fifth insulating layer 16, the sixth insulating layer 17 and the seventh insulating layer 18 are etched away. Fig. 20C It is a cross-sectional view along the cc' direction after the fifth insulating layer 16, the sixth insulating layer 17 and the seventh insulating layer 18 are etched away. Fig.20D The cross-sectional view along the dd' direction after etching away the fifth insulating layer 16, the sixth insulating layer 17 and the seventh insulating layer 18. At this time, the third hole K3, the first groove A1, the second groove A2 and the second trench T2 are connected, which facilitates the subsequent one-time formation of the bit line 30 and the semiconductor layer 23. In some embodiments, the fifth insulating layer 16 can be removed by wet etching.

[0220] 119) forming a gate insulating layer 24;

[0221] The forming of the gate insulating layer 24 may include: depositing a gate insulating film on the substrate 1 having the above structure to form the gate insulating layer 24, such as Fig.21A , Fig.21B , Fig. 21C and Fig.21D As shown, Fig.21A A cross-sectional view along the aa' direction after forming the gate insulating layer 24 is provided for an exemplary embodiment. Fig.21B is a cross-sectional view along the bb' direction after the gate insulating layer 24 is formed. Fig. 21C is a cross-sectional view along the cc' direction after the gate insulating layer 24 is formed. Fig.21D It is a cross-sectional view along the dd′ direction after the gate insulating layer 24 is formed.

[0222] In some embodiments, the gate insulating film may include one or more layers of High-K dielectric material, such as a dielectric material with a dielectric constant K>3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0223] 120) forming a semiconductor layer 23, a bit line 30 and a first portion 511 of a first source / drain electrode 51;

[0224] The forming of the semiconductor layer 23, the bit line 30 and the first part 511 of the first source / drain electrode 51 may include: depositing a semiconductor film and a third conductive film in sequence on the substrate 1 forming the aforementioned structure to form the semiconductor layer 23, the bit line 30 and the first part 511 of the first source / drain electrode 51; wherein the semiconductor layer 23 covers the surface of the gate insulating layer 24 and fills the first groove A1, the bit line 30 fills the third hole K3, the semiconductor layer 23 surrounds the bit line 30, the gate insulating layer 24 surrounds the semiconductor layer 23, the gate electrode 26 surrounds the gate insulating layer 24, the first part 511 of the first source / drain electrode 51 fills the second groove A2 and the second trench T2, and is disconnected from the bit line 30 (separated by the semiconductor layer 23), as shown in FIG. Fig.22A , Fig. 22B , Fig. 22C and Fig.22D As shown, Fig.22A A cross-sectional view along the aa' direction after forming the semiconductor layer 23 and the bit line 30 is provided for an exemplary embodiment. Fig. 22B FIG. 2 is a cross-sectional view along the bb' direction after the semiconductor layer 23 and the bit line 30 are formed. Fig. 22C is a cross-sectional view along the cc' direction after the semiconductor layer 23 and the bit line 30 are formed. Fig.22D It is a cross-sectional view along the dd′ direction after the semiconductor layer 23 and the bit line 30 are formed.

[0225] In this embodiment, the thickness of the gate electrode 26 can be controlled so that the semiconductor layer 23 can fill the first groove A1 when the semiconductor film is deposited.

[0226] In some embodiments, the semiconductor layer 23 widens at the end of the transistor (the end of the transistor region 102 close to the capacitor region 101 ) to form a structure similar to a channel all around (CAA) to ensure the gate control capability at the end of the transistor.

[0227] In some embodiments, the material of the semiconductor layer 23 may be silicon or polysilicon with a band gap less than 1.65 eV, or may be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0228] For example, the material of the metal oxide semiconductor layer or channel may include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may contain compounds of other elements, such as N, Si, etc., and may contain other small amounts of doping elements.

[0229] In some embodiments, the material of the metal oxide semiconductor layer or the channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.

[0230] These materials have a wide band gap and a low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A, thereby improving the working performance of dynamic memory.

[0231] The material of the metal oxide semiconductor layer or channel only emphasizes the element type of the material, and does not emphasize the atomic proportion in the material and the film quality of the material.

[0232] 121) etching the first portion 511 of the first source / drain electrode 51;

[0233] The etching of the first portion 511 of the first source / drain electrode 51 may include:

[0234] Depositing an eighth insulating film to form an eighth insulating layer 19, wherein the eighth insulating layer 19 covers the stacked structure and is used to protect the film layer in the third hole K3;

[0235] The first portion 511 in the second trench T2 is removed by dry etching to facilitate the subsequent lateral etching of the film layer in the second groove A2; Fig.23A , Fig. 23B , Fig.23C and Fig.23D As shown, Fig.23A A cross-sectional view along the aa' direction after etching the first portion 511 provided in an exemplary embodiment, Fig. 23B is a cross-sectional view along the bb' direction after etching the first portion 511, Fig.23Cis a cross-sectional view along the cc' direction after etching the first portion 511, Fig.23D It is a cross-sectional view along the dd' direction after etching the first portion 511 .

[0236] 122) etching the first portion 511, the semiconductor layer 23 and the gate insulating layer 24;

[0237] The etching of the first portion 511, the semiconductor layer 23, and the gate insulating layer 24 may include: etching away the semiconductor layer 23 and the gate insulating layer 24 in the second trench T2, and etching the first portion 511, the semiconductor layer 23, and the gate insulating layer 24 of a preset length in the second groove A2, and retaining a portion of the first portion 511, the semiconductor layer 23, and the gate insulating layer 24, such as Fig.24A , Fig. 24B , Fig.24C and Fig.24D As shown, Fig.24A A cross-sectional view along the aa' direction after etching the first portion 511, the semiconductor layer 23 and the gate insulating layer 24 is provided for an exemplary embodiment. Fig. 24B It is a cross-sectional view along the bb' direction after etching the first portion 511, the semiconductor layer 23 and the gate insulating layer 24. Fig.24C is a cross-sectional view along the cc' direction after etching the first portion 511, the semiconductor layer 23 and the gate insulating layer 24. Fig.24D It is a cross-sectional view along the dd′ direction after etching the first portion 511 , the semiconductor layer 23 , and the gate insulating layer 24 .

[0238] The first source / drain electrode 51 contacts the semiconductor layer 23 through the first portion 511. Therefore, retaining part of the first portion 511 can improve the contact performance between the semiconductor layer 23 and the first source / drain electrode 51. If part of the first portion 511 is not retained, the semiconductor layer 23 is easily damaged by etching, and the semiconductor layer 23 is in direct contact with the subsequently formed first source / drain electrode 51, and the contact performance is not as good as the contact performance between the first portion 511 and the semiconductor layer 23. The retained first portion 511 can be as small as possible to leave more space for the subsequent formation of the capacitor.

[0239] 123) forming a second portion 512 of the first source / drain electrode 51;

[0240] The forming of the second portion 512 of the first source / drain electrode 51 may include: depositing a fourth conductive film on the substrate 1 forming the aforementioned structure to form the second portion 512 of the first source / drain electrode 51, such as Fig.25A , Fig.25B , Fig.25C and Fig.25D As shown, Fig.25A A cross-sectional view along the aa' direction after the second portion 512 is formed is provided for an exemplary embodiment. Fig.25B This is a cross-sectional view along the bb' direction after the second portion 512 is formed. Fig.25C This is a cross-sectional view along the cc' direction after the second portion 512 is formed. Fig.25D 2 is a cross-sectional view along the dd' direction after the second portion 512 is formed. The second portion 512 covers the inner wall of the second groove A2, is connected to the first portion 511, and is connected to the semiconductor layer 23, and is insulated from the gate electrode 26 by the gate insulating layer 24. The second portion 512 also covers the sidewall of the second trench T2, so at this time, the second portions 512 of different layers are connected together.

[0241] 124) disconnecting the second portion 512 of the different layers;

[0242] The disconnecting of the second portion 512 of different layers may include: etching and removing the second portion 512 located in the second trench T2 to disconnect the second portion 512 of different layers, such as Fig.26A , Fig.26B , Fig.26C and Fig.26D As shown, Fig.26A A cross-sectional view along the aa' direction after the second portion 512 of different layers is cut off according to an exemplary embodiment. Fig.26B The cross-sectional view along the bb' direction after the second portion 512 of different layers is disconnected, Fig.26C This is a cross-sectional view along the cc' direction after the second portion 512 of different layers is disconnected. Fig.26D It is a cross-sectional view along the dd' direction after the second portion 512 of different layers is disconnected. The second portion 512 of the first source / drain electrode 51 also serves as the first electrode 41 of the capacitor.

[0243] 125) forming a dielectric layer 43;

[0244] The forming of the dielectric layer 43 may include: depositing a dielectric layer film on the substrate 1 having the aforementioned structure to form the dielectric layer 43, such as Fig.27A , Fig.27B , Fig.27C and Fig.27D As shown, Fig.27A A cross-sectional view along the aa' direction after forming the dielectric layer 43 is provided for an exemplary embodiment. Fig.27B is a cross-sectional view along the bb' direction after the dielectric layer 43 is formed. Fig.27C is a cross-sectional view along the cc' direction after the dielectric layer 43 is formed. Fig.27D It is a cross-sectional view along the dd' direction after the dielectric layer 43 is formed. The dielectric layer 43 covers the surface of the second portion 512 of the first source / drain electrode 51 away from the semiconductor layer 23, and covers the sidewalls and bottom wall of the second trench T2.

[0245] In some embodiments, the dielectric layer film may be a Low-K material, such as silicon oxide. Or it may be a High-K material. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary, for example, it may include but is not limited to at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2) and other high-K materials.

[0246] 126) forming a second pole 42;

[0247] The forming of the second electrode 42 may include: depositing a fifth conductive film on the substrate 1 forming the aforementioned structure to form the second electrode 42, wherein the second electrode 42 fills the second trench T2 and the second groove A2, such as Fig.28A , Fig.28B , Fig.28C and Fig.28D As shown, Fig.28A A cross-sectional view along the aa' direction after forming the second pole 42 provided in an exemplary embodiment, Fig.28B It is a cross-sectional view along the bb' direction after the second pole 42 is formed. Fig.28C This is a cross-sectional view along the cc' direction after the second pole 42 is formed. Fig.28D It is a cross-sectional view along the dd' direction after the second pole 42 is formed.

[0248] 127) removing the eighth insulating layer 19;

[0249] The removing of the eighth insulating layer 19 may include: removing the eighth insulating layer 19 by grinding or etching to expose the bit line 30, so as to facilitate the connection between other devices and the memory cell, such as Fig.29A , Fig.29B , Fig.29C and Fig.29D As shown, Fig.29A A cross-sectional view along the aa' direction after the eighth insulating layer 19 is removed is provided for an exemplary embodiment. Fig.29B is a cross-sectional view along the bb' direction after the eighth insulating layer 19 is removed. Fig.29C is a cross-sectional view along the cc' direction after the eighth insulating layer 19 is removed. Fig.29D It is a cross-sectional view along the dd' direction after removing the eighth insulating layer 19. However, the embodiment of the present disclosure is not limited thereto, and the eighth insulating layer 19 may not be removed according to the needs of the subsequent manufacturing process.

[0250] In another exemplary embodiment, a process for manufacturing the semiconductor device may include:

[0251] 201), same as 101), forming FIG. 3A to FIG. 3D The stacking structure shown.

[0252] 202) etching the stacked structure to form a second preset pattern;

[0253] The etching of the plurality of stacked structures to form a second preset pattern may include:

[0254] Depositing a second insulating film to form a second insulating layer 13;

[0255] The stack structure is etched to form a first trench T1 and a second hole K2 that penetrates the stack structure; the first trench T1 enables the first insulating layer 10 and the sacrificial layer 11 to form a second preset pattern; the first trench T1 defines a memory cell area 100 and a word line area 200, and the second hole K2 is arranged in the word line area 200 to disconnect the areas where two adjacent word lines are located; the memory cell area 100 can extend along a first direction X, and the word line area 200 can extend along a second direction Y; Fig. 30A , Fig. 30B , Fig. 30C and Fig.30D As shown, Fig. 30A A cross-sectional view along the aa' direction after forming a second preset pattern provided by an exemplary embodiment; Fig. 30B The cross-sectional view along the bb' direction after the second preset pattern is formed, Fig. 30C A cross-sectional view along the cc' direction after forming the second preset pattern, Fig.30D It is a cross-sectional view along the dd' direction after the second preset pattern is formed.

[0256] 203) forming a third insulating layer 14;

[0257] The forming of the third insulating layer 14 may include: depositing a third insulating film on the substrate 1 forming the aforementioned structure and grinding it flat to form a third insulating layer 14 filling the first trench T1 and the second hole K2; the third insulating layer 14 may be flush with the second insulating layer 13. Fig.31A , Fig.31B , Fig.31C and Fig.31D As shown, Fig.31A A cross-sectional view along the aa' direction after forming the third insulating layer 14 is provided for an exemplary embodiment. Fig.31B is a cross-sectional view along the bb' direction after the third insulating layer 14 is formed. Fig.31C is a cross-sectional view along the cc' direction after the third insulating layer 14 is formed. Fig.31D It is a cross-sectional view along the dd' direction after forming the third insulating layer 14. The third insulating layer 14 isolates a plurality of memory cells formed subsequently.

[0258] 204) forming a first hole K1 and a second hole K2;

[0259] The forming of the first hole K1 and the second hole K2 may include: forming the first hole K1 and the second hole K2 penetrating the third insulating layer 14 in a direction perpendicular to the substrate 1, wherein the sidewall of the first hole K1 exposes the sacrificial layer 11 of the word line region 200 and does not expose the sacrificial layer 11 of the memory cell region 100, such as Fig.32A , Fig.32B , Fig.32C and Fig.32D As shown, Fig.32A A cross-sectional view along the aa' direction after forming the first hole K1 and the second hole K2 provided in an exemplary embodiment, Fig.32B This is a cross-sectional view along the bb' direction after the first hole K1 and the second hole K2 are formed. Fig.32C This is a cross-sectional view along the cc' direction after the first hole K1 and the second hole K2 are formed. Fig.32D It is a cross-sectional view along the dd' direction after the first hole K1 and the second hole K2 are formed. Fig.32C As shown, it can be seen that the sacrificial layer 11 in the cc′ direction is protected by the third insulating layer 14 and is not exposed, thereby preventing the sacrificial layer 11 in the memory cell area 100 from being etched away when the sacrificial layer 11 in the word line area 200 is subsequently etched.

[0260] 205) etching the sacrificial layer 11 of the word line region 200;

[0261] The step of etching the sacrificial layer 11 in the word line region 200 may include: introducing an etching solution into the first hole K1, and laterally etching and removing the sacrificial layer between the first hole K1 and the second hole K2, such as Fig.33A , Fig.33B , Fig.33C and Fig.33D As shown, at this time, part of the sacrificial layer 11 in the word line area 200 is removed, and part of the sacrificial layer is not removed, that is, the sacrificial layer 11 in the extending direction of the memory cell area 100 is not removed, and the sacrificial layer 11 in the word line area 200 forms a plurality of segments spaced along the second direction Y (similar to Fig.33C and Fig.33D The sacrificial layer 11 shown in FIG. Fig.33A A cross-sectional view along the aa' direction after etching the sacrificial layer 11 of the word line region 200 provided in an exemplary embodiment, Fig.33B is a cross-sectional view along the bb' direction after etching the sacrificial layer 11 of the word line region 200, Fig.33C is a cross-sectional view along the cc' direction after etching the sacrificial layer 11 of the word line region 200, Fig.33D It is a cross-sectional view along the dd' direction after etching the sacrificial layer 11 of the word line region 200. It can be seen that in the aa' direction, the sacrificial layer 11 of the word line region 200 is not etched away (in the aa' direction, the sacrificial layer 11 extends continuously along the first direction X).

[0262] 206) forming a word line structure layer 40';

[0263] The forming of the word line structure layer 40' may include: depositing a first conductive film on the substrate 1 forming the aforementioned structure to form the word line structure layer 40'. In this embodiment, the word line structure layer 40' fills the first hole K1, the second hole K2 and the area where the sacrificial layer 11 of the word line region 200 is laterally etched, such as Fig.34A , Fig.34B , Fig.34C and Fig.34D As shown, Fig.34A FIG. 4 is a cross-sectional view along the aa′ direction after forming a word line structure layer 40′ according to an exemplary embodiment. Fig.34B It is a cross-sectional view along the bb' direction after the word line structure layer 40' is formed. Fig.34C is a cross-sectional view along the cc' direction after the word line structure layer 40' is formed. Fig.34D It is a cross-sectional view along the dd' direction after the word line structure layer 40' is formed.

[0264] 207) forming a word line 40;

[0265] The forming of the word line 40 may include: etching and removing the word line structure layer 40' in the first hole K1 and the second hole K2 to form two independent word lines 40, such as Fig.35A , Fig.35B , Fig.35C and Fig.35D As shown, Fig.35A A cross-sectional view along the aa' direction after forming a word line 40 is provided for an exemplary embodiment. Fig.35B is a cross-sectional view along the bb' direction after the word line 40 is formed. Fig.35C is a cross-sectional view along the cc' direction after the word line 40 is formed. Fig.35D The cross-sectional view along the dd' direction after the word line 40 is formed. Each of the word lines 40 includes multiple segments, and the multiple segments are distributed along the second direction Y. Subsequently, the multiple segments are connected by the gate electrodes 26 of multiple transistors distributed along the second direction Y. Compared with the previous embodiment, the solution provided in this embodiment does not need to etch the stack formed by the metal and the insulating film layer at the location of the second hole K2, and the metal can be directly etched. Compared with etching the stack formed by the metal and the insulating film layer, the process difficulty can be reduced. In addition, compared with the subsequent two embodiments, it can avoid damaging the gate electrode during the word line truncation process.

[0266] 208)~227), same as 108)~127), no further details will be given.

[0267] The solution provided in this embodiment uses another method to form the word line 40, which can avoid etching the metal insulation layer stack.

[0268] In another exemplary embodiment, a process for manufacturing a semiconductor device may include:

[0269] 301)~305), same as steps 101~105, forming Figures 7A to 7D The structure shown;

[0270] 306) The third insulating layer 14 is etched to enlarge the first hole K1 so that the sidewall of the first hole K1 exposes the sacrificial layer 11 of the memory cell area 100, that is, the third insulating layer 14 retained on both sides of the sacrificial layer 11 in the cc' direction in step 304 is etched away. Fig.36A , Fig.36B , Fig.36C and Fig.36D As shown, Fig.36A A cross-sectional view along the aa' direction after etching the third insulating layer 14 is provided for an exemplary embodiment. Fig.36B is a cross-sectional view along the bb' direction after etching the third insulating layer 14. Fig.36C is a cross-sectional view along the cc' direction after etching the third insulating layer 14, Fig.36D It is a cross-sectional view along the dd' direction after etching the third insulating layer 14.

[0271] 307) forming a word line structure layer 40';

[0272] The forming of the word line structure layer 40' may include: depositing a first conductive film on the substrate 1 forming the aforementioned structure to form the word line structure layer 40', wherein the word line structure layer 40' fills the first hole K1 (the first hole K1 enlarged in step 306) and the area where the sacrificial layer 11 of the word line region 200 is laterally etched, such as Fig.37 As shown, Fig.37 A cross-sectional view along the cc' direction after forming the word line structure layer 40' is provided for an exemplary embodiment. The cross-sectional views along the aa' direction, the bb' direction and the dd' direction can be referred to Fig. 8A , Figure 8B and Fig.8D , omitted here.

[0273] 308) forming a fourth hole K4;

[0274] The forming of the fourth hole K4 may include: forming a fourth hole K4 penetrating the third insulating layer 14 in a direction perpendicular to the substrate 1, wherein the sidewall of the fourth hole K4 exposes the sacrificial layer 11 of the transistor region 102 and does not expose the sacrificial layer 11 of the capacitor region 101, and exposes the word line structure layer 40', such as Fig.38A , Fig.38B , Fig.38C , Fig.38D and Fig.38E As shown, Fig.38AA cross-sectional view along the aa' direction after the fourth hole K4 is formed is provided for an exemplary embodiment. Fig.38B This is a cross-sectional view along the bb' direction after the fourth hole K4 is formed. Fig.38C This is a cross-sectional view along the cc' direction after the fourth hole K4 is formed. Fig.38D This is a cross-sectional view along the dd' direction after the fourth hole K4 is formed. Fig.38E Schematic diagram of the plane position of the fourth hole K4.

[0275] 309) etching the sacrificial layer 11;

[0276] The etching of the sacrificial layer 11 may include: laterally etching the sacrificial layer 11 exposed by the sidewall of the fourth hole K4 through the fourth hole K4, such as Fig.39A , Fig.39B , Fig.39C and Fig.39D As shown, Fig.39A A cross-sectional view along the aa' direction after etching the sacrificial layer 11 provided in an exemplary embodiment. Fig.39B It is a cross-sectional view along the bb' direction after etching the sacrificial layer 11. Fig.39C is a cross-sectional view along the cc' direction after etching the sacrificial layer 11, Fig.39D It is a cross-sectional view along the dd' direction after etching the sacrificial layer 11.

[0277] 310) forming a dummy layer 9;

[0278] The forming of the dummy layer 9 may include: depositing a dummy layer thin film on the substrate 1 forming the aforementioned structure to form the dummy layer 9, wherein the dummy layer 9 fills the fourth hole K4 and the area where the sacrificial layer 11 etched away in step 309 is located. Fig.40A , Fig.40B , Fig.40C and Fig.40D As shown, Fig.40A A cross-sectional view along the aa' direction after forming the dummy layer 9 provided in an exemplary embodiment. Fig.40B It is a cross-sectional view along the bb' direction after forming the dummy layer 9. Fig.40C is a cross-sectional view along the cc' direction after forming the dummy layer 9, Fig.40D It is a cross-sectional view along the dd' direction after the dummy layer 9 is formed.

[0279] In some embodiments, the dummy layer film may be a material having a higher etching selectivity ratio with the sacrificial layer film, such as polysilicon (poly), spin on carbon (SOC), and the like.

[0280] 311) The dummy layer 9 in the fourth hole K4 is removed by etching, as shown in FIG. Fig.41 As shown, Fig.41A cross-sectional view along the cc' direction after etching the dummy layer 9 provided in an exemplary embodiment. The cross-sectional views along the aa' direction, the bb' direction and the dd' direction can be referred to Fig.40A , Fig.40B and Fig.40D , omitted here.

[0281] 312) forming a tenth insulating layer 20;

[0282] The forming of the fourth insulating layer 20 may include: depositing a tenth insulating film to form the tenth insulating layer 20 filling the fourth hole K4, such as Fig.42 As shown, Fig.42 A cross-sectional view along the cc' direction after forming the tenth insulating layer 20 is provided for an exemplary embodiment. The cross-sectional views along the aa' direction, the bb' direction and the dd' direction can be referred to. Fig.40A , Fig.40B and Fig.40D , omitted here.

[0283] 313) forming a third hole K3;

[0284] The forming of the third hole K3 may include: forming the third hole K3 penetrating the stacked structure in a direction perpendicular to the substrate 1, such as Fig.43A , Fig.43B , Fig.43C and Fig.43D As shown, Fig.43A A cross-sectional view along the aa' direction after the third hole K3 is formed is provided for an exemplary embodiment. Fig.43B This is a cross-sectional view along the bb' direction after the third hole K3 is formed. Fig.43C This is a cross-sectional view along the cc' direction after the third hole K3 is formed. Fig.43D It is a cross-sectional view along the dd' direction after forming the third hole K3. The third hole K3 may be located in the word line region 200, and the third hole K3 penetrates the first insulating layer 10 and the sacrificial layer 11. A bit line 30 may be formed in the third hole K3 later.

[0285] 314) forming a first sub-groove A11;

[0286] The forming of the first sub-groove A11 may include: removing the sacrificial layer 11 of the transistor region 102 by transverse etching through the third hole K3 to form the first sub-groove A1; at this time, the dummy layer 9 of the transistor region 102 is retained, and the sacrificial layer 11 of the capacitor region 101 is retained, such as Fig.44A , Fig.44B , Fig.44C and Fig.44D As shown, Fig.44A A cross-sectional view along the aa' direction after the first sub-groove A11 is formed according to an exemplary embodiment. Fig.44BThis is a cross-sectional view along the bb' direction after the first sub-groove A11 is formed. Fig.44C This is a cross-sectional view along the cc' direction after the first sub-groove A11 is formed. Fig.44D It is a cross-sectional view along the dd' direction after the first sub-groove A11 is formed.

[0287] In some embodiments, the sacrificial layer 11 may be removed by wet lateral etching.

[0288] 315) forming a second sub-groove A12;

[0289] The forming of the second sub-groove A12 may include: removing the dummy layer 9 by lateral etching to form the second sub-groove A12, the first sub-groove A11 and the second sub-groove A12 are connected, and the combination of the two is the first groove A1. Fig.45 As shown, Fig.45 A cross-sectional view along the aa' direction after the second sub-groove A12 is formed is provided for an exemplary embodiment. The cross-sectional views along the bb' direction, the cc' direction and the dd' direction can be referred to Fig.44B , Fig.44C and Fig.44D , which is omitted here. A gate electrode 26 may be formed in the first groove A1 later.

[0290] In some embodiments, the dummy layer 9 may be removed by wet etching.

[0291] The solution provided in this embodiment forms the first groove A1 by two-step selective etching, and utilizes the different etching rates of the sacrificial layer film and the dummy layer film to make them barrier layers for each other. Compared with the solution of forming the first groove A1 by one-step etching, the dimensional uniformity of the device can be improved.

[0292] 316) forming a gate electrode 26;

[0293] The gate electrode 26 may include: depositing a second conductive film on the substrate 1 forming the aforementioned structure to form a gate electrode 26 covering the inner wall of the first groove A1 and the inner wall of the third hole K3 (including the bottom wall and side wall of the third hole K3);

[0294] The gate electrode 26 in the third hole K3 is removed by etching to disconnect the gate electrodes 26 of different layers; Fig.46A , Fig.46B , Fig.46C and Fig.46D As shown, Fig.46A A cross-sectional view along the aa' direction after forming the gate electrode 26 is provided for an exemplary embodiment. Fig.46B is a cross-sectional view along the bb' direction after the gate electrode 26 is formed. Fig.46C is a cross-sectional view along the cc' direction after the gate electrode 26 is formed. Fig.46DIt is a cross-sectional view along the dd′ direction after the gate electrode 26 is formed.

[0295] 317) forming a fifth insulating layer 16, a sixth insulating layer 17 and a second trench T2;

[0296] The forming of the fifth insulating layer 16, the sixth insulating layer 17 and the second trench T2 may include: depositing a fifth insulating film on the substrate 1 having the aforementioned structure and then grinding it flat to form the fifth insulating layer 16 filling the first groove A1 and the third hole K3;

[0297] Depositing a sixth insulating film to form a sixth insulating layer 17 covering the stacked structure;

[0298] A second trench T2 is formed at one end of the capacitor region 101 away from the bit line 30 and passes through the stacked structure in a direction perpendicular to the substrate 1. The sidewall of the second trench T2 exposes the sacrificial layer 11 so that the sacrificial layer 11 of the capacitor region 101 can be removed later. Fig.47A , Fig.47B , Fig.47C and Fig.47D As shown, Fig.47A A cross-sectional view along the aa' direction after forming the second trench T2 is provided for an exemplary embodiment. Fig.47B is a cross-sectional view along the bb' direction after the second trench T2 is formed. Fig.47C This is a cross-sectional view along the cc' direction after the second trench T2 is formed. Fig.47D It is a cross-sectional view along the dd' direction after the second trench T2 is formed.

[0299] 318) forming a second groove A2 and etching the gate electrode 26;

[0300] The forming of the second groove A2 and etching the gate electrode 26 may include: removing the sacrificial layer 11 of the capacitor region 101 by transverse etching through the second groove T2 to form the second groove A2;

[0301] The side wall of the gate electrode 26 extending in a direction perpendicular to the substrate 1 (i.e., the bottom wall of the first groove A1) is removed by etching, so that the gate electrode 26 forms a ring-shaped membrane layer with double-side openings (previously, a ring-shaped membrane layer with single-side openings), as shown in FIG. Fig.48A , Fig.48B , Fig.48C and Fig.48D As shown, Fig.48A A cross-sectional view along the aa' direction after etching the gate electrode 26 provided in an exemplary embodiment. Fig.48B is a cross-sectional view along the bb' direction after etching the gate electrode 26, Fig.48C is a cross-sectional view along the cc' direction after etching the gate electrode 26, Fig.48D It is a cross-sectional view along the dd' direction after etching the gate electrode 26.

[0302] In some embodiments, the sidewalls of the gate electrode 26 extending in a direction perpendicular to the substrate 1 may be removed by wet etching.

[0303] 318) etching and removing the fifth insulating layer 16 and the sixth insulating layer 17;

[0304] The etching and removing of the fifth insulating layer 16 and the sixth insulating layer 17 may include: depositing a seventh insulating film on the substrate 1 forming the aforementioned structure to form a seventh insulating layer 18, wherein the seventh insulating layer 18 fills the second trench T2 and the second groove A2; the seventh insulating layer 18 is used to protect the gate electrode 26 when the sixth insulating layer 17 is subsequently removed;

[0305] Grinding or dry etching to remove the sixth insulating layer 17 to expose the fifth insulating layer 16;

[0306] The fifth insulating layer 16 (ie, the fifth insulating layer 16 filled in the first groove A1 and the third hole K3) and the seventh insulating layer 18 are removed by etching. Fig.49A , Fig.49B , Fig.49C and Fig.49D As shown, Fig.49A A cross-sectional view along the aa' direction after the fifth insulating layer 16 and the sixth insulating layer 17 are removed by etching according to an exemplary embodiment. Fig.49B It is a cross-sectional view along the bb' direction after the fifth insulating layer 16 and the sixth insulating layer 17 are etched away. Fig.49C It is a cross-sectional view along the cc' direction after the fifth insulating layer 16 and the sixth insulating layer 17 are etched away. Fig.49D It is a cross-sectional view along the dd' direction after etching away the fifth insulating layer 16 and the sixth insulating layer 17. At this time, the third hole K3, the first groove A1, the second groove A2 and the second trench T2 are connected, which facilitates the subsequent one-time formation of the bit line 30 and the semiconductor layer 23.

[0307] FIG. 49A to FIG. 49D The seventh insulating layer 18 is not shown. 19A to 19D The position of the seventh insulating layer 18 is shown in FIG.

[0308] 319)-327), the same as steps 119)-127), forming the bit line 30, the gate insulating layer 24, the semiconductor layer 23, the first source and drain electrode 51, the dielectric layer 43, and the second electrode 42, as shown in FIG. Fig.50A , Fig.50B , Fig.50C and Fig.50D As shown, Fig.50A A cross-sectional view along the aa' direction after forming the second pole 42 provided in an exemplary embodiment, Fig.50B It is a cross-sectional view along the bb' direction after the second pole 42 is formed. Fig.50C This is a cross-sectional view along the cc' direction after the second pole 42 is formed. Fig.50D It is a cross-sectional view along the dd' direction after the fifth insulating layer 16 and the sixth insulating layer 17 are removed by etching.

[0309] 328) forming a word line 40;

[0310] The forming of the word line 40 may include: etching away the word line structure layer 40' in the first hole K1, and forming a plurality of second holes K2 penetrating the word line structure layer 40' and the first insulating layer 10 in a direction perpendicular to the substrate 1, wherein the plurality of second holes K2 disconnect the word line structure layer 40' to form two independent word lines 40, such as Fig.51A , Fig.51B , Fig.51C and Fig.51D As shown, Fig.51A A cross-sectional view along the aa' direction after forming a word line 40 is provided for an exemplary embodiment. Fig.51B is a cross-sectional view along the bb' direction after the word line 40 is formed. Fig.51C is a cross-sectional view along the cc' direction after the word line 40 is formed. Fig.51D It is a cross-sectional view along the dd' direction after the word line 40 is formed. The word line 40 includes multiple segments, and the multiple segments are distributed along the second direction Y. Subsequently, the multiple segments are connected by the gate electrodes 26 of multiple transistors distributed along the second direction Y.

[0311] In some embodiments, on a plane parallel to the substrate 1 , a cross section of the second hole K2 is, for example, square.

[0312] 329) forming a fourth insulating layer 15;

[0313] The forming of the fourth insulating layer 15 may include: depositing a fourth insulating film on the substrate 1 forming the aforementioned structure to form the fourth insulating layer 15, wherein the fourth insulating layer 15 fills the first hole K1 and the second hole K2; Fig.52A , Fig.52B , Fig.52C and Fig.52D As shown, Fig.52A A cross-sectional view along the aa' direction after forming the fourth insulating layer 15 is provided for an exemplary embodiment. Fig.52B is a cross-sectional view along the bb' direction after the fourth insulating layer 15 is formed. Fig.52C is a cross-sectional view along the cc' direction after the fourth insulating layer 15 is formed. Fig.52D It is a cross-sectional view along the dd' direction after the fourth insulating layer 15 is formed.

[0314] In another exemplary embodiment, a process for manufacturing a semiconductor device may include:

[0315] 401)~407), same as steps 301)~307), forming Fig.53A , Fig.53B , Fig.53C and Fig.53D The structure shown, in which Fig.53A FIG. 4 is a cross-sectional view along the aa′ direction after forming a word line structure layer 40′ according to an exemplary embodiment. Fig.53B It is a cross-sectional view along the bb' direction after the word line structure layer 40' is formed. Fig.53C is a cross-sectional view along the cc' direction after the word line structure layer 40' is formed. Fig.53D It is a cross-sectional view along the dd' direction after the word line structure layer 40' is formed.

[0316] 408) to 421), the same as steps 109) to 122), forming the bit line 30, the gate electrode 26, the gate insulating layer 24, the semiconductor layer 23 and the first portion 511 of the first source-drain electrode 51, as shown in Fig.54A , Fig.54B , Fig.54C and Fig.54D ,in, Fig.54A FIG. 4 is a cross-sectional view along the aa′ direction after forming a word line structure layer 40′ according to an exemplary embodiment. Fig.54B It is a cross-sectional view along the bb' direction after the word line structure layer 40' is formed. Fig.54C is a cross-sectional view along the cc' direction after the word line structure layer 40' is formed. Fig.54D It is a cross-sectional view along the dd' direction after the word line structure layer 40' is formed.

[0317] 422) forming a second portion 512 of the first source / drain electrode 51;

[0318] The forming of the second portion 512 of the first source / drain electrode 51 may include: depositing a fourth conductive film on the substrate 1 forming the aforementioned structure to form the second portion 512 of the first source / drain electrode 51, wherein the second portion 512 fills the second groove A2, such as Fig.55A , Fig.55B , Fig.55C and Fig.55D As shown, Fig.55A A cross-sectional view along the aa' direction after the second portion 512 is formed is provided for an exemplary embodiment. Fig.55B This is a cross-sectional view along the bb' direction after the second portion 512 is formed. Fig.55C This is a cross-sectional view along the cc' direction after the second portion 512 is formed. Fig.55D2 is a cross-sectional view along the dd' direction after the second portion 512 is formed. The second portion 512 is connected to the first portion 511 and the semiconductor layer 23, and is insulated from the gate electrode 26 by the gate insulating layer 24. The second portion 512 also covers the sidewall of the second trench T2, so at this time, the second portions 512 of different layers are connected together.

[0319] 423) disconnecting the second portion 512 of the different layers;

[0320] The disconnecting of the second portion 512 of different layers may include: etching and removing the second portion 512 located in the second trench T2 to disconnect the second portion 512 of different layers, such as Fig.56A , Fig.56B , Fig.56C and Fig.56D As shown, Fig.56A A cross-sectional view along the aa' direction after the second portion 512 of different layers is cut off according to an exemplary embodiment. Fig.56B The cross-sectional view along the bb' direction after the second portion 512 of different layers is disconnected, Fig.56C This is a cross-sectional view along the cc' direction after the second portion 512 of different layers is disconnected. Fig.56D It is a cross-sectional view along the dd' direction after the second portion 512 of different layers is disconnected. The second portion 512 of the first source / drain electrode 51 also serves as the first electrode 41 of the capacitor.

[0321] 424) exposing the second portion 512 of the first source / drain electrode 51;

[0322] The second portion 512 exposing the first source / drain electrode 51 may include:

[0323] Etching and removing the eighth insulating layer 19;

[0324] The first insulating layer 10 and the third insulating layer 14 of the capacitor region 101 are removed by etching to expose the upper surface, the lower surface, and the three side walls extending in a direction perpendicular to the substrate 1 (i.e., the other side walls except the side wall facing the semiconductor layer 23), as shown in FIG. Fig.57A , Fig.57B , Fig.57C and Fig.57D As shown, Fig.57A A cross-sectional view along the aa' direction after the second portion 512 is exposed is provided for an exemplary embodiment. Fig.57B is a cross-sectional view along the bb' direction after the second portion 512 is exposed. Fig.57C is a cross-sectional view along the cc' direction after the second portion 512 is exposed. Fig.57D It is a cross-sectional view along the dd′ direction after the second portion 512 is exposed.

[0325] 425) forming a dielectric layer 43 and a second electrode 42;

[0326] The formation of the dielectric layer 43 and the second electrode 42 may include: depositing a dielectric layer film on the substrate 1 forming the aforementioned structure to form a dielectric layer 43, wherein the dielectric layer 43 covers the side wall of the second part 512 of the first source / drain electrode 51 away from the semiconductor layer 23, and covers the side wall of the second part 512 of the first source / drain electrode 51 extending in a direction perpendicular to the substrate 1, and the upper surface and lower surface of the second part 512 of the first source / drain electrode 51.

[0327] A fifth conductive film is deposited on the substrate 1 forming the aforementioned structure to form a second electrode 42, and the second electrode 42 fills the area between the second trench T2 and the adjacent second portion 512 along the direction perpendicular to the substrate 1 (i.e., the area where the first insulating layer 10 etched away in the previous step is located), as shown in FIG. Fig.58A , Fig.58B , Fig.58C and Fig.58D As shown, Fig.58A A cross-sectional view along the aa' direction after forming the second pole 42 provided in an exemplary embodiment, Fig.58B It is a cross-sectional view along the bb' direction after the second pole 42 is formed. Fig.58C This is a cross-sectional view along the cc' direction after the second pole 42 is formed. Fig.58D It is a cross-sectional view along the dd' direction after the second pole 42 is formed.

[0328] The solution provided in this embodiment forms an external capacitor. Compared with the internal capacitors in the aforementioned embodiments, the electrode area of ​​the capacitor is larger and the capacitance value is larger while the area occupied by the capacitor remains unchanged, thereby improving the area utilization.

[0329] 426) forming word line 40;

[0330] The forming of the word line 40 may include: etching away the word line structure layer 40' in the first hole K1, and forming a plurality of second holes K2 penetrating the word line structure layer 40' and the first insulating layer 10 in a direction perpendicular to the substrate 1, wherein the plurality of second holes K2 disconnect the word line structure layer 40' to form two independent word lines 40, such as Fig.59A , Fig.59B , Fig.59C and Fig.59D As shown, Fig.59A A cross-sectional view along the aa' direction after forming a word line 40 is provided for an exemplary embodiment. Fig.59B is a cross-sectional view along the bb' direction after the word line 40 is formed. Fig.59C is a cross-sectional view along the cc' direction after the word line 40 is formed. Fig.59DIt is a cross-sectional view along the dd' direction after the word line 40 is formed. The word line 40 includes multiple segments, and the multiple segments are distributed along the second direction Y. Subsequently, the multiple segments are connected by the gate electrodes 26 of multiple transistors distributed along the second direction Y.

[0331] 427) forming a fourth insulating layer 15;

[0332] The forming of the fourth insulating layer 15 may include: depositing a fourth insulating film on the substrate 1 forming the aforementioned structure to form the fourth insulating layer 15, wherein the fourth insulating layer 15 fills the first hole K1 and the second hole K2; Fig.60A , Fig.60B , Fig.60C and Fig.60D As shown, Fig.60A A cross-sectional view along the aa' direction after forming the fourth insulating layer 15 is provided for an exemplary embodiment. Fig.60B is a cross-sectional view along the bb' direction after the fourth insulating layer 15 is formed. Fig.60C is a cross-sectional view along the cc' direction after the fourth insulating layer 15 is formed. Fig.60D It is a cross-sectional view along the dd' direction after the fourth insulating layer 15 is formed.

[0333] The present disclosure provides a method for manufacturing a semiconductor device, wherein the semiconductor device comprises: a plurality of transistors distributed in different layers and stacked along a direction perpendicular to a substrate; and a bit line, wherein the transistor comprises a gate electrode and a semiconductor layer, and comprises:

[0334] Forming a stack structure of alternately stacked first insulating layers and sacrificial layers on a substrate;

[0335] The stack structure is patterned to form a word line region extending along a second direction and a plurality of memory cell regions extending along a first direction and spaced apart along the second direction; a groove extending along the first direction and penetrating the stack structure is provided between any two adjacent memory cell regions;

[0336] forming a first hole penetrating the stacked structure in the word line region; removing a portion of each sacrificial layer to form a plurality of first grooves communicating with the first hole;

[0337] forming a gate electrode covering the sidewall of the first groove;

[0338] Depositing a gate insulating film and a semiconductor film in the first groove and the first hole in sequence to form a gate insulating layer and a semiconductor layer of the transistor, wherein the semiconductor layer fills the first groove and covers the bottom wall and the side wall of the first hole, the gate insulating layer surrounds the semiconductor layer, and the gate electrode surrounds the gate insulating layer;

[0339] The bit line is formed by depositing a first conductive film in the first hole where the semiconductor layer is formed.

[0340] In some embodiments, the method may further include:

[0341] Removing the sacrificial layer of the storage unit area to form a second groove connected to the first groove, wherein the second groove is arranged on a side of the first groove away from the first hole;

[0342] The step of sequentially depositing a gate insulating film and a semiconductor film in the first groove and the first hole to form a gate insulating layer and a semiconductor layer of the transistor, wherein the semiconductor layer fills the first groove and covers the bottom wall and the side wall of the first hole, the gate insulating layer surrounds the semiconductor layer, and the gate electrode surrounds the gate insulating layer; and depositing a first conductive film in the first hole where the semiconductor layer is formed to form the bit line comprises:

[0343] Depositing a gate insulating film, a semiconductor film, and a first conductive film in the second groove, the first groove, and the first hole in sequence, and the semiconductor film fills the first groove, etching the gate insulating film, the semiconductor film, and the first conductive film in the second groove to a preset length to form the gate insulating layer, the semiconductor layer, and the bit line, and the first conductive film retained in the second groove forms a first part of a first source / drain electrode of the transistor;

[0344] A second portion of the first source / drain electrode is formed in the second groove, and the second portion of the first source / drain electrode overlaps the first portion of the first source / drain electrode.

[0345] In some embodiments, the second portion of the first source / drain electrode covers the bottom wall and sidewalls of the second groove; the method further includes: forming a second pole filling the second groove, and a dielectric layer disposed between the second pole and the first source / drain electrode.

[0346] In some embodiments, the second portion of the first source / drain electrode fills the second groove; the method also includes exposing an outer side wall of the second portion of the first source / drain electrode, the outer side wall including an end surface of the second portion of the first source / drain electrode facing away from the first portion of the first source / drain electrode, and each side wall connected to the end surface; forming a second pole surrounding the outer side wall, and forming a dielectric layer disposed between the outer side wall and the second pole.

[0347] In some embodiments, removing a portion of each of the sacrificial layers to form a plurality of first grooves communicating with the first holes comprises:

[0348] Performing lateral etching through the first hole to remove a portion of each of the sacrificial layers to form a plurality of first grooves communicating with the first hole;

[0349] Alternatively, before forming the first hole, the first part of each sacrificial layer is replaced with a dummy layer, and a second sacrificial layer exists between the dummy layer and the first hole; after etching away the second part of the sacrificial layer, the dummy layer is etched away to form a plurality of first grooves connected to the first hole.

[0350] In some embodiments, the method further comprises:

[0351] A second hole penetrating the stacked structure is formed in each of the grooves, the second hole exposing the side wall of the sacrificial layer in the word line region but not exposing the side wall of the sacrificial layer in the memory cell region; a plurality of third grooves are formed by transversely etching the sacrificial layer in the word line region through each of the second holes, the third grooves connecting two second holes adjacent to each other along the first direction;

[0352] Depositing a second conductive film filling the third grooves in the plurality of third grooves, forming a third hole penetrating the stacked structure in the word line region, wherein the third hole disconnects the second conductive film of each third groove to form two disconnected connection electrodes, wherein the connection electrode is connected to the gate electrode, and a plurality of connection electrodes distributed along the second direction are connected to form a word line through a plurality of gate electrodes distributed along the second direction;

[0353] Alternatively, a second hole penetrating the stacked structure is formed in each of the grooves, the second hole exposing the side wall of the sacrificial layer in the word line region and not exposing the side wall of the sacrificial layer in the memory cell region; the sacrificial layer in the word line region is laterally etched through each of the second holes to form a plurality of third grooves, the third grooves connecting two second holes adjacent to each other along the first direction; and the second hole is enlarged along the second direction to expose the side wall of the sacrificial layer in the memory cell region;

[0354] A second conductive film filling the third grooves is deposited in the plurality of third grooves, and a third hole penetrating the stacked structure is formed in the word line region. The third hole disconnects the second conductive film of each of the third grooves to form two disconnected connecting electrodes, and the connecting electrode is connected to the gate electrode. A plurality of connecting electrodes distributed along the second direction are connected through a plurality of gate electrodes distributed along the second direction to form a word line.

[0355] In some embodiments, the method further comprises:

[0356] When patterning the stack structure, a plurality of third holes penetrating the stack structure are formed in the word line region;

[0357] After the third hole and the trench are filled with the second insulating layer, a second hole penetrating the stacked structure is formed in each of the trenches, and the second insulating layer in the third hole is removed, wherein the second hole exposes the side wall of the sacrificial layer in the word line region and does not expose the side wall of the sacrificial layer in the memory cell region; the sacrificial layer in the word line region is laterally etched through each of the second hole and the third hole to form a plurality of fourth grooves, wherein the fourth grooves are arranged between the second hole and the third hole and connect the second hole and the third hole;

[0358] A second conductive film filling the fourth grooves is deposited in the plurality of fourth grooves to form a connecting electrode connected to the gate electrode. The plurality of connecting electrodes distributed along the second direction are connected through the plurality of gate electrodes distributed along the second direction to form a word line.

[0359] The present disclosure also provides an electronic device, including the semiconductor device described in any of the above embodiments or a semiconductor device formed by the method for manufacturing the semiconductor device described in any of the above embodiments. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0360] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A semiconductor device, characterized in that: include: Multiple transistors are distributed in different layers and stacked along the direction perpendicular to the substrate; A bit line connected to the plurality of transistors at different layers and extending in a direction perpendicular to the substrate; The transistor includes a gate electrode and a semiconductor layer, the semiconductor layer includes a first semiconductor sublayer extending in a direction parallel to the substrate and a second semiconductor sublayer extending in a direction perpendicular to the substrate, the first semiconductor sublayer includes a strip-shaped portion extending in a first direction, the second semiconductor sublayer is connected to the bit line, and the gate electrode extends in a direction parallel to the substrate and surrounds the strip-shaped portion.

2. The semiconductor device according to claim 1, wherein: The second semiconductor sublayer surrounds the bit line.

3. The semiconductor device according to claim 1, wherein: On a plane perpendicular to the substrate and the first direction, the orthographic projection of the strip portion is located within the orthographic projection of the second semiconductor sublayer, and the orthographic projection of the gate electrode on the substrate is located outside the orthographic projection of the second semiconductor sublayer on the substrate.

4. The semiconductor device according to claim 1, wherein: The first semiconductor sublayer also includes an end portion of the strip portion away from one end of the bit line, and on a plane perpendicular to the substrate and the first direction, the orthographic projection of the strip portion is located within the orthographic projection of the end portion, and the orthographic projection of the gate electrode on the substrate is located outside the orthographic projection of the end portion on the substrate.

5. The semiconductor device according to claim 4, characterized in that The end portion is provided with a first groove with an opening facing away from the bit line. The transistor further includes: a first source / drain electrode, and the first source / drain electrode fills the first groove.

6. The semiconductor device according to claim 5, characterized in that The first source / drain electrode includes a first portion filling the first groove and a second portion disposed at a side of the first groove away from the bit line, wherein the second portion overlaps the first portion.

7. The semiconductor device according to claim 6, characterized in that The second portion of the first source / drain electrode is provided with a second groove opening away from the bit line. The semiconductor device further comprises: a capacitor comprising a second electrode insulated from the first source / drain electrode by a dielectric layer and filling the second groove.

8. The semiconductor device according to claim 6, characterized in that The second part of the first source / drain electrode is a block electrode, and the semiconductor device also includes: a capacitor, the capacitor includes a second pole, the second pole is provided with a third groove opening toward the bit line, the second part of the first source / drain electrode is insulated from the second pole by a dielectric layer and fills the third groove.

9. The semiconductor device according to claim 8, characterized in that The semiconductor device includes a multi-layer memory cell array distributed along a direction perpendicular to the substrate, wherein each layer of the memory cell array includes a plurality of rows and columns of memory cells distributed along a first direction and a second direction, respectively, a plurality of word lines extending along the second direction and arranged at intervals along a direction perpendicular to the substrate, and a plurality of bit lines extending along a direction perpendicular to the substrate and arranged at intervals along the second direction; the memory cell includes the transistor and the capacitor, the plurality of transistors are located in different layers and arranged in an array; the same word line includes a plurality of connection electrodes distributed along the second direction; the plurality of connection electrodes of the same word line are connected through gate electrodes of transistors in the same column distributed along the second direction; each bit line is connected to a transistor in at least one column of the memory cells arranged perpendicular to the substrate.

10. The semiconductor device according to claim 9, characterized in that The connection electrode is connected to a region of the gate electrode close to the bit line.

11. The semiconductor device according to claim 9, characterized in that The semiconductor layers of the plurality of transistors at the same position in different layers are connected to form an integrated structure.

12. The semiconductor device according to claim 11, characterized in that The arrangement direction of the transistor and the capacitor of the same storage unit is parallel to the first direction. In the storage units of the same layer, the arrangement directions of the transistors and capacitors of the storage units adjacent along the first direction are opposite to each other; the semiconductor layers of the storage units adjacent along the first direction and whose transistors are close to each other are connected to form an integrated structure.

13. The semiconductor device according to claim 12, characterized in that The semiconductor layer of the integrated structure is connected to the same bit line and surrounds the connected bit line.

14. A method for manufacturing a semiconductor device, characterized in that: The semiconductor device comprises: a plurality of transistors and bit lines distributed in different layers and stacked along a direction perpendicular to a substrate, wherein the transistor comprises a gate electrode and a semiconductor layer, including: Forming a stack structure of alternately stacked first insulating layers and sacrificial layers on a substrate; The stack structure is patterned to form a word line region extending along a second direction and a plurality of memory cell regions extending along a first direction and spaced apart along the second direction; a groove extending along the first direction and penetrating the stack structure is provided between any two adjacent memory cell regions; forming a first hole penetrating the stacked structure in the word line region; removing a portion of each sacrificial layer to form a plurality of first grooves communicating with the first hole; forming a gate electrode covering the sidewall of the first groove; Depositing a gate insulating film and a semiconductor film in the first groove and the first hole in sequence to form a gate insulating layer and a semiconductor layer of the transistor, wherein the semiconductor layer fills the first groove and covers the bottom wall and the side wall of the first hole, the gate insulating layer surrounds the semiconductor layer, and the gate electrode surrounds the gate insulating layer; The bit line is formed by depositing a first conductive film in the first hole where the semiconductor layer is formed.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The method further comprises: Removing the sacrificial layer of the storage unit area to form a second groove connected to the first groove, wherein the second groove is arranged on a side of the first groove away from the first hole; The step of sequentially depositing a gate insulating film and a semiconductor film in the first groove and the first hole to form a gate insulating layer and a semiconductor layer of the transistor, wherein the semiconductor layer fills the first groove and covers the bottom wall and the side wall of the first hole, the gate insulating layer surrounds the semiconductor layer, and the gate electrode surrounds the gate insulating layer; and depositing a first conductive film in the first hole where the semiconductor layer is formed to form the bit line comprises: Depositing a gate insulating film, a semiconductor film, and a first conductive film in the second groove, the first groove, and the first hole in sequence, and the semiconductor film fills the first groove, etching the gate insulating film, the semiconductor film, and the first conductive film in the second groove to a preset length to form the gate insulating layer, the semiconductor layer, and the bit line, and the first conductive film retained in the second groove forms a first part of a first source / drain electrode of the transistor; A second portion of the first source / drain electrode is formed in the second groove, and the second portion of the first source / drain electrode overlaps the first portion of the first source / drain electrode.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: The second portion of the first source / drain electrode covers the bottom wall and the sidewall of the second groove; the method further includes: forming a second electrode filling the second groove, and a dielectric layer disposed between the second electrode and the first source / drain electrode.

17. The method for manufacturing a semiconductor device according to claim 15, wherein: The second portion of the first source / drain electrode fills the second groove; the method also includes exposing an outer side wall of the second portion of the first source / drain electrode, the outer side wall including an end surface of the second portion of the first source / drain electrode facing away from the first portion of the first source / drain electrode, and each side wall connected to the end surface; forming a second pole surrounding the outer side wall, and forming a dielectric layer disposed between the outer side wall and the second pole.

18. The method for manufacturing a semiconductor device according to claim 14, wherein: The removing a portion of each of the sacrificial layers to form a plurality of first grooves communicating with the first holes comprises: Performing lateral etching through the first hole to remove a portion of each of the sacrificial layers to form a plurality of first grooves communicating with the first hole; Alternatively, before forming the first hole, the first part of each sacrificial layer is replaced with a dummy layer, and a second part of the sacrificial layer exists between the dummy layer and the first hole; after etching away the second part of the sacrificial layer, the dummy layer is etched away to form a plurality of first grooves connected to the first hole.

19. The method for manufacturing a semiconductor device according to claim 14, wherein: The method further comprises: A second hole penetrating the stacked structure is formed in each of the grooves, the second hole exposing the side wall of the sacrificial layer in the word line region but not exposing the side wall of the sacrificial layer in the memory cell region; a plurality of third grooves are formed by transversely etching the sacrificial layer in the word line region through each of the second holes, the third grooves connecting two second holes adjacent to each other along the first direction; Depositing a second conductive film filling the third grooves in the plurality of third grooves, forming a third hole penetrating the stacked structure in the word line region, wherein the third hole disconnects the second conductive film of each third groove to form two disconnected connection electrodes, wherein the connection electrode is connected to the gate electrode, and a plurality of connection electrodes distributed along the second direction are connected to form a word line through a plurality of gate electrodes distributed along the second direction; Alternatively, a second hole penetrating the stacked structure is formed in each of the grooves, the second hole exposing the side wall of the sacrificial layer in the word line region and not exposing the side wall of the sacrificial layer in the memory cell region; the sacrificial layer in the word line region is laterally etched through each of the second holes to form a plurality of third grooves, the third grooves connecting two second holes adjacent to each other along the first direction; and the second hole is enlarged along the second direction to expose the side wall of the sacrificial layer in the memory cell region; A second conductive film filling the third grooves is deposited in the plurality of third grooves, and a third hole penetrating the stacked structure is formed in the word line region. The third hole disconnects the second conductive film of each of the third grooves to form two disconnected connecting electrodes, and the connecting electrode is connected to the gate electrode. A plurality of connecting electrodes distributed along the second direction are connected through a plurality of gate electrodes distributed along the second direction to form a word line.

20. The method for manufacturing a semiconductor device according to claim 14, wherein: The method further comprises: When patterning the stack structure, a plurality of third holes penetrating the stack structure are formed in the word line region; After the third hole and the trench are filled with the second insulating layer, a second hole penetrating the stacked structure is formed in each of the trenches, and the second insulating layer in the third hole is removed, wherein the second hole exposes the side wall of the sacrificial layer in the word line region and does not expose the side wall of the sacrificial layer in the memory cell region; the sacrificial layer in the word line region is laterally etched through each of the second hole and the third hole to form a plurality of fourth grooves, wherein the fourth grooves are arranged between the second hole and the third hole and connect the second hole and the third hole; A second conductive film filling the fourth grooves is deposited in the plurality of fourth grooves to form a connecting electrode connected to the gate electrode. The plurality of connecting electrodes distributed along the second direction are connected through the plurality of gate electrodes distributed along the second direction to form a word line.

21. An electronic device, characterized in that: A semiconductor device comprising the semiconductor device according to any one of claims 1 to 13, or a semiconductor device formed by the semiconductor device manufacturing method according to any one of claims 14 to 20.

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