Manufacturing method of IGBT (Insulated Gate Bipolar Translator) device
By abolishing the CMP process in the IGBT device manufacturing process and adopting the stress reduction process, the problem of high process cost in small-sized cell structures is solved, and the dual effects of cost reduction and performance stability are achieved.
Patent Information
- Application Number
- CN202411859459.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-17
- Publication Date
- 2025-03-18
AI Technical Summary
In the existing IGBT device manufacturing processes, the CMP process cost is relatively high, especially in small-sized cell structures. How to reduce costs through process optimization has become a challenge.
IGBT devices are manufactured using CMP-free process. By abolishing the CMP process after polysilicon deposition, and using the first stress reduction process and the second stress reduction process, the stress reduction function of the CMP process after polysilicon deposition and the CMP process after field oxide layer formation is replaced respectively.
It realizes the reduction of process costs, especially suitable for small-sized cell structures, and the stress reduction process compensates for the stress impact after the cancellation of the CMP process, ensuring the stability of device performance.
Smart Images
Figure CN119653799A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing an IGBT device. Background Art
[0002] IGBT devices are developed on the basis of vertical double diffused MOS field effect transistors. They have a conductive channel and a PN junction, and the current flowing through the channel and the junction is controlled by the electric field generated by the voltage applied between the gate and the collector-emitter. The PN junction is composed of a P-type doped collector region and an N-type doped drift region. In existing MOS field effect transistors, since both the drain region and the drift region are N-type doped, there is no back PN junction of IGBT devices. When the IGBT device is turned on, the PN junction will realize hole injection, thereby modulating the conductance of the drift region, and finally reducing the on-resistance and on-voltage drop of the device. In the process of pursuing the reduction of the on-voltage drop of IGBT, the gate structure of IGBT devices has undergone significant optimization changes, gradually evolving from the traditional planar gate structure to the more advanced trench gate structure. In the trench gate IGBT, its channel has achieved a key transformation from horizontal to vertical, and this change has successfully eliminated the influence of JFET in the on-resistance. At the same time, with the change of structure, the area of polysilicon gate is increased. The direct benefit of this area expansion is the effective reduction of distributed resistance, which has a very positive effect on improving switching speed. Not only that, in another important aspect, by reducing the size of the primitive cell, the so-called pitch, the density of the primitive cell has been greatly improved. In this way, the total channel width of each chip is significantly increased, which effectively reduces the channel resistance and lays a solid foundation for improving the overall performance of IGBT. For small primitive cell structures, how to further save costs by optimizing the process is the subject to be studied in this application. Summary of the invention
[0003] The technical problem to be solved by the present invention is to provide a method for manufacturing an IGBT device, which can be implemented by a non-CMP process, thereby reducing the process cost, and is particularly suitable for reducing the process cost of a small-sized primitive cell.
[0004] In order to solve the above technical problems, the present invention provides a method for manufacturing an IGBT device, which adopts a CMP-free process and comprises the following steps:
[0005] Gate trenches are formed in selected regions of the semiconductor substrate.
[0006] A gate oxide layer is formed on the inner surface of the gate trench and the surface of the semiconductor substrate outside the gate trench.
[0007] A first polysilicon layer is deposited, wherein the first polysilicon layer completely fills the gate trench and extends to a surface of the gate oxide layer outside the gate trench.
[0008] The post-polysilicon deposition CMP process is cancelled and polysilicon etching is performed, wherein the polysilicon etching removes the first polysilicon layer outside the gate trench and stops on the top surface of the gate oxide layer, and the first polysilicon layer remaining in the gate trench forms a polysilicon gate.
[0009] A first stress reduction process is performed to replace the stress reduction function of the polysilicon post-deposition CMP process, wherein the first stress reduction process comprises:
[0010] A stress relief groove is formed in the scribe line.
[0011] A further improvement is that the first stress reduction process further comprises:
[0012] In the field plate formation process of the termination region, the polysilicon field plate is removed.
[0013] A further improvement is that the first stress reduction process further comprises:
[0014] In the process of forming the contact hole, the width of the contact hole at the top of the terrace region between the gate trenches is reduced.
[0015] A further improvement is that the method further comprises the following steps:
[0016] A field oxide layer is formed on the surface of the semiconductor substrate. The field oxide layer is located in a terminal region. The terminal region surrounds the periphery of an active region. The active region is a primary cell formation region of an IGBT device.
[0017] The CMP process after the field oxide layer is formed is cancelled and a second stress reduction process is performed to replace the stress reduction function of the CMP process after the field oxide layer is formed, and the second stress reduction process includes:
[0018] The thermal stress is reduced and stress reduction is achieved by reducing the first thermal process driven by annealing of the doped regions formed after the field oxide layer is formed.
[0019] A further improvement is that in the second stress reduction process, the doped region formed after the field oxide layer is formed includes the second conductivity type doped ring region of the terminal region, the second conductivity type first well region of the active region or the first conductivity type second well region.
[0020] A further improvement is that the step of reducing the first thermal process comprises:
[0021] reducing the process time of the first thermal process;
[0022] Optimizing the temperature curve in the first thermal process includes reducing the heating rate or the cooling rate.
[0023] A further improvement is to optimize the temperature curve in the first thermal process and adopt multi-stage temperature control to reduce the heating rate or the cooling rate.
[0024] A further improvement is that the second stress reduction process comprises the following sub-steps:
[0025] Ions of the second conductivity type are implanted in a selected area of the terminal region to form a second conductivity type doped annular region.
[0026] A uniform first oxide layer is formed on the surface of the semiconductor substrate by using a PECVD process.
[0027] Ions of the second conductivity type are implanted in selected areas of the active area to form the first well area, or ions of the first conductivity type are implanted to form the second well area.
[0028] The annealing process is carried out with the first thermal process.
[0029] A further improvement is that the semiconductor substrate has a first conductivity type doping, the gate trench passes through the first well region, and the surface of the first well region covered by the side surface of the gate trench is used to form a conductive channel.
[0030] The semiconductor substrate at the bottom of the first well region serves as a drift region.
[0031] A further improvement is that the second stress reduction process further comprises:
[0032] A carrier storage layer heavily doped with a first conductive type is formed in a top region of the drift region at the bottom of the first well region in the active region.
[0033] A further improvement is that the field oxide layer is formed before the gate trench; or, the field oxide layer is formed after the polysilicon gate is formed.
[0034] A further improvement is that when forming the gate groove, a first photoresist pattern formed by a photolithography process is first used to define the formation area of the gate groove, and then the semiconductor substrate is dry-etched using the first photoresist pattern as a mask to form the gate groove, and then the semiconductor substrate is cleaned to remove etching residues.
[0035] A further improvement is that the gate oxide layer is formed by a thermal oxidation process, the temperature of the thermal oxidation process of the gate oxide layer includes 1000° C. to 1100° C., and the process gas includes oxygen or water vapor.
[0036] A further improvement is that the second conductivity type doped annular region includes an equipotential ring.
[0037] A further improvement is that the field oxide layer is formed by stacking a first thermal oxide layer formed by a thermal oxidation process and a second CVD oxide layer formed by CVD deposition.
[0038] A further improvement is that the material of the semiconductor substrate includes silicon.
[0039] The present invention adopts a non-CMP process to manufacture IGBT devices. Since the function of reducing stress by the CMP process cannot be realized after the CMP process is cancelled, the present invention also adopts a first stress reduction process to reduce stress after the CMP process after polysilicon deposition is cancelled to achieve the same stress reduction effect as the CMP process after polysilicon deposition. The first stress reduction process of the present invention can be achieved by forming a stress release groove in the scribe groove, or further combined with removing the polysilicon field plate or reducing the width of the contact hole on the top of the platform area. Therefore, even if the CMP process after polysilicon deposition is cancelled, the present invention can compensate for the influence of the CMP process after polysilicon deposition on stress by making special settings and adjustments to the overall process, that is, the present invention can achieve the same improvement in stress. In addition, the present invention can further cancel the CMP process after the field oxide layer is formed, and adopt the second stress reduction process to eliminate the adverse influence of the CMP process after the field oxide layer is formed on stress. It can be seen that the present invention can not only achieve the cost reduction effect brought about by canceling the CMP process, but also overcome the adverse effect of canceling the CMP process on stress. Therefore, the present invention can be implemented by a CMP-free process, thereby reducing the process cost, and is particularly suitable for reducing the process cost of small-sized primitives. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:
[0041] Figure 1 It is a flow chart corresponding to the elimination of the CMP process after polysilicon deposition in the method for manufacturing an IGBT device according to an embodiment of the present invention;
[0042] Figure 2 It is a flowchart corresponding to the CMP process after the field oxide layer is formed in the manufacturing method of the IGBT device according to the embodiment of the present invention;
[0043] Figure 3 It is a schematic structural diagram of an IGBT device manufactured by the method for manufacturing an IGBT device according to an embodiment of the present invention. DETAILED DESCRIPTION
[0044] like Figure 1As shown in FIG. 1 , it is a flowchart corresponding to the CMP process after polysilicon deposition in the method for manufacturing an IGBT device according to an embodiment of the present invention; Figure 2 As shown, it is a flowchart corresponding to the CMP process after the field oxide layer 6 is formed in the manufacturing method of the IGBT device according to the embodiment of the present invention; Figure 3 FIG. 1 is a schematic diagram of the structure of an IGBT device manufactured by the method for manufacturing an IGBT device according to an embodiment of the present invention; In the method for manufacturing an IGBT device according to an embodiment of the present invention, a non-CMP process is adopted, such as Figure 1 As shown, the following steps are included:
[0045] Step S101 : forming a gate trench in a selected region of a semiconductor substrate 1 .
[0046] In the embodiment of the present invention, the material of the semiconductor substrate 1 includes silicon.
[0047] When forming a gate trench, a first photoresist pattern formed by a photolithography process is first used to define a formation area of the gate trench, and then the semiconductor substrate 1 is dry-etched using the first photoresist pattern as a mask to form a gate trench. The dry etching includes etching such as reactive ion etching (RIT); the etching gas used in the dry etching includes chlorine and boron trichloride, etc. The etching gas chemically reacts with the silicon of the semiconductor substrate 1 to etch away the silicon not protected by the photoresist.
[0048] The semiconductor substrate 1 is then cleaned to remove etching residues.
[0049] Step S102 : forming a gate oxide layer 2 on the inner surface of the gate trench and the surface of the semiconductor substrate 1 outside the gate trench.
[0050] In the embodiment of the present invention, a thermal oxidation process is used to form the gate oxide layer 2. The temperature of the thermal oxidation process of the gate oxide layer 2 includes 1000° C. to 1100° C. The process gas includes oxygen or water vapor; in an oxygen or water vapor environment. In this environment, silicon atoms on the surface of the semiconductor substrate 1 react with oxygen to grow a layer of silicon dioxide (SiO2) as the gate oxide layer.
[0051] Step S103 , depositing a first polysilicon layer 3 , wherein the first polysilicon layer 3 completely fills the gate trench and extends to the surface of the gate oxide layer 2 outside the gate trench.
[0052] Step S104, cancel the CMP process after polysilicon deposition and perform polysilicon etching back, the polysilicon etching back removes the first polysilicon layer 3 outside the gate trench and stops on the top surface of the gate oxide layer 2, and the first polysilicon layer 3 retained in the gate trench forms a polysilicon gate.
[0053] In the embodiment of the present invention, a wafer on which polysilicon deposition has been completed in a related front-end process is loaded into a reaction chamber of a plasma etching device through a wafer transport system, and poly etchback is completed by chemically reacting etching gas with polysilicon.
[0054] Step S105: performing a first stress reduction process to replace the stress reduction function of the CMP process after polysilicon deposition, the first stress reduction process comprising:
[0055] A stress release groove is formed in a scribe line (not shown). On a wafer formed of a semiconductor substrate 1, the scribe line is located at the periphery of a die corresponding to an IGBT device chip.
[0056] In the embodiment of the present invention, the first stress reduction process further includes:
[0057] In the field plate formation process of the termination region 102 , the polysilicon field plate is removed.
[0058] In the process of forming the contact hole 4, the width of the contact hole 4 at the top of the terrace region between the gate trenches is reduced.
[0059] like Figure 3 As shown, the contact hole 4 passes through the interlayer film 7 and is connected to the front metal layer 8 formed on the top of the interlayer film 7. A contact hole 4 is also formed on the top of a portion of the polysilicon gate, and the size of the contact hole 4 on the top of the polysilicon gate is also reduced.
[0060] like Figure 2 As shown, the following steps are also included:
[0061] Step S201, forming a field oxide layer 6 on the surface of the semiconductor substrate 1, the field oxide layer 6 is located in the terminal region 102, the terminal region 102 surrounds the active region 101, and the active region 101 is the primary cell formation region of the IGBT device. Usually, there is a transition region between the terminal region 102 and the active region 101.
[0062] In the embodiment of the present invention, the field oxide layer 6 is formed by stacking a first thermal oxide layer formed by a thermal oxidation process and a second CVD oxide layer formed by CVD deposition.
[0063] Before performing the thermal oxidation process of the first thermal oxide layer, the process further includes: etching the surface of the semiconductor substrate 1 and then performing wet cleaning.
[0064] The formation area of the field oxide layer 6 is defined by using a hard mask layer.
[0065] In some embodiments, after the second CVD oxide layer of the field oxide layer 6 is formed, a hard mask layer is formed, and then the hard mask layer is patterned and etched, and then the field oxide layer 6 is etched.
[0066] In some embodiments, the field oxide layer 6 is formed before the gate trench is formed. In some embodiments, the field oxide layer 6 is formed after the polysilicon gate is formed.
[0067] Step S202, canceling the CMP process after the field oxide layer 6 is formed and performing a second stress reduction process to replace the stress reduction function of the CMP process after the field oxide layer 6 is formed, the second stress reduction process includes:
[0068] By reducing the first thermal process promoted by annealing of the doped regions formed after the field oxide layer 6 is formed, thermal stress is reduced and stress reduction is thereby achieved.
[0069] In an embodiment of the present invention, in the second stress reduction process, the doped region formed after the field oxide layer 6 is formed includes a second conductivity type doped ring region of the terminal region 102, a second conductivity type first well region (not shown) or a first conductivity type second well region (not shown) of the active region 101.
[0070] In some embodiments, the second conductivity type doped annular region includes an equipotential ring 5 .
[0071] The steps to reduce the first heat process include:
[0072] Reducing the process time of the first thermal process;
[0073] Optimizing the temperature curve in the first thermal process includes reducing the heating rate or the cooling rate. In some embodiments, in optimizing the temperature curve in the first thermal process, multi-stage temperature control is used to reduce the heating rate or the cooling rate.
[0074] The second stress reduction process includes the following sub-steps:
[0075] Ions of the second conductivity type are implanted in the selected area of the terminal region 102 to form a second conductivity type doped annular region. Taking an N-type device as an example, in the preparation of the terminal structure, specific impurities (such as boron ions) are implanted into the edge area of the semiconductor substrate 1, such as a silicon substrate, by ion implantation to change the doping concentration of the region, forming a plurality of concentric annular high-doping regions.
[0076] A uniform first oxide layer is formed on the surface of the semiconductor substrate 1 by using the PECVD process. That is, a layer of passivation material is deposited on the surface of the terminal area, and the reaction gas is introduced into the reaction chamber by using the chemical vapor deposition (CVD) technology, and a chemical reaction occurs under the action of plasma to form a uniform oxide layer on the surface of the chip;
[0077] Ions of the second conductivity type are implanted in selected regions of the active region 101 to form a first well region, or ions of the first conductivity type are implanted to form a second well region.
[0078] A carrier storage layer (not shown) heavily doped with the first conductive type is formed in the top region of the drift region at the bottom of the first well region in the active region 101 .
[0079] Afterwards, an annealing process with a first thermal process is performed.
[0080] That is, in the preparation of the device cell region, i.e., the active region, impurities such as phosphorus and boron are implanted into the region defined by the photoresist, and the diffused impurities are driven forward by a thermal process to form a P-well and an N-well.
[0081] In the embodiment of the present invention, the semiconductor substrate 1 has a first conductive type of doping, the gate trench passes through the first well region, and the surface of the first well region covered by the side of the gate trench is used to form a conductive channel.
[0082] The semiconductor substrate 1 at the bottom of the first well region serves as a drift region.
[0083] like Figure 3 As shown, after forming the contact hole 4, the method further includes:
[0084] A front metal layer 8 is formed, and the front metal layer 8 is patterned to form a gate and an emitter. The gate will be connected to the polysilicon gate through the corresponding contact hole 4 at the bottom. The emitter will be connected to the emitter region at the bottom through the corresponding contact hole 4 at the bottom, and the emitter region will be self-aligned to the surface area of the first well region formed on the side of the gate trench corresponding to the polysilicon gate. Part of the polysilicon gate will also be connected to the emitter through the contact hole 4 at the top, and the polysilicon gate connected to the emitter is no longer used to control the conductive channel.
[0085] A first passivation layer 9 is formed. The material of the first passivation layer 9 includes a SiON layer, a SiO2 layer, a SiN layer and a Si-rich silicon oxide layer.
[0086] A second passivation layer 10 is formed, and the material of the second passivation layer 10 includes polyimide.
[0087] After that, the back process is also included:
[0088] The semiconductor substrate 1 is back-thinned.
[0089] A collector region 12 doped with the second conductivity type is formed on the back side of the semiconductor substrate 1 .
[0090] A back metal layer 13 is formed on the back side of the collector region 12 and constitutes a collector electrode.
[0091] In some embodiments, a buffer layer 11 heavily doped with the first conductivity type is further formed between the drift region and the collector region 12 formed by the semiconductor substrate 1. The buffer layer 11 is formed by a front-side process or a back-side process.
[0092] The embodiment of the present invention adopts a non-CMP process to manufacture IGBT devices. Since the function of reducing stress by the CMP process cannot be achieved after the CMP process is cancelled, the embodiment of the present invention also adopts a first stress reduction process to reduce stress after the CMP process after polysilicon deposition is cancelled to achieve the same stress reduction effect as the CMP process after polysilicon deposition. The first stress reduction process of the embodiment of the present invention can be achieved by forming a stress release groove in the scribe groove, or further combined with removing the polysilicon field plate or reducing the width of the contact hole 4 at the top of the platform area. Therefore, even if the CMP process after polysilicon deposition is cancelled in the embodiment of the present invention, the influence of the CMP process after polysilicon deposition on stress can be compensated by making special settings and adjustments to the overall process, that is, the embodiment of the present invention can achieve the same improvement in stress. In addition, the embodiment of the present invention can further cancel the CMP process after the field oxide layer 6 is formed, and adopt the second stress reduction process to eliminate the adverse effect of the CMP process after the field oxide layer 6 is cancelled on stress. It can be seen that the embodiment of the present invention can not only achieve the cost reduction effect brought about by canceling the CMP process, but also overcome the adverse effect of canceling the CMP process on stress. Therefore, the embodiment of the present invention can be implemented using a CMP-free process, thereby reducing the process cost, and is particularly suitable for reducing the process cost of small-sized primitives.
[0093] In the conventional IGBT process with small steps, CMP is performed after polysilicon (poly) deposition (depo) due to stress problems. However, in the embodiment of the present invention, CMP is cancelled after poly deposition, and polysilicon is etched back (polyetch back) instead, and the process stops when the polysilicon contacts the gate oxide layer (gate oxide).
[0094] The stress problem is solved by adding trench etching design in the scribe lines on both sides of the chip, removing the polysilicon field plate design, and reducing the size of the contact hole (CT) in the platform area (mesa) to reduce the stress generated during the wafer manufacturing process.
[0095] Adding trench etching design in the scribe groove: After the grooves, i.e. stress relief grooves, are etched in the scribe grooves, the stress can be released through these stress relief grooves. From a physical point of view, it is like opening up some "release channels" in a constrained structure. The stress will be redistributed along the weak areas of the material or the areas with space buffer, i.e. the stress relief groove areas.
[0096] The design of removing the polysilicon field plate can effectively reduce the in-plane height difference, create more favorable conditions for subsequent layer alignment, and expand the process window.
[0097] When the CT size in a mesa structure is reduced, the stress concentration on the surrounding material will be reduced. Because stress is usually concentrated at the edges and corners of the structure, a smaller CT size means that the range of edge effects is relatively reduced.
[0098] In addition, in the embodiment of the present invention, after the field oxide layer 6 is grown, CMP is not used, and a hard mask layer (depo) is directly deposited. It includes: etching on the surface of a semiconductor substrate such as a silicon substrate in sequence, wet cleaning, and then compounding a silicon dioxide layer generated by thermal oxidation and a silicon dioxide layer generated by chemical vapor deposition to form a field oxide layer 6. The stress increase caused by the cancellation of CMP can be reduced by shortening the thermal process of the P-type well (P well) drive or the carrier storage layer (CS) drive in the subsequent process. Reduce the thermal process time or optimize the temperature curve: In the thermal process, the rapid change of temperature is one of the main reasons for the generation of stress. By reducing the heating and cooling rates, the material can be given enough time to adapt to the temperature change, thereby reducing thermal stress. A multi-stage temperature control strategy is adopted to avoid direct transition from one extreme temperature to another.
[0099] Compared with the prior art, the embodiment of the present invention does not adopt the CMP process, and then reduces the stress caused by adjusting the design or process. After a series of rigorous and comprehensive testing and optimization processes, the final effect presented has excellently met the stringent requirements of practical applications in terms of accuracy, stability, reliability and other aspects. At the same time, the process parameters involved in each link, whether it is temperature, pressure, duration, or material ratio, have been carefully adjusted and strictly controlled to achieve a high degree of adaptation with the actual application scenario. Through such scientific and reasonable integration and improvement, it is possible to effectively and effectively achieve a significant reduction in production costs while ensuring that product quality and performance are not affected, thereby winning greater advantages and more development opportunities for enterprises in the fierce market competition.
[0100] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.
Claims
1. A method for manufacturing an IGBT device, characterized in that: The CMP-free process includes the following steps: forming a gate trench in a selected region of the semiconductor substrate; forming a gate oxide layer on the inner surface of the gate trench and the surface of the semiconductor substrate outside the gate trench; Depositing a first polysilicon layer, wherein the first polysilicon layer completely fills the gate trench and extends to a surface of the gate oxide layer outside the gate trench; canceling the post-polysilicon deposition CMP process and performing polysilicon etching back, wherein the polysilicon etching back removes the first polysilicon layer outside the gate trench and stops on the top surface of the gate oxide layer, and the first polysilicon layer remaining in the gate trench forms a polysilicon gate; A first stress reduction process is performed to replace the stress reduction function of the polysilicon post-deposition CMP process, wherein the first stress reduction process comprises: A stress relief groove is formed in the scribe line.
2. The method for manufacturing an IGBT device according to claim 1, wherein: The first stress reduction process further comprises: In the field plate formation process of the termination region, the polysilicon field plate is removed.
3. The method for manufacturing an IGBT device according to claim 2, wherein: The first stress reduction process further comprises: In the process of forming the contact hole, the width of the contact hole at the top of the terrace region between the gate trenches is reduced.
4. The method for manufacturing an IGBT device according to claim 1, wherein: The following steps are also included: Forming a field oxide layer on the surface of the semiconductor substrate, wherein the field oxide layer is located in a terminal region, wherein the terminal region surrounds an active region, and the active region is a region where a primitive cell of an IGBT device is formed; The CMP process after the field oxide layer is formed is cancelled and a second stress reduction process is performed to replace the stress reduction function of the CMP process after the field oxide layer is formed, and the second stress reduction process includes: The thermal stress is reduced and stress reduction is achieved by reducing the first thermal process driven by annealing of the doped regions formed after the field oxide layer is formed.
5. The method for manufacturing an IGBT device according to claim 4, wherein: In the second stress reduction process, the doped region formed after the field oxide layer is formed includes the second conductivity type doped annular region of the terminal region, the second conductivity type first well region of the active region or the first conductivity type second well region.
6. The method for manufacturing an IGBT device according to claim 5, wherein: The step of reducing the first thermal process comprises: reducing the process time of the first thermal process; Optimizing the temperature curve in the first thermal process includes reducing the heating rate or the cooling rate.
7. The method for manufacturing an IGBT device according to claim 6, wherein: In optimizing the temperature curve in the first thermal process, multi-stage temperature control is used to reduce the heating rate or the cooling rate.
8. The method for manufacturing an IGBT device according to claim 6, wherein: The second stress reduction process comprises the following steps: Performing ion implantation of a second conductivity type in a selected area of the terminal region to form a second conductivity type doped annular region; A uniform first oxide layer is formed on the surface of the semiconductor substrate by using a PECVD process; Performing ion implantation of the second conductivity type in a selected area of the active area to form the first well area or performing ion implantation of the first conductivity type to form the second well area; The annealing process is carried out with the first thermal process.
9. The method for manufacturing an IGBT device according to claim 8, wherein: The semiconductor substrate has a first conductive type doping, the gate trench passes through the first well region, and the surface of the first well region covered by the side of the gate trench is used to form a conductive channel; The semiconductor substrate at the bottom of the first well region serves as a drift region.
10. The method for manufacturing an IGBT device according to claim 9, wherein: The second stress reduction process further comprises: A carrier storage layer heavily doped with a first conductive type is formed in a top region of the drift region at the bottom of the first well region in the active region.
11. The method for manufacturing an IGBT device according to claim 4, wherein: The field oxide layer is formed before the gate trench is formed; or, the field oxide layer is formed after the polysilicon gate is formed.
12. The method for manufacturing an IGBT device according to claim 1, wherein: When forming the gate trench, a first photoresist pattern formed by a photolithography process is first used to define the formation area of the gate trench, and then the semiconductor substrate is dry-etched using the first photoresist pattern as a mask to form the gate trench, and then the semiconductor substrate is cleaned to remove etching residues.
13. The method for manufacturing an IGBT device according to claim 1, wherein: The gate oxide layer is formed by a thermal oxidation process, the temperature of the thermal oxidation process of the gate oxide layer includes 1000° C. to 1100° C., and the process gas includes oxygen or water vapor.
14. The method for manufacturing an IGBT device according to claim 5 or 8, characterized in that: The second conductivity type doped annular region includes an equipotential ring.
15. The method for manufacturing an IGBT device according to claim 4, wherein: The field oxide layer is formed by stacking a first thermal oxide layer formed by a thermal oxidation process and a second CVD oxide layer formed by CVD deposition.