Semiconductor device

Abstract

The invention discloses a semiconductor device, and aims to reduce conduction loss and optimize device performance. The device comprises an arranged unit structure, and the unit structure comprises a drift layer formed on a substrate; the fin structure protrudes out of the substrate and is formed by stacking regions of different conductive types; a recess is formed between the adjacent fins; the grid electrode wraps the fin through the dielectric layer and is isolated, the fin is transversely clamped between the recesses, and the depths of the recesses reach the carrier expansion layer; the distance between the longitudinal adjacent recesses is less than or equal to 1 micron; and source / emitter and drain contact regions are respectively formed on two sides of the substrate. The lateral recess width is less than the recess width at the interruption of the longitudinal source / emitter contact region. According to the invention, by interrupting the grid electrode in the source electrode contact area, the JFET effect is weakened, and low conduction loss and performance improvement are realized.

Description

Technical Field

[0001] The present invention relates to the field of power semiconductor devices. Power semiconductor devices can withstand blocking voltages of several hundred volts and can therefore be implemented as vertical structures. The semiconductor wafer is based on semiconductor materials such as silicon, silicon carbide or gallium nitride. The present invention demonstrates a novel structure that allows the device to have low state losses, high cell stacking density and reduced electric field stress on the gate oxide. Background Art

[0002] Medium voltage power semiconductor devices can be realized with planar and recessed MOS cell designs like IGBT and MOSFET designs. These devices have a gate contact which is electrically isolated from the rest of the transistor structure by a suitable dielectric material such as silicon dioxide, which is used to control the device and switch it from a blocking state to a conducting state and vice versa. They are usually manufactured with a layer structure arranged between the source and the drain on the other side. An N-doped drift layer is arranged between the drain and the source. On the source side, a P-doped base layer is in direct contact with the source electrode. The N-doped source region is embedded in the base layer and is in contact with the source electrode through an opening.

[0003] The recessed cell concept is often used to reduce on-resistance, increase packing density, and widen channel width to optimize the device and achieve a better technology curve. However, the blocking capability of the recessed structure is low due to the high electric field at the bottom corner of the recess. In addition, the increased capacitance leads to poor controllability and high switching losses, and high short-circuit current is expected due to the high cell density in the recessed design. Therefore, many designs for optimizing the device structure have been proposed in the prior art, with special attention paid to the area between active MOS cells. The advantage is that the conduction loss is reduced by reducing the distance between the recesses. IGBT and MOSFET (Si and SiC) have solved these device optimization issues. As shown in the following prior art documents: [1] EP 3227924 B1 Power Semiconductor Device; [2] Proc. ISPSD 2023 Proposal of Vertical-channel Fin-SiC MOSFETtoward Future Device Scaling; [3] GB 2587645 A Semiconductor Device having a gate electrode formed in a trench structure [4] US 0216331 Semiconductor Device and Method for Designing Thereof Semiconductor device and its design method.

[0004] In [2], a silicon carbide recessed etched double implanted MOS (SiC TED MOS) was proposed, in which three channel types were proposed to increase channel mobility and improve R ON A. Basically, the current flows horizontally as in the planar cell concept, but with the addition of some advantages of the recessed cell concept. The disadvantage of this design is that a long channel length is required, which reduces the on-current, therefore, the cell requires a large area and the JFET area has to be carefully taken care of.

[0005] In [1], a silicon carbide recessed field effect transistor device with dual gates is proposed in which current flows vertically. The semiconductor is arranged in multiple vertical field effect transistor units, including a body region surrounded by a gate layer, where the distance between the two sides is 1 μm or less. In this design, the current flows vertically, but due to the significant JFET effect, electrons are horizontally transferred before reaching the drain contact, which increases the on-resistance. Summary of the invention

[0006] In order to solve the above problems, the present invention provides a semiconductor device having low conduction loss, stable gate characteristics, improved blocking capability and good controllability.

[0007] In order to achieve the above object, a semiconductor device designed by the present invention includes a plurality of arranged units, wherein the units include: a drift layer formed of a substrate of a first conductivity type; The fin structure is arranged on the first main side of the substrate and protrudes along the y direction, and is disposed above the semiconductor surface. The fin structure is composed of a stack of a first conductive type region, a second conductive type body region, and a first conductive type carrier expansion layer region from top to bottom; A depression is formed between two adjacent fin structures; A gate is coated on the outside of the fin structure through a gate dielectric layer and isolated from the fin structure, wherein each fin structure is laterally sandwiched between two recesses in the x direction, the depth of the recess is greater than or equal to the position where the first conductive type carrier extension layer region is located; and the distance between two longitudinally adjacent recesses in the z direction is less than or equal to 1 μm; a contact region formed on the first main side of the substrate and connected to a source or emitter electrode of the semiconductor device; A contact region is formed at the second main side of the substrate and connected to the drain of the semiconductor device.

[0008] The width between two laterally adjacent recesses in the x direction is d1, d1 is in the submicron or micron range, and the recesses interrupt the contact area of ​​the source or emitter electrode in the z direction, the width of the interruption is d2, and width d1<width d2.

[0009] Further, the semiconductor device includes a second conductivity type blocking region, wherein the second conductivity type blocking region is implanted at the bottom of the recess and is floating; Of course, the second conductive type blocking region can also be implanted at the bottom of the recess and be in electrical contact. The electrical contact refers to the contact region where the second conductive type blocking region is electrically connected to the source or emitter electrode. The electrical contact of the second conductive type blocking region is formed by etching the middle part of the recess, thereby defining the potential of the second conductive type blocking region.

[0010] In another solution, the gate dielectric layer covering the fin structure includes a recessed top dielectric layer, a fin structure top dielectric layer and a fin structure side dielectric layer, and the thicknesses of the recessed top dielectric layer, the fin structure top dielectric layer and the fin structure side dielectric layer are different.

[0011] At the same time, the gate dielectric layer extends to the contact region of the source or emitter electrode and overlaps with the source or emitter electrode contact region in the y direction, or does not extend to the source or emitter electrode contact region as required.

[0012] In some different embodiments, the cells are arranged in a hexagonal shape. The semiconductor device designed by the present invention has a three-dimensional layout structure of the region of the vertical channel, that is, the described fin structure, which is surrounded by a gate electrode and a recess. Although the distance between the recesses is in the range of 1 μm or less, the JFET effect is significantly larger. However, the gate is interrupted in the area where the source contact is arranged, and the distance between the two gates in this area is larger, thereby significantly weakening the JFET effect. Therefore, this semiconductor device not only has the advantage of reducing the low conduction loss caused by the recess, but also avoids the disadvantage of increased on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a top view of Example 1.

[0014] Figure 2 This is a three-dimensional view of Example 1.

[0015] Figure 3 It is a top view of Example 2.

[0016] Figure 4 yes Figure 3 Middle AA section view.

[0017] Figure 5 This is an enlarged view of the fin structure.

[0018] Figure 6 It is a structural schematic diagram of Example 3.

[0019] Figure 7 It is a top view of the prior art. DETAILED DESCRIPTION

[0020] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0021] Example 1.

[0022] like Figure 1 As shown, the semiconductor device described in this embodiment includes semiconductors with layers of different conductivity types, which are arranged between a source 1 on one side and a drain 2 on the other side. A substrate of the first conductivity type forms a drift layer 3. A recess 5 is formed by selectively etching the substrate to a certain depth, thereby forming a micron or submicron scale fin structure 4 protruding above the substrate between two adjacent recesses 5. Naturally, multiple fin structures 4 will be formed between multiple recesses 5. Figure 1 One embodiment of the present invention is presented in FIG. 1 , but it is not a preferred embodiment for carrying out the present invention. Its layout is similar to that of FIG. Figure 7 The prior art shown in FIG. 5 is provided around the vertical field effect transistor unit to form a plurality of fin structures 4 .

[0023] The fin structure 4 includes, from top to bottom, a first conductive type region 6 (N+ source), a second conductive type body region 7 (P+ body) and a first conductive type carrier expansion layer region 8 (N+ CSL). The first conductive type region 6 is a highly doped region, the first conductive type carrier expansion layer region 8 is also a highly doped region, and the doping concentration of the first conductive type carrier expansion layer region 8 is higher than the doping concentration of the drift layer 3. At the same time, the outside of the fin structure 4 is covered by the dielectric layer of the gate 11.

[0024] The function of the first conductive type carrier extension layer region 8 is to conduct electrons to the region without JFET effect. The gate dielectric layer 9 is connected to the gate electrode 11 of the device through a layer of conductive material (such as highly doped polysilicon). By modulating the voltage applied to the gate electrode 11, a vertical MOS channel can be formed in the fin structure 4, so that the semiconductor device is switched from a blocking state to a conducting state, and vice versa.

[0025] At the same time, if Figure 2As shown, the height of the fin structure 4 in the y direction is defined by the etching depth on the substrate. In this embodiment, the recess 5, that is, the upper surface 5 - 1 of the recess 5 is lower than the lower surface 8 - 1 of the first conductive type carrier extension layer region 8 .

[0026] The distance between two adjacent recesses 5 , that is, the maximum width of the fin structure 4 is d1 . Reducing the width d1 can increase the density of the recesses 5 , thereby improving device performance.

[0027] The fin structures 4 are arranged in the x direction with a micron or submicron pitch, and the recesses 5 are blocked in the z direction by the contact area of ​​the source 1 or the emitter to form an interruption 1-1, forming an area with a larger distance between the recesses 5. The width of the interruption 1-1 is d2, and the size of the width d2 is less than or equal to 1μm. In general, the width d2 is much larger than the width d1.

[0028] When the width of the fin structure 4 is small, that is, the width d1 is small, there will be a larger JFET effect, so the electron path will be deflected, such as Figure 1 The electron flow path shown in is deflected in the z direction. In the y direction, Figure 2 As shown, the electrons first flow through the first conductive type region 6, i.e., the N+ source region, in the z direction, then flow vertically through the second conductive type body region 7, i.e., the P+ body region, to the first conductive type carrier expansion layer region 8, i.e., the N+ CSL region, and then turn back in the z direction and flow along the first conductive type carrier expansion layer region 8 (opposite to the first z direction), until the electrons reach the region where the JFET effect is extremely low or non-existent. That is, the region where the distance between the recesses 5 is large, as shown in FIG. Figure 2 As shown, the electrons return to the area below where the source 1 contact 10-1 is arranged. In this way, the electrons can flow longitudinally toward the drain 2 in the y direction again.

[0029] The advantage of this structure is that the electric field at the bottom of the recess 5 is relatively low, which means that during the turn-off operation, the oxide forming the gate dielectric layer 9 will not be affected by excessive electric field.

[0030] In addition, in some embodiments, a second conductive type blocking region 10 (P+blocking) may be provided below the recess 5, and an additional high-doping blocking layer may be provided to further reduce static and dynamic electric fields, especially high electric fields, experienced by the gate dielectric layer 9. At the same time, most carriers will not flow around the second conductive type blocking region 10.

[0031] In the most preferred embodiment, the second conductivity type blocking region 10 is floating, that is, electrically isolated from the source 1. In other embodiments, it can be electrically connected to the source 1 of the semiconductor device.

[0032] Example 2.

[0033] like Figure 3-5 As shown, the semiconductor device described in this embodiment is a preferred embodiment of the present invention. Figure 3 As shown, the semiconductor device described in this embodiment is similar to the semiconductor device described in the embodiment in a top view. Figure 1 The disclosed semiconductor device is slightly different, but the concepts are the same. The second conductive type blocking region 10 has a contact 10-1, which is made by etching the middle position of the recess 5. The potential of the second conductive type blocking region 10 can be controlled by the contact 10-1. The source 1 and the second conductive type blocking region 10 contact 10-1 are arranged in an interlaced manner, so the corresponding fin structure 4 also forms an interlaced layout.

[0034] At the same time Figure 3 The path of the electron current is also shown in the figure. Starting from the source 1, under the action of the gate 11, the electron current flows in the longitudinal y direction to the first conductive type carrier expansion layer region 8 through the vertical channel composed of the first conductive type region 6 and the second conductive type body region 7, and then flows horizontally in the z direction on the first conductive type carrier expansion layer 8 until the electrons reach the region without JFET effect, which is located in another region such as Figure 3 The light passes under the source electrode 1 on the other side of the electrode, and finally flows vertically to the drain electrode 2.

[0035] like Figure 4 , Figure 5 As shown, a second conductive type blocking region 10 is provided at the bottom of the recess 5. The thickness of the gate dielectric layer 9 surrounding the fin structure 4 corresponding to different surfaces of the fin structure 4 can be set according to the needs of the actual application, that is, there is no restriction on the thickness. However, in some embodiments, the thickness of the gate dielectric layer 9 of the fin structure 4 corresponding to different surfaces of the fin structure 4 is not the same, that is, Figure 5 As shown in the bottom Ox1 position of the recess 5 , the top Ox2 position of the fin structure 4 , and the side Gox position of the fin structure 4 , preferably Ox1≠Ox2≠Gox.

[0036] Example 3.

[0037] like Figure 6 As shown, the semiconductor device described in this embodiment is a multi-unit arrangement structure composed of hexagonal transistor units 12, and the gate 11 can be located in the recess 5 forming the fin structure 4. Multiple fin structures 4 connect the source 1 contact regions to each other.

[0038] In the description of the present invention, it should be noted that the xyz axes are the directions marked in the accompanying drawings, and the terms "vertical", "up", "down", "horizontal", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.

[0039] In the description of the present invention, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be a connection between the two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. Finally, it should be explained that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions recorded in the aforementioned embodiments, or to make equivalent substitutions for some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device comprising a plurality of arranged units, wherein the units include: A drift layer formed by a first conductive type substrate; Features: The fin structure is arranged on the first main side of the substrate and protrudes along the y direction, and is disposed above the semiconductor surface. The fin structure is composed of a stack of a first conductive type region, a second conductive type body region, and a first conductive type carrier expansion layer region from top to bottom; A depression is formed between two adjacent fin structures; A gate is coated on the outside of the fin structure through a gate dielectric layer and isolated from the fin structure, wherein each fin structure is laterally sandwiched between two recesses in the x direction, the depth of the recess is greater than or equal to the depth of the first conductive type carrier extension layer region; and the distance between two longitudinally adjacent recesses in the z direction is less than or equal to 1 μm; a contact region formed on the first main side of the substrate and connected to a source or emitter electrode of the semiconductor device; A contact region is formed at the second main side of the substrate and connected to the drain of the semiconductor device.

2. The semiconductor device according to claim 1, wherein: The width between two laterally adjacent recesses in the x direction is d1, d1 is in the submicron or micron range, and the recesses interrupt the contact area of ​​the source or emitter electrode in the z direction, the width of the interruption is d2, and width d1<width d2.

3. The semiconductor device according to claim 1 or 2, characterized in that: A second conductive type blocking region is included. The second conductive type blocking region is implanted at the bottom of the recess and is floating.

4. The semiconductor device according to claim 1 or 2, characterized in that: A second conductive type blocking region is included. The second conductive type blocking region is implanted in the bottom of the recess and is in electrical contact.

5. The semiconductor device according to claim 4, wherein: The second conductivity type blocking region is electrically connected to the contact region of the source or emitter electrode.

6. The semiconductor device according to claim 5, characterized in that: An electrical contact of the second conductive type blocking region is formed by etching the gate and the middle portion of the recess.

7. The semiconductor device according to claim 1 or 2, characterized in that: The gate dielectric layer covering the fin structure includes a recessed top dielectric layer, a fin structure top dielectric layer and a fin structure side dielectric layer, and the thicknesses of the recessed top dielectric layer, the fin structure top dielectric layer and the fin structure side dielectric layer are different.

8. The semiconductor device according to claim 7, wherein: The gate dielectric layer extends to the contact region of the source or emitter electrode and overlaps with the source or emitter electrode contact region in the y direction, or does not extend to the source or emitter electrode contact region.

9. The semiconductor device according to claim 1, wherein: The cells are arranged in a hexagonal shape.

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