Semiconductor device and preparation method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, and relates to the technical field of semiconductors. An epitaxial layer; the epitaxial layer comprises a first surface far away from one side of the substrate, and the epitaxial layer further comprises a well region and a first region; a gate trench is arranged on the first surface, and the gate trench extends into the epitaxial layer from the first surface; the gate structure is located in the gate groove, the gate structure comprises a first insulating layer formed on the surface of the gate groove, a first polycrystalline silicon layer and a first conductive material layer, the first polycrystalline silicon layer and the first conductive material layer are formed in the first insulating layer, and the conductivity of the first conductive material layer is larger than that of the first polycrystalline silicon layer; the source electrode is formed on the first surface and is electrically connected with the first region; and the drain electrode is arranged on one side, far away from the epitaxial layer, of the substrate. According to the technical scheme disclosed by the invention, the square resistance of the gate structure is reduced, so that the on resistance of the device in the starting transient state is reduced.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a semiconductor device and a method for preparing the same, a power module, a power conversion circuit and a vehicle. Background Art

[0002] In the field of semiconductor technology, trench power devices have the advantages of high current density and small unit cell size of a single device. The device usually has a trench gate structure, and the gate is formed by filling polysilicon in the trench. However, for the trench gate structure, the gate is long. When the gate bias voltage is applied to the device, the gate resistance is large, and the gate voltage cannot reach the end point of the gate immediately, causing a delay. This delay in the propagation of the gate voltage will cause a large on-resistance when the device is turned on. Summary of the invention

[0003] The embodiments of the present application provide a semiconductor device and a method for preparing the same, a power module, a power conversion circuit and a vehicle, which can reduce the block resistance of the gate structure, thereby reducing the on-resistance of the device in the transient state of being turned on.

[0004] In one aspect, an embodiment of the present application provides a semiconductor device, including: A substrate; an epitaxial layer, arranged on the substrate, the epitaxial layer is set to a first conductivity type, the epitaxial layer includes a first surface away from the substrate, the epitaxial layer also includes a well region and a first region, the first region is arranged on the first surface, the first region is of the first conductivity type, the well region is set to a second conductivity type, the well region is arranged on a side of the first region away from the first surface, the first surface is provided with a gate trench, the gate trench extends from the first surface to the epitaxial layer, and runs through the first region and the well region; A gate structure is located in the gate trench, the gate structure includes a first insulating layer formed on the surface of the gate trench, and a first polysilicon layer and a first conductive material layer formed in the first insulating layer, the conductivity of the first conductive material layer is greater than the conductivity of the first polysilicon layer; A source electrode is formed on the first surface and is electrically connected to the first region; The drain is arranged on a side of the substrate away from the epitaxial layer.

[0005] In some embodiments, the first polysilicon layer is formed between the first insulating layer and the first conductive material layer.

[0006] In some embodiments, the first polysilicon layer includes an end portion adjacent to the first surface, and the first conductive material layer covers the end portion.

[0007] In some embodiments, the first insulating layer includes an extension portion extending onto the first surface, and the first polysilicon layer at least partially covers the extension portion.

[0008] In some embodiments, the first conductive material layer is a metal material layer.

[0009] In some embodiments, the metal material layer includes molybdenum, tungsten or titanium.

[0010] In some embodiments, a source trench is disposed on the first surface, the source extends into the source trench, and the semiconductor device further includes a second insulating layer disposed on the surface of the source trench, and a second polysilicon layer disposed between the second insulating layer and the source.

[0011] In some embodiments, the epitaxial layer further includes a second region, the second region is disposed on the first surface and is located outside the first region and the well region, the second region is of the second conductivity type, and the source trench is formed in the second region.

[0012] In some embodiments, the portion of the source electrode extending into the source trench is a second conductive material layer, and the second polysilicon layer is formed between the second conductive material layer and the second insulating layer.

[0013] The technical solution provided in the embodiment of the present application, wherein the semiconductor device includes a gate structure formed in a gate trench, and the gate structure specifically includes a first insulating layer formed on the surface of the gate trench, and a first polysilicon layer and a first conductive material layer formed in the first insulating layer, and the conductivity of the first conductive material layer is greater than the conductivity of the first polysilicon layer. Therefore, compared with the prior art, this structure can effectively reduce the square resistance of the gate, thereby reducing the on-resistance of the device when it is turned on transiently, and improves the charging capacity of the gate, that is, under the same gate voltage, the gate can be charged to the required potential level more quickly, thereby improving the response speed and performance of the semiconductor device.

[0014] On the other hand, an embodiment of the present application further provides a method for preparing a semiconductor device, comprising: An epitaxial layer is formed on a substrate, the epitaxial layer includes a first surface on a side away from the substrate, and the epitaxial layer also includes a well region and a first region, the first region is located on the first surface, the well region is located on a side of the first region away from the first surface, and a gate trench is formed in the first surface, the gate trench extends from the first surface to the epitaxial layer and passes through the first region and the well region; forming a gate structure in the gate trench, the gate structure comprising a first insulating layer formed on a surface of the gate trench, and a first polysilicon layer and a first conductive material layer formed in the first insulating layer, wherein the conductivity of the first conductive material layer is greater than the conductivity of the first polysilicon layer; Forming a source electrode on the first surface, the source electrode being electrically connected to the first region and the second region; A drain is formed, where the drain is located on a side of the substrate away from the epitaxial layer.

[0015] The preparation method provided in the embodiment of the present application, in the process of forming the gate structure of the semiconductor device, forms a first insulating layer on the surface of the gate groove, and forms a first polysilicon layer and a first conductive material layer in the first insulating layer, and the conductivity of the first conductive material layer is greater than the conductivity of the first polysilicon layer. Therefore, the gate structure obtained can reduce the square resistance of the effective gate, thereby reducing the on-resistance of the device when it is turned on, and improves the charging capacity of the gate, that is, under the same gate voltage, the gate can be charged to the required potential level more quickly, thereby improving the response speed and performance of the semiconductor device.

[0016] In some embodiments, forming a gate structure in the gate trench includes: A first insulating layer is formed on the surface of the gate trench, and a first polysilicon layer and a first conductive material layer are sequentially formed in the first insulating layer, wherein the first polysilicon layer is arranged between the first conductive material layer and the first insulating layer.

[0017] On the other hand, an embodiment of the present application further provides a power module, which includes a substrate and a semiconductor device as described in any of the above embodiments, wherein the substrate is used to carry the semiconductor device.

[0018] In another aspect, an embodiment of the present application further provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and a semiconductor device as in any of the above embodiments, and the semiconductor device is electrically connected to the circuit board.

[0019] On the other hand, an embodiment of the present application also provides a vehicle, which includes a load and a power conversion circuit as described in the above embodiment, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0020] The above-mentioned power module, power conversion circuit and vehicle have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above-mentioned embodiments, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present application; Figure 3A schematic diagram of a process for preparing a semiconductor device provided in an embodiment of the present application; Figure 4 A schematic flow chart of another method for preparing a semiconductor device provided in an embodiment of the present application; Figure 5~Figure 15 A schematic diagram of the structures corresponding to each step in the preparation method provided in the embodiment of the present application; Fig.16 A schematic diagram of the structure of a power module provided in an embodiment of the present application; Fig.17 A schematic diagram of the structure of a power conversion circuit provided in an embodiment of the present application; Fig.18 A schematic diagram of the structure of a vehicle provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0023] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0024] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0025] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0026] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0027] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0028] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0029] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0030] Semiconductor devices in the field of semiconductor technology, such as SiC power devices, can be provided with a trench gate structure. The trench gate structure generally fills polysilicon in the trench to form a gate. However, for the trench gate structure, the gate is relatively long. When a gate bias voltage is applied to the device, the gate resistance is relatively large, and the gate voltage cannot reach the end point of the gate immediately, causing a delay. This delay in the propagation of the gate voltage will cause the on-resistance of the device to be relatively large when it is turned on.

[0031] In view of the above problems, an embodiment of the present application provides a semiconductor device, which may be a SiC metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-EffectTransistor, referred to as MOSFET). Figure 1 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present application.

[0032] like Figure 1As shown, the semiconductor device 10 includes a substrate 101, an epitaxial layer 102, a gate structure 103, a source 104, and a drain 105. The epitaxial layer 102 is disposed on the substrate 101, and the epitaxial layer 102 includes a first surface P1 away from the substrate 101. The epitaxial layer 102 also includes a well region 107 and a first region 108. The first region 108 is disposed on the first surface P1, and the well region 107 is disposed on a side of the first region 108 away from the first surface P1. The second region 109 is disposed on the first surface P1 and is located outside the first region 108 and the well region 107. The "outside" in this embodiment refers to the side away from the gate structure 103.

[0033] In the embodiment of the present application, a gate trench T1 is formed on the first surface P1 . The gate trench T1 extends from the first surface P1 into the epitaxial layer 102 and penetrates the first region 108 and the well region 107 .

[0034] For example, Figure 1 As shown, a gate structure 103 is disposed in the gate trench T1, and the gate structure 103 includes a first insulating layer 1031 formed on the surface of the gate trench T1, and a first polysilicon layer 1032 and a first conductive material layer 1033 formed in the first insulating layer 1031. In addition, in some embodiments, the first surface P1 further includes a first passivation layer 106, and the first passivation layer 106 can cover the gate structure 103 to play a role of isolation and protection.

[0035] Furthermore, the source 104 is formed on the first surface P1 and is electrically connected to the first region 108 and the second region 109; and the drain 105 is arranged on the side of the substrate 101 away from the epitaxial layer 102. In the embodiment of the present application, the conductivity type of the substrate 101, the epitaxial layer 102 and the first region 108 is the same, and can all be the first conductivity type, and the well region 107 can be the second conductivity type. For example, Al ions are injected into the well region 107, and the conductivity type is P type. The well region 107 can also be called a "P-type well region (P-well)". The conductivity type of the substrate 101, the epitaxial layer 102 and the first region 108 are all N type, and P (phosphorus) or N is injected into the first region 108. + (nitrogen) ions, the first region 108 may also be referred to as “N + contact area".

[0036] By transmitting a turn-on voltage to the gate structure 103 , when the semiconductor device 10 is forward-conducting and the operating current is small, the operating current reaches the drain 105 from the source 104 through the first region 108 , the well region 107 , the epitaxial layer 102 and the substrate 101 .

[0037] The technical solution provided by the embodiment of the present application, wherein the gate structure 103 of the semiconductor device includes a first insulating layer 1031, and a first polysilicon layer 1032 and a first conductive material layer 1033 formed in the first insulating layer 1031. The conductivity of the first conductive material layer 1033 is greater than the conductivity of the first polysilicon layer 1032, so that the square resistance of the gate structure 103 becomes smaller, thereby reducing the square resistance of the gate and reducing the on-resistance of the semiconductor device when it is turned on; through the above technical solution, the charging capacity of the gate can be improved, that is, under the same gate voltage, the gate can be charged to the required potential level faster, thereby improving the response speed and performance of the semiconductor device.

[0038] In some embodiments, still refer to the above Figure 1 As shown, the first polysilicon layer 1032 can be formed between the first insulating layer 1031 and the first conductive material layer 1033, that is, in the gate trench T1, the first insulating layer 1031, the first polysilicon layer 1032 and the first conductive material layer 1033 are sequentially formed. In this embodiment, the first insulating layer 1031 and the first polysilicon layer 1032 are in direct contact. Since there are some discrete or continuous energy levels at the interface contact between the first insulating layer 1031 and the first polysilicon layer 1032, these energy levels can be used as traps to capture carriers (electrons or holes), thereby affecting the control ability of the gate over the channel carriers. The threshold voltage can be adjusted by changing the doping concentration of the first polysilicon layer 1032, so as to maintain good interface characteristics.

[0039] In the embodiment of the present application, the first conductive material layer 1033 is mainly used to reduce its gate resistance, and its conductivity is mainly greater than the conductivity of the above-mentioned polysilicon material. There is no restriction on its specific type, for example, it can be a metal material, or other oxide materials, etc. For example, if the first conductive material layer 1033 is a metal material layer, the metal material layer can include molybdenum, tungsten or titanium, all of which have high temperature resistance and small square resistance, and can achieve the technical effect of reducing the total gate resistance. When the first conductive material layer 1033 uses an oxide material to form an oxide material layer, for example, it can be indium tin oxide (ITO), fluorine-doped tin oxide (FTO), etc. Among them, the main components of ITO are indium oxide (In2O3) and tin oxide (SnO2). The crystal structure of ITO is a cubic system, and the presence of oxygen vacancies provides free electrons, which enhances the conductivity of the material. At the same time, In2O3, as a semiconductor matrix, brings good light transmittance and a large optical band gap, while the doping of SnO2 changes the carrier concentration and electronic structure of the material to give it ideal electrical properties. Therefore, ITO material has both good transparency and certain conductivity. FTO is a transparent conductive oxide formed by doping fluorine into tin dioxide (SnO2). - ) to replace oxygen ions (O 2- ) is doped into the tin dioxide lattice in the form of fluorine. Doping with fluorine will introduce additional free electrons into the crystal, which become the carriers of the material, thereby enhancing the conductivity.

[0040] In some embodiments, the first insulating layer 1031 includes an extension portion 113 extending onto the first surface P1, and the first polysilicon layer 1032 includes an end portion 114 adjacent to the first surface P1, and the first conductive material layer 1033 covers the end portion 114 and at least partially covers the extension portion 113, which can avoid etching the first polysilicon layer 1032 and the first insulating layer 1031 simultaneously when etching the first conductive material layer 1033, and can also protect the corner of the first insulating layer 1031, which is thin and easily etched through. In some embodiments, a source trench T2 is provided on the first surface, and the source 104 extends into the source trench T2. The semiconductor device also includes a second insulating layer 1121 provided on the surface of the source trench T2, and a second polysilicon layer 1122 provided between the second insulating layer 1121 and the source 104.

[0041] In some embodiments, the epitaxial layer 102 further includes a second region 109, which is disposed on the first surface P1 and outside the first region 108 and the well region 107. The second region 109 is of the second conductivity type, and the source trench T2 is formed in the second region 109. Since the P-type ion concentration in the second region 109 is higher than that in the well region 107, more PN junctions are formed between the second region 109 and the epitaxial layer 102. When the operating current is large, the operating current flows from the source 104 through the second region 109, the epitaxial layer 102, and the substrate 101 to the drain 105, thereby preventing the large operating current from flowing through the well region 107, thereby protecting the channel in the well region 107.

[0042] The second region 109 penetrates the first region 108 and the well region 107 and extends to the epitaxial layer 102 , thereby optimizing the electric field distribution in the device and protecting the gate structure 103 .

[0043] In some embodiments, a source structure 112 may also be formed in the second region 109. For details, see Figure 2 As shown, Figure 1 The difference is that a source trench T2 is formed in the second region 109, and the source structure 112 in the source trench T2 includes a second insulating layer 1121 formed on the surface of the source trench T2, and a second polysilicon layer 1122 and a second conductive material layer 1123 formed in the second insulating layer 1121. The second conductive material layer 1123 is the portion where the source 104 extends into the source trench T2. The source trench T2 can also be called a "Dummy Trench", and the source structure 112 is disposed in the source trench T2.

[0044] Moreover, in some embodiments, the second polysilicon layer 1122 may be formed between the second insulating layer 1121 and the second conductive material layer 1123. In some embodiments of the present application, the source structure 112 may be formed at the same time as the gate structure 103, or may be formed one after another, or at least part of the gate structure 103 and the source structure 112 may be formed simultaneously, which is not limited in the embodiments of the present application. In the embodiments of the present application, the second insulating layer 1121 and the first insulating layer 1031 may be of the same material, the second polysilicon layer 1122 and the first polysilicon layer 1032 may be of the same material, and the second conductive material layer 1123 and the source 104 may be of the same material, for example, they are all of the same metal material.

[0045] The present application also provides a method for preparing a semiconductor device, by which the above-mentioned Figure 1 The semiconductor device in the illustrated embodiment. Figure 3A schematic diagram of a method for preparing a semiconductor device provided in an embodiment of the present application, wherein the specific structure can be referred to Figure 1 As shown, Figure 3 As shown, the preparation method comprises the following steps: Step 301, forming an epitaxial layer 102 on a substrate 101; In this step, a substrate 101 may be provided first, and then an epitaxial layer 102 may be formed on the substrate 101, and finally a specific structure may be formed on the epitaxial layer 102. Specifically, the epitaxial layer 102 includes a first surface P1 away from the substrate 101. A well region 107 and a first region 108 may be formed in the epitaxial layer 102. The first region 108 is located on the first surface P1, and the well region 107 is located on a side of the first region 108 away from the first surface P1. Step 302 , forming a gate trench T1 in the first surface P1 , wherein the gate trench T1 extends from the first surface P1 into the epitaxial layer 102 and penetrates the first region 108 and the well region 107 in the epitaxial layer; In the embodiment of the present application, SiC material can be used, and the conductivity type of the substrate 101, the epitaxial layer 102 and the first region 108 is the same, and can all be the first conductivity type. The well region 107 can be of the second conductivity type. For example, Al ions are injected into the well region 107, and the conductivity type is P-type. The well region 107 can also be called a "P-type well region (P-well)". The conductivity type of the substrate 101, the epitaxial layer 102 and the first region 108 are all N-type, and P (phosphorus) or N (nitrogen) ions are injected into the first region 108. The first region 108 can also be called an "N-type well region (P-well)". + contact area".

[0046] Step 303, forming a gate structure 103 in the gate trench T1, the gate structure 103 comprising a first insulating layer 1031 formed on the surface of the gate trench T1, and a first polysilicon layer 1032 and a first conductive material layer 1033 formed in the first insulating layer 1031, the conductivity of the first conductive material layer 1033 being greater than the conductivity of the first polysilicon layer 1032; As described in the above embodiment, in the embodiment of the present application, the specific type of material used for the first conductive material layer 1033 is not limited, for example, it can be a metal material, or other oxide materials, etc. If a metal material is used, it can be molybdenum, tungsten or titanium, which have high temperature resistance and small sheet resistance.

[0047] Step 304 , forming a source electrode 104 on the first surface P1 , wherein the source electrode 104 is electrically connected to the first region 108 ; Step 305: forming a drain electrode 105, which is located on the side of the substrate 101 away from the epitaxial layer 102. Figure 1 The semiconductor device shown in the figure, in the process of forming the gate structure 103, by forming a first insulating layer 1031 on the surface of the gate trench T1, forming a first polysilicon layer 1032 and a first conductive material layer 1033 in the first insulating layer 1031, wherein the conductivity of the first conductive material layer 1033 is greater than the conductivity of the first polysilicon layer 1032, so that in the prepared semiconductor device, compared with the prior art, the square resistance of the gate can be effectively reduced, thereby improving the charging capacity of the gate, that is, under the same gate voltage, the gate can be charged to the required potential level more quickly, thereby improving the response speed and performance of the semiconductor device.

[0048] In the embodiment of the present application, the step 303 of forming the gate structure 103 in the gate trench T1 may specifically include: A first insulating layer 1031 is formed on the surface of the gate trench T1, and a first polysilicon layer 1032 and a first conductive material layer 1033 are sequentially formed in the first insulating layer 1031, and the first polysilicon layer 1032 is disposed between the first conductive material layer 1033 and the first insulating layer 1031. Therefore, through the direct contact between the first insulating layer 1031 and the first polysilicon layer 1032, since there are some discrete or continuous energy levels at the interface contact between the first insulating layer 1031 and the first polysilicon layer 1032, these energy levels can be used as traps to capture carriers (electrons or holes), thereby affecting the control ability of the gate over the channel carriers, and the threshold voltage can be adjusted by changing the doping concentration of the first polysilicon layer 1032, so as to maintain good interface characteristics.

[0049] In some embodiments, in addition to the above steps, Figure 2 As shown, a source trench T2 may be formed in the second region 109, and a source structure 112 may be formed in the source trench T2. Specifically, the source structure 112 includes a second insulating layer 1121 formed on the surface of the source trench T2, and a second polysilicon layer 1122 and a second conductive material layer 1123 formed in the second insulating layer 1121. The steps of forming the source trench T2 and the source structure 112 may be formed simultaneously with the gate trench T1 and the gate structure 103, may be formed simultaneously with some layers, or may be formed in separate sequential steps.

[0050] Figure 4 A specific process flow chart of a method for preparing a semiconductor device provided in an embodiment of the present application, which can be combined with Figure 5-Figure 15 The schematic diagram of the preparation process shown is used to understand the preparation method of the semiconductor device in the embodiment of the present application.

[0051] like Figure 4 As shown, and also refer to Figure 5-Figure 15The method for preparing a semiconductor device provided in the embodiment of the present application may include the following steps: Step S10: Figure 5 As shown, an epitaxial layer 102 is formed on a substrate 101 .

[0052] Exemplarily, the substrate 101 in the embodiment of the present application may be a SiC substrate, and may be heavily N-type doped; in this step, an N-type lightly doped semiconductor material may be deposited on the substrate 101 to form the epitaxial layer 102 .

[0053] Step S20: Figure 6 As shown, a well region 107 and a first region 108 are formed in the first surface P1 of the epitaxial layer 102, wherein the first surface P1 is located on a side away from the substrate 101, the first region 108 formed in this step is located on the first surface P1, and the well region 107 is located on a side of the first region 108 away from the first surface P1.

[0054] Exemplarily, in this step, a mask may be formed on the first surface P1 by a photolithography process, an ion implantation region may be defined, and P + Ion implantation is performed to form a well region 107. After the mask is removed, a mask is formed again through a photolithography process to define the ion implantation area and perform N + Ion implantation is performed to form the first region 108. The implantation energy is controlled to control the ion implantation depth, so that the first region 108 is located on the first surface P1, and the well region 107 is located on a side of the first region 108 away from the first surface P1.

[0055] Step S30: Figure 7 As shown, a second region 109 is formed in the epitaxial layer 102 . The second region 109 is located at the first surface P1 and outside the first region 108 and the well region 107 .

[0056] For example, a mask may be formed by a photolithography process, an ion implantation region may be defined, and P may be performed. + Ions are implanted to form the second region 109 .

[0057] Step S40: Figure 8 As shown, a gate trench T1 is formed, which extends from the first surface P1 into the epitaxial layer 102 and penetrates the first region 108 and the well region 107 .

[0058] In some embodiments, during the process of forming the gate trench T1, a source trench T2 may also be formed on the first surface P1, and the source trench T2 is formed in the second region 109. In this step, the gate trench T1 and the source trench T2 may be simultaneously formed by an etching process.

[0059] Step S50: Fig. 9As shown, a first insulating layer 1031 is formed in the gate trench T1, and a second insulating layer 1121 is formed in the source trench T2. In this step, the insulating layer can be formed by a gate oxide process. The first insulating layer 1031 includes an extension portion 113 extending to the first surface P1.

[0060] Step S60: Fig.10 As shown, polysilicon is deposited and the excess portion is removed, and the deposited polysilicon material is patterned into a specific shape, that is, a first polysilicon layer 1032 is finally formed in the gate trench T1, and the first polysilicon layer 1032 includes an end portion 114 adjacent to the first surface P1. A second polysilicon layer 1122 is formed in the source trench T2.

[0061] Step S70: Fig.11 As shown, a first conductive material layer 1033 is formed in the gate trench T1. The conductivity of the first conductive material layer 1033 is greater than the conductivity of the first polysilicon layer 1032. The first conductive material layer 1033 covers the end 114 of the first polysilicon layer 1032 adjacent to the first surface P1, and at least partially covers the extension 113 of the first insulating layer 1031 extending to the first surface P1, which can avoid etching the first polysilicon layer 1032 and the first insulating layer 1031 at the same time when etching the first conductive material layer 1033, and can also protect the corner of the first insulating layer 1031, which is thin and easy to be etched through.

[0062] Through the above steps S50-S70, a first insulating layer 1031, a first polysilicon layer 1032 and a first conductive material layer 1033 are formed in the gate trench T1, and the above first insulating layer 1031, the first polysilicon layer 1032 and the first conductive material layer 1033 constitute the gate structure 103 of the semiconductor device. Since the conductivity of the first conductive material layer 1033 is greater than the conductivity of the first polysilicon layer 1032, the gate structure 103 can effectively reduce the square resistance of the gate, thereby improving the charging capacity of the gate. Optionally, the above first conductive material layer 1033 can generally be a metal material layer, including molybdenum, tungsten or titanium, which have high temperature resistance and the advantage of small square resistance.

[0063] Step S80: Isolate and protect the gate structure 103, such as Fig.12 As shown, a first passivation layer 106 is deposited on the first surface P1.

[0064] Step S90: Fig.13 As shown, a source 104 is formed on the first surface, and the source 104 simultaneously enters into the source trench T2 , thus obtaining a second conductive material layer 1123 .

[0065] Through the above steps S50 , S60 and S90 , a second insulating layer 1121 , a second polysilicon layer 1122 and a second conductive material layer 1123 are formed in the source trench T2 , thereby forming a source structure 112 .

[0066] For example, the source electrode 104 may be formed by depositing metal by sputtering or evaporation.

[0067] Step S100: Fig.14 As shown, a second passivation layer 110 is deposited and a pad window is formed by etching, and an insulating material is spin-coated on the surface of the second passivation layer 110 and cured after development and exposure to form an insulating dielectric layer 111. The pad window is used for subsequent electrical connection with other components.

[0068] Step S110: Fig.15 As shown, a drain 105 is formed, and the drain 105 is located on a side of the substrate 101 away from the epitaxial layer 102 .

[0069] Specifically, the substrate 101 is thinned to reduce the thickness of the substrate 101 and form a relatively flat surface, and then metal is deposited and annealed to form an ohmic contact of the drain 105 .

[0070] So far, the above embodiments of the present application Figure 2 The semiconductor device 10 shown is manufactured. It can be understood that the above manufacturing method is only an example, and some steps thereof can be adjusted to realize the manufacturing of the above semiconductor device 10.

[0071] On the other hand, an embodiment of the present application further provides a power module, Fig.16 A schematic diagram of the structure of a power module provided in an embodiment of the present application.

[0072] like Fig.16 As shown, the power module 200 includes a substrate 201 and the semiconductor device 10 in any of the above embodiments, and the substrate 201 is used to carry the semiconductor device 10 .

[0073] Exemplarily, the power module 200 can be used as one of a power amplifier, a power converter, a power controller, a power management module, or a power regulator. The power amplifier is used to amplify the power of an electrical signal. The power converter is used to convert electrical energy from one form to another form. For example, the power converter can be an AC / DC converter or a DC / DC converter. The power controller is used to control the device of power flow. The power management module is used to manage the power supply to ensure that the power is stably and efficiently distributed to different parts of the electronic device. The power regulator is used to adjust the power output to meet the needs of a specific application.

[0074] On the other hand, an embodiment of the present application further provides a power conversion circuit, Fig.17 A schematic diagram of the structure of a power conversion circuit provided in an embodiment of the present application.

[0075] like Fig.17 As shown, the power conversion circuit 300 includes a circuit board 310 and a semiconductor device 10 in any of the above embodiments. The semiconductor device 10 is electrically connected to the circuit board 310. The power conversion circuit 300 can be used for current conversion, voltage conversion or power factor correction.

[0076] Exemplarily, the power conversion circuit 300 can be used as one of an AC / DC converter, an AC / AC converter, a DC / DC converter, a DC / AC inverter or a power factor correction (PFC) circuit, wherein the AC / DC converter is used to convert alternating current into direct current, the AC / AC converter is used to convert alternating current into alternating current, the DC / DC converter is used to convert direct current into direct current, the DC / AC inverter is used to convert direct current into alternating current, and the power factor correction circuit is used to improve the power factor of the power supply and reduce the harmonic pollution of the power grid.

[0077] On the other hand, an embodiment of the present application further provides a vehicle, Fig.18 A schematic diagram of the structure of a vehicle provided in an embodiment of the present application.

[0078] like Fig.18 As shown, the vehicle 400 includes a load 401 and the power conversion circuit 300 in the above embodiment, and the power conversion circuit 300 is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power, and then input it into the load 401 to power the load 401.

[0079] The above-mentioned power module, power conversion circuit and vehicle have the same structure and beneficial technical effects as the semiconductor devices provided in some of the above-mentioned embodiments, which will not be repeated here.

[0080] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; An epitaxial layer is arranged on the substrate, the epitaxial layer is set to a first conductivity type, the epitaxial layer includes a first surface away from the substrate, the epitaxial layer also includes a well region and a first region, the first region is arranged on the first surface, the first region is set to the first conductivity type, the well region is set to a second conductivity type, the well region is arranged on a side of the first region away from the first surface, the first surface is provided with a gate trench, the gate trench extends from the first surface to the epitaxial layer, and runs through the first region and the well region; A gate structure is located in the gate trench, the gate structure includes a first insulating layer formed on a surface of the gate trench, and a first polysilicon layer and a first conductive material layer formed in the first insulating layer, the conductivity of the first conductive material layer is greater than the conductivity of the first polysilicon layer; a source electrode, formed on the first surface and electrically connected to the first region; The drain is arranged on a side of the substrate away from the epitaxial layer.

2. The semiconductor device according to claim 1, wherein: The first polysilicon layer is formed between the first conductive material layer and the first insulating layer.

3. The semiconductor device according to claim 2, characterized in that The first polysilicon layer includes an end portion adjacent to the first surface, and the first conductive material layer covers the end portion.

4. The semiconductor device according to claim 3, characterized in that The first insulating layer includes an extending portion extending onto the first surface, and the first polysilicon layer at least partially covers the extending portion.

5. The semiconductor device according to claim 1, wherein: The first conductive material layer is a metal material layer or an oxide material layer.

6. The semiconductor device according to claim 5, characterized in that The metal material layer includes molybdenum, tungsten or titanium, and the oxide material layer includes indium tin oxide or fluorine-doped tin oxide.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that: The first surface is provided with a source trench, the source extends into the source trench, and the semiconductor device further includes a second insulating layer provided on the surface of the source trench, and a second polysilicon layer provided between the second insulating layer and the source.

8. The semiconductor device according to claim 7, characterized in that The epitaxial layer further includes a second region, the second region is disposed on the first surface and is located outside the first region and the well region, the second region is of a second conductivity type, and the source trench is formed in the second region.

9. The semiconductor device according to claim 7, characterized in that The portion of the source electrode extending into the source trench is a second conductive material layer, and the second polysilicon layer is formed between the second conductive material layer and the second insulating layer.

10. A method for preparing a semiconductor device, characterized in that: include: Forming an epitaxial layer on a substrate, the epitaxial layer comprising a first surface away from the substrate, the epitaxial layer further comprising a well region and a first region, the first region being located on the first surface, and the well region being located on a side of the first region away from the first surface; forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the epitaxial layer and penetrates the first region and the well region; forming a gate structure in the gate trench, the gate structure comprising a first insulating layer formed on the surface of the gate trench, and a first polysilicon layer and a first conductive material layer formed in the first insulating layer, the conductivity of the first conductive material layer being greater than the conductivity of the first polysilicon layer; forming a source electrode on the first surface, the source electrode being electrically connected to the first region; A drain is formed, wherein the drain is located on a side of the substrate away from the epitaxial layer.

11. The preparation method according to claim 10, characterized in that: A gate structure is formed in the gate trench, comprising: A first insulating layer is formed on the surface of the gate trench, and a first polysilicon layer and a first conductive material layer are sequentially formed in the first insulating layer, wherein the first polysilicon layer is disposed between the first conductive material layer and the first insulating layer.

12. A power module, characterized in that: include: At least one semiconductor device according to any one of claims 1 to 9; A substrate is used to carry the semiconductor device.

13. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device is electrically connected to the circuit board.

14. A vehicle, characterized in that: include: A load and a power conversion circuit as claimed in claim 13, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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