Doherty amplifier circuit

Abstract

The Doherty amplifier circuit includes: a carrier amplifier that amplifies a high-frequency signal; the peak amplifier is used for amplifying the high-frequency signal; and a control circuit that includes a first passage characteristic variable circuit that allows passage characteristics of the high-frequency signal to be variable in accordance with the supply voltage, and a detector that detects the high-frequency signal that has passed through the first passage characteristic variable circuit, and that controls the bias of the peak amplifier on the basis of the detection result by the detector.

Description

Technical Field

[0001] The present disclosure relates to a Doherty amplification circuit. Background Art

[0002] As a high-efficiency power amplifier circuit, a Doherty amplifier circuit is known. Generally speaking, a Doherty amplifier circuit is a structure in which a carrier amplifier and a peak amplifier are connected in parallel, wherein the carrier amplifier operates independently of the power level of the high-frequency input signal, and the peak amplifier is cut off when the power level of the high-frequency input signal is low, and is turned on when the power level of the high-frequency input signal is high. In this structure, when the power level of the high-frequency input signal is high, the carrier amplifier operates while maintaining saturation at a saturated output power level. As a result, the Doherty amplifier circuit can improve efficiency compared to a conventional power amplifier circuit.

[0003] In the Doherty amplifier circuit, in order to suppress distortion of a high-frequency output signal or to suppress power consumption, it is desirable to appropriately control the operation of the peak amplifier.

[0004] The following non-patent document 1 describes an adaptive bias circuit that supplies a bias current to a peak amplifier. If the collector bias voltage decreases, the adaptive bias circuit increases the bias current of the peak amplifier. Also, if the collector bias voltage increases, the adaptive bias circuit decreases the bias current of the peak amplifier.

[0005] Prior Art Literature

[0006] Non-patent literature

[0007] Non-patent literature 1: Yunsung Cho, and four others, “Linear Doherty power amplifier with adaptive bias circuit for average power-tracking”, 2016 IEEE MTT-S International Microwave Symposium (IMS), May 22-27, 2016, p.1-3, DOI: 10.1109 / MWSYM.2016.7540180 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] In the technology described in non-patent document 1, the following undesirable conditions occur. For example, when the collector bias voltage has a time delay or noise error, the timing of starting the peak amplifier is shifted. As a result, the peak amplifier is started when it is not necessary, thereby increasing power consumption. In addition, the peak amplifier is not started when it is necessary, thereby causing large distortion in the high-frequency output signal.

[0010] The present disclosure has been made in view of the above circumstances, and an object of the present disclosure is to suppress an increase in power consumption and suppress distortion of a high-frequency output signal.

[0011] Technical solutions to solve problems

[0012] A Doherty amplifier circuit according to one aspect of the present disclosure includes: a carrier amplifier for amplifying a high-frequency signal; a peak amplifier for amplifying a high-frequency signal; and a control circuit, including a first variable pass characteristic circuit that allows a pass characteristic of the high-frequency signal to be variable according to a supply voltage, and a detector that detects the high-frequency signal after passing through the first variable pass characteristic circuit, and controls the bias of the peak amplifier according to the detection result in the detector.

[0013] Effects of the Invention

[0014] According to the present disclosure, it is possible to suppress an increase in power consumption and suppress distortion of a high-frequency output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a diagram showing the configuration of a Doherty amplifier circuit according to the first embodiment.

[0016] Figure 2 It is a graph showing the relationship among the bias voltage, input power, and supply voltage in a comparative example.

[0017] Figure 3 This is a diagram showing the relationship among the bias voltage, input power, and supply voltage of the control circuit according to the first embodiment.

[0018] Figure 4 It is a diagram showing the configuration of a Doherty amplifier circuit according to the second embodiment.

[0019] Figure 5 It is a diagram showing the configuration of an amplification system according to a third embodiment.

[0020] Figure 6 It is a diagram showing the configuration of a Doherty amplifier circuit according to a fourth embodiment.

[0021] Figure 7 It is a diagram showing the configuration of a control circuit according to the fifth embodiment.

[0022] Figure 8It is a diagram showing the pass characteristic of the first pass characteristic variable circuit of the control circuit according to the fifth embodiment.

[0023] Fig. 9 It is a diagram showing the structure of a control circuit according to the sixth embodiment.

[0024] Fig.10 It is a diagram showing the structure of the control circuit according to the seventh embodiment.

[0025] Fig.11 is a diagram showing a circuit example of a variable current source circuit. DETAILED DESCRIPTION

[0026] Hereinafter, the embodiments of the present disclosure are described in detail based on the accompanying drawings. In addition, the present invention is not limited to the embodiments. Each embodiment is an example, and it is self-evident that partial replacement or combination of the structures shown in different embodiments can be performed. After the second embodiment, the description of matters common to the first embodiment is omitted, and only the differences are described. In particular, the same effects brought about by the same structure will not be mentioned one by one in each embodiment.

[0027] <First Embodiment>

[0028] (structure)

[0029] Figure 1 1 is a diagram showing a configuration of a Doherty amplifier circuit according to Embodiment 1. The Doherty amplifier circuit 1 amplifies a high-frequency input signal RFin input to an input terminal 1a, and outputs a high-frequency output signal RFout from an output terminal 1b.

[0030] The Doherty amplifier circuit 1 includes a bias circuit 10 , a carrier amplifier 11 , a peak amplifier 12 , a divider 13 , a coupler 14 , a detector 15 , and a control circuit 16 .

[0031] The bias circuit 10 sets the bias voltage V BIAS1 Output to the carrier amplifier 11.

[0032] The carrier amplifier 11 outputs a high-frequency signal RF1 obtained by amplifying the high-frequency input signal RFin to the coupler 14 .

[0033] The distributor 13 outputs the high frequency signal RF2 having a phase difference of approximately 90° from the high frequency input signal RFin to the peak amplifier 12. In addition, the so-called "approximately 90°" is assumed to include not only a phase of 90° but also a phase of 90°±45°. Regarding the distributor 13, a 90° hybrid circuit can be exemplified, but the present disclosure is not limited thereto.

[0034] The peak amplifier 12 outputs a high-frequency signal RF3 obtained by amplifying the high-frequency signal RF2.

[0035] The coupler 14 outputs a high-frequency output signal RFout obtained by coupling the high-frequency signal RF1 and the high-frequency signal RF3 from the output terminal 1 b of the Doherty amplifier circuit 1 .

[0036] The detector 15 detects the high-frequency input signal RFin, and outputs a high-frequency signal RF4 corresponding to the high-frequency input signal RFin to the control circuit 16 .

[0037] The supply voltage Vcc supplied to the final-stage amplifier is input to the input terminal 1c of the Doherty amplifier circuit 1. For example, when there is no amplifier in the subsequent stage of the Doherty amplifier circuit 1, the amplifiers in the final stage are the carrier amplifier 11 and the peak amplifier 12. In addition, for example, when there is an amplifier in the subsequent stage of the Doherty amplifier circuit 1, the amplifier in the final stage is the amplifier. In addition, regarding the supply voltage Vcc input to the input terminal 1c of the Doherty amplifier circuit 1, when there are more than one amplifier in the previous stage of the Doherty amplifier circuit 1, it can also be the supply voltage Vcc supplied to any one of the more than one amplifiers. In addition, even when there are more than one amplifier in the subsequent stage of the Doherty amplifier circuit 1, it can also be the supply voltage Vcc supplied to the carrier amplifier 11 and the peak amplifier 12.

[0038] The supply voltage Vcc may be, for example, a power supply voltage that changes according to the envelope of the high-frequency input signal RFin, that is, is subjected to envelope tracking control, but the present disclosure is not limited thereto.

[0039] The control circuit 16 sets the bias voltage V BIAS2 The output is sent to the peak amplifier 12.

[0040] (Comparative Example)

[0041] Figure 2 is a graph showing the relationship among bias voltage, input power, and supply voltage of a comparative example. Figure 2 In the figure, the vertical axis represents the bias voltage V BIAS2 , the horizontal axis represents the input power of the high-frequency input signal RFin.

[0042] The comparative example is similar to Non-Patent Document 1, and outputs a bias voltage V based only on the supply voltage Vcc without depending on the input power. BIAS2 .

[0043] Line 201 represents the bias voltage V when the supply voltage Vcc is relatively low. BIAS2 Line 202 represents the bias voltage V when the supply voltage Vcc is relatively medium.BIAS2 Line 203 represents the bias voltage V when the supply voltage Vcc is relatively high. BIAS2 .

[0044] The lower the supply voltage Vcc is, the easier it is for the carrier amplifier 11 to saturate. Therefore, in the comparative example, the lower the supply voltage Vcc is, the higher the bias voltage V BIAS2 , thereby making the peak amplifier 12 operate more (start up). On the contrary, the higher the supply voltage Vcc is, the harder it is for the carrier amplifier 11 to saturate. Therefore, in the comparative example, the higher the supply voltage Vcc is, the lower the bias voltage V is. BIAS2 , thereby suppressing the operation of the peak amplifier 12 (stopping it).

[0045] (Implementation Method)

[0046] Figure 3 1 is a diagram showing the relationship among the bias voltage, input power, and supply voltage of the control circuit of the first embodiment. Figure 3 In the figure, the vertical axis represents the bias voltage V BIAS2 , the horizontal axis represents the input power of the high-frequency input signal RFin.

[0047] The control circuit 16 of the first embodiment outputs a bias voltage V based on input power and a supply voltage Vcc. BIAS2 .

[0048] Line 211 represents the bias voltage V when the supply voltage Vcc is relatively low. BIAS2 Line 212 represents the bias voltage V when the supply voltage Vcc is relatively medium. BIAS2 Line 213 represents the bias voltage V when the supply voltage Vcc is relatively high. BIAS2 .

[0049] The lower the supply voltage Vcc is, the easier it is for the carrier amplifier 11 to saturate. Therefore, the lower the supply voltage Vcc is, the more the control circuit 16 increases the bias voltage V BIAS2 , thereby making the peak amplifier 12 operate more (start up). Conversely, the higher the supply voltage Vcc is, the harder it is for the carrier amplifier 11 to saturate. Therefore, the higher the supply voltage Vcc is, the more the control circuit 16 reduces the bias voltage V BIAS2 , thereby suppressing the operation of the peak amplifier 12 (stopping it).

[0050] In addition, the greater the input power, the easier it is for the carrier amplifier 11 to saturate. Therefore, the greater the input power, the more the control circuit 16 increases the bias voltage V BIAS2 , thereby making the peak amplifier 12 more active (starting up). Conversely, the smaller the input power, the harder it is for the carrier amplifier 11 to saturate. Therefore, the smaller the input power, the more the control circuit 16 reduces the bias voltage VBIAS2 , thereby suppressing the operation (stopping it) of the peak amplifier 12.

[0051] Based on the above, when the supply voltage Vcc is relatively low (line 211), the threshold value of the input power is set as threshold value A; when the supply voltage Vcc is relatively medium (line 212), the threshold value of the input power is set as threshold value B; when the supply voltage Vcc is relatively high (line 213), the threshold value of the input power is set as threshold value C. Here, A < B < C. Moreover, when the input power is less than the threshold value, the control circuit 16 makes the bias voltage V BIAS2 fixed, and when the input power is above the threshold value, the larger the input power, the higher the bias voltage V BIAS2 .

[0052] (Effect)

[0053] (1) In the Doherty amplifier circuit 1 of the first embodiment, when the supply voltage Vcc rises sharply, by suppressing the unnecessary operation of the peak amplifier 12, the power consumption can be suppressed.

[0054] Generally, the supply voltage Vcc is often determined by the input power. That is, the larger the input power, the higher the supply voltage Vcc becomes, and the smaller the input power, the lower the supply voltage Vcc becomes. However, due to the influence of temperature changes, interference noise, etc., it is possible that although the input power is small, the supply voltage Vcc瞬间变高.

[0055] At this time, in Non-Patent Document 1 and the comparative example, an operation is performed to lower the bias point of the peak amplifier 12. However, due to the hysteresis caused by the delay (time constant) of the control circuit, a state where the supply voltage Vcc is high and the bias voltage V BIAS2 is high will occur instantaneously. As a result, when a high supply voltage Vcc is input to the peak amplifier 12 and a large bias current flows, a lot of power will be wasted.

[0056] On the other hand, as shown by lines 211 to 213 of the Doherty amplifier circuit 1 Figure 3 , when the input power is small, the bias voltage V BIAS2 becomes low and the peak amplifier 12 is stopped. Therefore, the Doherty amplifier circuit 1 can suppress the wasted power consumption as in Non-Patent Document 1 and the comparative example.

[0057] (2) In the Doherty amplifier circuit 1 of the first embodiment, when the supply voltage Vcc drops sharply, the start-up hysteresis of the peak amplifier 12 can be suppressed, and the generation of distortion of the high-frequency output signal RFout can be suppressed.

[0058] It should be noted that the phrase "供给电压Vcc瞬间变高" in the original text seems to be incomplete or incorrect in expression. I translated it as "the supply voltage Vcc瞬间变高" as it was, but it might need to be further corrected or clarified in the original context.Contrary to the above (1), the supply voltage Vcc may drop momentarily due to the influence of temperature change, interference noise, etc. This can be exemplified by the momentary low voltage generated when other devices connected to the same power supply system consume a large current when the engine is started, for example, when the Doherty amplifier circuit 1 is mounted on the vehicle.

[0059] At this time, in Non-Patent Document 1 and the comparative example, the bias point of the peak amplifier 12 is intended to be raised. However, due to the hysteresis caused by the delay (time constant) of the control circuit, the supply voltage Vcc is low and the bias voltage V BIAS2 As a result, the peak amplifier 12 is not activated, the peak amplifier 12 does not amplify the high-frequency signal RF2, and a large distortion occurs in the high-frequency output signal RFout.

[0060] On the other hand, the Doherty amplifier circuit 1 is as follows Figure 3 As shown by lines 211 to 213, when the input power is large, the bias voltage V BIAS2 becomes high, and the peak amplifier 12 is activated. Therefore, the Doherty amplifier circuit 1 can suppress the generation of distortion of the high-frequency output signal RFout.

[0061] <Second Embodiment>

[0062] Among the components of the second embodiment, components that are the same as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

[0063] Figure 4 It is a diagram showing the configuration of a Doherty amplifier circuit according to the second embodiment.

[0064] Doherty amplifier circuit 1A and Doherty amplifier circuit 1 (refer to Figure 1 ) In comparison, control circuit 16 is replaced by control circuit 16A.

[0065] The control circuit 16A includes a first transmission characteristic variable circuit 21 , a detector 22 , and a bias circuit 23 .

[0066] In the first pass characteristic variable circuit 21, the threshold value of the pass characteristic changes according to the supply voltage Vcc, and the pass characteristic of the high frequency signal RF4 is changed. In the first pass characteristic variable circuit 21, when the supply voltage Vcc is relatively low, the pass characteristic becomes high. In the first pass characteristic variable circuit 21, when the supply voltage Vcc is relatively high, the pass characteristic becomes low.

[0067] The first pass characteristic variable circuit 21 controls the pass amount (pass degree) of the high frequency signal RF4 according to the pass characteristic, and outputs the high frequency signal RF5 to the detector 22. That is, the high frequency signal RF5 has a power corresponding to both the supply voltage Vcc and the input power of the high frequency input signal RFin.

[0068] The detector 22 detects (or rectifies) the high-frequency signal RF5 , and outputs a signal S1 corresponding to the high-frequency signal RF5 to the bias circuit 23 .

[0069] The bias circuit 23 generates a bias voltage V corresponding to the signal S1. BIAS2 The output is sent to the peak amplifier 12.

[0070] Furthermore, if the circuit structure of the detector 22 is improved, a part of the function of the bias circuit 23 can be shared, so this is also possible.

[0071] (Effect)

[0072] The control circuit 16A can auxiliaryly use the supply voltage Vcc to appropriately control the bias point of the peak amplifier 12. That is, even if the supply voltage Vcc varies due to interference noise or the like, the Doherty amplifier circuit 1A can suppress power consumption and suppress distortion of the high-frequency output signal RFout.

[0073] (Variation)

[0074] In the second embodiment, the detector 22 is set as a single-ended detector, but the present disclosure is not limited to this. The detector 22 may also be a differential detector. In this case, a balanced-unbalanced converter that converts the high-frequency signal RF5 into a differential high-frequency signal may be provided between the first pass characteristic variable circuit 21 and the detector 22, so that the detector 22 detects the differential high-frequency signal output from the balanced-unbalanced converter.

[0075] <Third Embodiment>

[0076] Among the components of the third embodiment, the same components as those of the other embodiments are denoted by the same reference numerals, and description thereof is omitted.

[0077] The supply voltage Vcc is also often managed by the system that controls the Doherty amplifier circuit 1A. In this case, the following method can also be adopted, that is, the pass characteristic of the first pass characteristic variable circuit 21 is digitally controlled according to the supply voltage Vcc managed by the system. However, the method of analog control of the pass characteristic of the first pass characteristic variable circuit 21 according to the supply voltage Vcc is more capable of coping with the change of the supply voltage Vcc that cannot be managed by the system, such as the aforementioned interference noise. The present disclosure can also set the pass characteristic of the first pass characteristic variable circuit 21 to analog processing, digital processing, or a combination of analog processing and digital processing.

[0078] Figure 5 3 is a diagram showing a configuration of an amplifier system according to the third embodiment. The amplifier system 31 includes a Doherty amplifier circuit 1B, a digital system 32 , and a voltage supply circuit 33 .

[0079] Doherty amplifier circuit 1B and Doherty amplifier circuit 1A (refer to Figure 4 ), the control circuit 16B is replaced by the control circuit 16A. The control circuit 16B is replaced by the first pass characteristic variable circuit 21A and is replaced by the first pass characteristic variable circuit 21B.

[0080] The digital system 32 controls the entire Doherty amplifier circuit 1B. An envelope tracking circuit can be exemplified as the digital system 32, but the present disclosure is not limited thereto.

[0081] The digital system 32 outputs a signal S11 indicating the supply voltage Vcc to the voltage supply circuit 33. For example, when the digital system 32 is an envelope tracking circuit, the signal S11 is changed according to the envelope of the high-frequency input signal RFin. The signal S11 can be a digital signal or an analog signal.

[0082] The voltage supply circuit 33 outputs a supply voltage Vcc corresponding to the signal S11 to the carrier amplifier 11 and the peak amplifier 12. The carrier amplifier 11 and the peak amplifier 12 operate using the supply voltage Vcc as a power supply voltage.

[0083] The digital system 32 outputs a signal S12 corresponding to the supply voltage Vcc to the first pass characteristic variable circuit 21B via the input terminal 1c. For example, when the digital system 32 is an envelope tracking circuit, the signal S12 is changed according to the envelope of the high-frequency input signal RFin. The signal S12 can be either a digital signal or an analog signal.

[0084] In the first pass characteristic variable circuit 21B, the pass characteristic changes according to the signal S12. That is, in the first pass characteristic variable circuit 21B, the pass characteristic changes according to the supply voltage Vcc. The first pass characteristic variable circuit 21B controls the pass amount (pass degree) of the high-frequency signal RF4 according to the pass characteristic, and outputs the high-frequency signal RF5 to the detector 22. That is, the high-frequency signal RF5 becomes a power corresponding to both the supply voltage Vcc and the input power of the high-frequency input signal RFin.

[0085] (Effect)

[0086] The Doherty amplifier circuit 1B can adjust the bias voltage V of the peak amplifier 12 according to the signal S12 input from the digital system 32. BIAS2 Thus, the Doherty amplifier circuit 1B is controlled by the input supply voltage Vcc itself (refer to Figure 4 ) In comparison, signal S12 does not pass through the voltage supply circuit 33, so the delay in the control circuit 16B can be suppressed.

[0087] <Fourth Implementation Method>

[0088] Among the components of the fourth embodiment, components that are the same as those of other embodiments are denoted by the same reference numerals, and description thereof is omitted.

[0089] The Doherty amplifier circuit of the present disclosure has good compatibility with other peak amplifier control technologies. For example, the Doherty amplifier circuit of the present disclosure can be used together with a technology for controlling the activation of the peak amplifier according to the drive level (saturation) and input power of an amplifier other than the peak amplifier (for example, a carrier amplifier, an amplifier at the subsequent stage of the Doherty amplifier circuit 1).

[0090] Figure 6 It is a diagram showing the configuration of a Doherty amplifier circuit according to a fourth embodiment.

[0091] Doherty amplifier circuit 1C and Doherty amplifier circuit 1A (refer to Figure 4 ) includes a control circuit 16C instead of the control circuit 16A. The control circuit 16C further includes a second pass characteristic variable circuit 24 compared to the control circuit 16A.

[0092] The second pass characteristic variable circuit 24 receives a signal S21 indicating the drive level of the carrier amplifier 11 from the bias circuit 10. The signal S21 may be a signal (inverted signal) that changes complementarily with the drive level of the carrier amplifier 11. Alternatively, the Doherty amplifier circuit 1C may include a detector 17 that detects the high-frequency signal RF1, and a drive level detector 18 that outputs a signal S22 indicating the drive level of the carrier amplifier 11 to the second pass characteristic variable circuit 24 based on the detection signal of the detector 17. The signal S22 may be a signal (inverted signal) that changes complementarily with the drive level of the carrier amplifier 11.

[0093] It is sufficient that at least one of the signal S21 and the signal S22 is input to the second pass characteristic variable circuit 24. Alternatively, a signal obtained by combining the signal S21 and the signal S22 into one signal may be input to the second pass characteristic variable circuit 24.

[0094] In the fourth embodiment, a signal indicating the drive level of the carrier amplifier 11 is input to the control circuit 16C, but the present disclosure is not limited thereto. It is sufficient that a signal indicating the drive level of an amplifier other than the peak amplifier 12 is input to the control circuit 16C. For example, a signal indicating the drive level of an amplifier in the subsequent stage of the Doherty amplifier circuit 1C may be input to the control circuit 16C.

[0095] In the second variable pass characteristic circuit 24, the pass characteristic changes according to the drive level of the carrier amplifier 11. In the second variable pass characteristic circuit 24, when the drive level of the carrier amplifier 11 is relatively low, the pass characteristic becomes low. In the second variable pass characteristic circuit 24, when the drive level of the carrier amplifier 11 is relatively high, the pass characteristic becomes high.

[0096] The second pass characteristic variable circuit 24 controls the pass amount (pass degree) of the high frequency signal RF5 according to the pass characteristic, and outputs the high frequency signal RF6 to the detector 22. That is, the high frequency signal RF6 becomes a power corresponding to the supply voltage Vcc, the input power of the high frequency input signal RFin, and the drive level of the carrier amplifier 11.

[0097] (Effect)

[0098] The Doherty amplifier circuit 1C can appropriately control the bias point of the peak amplifier 12 by auxiliary use of the supply voltage Vcc, similarly to the Doherty amplifier circuit 1A. That is, even if the supply voltage Vcc varies due to the influence of interference noise or the like, the Doherty amplifier circuit 1C can suppress power consumption and suppress the generation of distortion of the high-frequency output signal RFout.

[0099] In addition, when the temperature or other surrounding environment changes (for example, when the gain of the carrier amplifier 11 increases at extremely low temperatures, etc.), the carrier amplifier 11 may be saturated even if the power of the high-frequency input signal RFin is small. In order to cope with this situation, the second pass characteristic variable circuit 24 detects the drive level of the carrier amplifier 11, and when the carrier amplifier 11 is close to saturation, the peak amplifier 12 is immediately activated even if the power of the high-frequency signal RF4 is small.

[0100] Since the high frequency signal RF4 is detected by the first pass characteristic variable circuit 21, the control circuit 16C can start the peak amplifier 12 without saturating the carrier amplifier 11 even if it takes time for the second pass characteristic variable circuit 24 to detect the driving level of the carrier amplifier 11. Thus, the Doherty amplifier circuit 1C can suppress the distortion of the high frequency output signal RFout.

[0101] It can also be considered that the control circuit 16C operates in a feedforward manner based on the high-frequency input signal RFin, and operates in a feedback manner based on at least one of the signal S21 and the signal S22.

[0102] <Fifth Implementation Method>

[0103] Among the components of the fifth embodiment, the same components as those of the other embodiments are denoted by the same reference numerals, and description thereof is omitted.

[0104] Figure 7 It is a diagram showing the configuration of a control circuit according to the fifth embodiment.

[0105] The control circuit 16D includes a first transmission characteristic variable circuit 21 and a detector 22. In the control circuit 16D, the detector 22 has a high current supply capability, so the bias circuit 23 can be omitted. That is, in the control circuit 16D, the detector 22 also functions as the bias circuit 23.

[0106] The first pass characteristic variable circuit 21 includes an extraction section 21 a , a bias section 21 b , and a signal passing section 21 c .

[0107] The extraction unit 21a extracts the current I2 from the bias unit 21b according to the supply voltage Vcc. The extraction unit 21a is a circuit that converts the increase or decrease of the supply voltage Vcc into the increase or decrease of the current I2.

[0108] The bias section 21 b is a circuit that outputs a bias current I4 to the signal passing section 21 c based on the current I2 .

[0109] The signal passing portion 21c is a circuit that amplifies the high-frequency signal RF4 based on the bias current I4 and outputs the high-frequency signal RF5.

[0110] The extraction unit 21a includes resistors R1 and R2, and transistors Q1, Q2, Q3, and Q4.

[0111] In the present disclosure, each transistor is a bipolar transistor, but the present disclosure is not limited to this. Regarding the bipolar transistor, a heterojunction bipolar transistor (HBT) can be exemplified, but the present disclosure is not limited to this. The transistor may also be a field effect transistor (FET), for example. The transistor may also be a multi-finger transistor in which a plurality of unit transistors are electrically connected in parallel. The so-called unit transistor refers to the minimum structure that constitutes a transistor.

[0112] When each transistor is a FET, the drain of the FET corresponds to the collector of the bipolar transistor, the gate of the FET corresponds to the base of the bipolar transistor, and the source of the FET corresponds to the emitter of the bipolar transistor.

[0113] A supply voltage Vcc is input to one end of the resistor R1, and the other end of the resistor R1 is electrically connected to the collector of the transistor Q1.

[0114] The base of the transistor Q1 is electrically connected to the node N1, and the emitter of the transistor Q1 is electrically connected to the node N2.

[0115] A set constant current I1 is input to one end of the resistor R2 from the current source 51. The other end of the resistor R2 is electrically connected to the node N1.

[0116] The collector and base of the transistor Q2 are electrically connected to the node N1. That is, the transistor Q1 and the transistor Q2 are current mirror-connected. The emitter of the transistor Q2 is electrically connected to the node N2.

[0117] The collector and base of the transistor Q3 are electrically connected to the node N2, and the emitter of the transistor Q3 is electrically connected to a reference potential.

[0118] The base of transistor Q4 is electrically connected to node N2. That is, transistor Q3 and transistor Q4 are current mirror-connected. The emitter of transistor Q4 is electrically connected to the reference potential. The collector of transistor Q4 is electrically connected to node N4 of bias unit 21b.

[0119] The current I2 flowing from the node N4 to the collector of the transistor Q4 is the output current of the extraction unit 21a.

[0120] The bias unit 21 b includes transistors Q5 , Q6 , and Q7 .

[0121] The collector and base of the transistor Q5 are electrically connected to the node N3. That is, the transistor Q5 is diode-connected. A set constant current I3 is input to the node N3 from the current source 52. The emitter of the transistor Q5 is electrically connected to the node N4.

[0122] The collector and base of the transistor Q6 are electrically connected to the node N4. That is, the transistor Q6 is diode-connected. The emitter of the transistor Q6 is electrically connected to the reference potential.

[0123] The power supply voltage is input to the collector of transistor Q7. The base of transistor Q7 is electrically connected to node N3. That is, transistor Q5 and transistor Q7 are connected in a current mirror manner. The emitter of transistor Q7 is electrically connected to one end of resistor R3 of signal passing section 21c. That is, transistor Q7 and resistor R3 are connected in an emitter follower manner.

[0124] The emitter current of transistor Q7 is bias current I4.

[0125] The signal passing portion 21c includes resistors R3 and R4, a capacitor C1, and a transistor Q8.

[0126] The other end of the resistor R3 is electrically connected to the base of the transistor Q8. The bias current I4 flowing into one end of the resistor R3 is input to the base of the transistor Q8.

[0127] The high frequency signal RF4 is input to one end of the capacitor C1. The other end of the capacitor C1 is electrically connected to the base of the transistor Q8. The capacitor C1 is a DC blocking capacitor that blocks the direct current component of the high frequency signal RF4.

[0128] A power supply voltage is input to one end of the resistor R4, and the other end of the resistor R4 is electrically connected to the collector of the transistor Q8.

[0129] The emitter of the transistor Q8 is electrically connected to the reference potential.

[0130] The signal passing portion 21c amplifies the high-frequency signal RF4 according to the bias current I4, and outputs a high-frequency signal RF5 from the collector.

[0131] The operation of the first pass characteristic variable circuit 21 will be described.

[0132] If the base-emitter voltage of each transistor is set to V BE , the voltage of the node N1 of the extraction unit 21a becomes approximately 2V BE .

[0133] When the supply voltage Vcc is relatively low (less than 2V BE ) for explanation.

[0134] In this case, the constant current I1 flows to the supply voltage Vcc side via the PN junction between the base and the collector of the transistor Q1. Therefore, the current does not flow into the node N2. Therefore, the current I2 does not flow between the collector and the emitter of the transistor Q4.

[0135] Since the current I2 does not flow, almost all of the constant current I3 flows to the diode-connected transistor Q5 and the diode-connected transistor Q6. As a result, a relatively high bias voltage is applied to the base of the transistor Q7, so the emitter current of the transistor Q7 becomes relatively large. In other words, the bias unit 21b outputs a relatively large bias current I4 to the base of the transistor Q8 of the signal passing unit 21c.

[0136] When a relatively large bias current I4 is input to the base of the transistor Q8, the transistor Q8 outputs a high-frequency signal RF5 having a relatively large power.

[0137] In summary, the first pass characteristic variable circuit 21 relatively increases the power of the high-frequency signal RF5 when the supply voltage Vcc is a relatively low voltage.

[0138] Next, a case where the supply voltage Vcc continues to rise will be described.

[0139] As the supply voltage Vcc continues to rise, the transistor Q1 gradually starts to operate properly, and the transistor Q1 and the transistor Q2 start to perform a current mirror operation.

[0140] The constant current I1 flows into the node N2 via the collector (base)-emitter of the transistor Q2. In addition, the transistors Q1 and Q2 perform a current mirror operation, whereby the emitter current of the transistor Q1 proportional to the emitter current of the transistor Q2 flows into the node N2. The current flowing into the node N2 flows between the collector (base)-emitter of the transistor Q3.

[0141] The transistor Q3 and the transistor Q4 are current mirror-connected, so that a current I2 proportional to the current flowing into the node N2 flows between the collector and the emitter of the transistor Q4.

[0142] The current I2 flows from the node N4 to the collector of the transistor Q4, so the current obtained by subtracting the current I2 from the constant current I3 flows to the transistor Q6. As a result, the collector-emitter voltage of the transistor Q6 becomes relatively low, and a relatively low bias voltage is applied to the base of the transistor Q7, so that the emitter current of the transistor Q7 becomes relatively small. That is, the bias unit 21b outputs a relatively small bias current I4 to the base of the transistor Q8 of the signal passing unit 21c.

[0143] When a relatively small bias current I4 is input to the base of the transistor Q8, the transistor Q8 outputs a high-frequency signal RF5 with relatively small power.

[0144] The high frequency signal RF5 output from the first pass characteristic variable circuit 21 is input to the detector 22 via the DC blocking capacitor 101 .

[0145] Figure 8 FIG. 2 is a diagram showing the pass characteristic of the first pass characteristic variable circuit of the control circuit according to the fifth embodiment. Figure 8 In FIG. 1 , the vertical axis represents the S parameter (S(2,1)) of the first pass characteristic variable circuit 21 , and the horizontal axis represents the frequency.

[0146] In the first pass characteristic variable circuit 21, the threshold value of the pass characteristic changes according to the supply voltage. Line 221 shows the S parameter of the first pass characteristic variable circuit 21 when the supply voltage Vcc=2.0V. Line 222 shows the S parameter of the first pass characteristic variable circuit 21 when the supply voltage Vcc=3.0V. Line 223 shows the S parameter of the first pass characteristic variable circuit 21 when the supply voltage Vcc=4.0V. Line 224 shows the S parameter of the first pass characteristic variable circuit 21 when the supply voltage Vcc=5.0V.

[0147] like Figure 8 As shown, over the range of 0 GHz to 10 GHz, the lower the supply voltage Vcc, the larger the S parameter of the first pass characteristic variable circuit 21 becomes, and the higher the supply voltage Vcc, the smaller the S parameter of the first pass characteristic variable circuit 21 becomes.

[0148] Refer again Figure 7 The detector 22 includes a bias unit 22a, a detection unit 22b, and a filter unit 22c.

[0149] The bias unit 22 a includes transistors Q11 , Q12 , and Q13 .

[0150] The collector and base of the transistor Q11 are electrically connected to the node N11. That is, the transistor Q11 is diode-connected. A set constant current I11 is input from the current source 53 to the node N11.

[0151] The collector and base of the transistor Q12 are electrically connected to the emitter of the transistor Q11. That is, the transistor Q12 is diode-connected. The emitter of the transistor Q12 is electrically connected to a reference potential.

[0152] That is, the voltage of the node N11 is approximately 2V. BE .

[0153] The base of the transistor Q13 is electrically connected to the collector and base of the transistor Q12. That is, the transistor Q12 and the transistor Q13 are current mirror-connected. The emitter of the transistor Q13 is electrically connected to a reference potential.

[0154] The detection unit 22b includes a resistor R11 and a transistor Q14.

[0155] One end of the resistor R11 is electrically connected to the node N11, and the other end of the resistor R11 is electrically connected to the base of the transistor Q14.

[0156] That is, the base bias voltage of the transistor Q14 is determined by the voltage of the node N11.

[0157] The power supply voltage is input to the collector of the transistor Q14. The high-frequency signal RF5 is input to the base of the transistor Q14 after passing through the DC blocking capacitor 101. The emitter of the transistor Q14 is electrically connected to the collector of the transistor Q13.

[0158] A certain amount of the emitter current of the transistor Q14 flows between the collector and the emitter of the transistor Q13, and the remaining current flows to the filter unit 22c.

[0159] The filter unit 22c includes an inductor L11 and a capacitor C11. The filter unit 22c is a low-pass filter that removes the fundamental wave component of the high-frequency signal RF5. When the detector 22 is a differential detector, the filter unit 22c can be omitted.

[0160] One end of the inductor L11 is electrically connected to the emitter of the transistor Q14. The other end of the inductor L11 is electrically connected to one end of the capacitor C11. The other end of the capacitor C11 is electrically connected to a reference potential. The voltage of the capacitor C11 becomes the bias voltage V of the peak amplifier 12. BIAS2 .

[0161] The operation of the detector 22 will be described.

[0162] When the high-frequency signal RF5 is equal to or higher than the threshold voltage of the transistor Q14 , the transistor Q14 is turned on and outputs an emitter current.

[0163] That is, the larger the amplitude of the high-frequency signal RF5 is, the larger the emitter current of the transistor Q14 becomes. In addition, the smaller the amplitude of the high-frequency signal RF5 is, the smaller the emitter current of the transistor Q14 becomes.

[0164] A certain amount of the emitter current of the transistor Q14 flows between the collector and the emitter of the transistor Q13, and the remaining current flows to the filter unit 22c.

[0165] Therefore, the larger the amplitude of the high-frequency signal RF5, the larger the bias voltage V BIAS2 In addition, the smaller the amplitude of the high-frequency signal RF5, the higher the bias voltage V BIAS2 The lower it gets.

[0166] (Effect)

[0167] The control circuit 16D can realize a circuit that uses the supply voltage Vcc to appropriately control the bias point of the peak amplifier 12. That is, the control circuit 16C can realize a circuit that can suppress power consumption and suppress the generation of distortion of the high-frequency output signal RFout even if the supply voltage Vcc fluctuates due to interference noise or the like.

[0168] <Sixth Implementation Method>

[0169] Among the components of the sixth embodiment, components that are the same as those of other embodiments are denoted by the same reference numerals, and description thereof is omitted.

[0170] Fig. 9 It is a diagram showing the structure of a control circuit according to the sixth embodiment.

[0171] The control circuit 16E and the control circuit 16D (refer to Figure 7 ) compared to the embodiment of the present invention, it also includes a second variable characteristic circuit 24.

[0172] The second pass characteristic variable circuit 24 includes a signal passing portion 24 a and a current source 24 b .

[0173] The signal passing portion 24a includes a transistor Q21.

[0174] The power supply voltage is input to the collector of the transistor Q21. The high-frequency signal RF5 is input to the base of the transistor Q21. The emitter of the transistor Q21 is electrically connected to the current source 24b.

[0175] The current source 24 b extracts a current corresponding to at least one of the signal S21 and the signal S22 indicating the drive level of the carrier amplifier 11 from the emitter of the transistor Q21 .

[0176] The current source 24b draws a large current from the emitter of the transistor Q21 when the carrier amplifier 11 is saturated. As a result, the transistor Q21 operates as an emitter follower circuit and maintains a high pass characteristic.

[0177] On the other hand, the current source 24b does not provide an appropriate bias to the emitter of the transistor Q21 when the carrier amplifier 11 is not saturated, thereby reducing the pass characteristic of the transistor Q21.

[0178] (Effect)

[0179] When the temperature or other surrounding environment changes (for example, when the gain of the carrier amplifier 11 increases at extremely low temperatures), the carrier amplifier 11 may be saturated even if the power of the high-frequency input signal RFin is small. In order to cope with this situation, the control circuit 16E can implement a circuit that detects the drive level of the carrier amplifier 11 and immediately activates the peak amplifier 12 when the carrier amplifier 11 is close to saturation, even if the power of the high-frequency signal RF4 is small.

[0180] <Seventh Implementation Method>

[0181] Among the components of the seventh embodiment, components that are the same as those of other embodiments are denoted by the same reference numerals and description thereof is omitted.

[0182] Fig.10 It is a diagram showing the structure of the control circuit according to the seventh embodiment.

[0183] The control circuit 16F and the control circuit 16D (refer to Figure 7 ) compared with the first variable pass characteristic circuit 21, the structure of the first variable pass characteristic circuit 21 is partially different. Specifically, in the control circuit 16F, the first variable pass characteristic circuit 21F includes an extraction unit 21d instead of the current source 51 and the extraction unit 21a compared with the first variable pass characteristic circuit 21.

[0184] The extraction unit 21 d includes resistors R1 d and R2 d , a comparator 61 , and a variable current source circuit 62 .

[0185] The supply voltage Vcc is input to one end of the resistor R1d, and the other end of the resistor R1d is electrically connected to one end of the resistor R2d, and the other end of the resistor R2d is electrically connected to a reference potential.

[0186] The comparator 61 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the comparator 61 is electrically connected to a connection point of the other end of the resistor R1d and one end of the resistor R2d, and a voltage Vcc1 obtained by dividing the supply voltage Vcc by the resistors R1d and R2d is applied. The reference voltage Vref is applied to the second input terminal of the comparator 61. The comparator 61 compares the voltage Vcc1 applied to the first input terminal with the reference voltage Vref applied to the second input terminal, and outputs a comparison result output signal Vcomp indicating the comparison result from the output terminal.

[0187] The variable current source circuit 62 is electrically connected to the output terminal of the comparator 61. The variable current source circuit 62 extracts the current I2 from the bias section 21b according to the comparison result output signal Vcomp output from the output terminal of the comparator 61. In other words, the variable current source circuit 62 converts the increase and decrease of the supply voltage Vcc into the increase and decrease of the current I2, and extracts the current I2 from the bias section 21b according to the supply voltage Vcc.

[0188] The operation of the extraction unit 21d and the operation of the first pass characteristic variable circuit 21F will be described.

[0189] A case where the supply voltage Vcc is a relatively low voltage (a case where the supply voltage Vcc is lower than the reference voltage Vref) will be described.

[0190] In this case, the comparator 61 outputs a Low-level signal as the comparison result output signal Vcomp. When the Low-level comparison result output signal Vcomp is input, the variable current source circuit 62 is not driven and is turned off. Therefore, the current I2 does not flow.

[0191] Since the current I2 does not flow, almost all of the constant current I3 flows to the transistors Q5 and Q6 included in the bias section 21b. As a result, a relatively high bias voltage is applied to the base of the transistor Q7, so the emitter current of the transistor Q7 becomes relatively large. In other words, the bias section 21b outputs a relatively large bias current I4 to the base of the transistor Q8 of the signal passing section 21c.

[0192] When a relatively large bias current I4 is input to the base of the transistor Q8, the transistor Q8 outputs a high-frequency signal RF5 having a relatively large power.

[0193] In summary, the first pass characteristic variable circuit 21F relatively increases the power of the high-frequency signal RF5 when the supply voltage Vcc is a relatively low voltage.

[0194] Next, a case where the supply voltage Vcc rises and becomes a relatively high voltage (a case where it becomes higher than the reference voltage Vref) will be described.

[0195] In this case, the comparator 61 outputs a High-level signal as the comparison result output signal Vcomp. When the High-level comparison result output signal Vcomp is input, the variable current source circuit 62 starts to drive and becomes conductive. Therefore, a current I2 proportional to the magnitude of the comparison result output signal Vcomp starts to flow.

[0196] The current I2 flows to the variable current source circuit 62, so the current obtained by subtracting the current I2 from the constant current I3 flows to the transistor Q6 of the bias section 21b. As a result, the collector-emitter voltage of the transistor Q6 becomes relatively low, and a relatively low bias voltage is applied to the base of the transistor Q7, so that the emitter current of the transistor Q7 becomes relatively small. In other words, the bias section 21b outputs a relatively small bias current I4 to the base of the transistor Q8 of the signal passing section 21c.

[0197] When a relatively small bias current I4 is input to the base of the transistor Q8, the transistor Q8 outputs a high-frequency signal RF5 with relatively small power.

[0198] In summary, when the supply voltage Vcc rises to a relatively high voltage, the first pass characteristic variable circuit 21F relatively increases the power of the high-frequency signal RF5.

[0199] In addition, the control circuit 16F may also be configured to include a plurality of semiconductor bare chips. Specifically, regarding the extraction unit 21d and the current source 52 included in the first variable characteristic circuit 21F in the control circuit 16F, for example, a first semiconductor bare chip formed on a semiconductor substrate including silicon (Si) may be exemplified. Furthermore, regarding the remaining portion of the control circuit 16F other than the extraction unit 21d and the current source 52, for example, a second semiconductor bare chip formed on a semiconductor substrate including gallium arsenide (GaAs) may be exemplified. In addition to the extraction unit 21d and the current source 52 of the control circuit 16F, other control circuits for controlling the carrier amplifier 11 and the peak amplifier 12 may be formed on the first semiconductor bare chip. In addition, in addition to the remaining portion of the control circuit 16F, the carrier amplifier 11 and the peak amplifier 12 may be formed on the second semiconductor bare chip.

[0200] Furthermore, a circuit example of the variable current source circuit 62 will be described.

[0201] Fig.11 is a diagram showing a circuit example of the variable current source circuit 62 .

[0202] The variable current source circuit 62 includes, for example, an operational amplifier OP1 , an inverter IN1 , PMOS transistors PM1 , PM2 , switches SW1 , SW2 , NMOS transistors NM1 , NM2 , and a resistor R3 .

[0203] The operational amplifier OP1 has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal of the operational amplifier OP1 is connected to a reference potential. The inverting input terminal of the operational amplifier OP1 is connected to one end of the resistor R3 and the output terminal of the operational amplifier OP1. The other end of the resistor R3 is grounded.

[0204] The source terminal of the PMOS transistor PM1 is connected to a fixed potential (eg, a power supply potential), the drain terminal of the PMOS transistor PM1 is connected to the output terminal of the operational amplifier OP1, and the gate of the PMOS transistor PM1 is connected to the gate of the PMOS transistor PM2 and one end of the switch SW1.

[0205] The source terminal of the PMOS transistor PM2 is connected to a fixed potential (eg, a power supply potential), the drain terminal of the PMOS transistor PM2 is connected to the drain of the NMOS transistor PM1, and the gate of the PMOS transistor PM2 is connected to the gate of the PMOS transistor PM1 and one end of the switch SW1.

[0206] One end of the switch SW1 is connected to the gates of the PMOS transistors PM1 and PM2 , and the other end is connected to a fixed potential (for example, a power supply potential).

[0207] Regarding the NMOS transistor NM1, the drain is connected to the gate, and the source is grounded. In addition, regarding the NMOS transistor NM2, the drain is connected to the bias unit 21b, the gate is connected to the gate of the NMOS transistor NM1, and the source is grounded. In other words, the NMOS transistors NM1 and NM2 constitute a current mirror circuit. The gate of the NMOS transistor NM1 and the gate of the NMOS transistor NM2 are grounded via the switch SW2.

[0208] The comparison result output signal Vcomp output from the output terminal of the comparator 61 is input as a control signal to the operational amplifier OP1. The comparison result output signal Vcomp output from the output terminal of the comparator 61 is input as a control signal to the switches SW1 and SW2 via the inverter IN1.

[0209] When the comparator 61 outputs a Low-level signal as the comparison result output signal Vcomp, the operational amplifier OP1 to which the Low-level signal is input as a control signal is turned off. In addition, the switches SW1 and SW2 to which the High-level signal obtained by inverting the Low-level signal is input as a control signal are both turned on. In this case, the gate potential and the source potential of the PMOS transistors PM1 and PM2 become the same potential through the switch SW1. In addition, the gate of the NMOS transistor NM1 and the gate of the NMOS transistor NM2 are fixed to the ground potential through the switch SW2. Therefore, the variable current source circuit 62 is turned off.

[0210] When the comparator 61 outputs a High-level signal as the comparison result output signal Vcomp, the operational amplifier OP1 to which the High-level signal is input as a control signal becomes conductive. In addition, the switches SW1 and SW2 to which the Low-level signal which is the inverted High-level signal is input as a control signal are both turned on. In this case, the gate potential and the source potential of the PMOS transistors PM1 and PM2 become different potentials through the switch SW1. In addition, the gate of the NMOS transistor NM1 and the gate of the NMOS transistor NM2 are not fixed to the ground potential through the switch SW2. Therefore, the variable current source circuit 62 becomes conductive.

[0211] <Configuration Example of the Present Disclosure>

[0212] The present disclosure can also take the following structures. (1)

[0214] A Doherty amplifier circuit, comprising:

[0215] Carrier amplifier, amplifies high-frequency signals;

[0216] A peak amplifier to amplify the high frequency signal; and

[0217] The control circuit includes a first variable pass characteristic circuit that makes the pass characteristic of the high-frequency signal variable according to a supply voltage, and a detector that detects the high-frequency signal after passing through the first variable pass characteristic circuit, and controls the bias of the peak amplifier according to the detection result in the detector. (2)

[0219] According to the Doherty amplifier circuit described in (1) above,

[0220] The control circuit further comprises:

[0221] The second variable pass characteristic circuit is electrically connected between the first variable pass characteristic circuit and the detector, and makes variable the pass characteristic of the high frequency signal according to the drive level of amplifiers other than the peak amplifier. (3)

[0223] The Doherty amplifier circuit according to (1) or (2) above, wherein:

[0224] The first pass characteristic variable circuit comprises:

[0225] A passing part, allowing the high-frequency signal to pass through;

[0226] a biasing section for controlling a bias of the passing section; and

[0227] The extraction unit extracts current from the bias unit according to the supply voltage. (4)

[0229] According to the Doherty amplifier circuit described in (3) above,

[0230] The extraction unit comprises:

[0231] A first transistor, wherein the supply voltage is input to a collector or a drain, a base or a gate is electrically connected to a first node into which a constant current flows, and an emitter or a source is electrically connected to a second node;

[0232] a second transistor, wherein the collector or drain and the base or gate are electrically connected to the first node, and the emitter or source is electrically connected to the second node;

[0233] a third transistor, wherein the collector or drain and the base or gate are electrically connected to the second node, and the emitter or source is electrically connected to the reference potential; and

[0234] The fourth transistor has a base or a gate electrically connected to the second node, an emitter or a source electrically connected to a reference potential, and draws current from the bias unit to a collector. (5)

[0236] The Doherty amplifier circuit according to any one of (1) to (4) above, wherein:

[0237] The supply voltage is a power supply voltage supplied to the amplifier of the final stage, or a voltage corresponding to the power supply voltage. (6)

[0239] A Doherty amplifier circuit, comprising:

[0240] Carrier amplifier, amplifies high-frequency signals;

[0241] A peak amplifier to amplify the high frequency signal; and

[0242] A control circuit controls the bias of the peak amplifier,

[0243] The control circuit comprises:

[0244] a first pass characteristic variable circuit that makes a first pass characteristic through which the high frequency signal passes variable, wherein a threshold of the pass characteristic varies according to a supply voltage, and the first pass characteristic becomes relatively lower as the supply voltage is relatively higher; and

[0245] a detector for detecting the high frequency signal after passing through the first passage characteristic variable circuit,

[0246] The bias of the peak amplifier is controlled according to the detection result in the detector. (7)

[0248] The Doherty amplifier circuit according to (1) or (6) above, wherein:

[0249] The control circuit further comprises:

[0250] The second pass characteristic variable circuit is electrically connected between the first pass characteristic variable circuit and the detector, and makes the second pass characteristic of the high-frequency signal pass variable. The higher the driving level of the amplifier other than the peak amplifier is, the higher the second pass characteristic is. (8)

[0252] A Doherty amplifier circuit, comprising:

[0253] Carrier amplifier, amplifies high-frequency signals;

[0254] A peak amplifier to amplify the high frequency signal; and

[0255] A control circuit controls the bias of the peak amplifier,

[0256] The control circuit controls the bias of the peak amplifier according to a supply voltage and the high-frequency signal. (9)

[0258] According to the Doherty amplifier circuit described in (8) above,

[0259] The control circuit also controls the bias of the peak amplifier according to the drive level of amplifiers other than the peak amplifier. (10)

[0261] The Doherty amplifier circuit according to (8) or (9) above, wherein:

[0262] The control circuit comprises:

[0263] a first variable pass characteristic circuit that makes the pass characteristic of the high frequency signal pass variable according to a supply voltage; and

[0264] The detector detects the high frequency signal after passing through the first passage characteristic variable circuit. (11)

[0266] According to the Doherty amplifier circuit described in (3) above,

[0267] The extraction unit comprises:

[0268] A first resistor element, to one end of which the supply voltage is input;

[0269] a second resistor element having one end electrically connected to the other end of the first resistor element and another end electrically connected to a reference potential;

[0270] a comparator having a first input terminal, a second input terminal, and an output terminal, wherein a signal output from a connection point between the other end of the first resistor and one end of the second resistor is input to the first input terminal, a reference voltage is input to the second input terminal, and a comparison result output signal is output from the output terminal; and

[0271] The variable current source circuit changes the current drawn from the bias unit according to the comparison result output signal output from the output terminal of the comparator. (12)

[0273] According to the Doherty amplifier circuit described in (11) above,

[0274] In the first pass characteristic variable circuit, the extraction section is formed on a first semiconductor bare chip, and the pass section and the bias section are formed on a second semiconductor bare chip.

[0275] A material of a first semiconductor substrate included in the first semiconductor bare chip is different from a material of a second semiconductor substrate included in the second semiconductor bare chip.

[0276] In addition, the above-mentioned embodiment is for easy understanding of the present invention, and is not intended to limit the interpretation of the present invention. The present invention can be changed / improved without departing from the gist thereof, and the present invention also includes its equivalents.

[0277] Description of Reference Numerals

[0278] 1. 1A, 1B, 1C: Doherty amplifier circuit;

[0279] 10, 23: bias circuit;

[0280] 11: Carrier amplifier;

[0281] 12: Peak amplifier;

[0282] 13: Distributor;

[0283] 14: Coupler;

[0284] 15: Detector;

[0285] 16, 16A, 16B, 16C, 16D, 16E, 16F: control circuit;

[0286] 21, 21B, 21F: 1st pass characteristic variable circuit;

[0287] 21a, 21d: extraction part;

[0288] 21b, 22a: offset portion;

[0289] 21c: signal passing part;

[0290] 22: Detector;

[0291] 22b: detection unit;

[0292] 22c: filter unit;

[0293] 24: 2nd pass characteristic variable circuit;

[0294] 24a: signal passing part;

[0295] 24b: current source;

[0296] 31: Amplification system;

[0297] 32: Digital system;

[0298] 33: voltage supply circuit;

[0299] 61: Comparator;

[0300] 62: Variable current source circuit.

Claims

1. A Doherty amplifier circuit, comprising: Carrier amplifier, amplifies high-frequency signals; A peak amplifier to amplify the high frequency signal; and The control circuit includes a first variable pass characteristic circuit that makes the pass characteristic of the high-frequency signal variable according to a supply voltage, and a detector that detects the high-frequency signal after passing through the first variable pass characteristic circuit, and controls the bias of the peak amplifier according to the detection result in the detector.

2. The Doherty amplifier circuit according to claim 1, wherein: The control circuit further comprises: The second variable pass characteristic circuit is electrically connected between the first variable pass characteristic circuit and the detector, and makes variable the pass characteristic of the high frequency signal according to the drive level of amplifiers other than the peak amplifier.

3. The Doherty amplifier circuit according to claim 1 or 2, wherein: The first pass characteristic variable circuit comprises: A passing part, allowing the high-frequency signal to pass through; a biasing section for controlling a bias of the passing section; and The extraction unit extracts current from the bias unit according to the supply voltage.

4. The Doherty amplifier circuit according to claim 3, wherein: The extraction unit comprises: A first transistor, wherein the supply voltage is input to a collector or a drain, a base or a gate is electrically connected to a first node into which a constant current flows, and an emitter or a source is electrically connected to a second node; a second transistor, wherein the collector or drain and the base or gate are electrically connected to the first node, and the emitter or source is electrically connected to the second node; a third transistor, wherein the collector or drain and the base or gate are electrically connected to the second node, and the emitter or source is electrically connected to the reference potential; and The fourth transistor has a base or a gate electrically connected to the second node, an emitter or a source electrically connected to a reference potential, and draws current from the bias unit to a collector.

5. The Doherty amplifier circuit according to any one of claims 1 to 4, wherein: The supply voltage is a power supply voltage supplied to the amplifier of the final stage, or a voltage corresponding to the power supply voltage.

6. A Doherty amplifier circuit, comprising: Carrier amplifier, amplifies high-frequency signals; A peak amplifier to amplify the high frequency signal; and A control circuit controls the bias of the peak amplifier, The control circuit comprises: a first pass characteristic variable circuit that makes a first pass characteristic through which the high frequency signal passes variable, wherein a threshold of the pass characteristic varies according to a supply voltage, and the first pass characteristic becomes relatively lower as the supply voltage is relatively higher; and a detector for detecting the high frequency signal after passing through the first passage characteristic variable circuit, The bias of the peak amplifier is controlled according to the detection result in the detector.

7. The Doherty amplifier circuit according to claim 1 or 6, wherein: The control circuit further comprises: The second pass characteristic variable circuit is electrically connected between the first pass characteristic variable circuit and the detector, and makes the second pass characteristic of the high-frequency signal pass variable. The higher the driving level of the amplifier other than the peak amplifier is, the higher the second pass characteristic is.

8. A Doherty amplifier circuit, comprising: Carrier amplifier, amplifies high-frequency signals; A peak amplifier to amplify the high frequency signal; and A control circuit controls the bias of the peak amplifier, The control circuit controls the bias of the peak amplifier according to a supply voltage and the high-frequency signal.

9. The Doherty amplifier circuit according to claim 8, wherein: The control circuit also controls the bias of the peak amplifier according to the drive level of amplifiers other than the peak amplifier.

10. The Doherty amplifier circuit according to claim 8 or 9, wherein: The control circuit comprises: a first variable pass characteristic circuit that makes the pass characteristic of the high frequency signal pass variable according to a supply voltage; and The detector detects the high frequency signal after passing through the first passage characteristic variable circuit.

11. The Doherty amplifier circuit according to claim 3, wherein: The extraction unit comprises: A first resistor element, to one end of which the supply voltage is input; a second resistor element having one end electrically connected to the other end of the first resistor element and another end electrically connected to a reference potential; A comparator having a first input terminal, a second input terminal, and an output terminal, wherein a signal output from a connection point between the other end of the first resistor and one end of the second resistor is input to the first input terminal, a reference voltage is input to the second input terminal, and a comparison result output signal is output from the output terminal; and The variable current source circuit changes the current drawn from the bias unit according to the comparison result output signal output from the output terminal of the comparator.

12. The Doherty amplifier circuit according to claim 11, wherein: In the first pass characteristic variable circuit, the extraction section is formed on a first semiconductor bare chip, and the pass section and the bias section are formed on a second semiconductor bare chip. A material of a first semiconductor substrate included in the first semiconductor bare chip is different from a material of a second semiconductor substrate included in the second semiconductor bare chip.

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