Chip self-checking method and chip
Through the chip self-test method that realizes fault detection, fault signal extraction and severity level judgment in the chip, the problem of imperfect mechanism of existing chip fault handling methods is solved, and the fault handling efficiency and chip safety are improved.
Patent Information
- Application Number
- CN202411829075.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-12
- Publication Date
- 2025-03-21
AI Technical Summary
The existing chip fault handling methods cannot confirm that the fault signal cannot be output normally, cannot query historical faults, and fail to distinguish between serious faults and ordinary faults, resulting in imperfect processing mechanisms.
Provide a chip self-test method, including fault detection of internal functions of the chip, determining whether the chip has a fault, generating a fault signal, and extracting the fault type and severity level from the fault signal. According to the fault severity level, select the output path of the fault signal and embed the fault information into the data stream to output or adjust the chip status.
It realizes that while ensuring the effective output of serious fault information, avoiding the use of too much resources from other fault information, improves the fault processing efficiency, and immediately stops the flow when a serious fault occurs, improving the safety of the chip.
Smart Images
Figure CN119667441A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor integrated circuit design, and in particular to a chip self-checking method and a chip. Background Art
[0002] With the development of industrial technology, the integration of electronic circuits is getting higher and higher, and at the same time, the quality requirements for chips are getting higher and higher. Therefore, when designing chips, it is usually necessary to consider effective detection of each functional module of the chip.
[0003] At present, a functional module for detecting chip functions is added to the chip, so as to realize the detection of various functions of the chip by using the functional module. Specifically, when the detection functional module detects that the chip fails, it will send a fault signal, so that the cause of the fault can be confirmed by using the fault signal.
[0004] However, the existing chip fault handling method can only analyze and process the fault signals that have been output. If the fault signal cannot be output normally, the fault information cannot be confirmed. In addition, the existing chip fault handling method cannot query historical faults, so that fault information cannot be effectively collected. In addition, the existing chip design does not distinguish between serious faults and ordinary faults, so effective measures cannot be taken accordingly, and the handling mechanism is imperfect. Summary of the invention
[0005] The object of the present invention is to provide a chip self-checking method and a chip, so as to at least solve the problem that the existing chip fault handling method mechanism is imperfect.
[0006] In order to solve the above technical problems, the present invention provides a chip self-test method, comprising: Perform fault detection on the internal functions of the chip; Determine whether the chip is faulty; If the chip fails, a fault signal is generated; Extracting the fault type from the fault signal, and judging the severity level of the fault according to the preset fault type, wherein the severity levels include level one fault, level two fault and level three fault from high to low; If the fault is a primary fault, a fault signal is sent in real time through the output port, and the fault information is embedded in the data stream output by the chip for output, and the state of the chip is adjusted to a stop-flow safety state; If the fault is a secondary fault, the fault information is embedded in the data stream output by the chip and the normal working state of the chip is maintained; If the fault is a level 3 fault, no fault signal and fault information are output, and the chip maintains its normal working state.
[0007] Optionally, in the chip self-checking method, the chip self-checking method further includes: Fault information is extracted from the fault signal and stored in a designated storage space according to the fault type.
[0008] Optionally, in the chip self-checking method, the chip self-checking method further includes: generating an alarm enable signal; If the fault is a primary fault or a secondary fault, the alarm enable signal is valid, and the fault signal and fault information output are controlled; If the fault is a level 3 fault, the alarm enable signal is invalid, and the control fault signal and fault information are not output.
[0009] Optionally, in the chip self-checking method, the chip self-checking method further includes: Statistically detect all fault signals generated to obtain historical fault information; According to the historical fault information, the fault differentiation conditions are set to classify the severity level of the fault according to the fault differentiation conditions.
[0010] In order to solve the above technical problems, the present invention further provides a chip for implementing the chip self-checking method as described in any one of the above items, the chip comprising: A fault detection module is used to perform function detection on each functional module in the chip to determine whether the chip has a fault and generate a fault signal when the chip has a fault; A fault management module is used to obtain a fault signal, analyze and process the fault signal to obtain the severity level of the fault, and select an output path of the fault signal according to the severity level of the fault; The chip control module is used to adjust the state of the chip according to the severity level of the fault.
[0011] Optionally, in the chip, the fault management module includes: A current fault information storage unit, used to store a fault signal generated by the current function test, and updated when a fault signal is generated by the next function test; A historical fault information storage unit is used to store all fault signals generated by the function detection and is cleared after reset; The fault classification unit is used to determine the severity level of the fault according to the fault signal, and select an output path of the fault signal according to the severity level of the fault.
[0012] Optionally, in the chip, the current fault information storage unit includes multiple single-field registers and one multi-field register; each of the single-field registers corresponds to a fault signal, and when the fault signal occurs, the corresponding single-field register is assigned a value of 1; each field of the multi-field register corresponds to a fault signal, and when the fault signal occurs, the corresponding field is assigned a value of 1.
[0013] Optionally, in the chip, the historical fault information storage unit includes multiple single-field registers; each of the single-field registers corresponds to a fault signal, and when the fault signal occurs, the corresponding single-field register is assigned a value of 1.
[0014] Optionally, in the chip, the fault management module also includes an enable control unit, which is used to generate a detection enable signal and an alarm enable signal, the detection enable signal is used to control the functional detection items performed by the fault detection module, and the alarm enable signal is used to control the output of the fault signal according to the severity level of the fault.
[0015] Optionally, in the chip, the enable control unit includes a detection control register group and an alarm control register group; the detection control register group includes multiple detection control registers, each of the detection control registers corresponds to a function detection, and when a detection control register is assigned a value of 1, the fault detection module is controlled to perform the function detection corresponding to the detection control register; the alarm control register group includes multiple alarm control registers, each of the alarm control registers corresponds to a fault signal, and when a certain alarm control register is assigned a value of 1, if the fault detection module generates a fault signal corresponding to the alarm control register, the fault signal is output.
[0016] The chip self-checking method and chip provided by the present invention include: performing fault detection on the internal functions of the chip; judging whether the chip fails; generating a fault signal if the chip fails; extracting the fault type from the fault signal, and judging the severity level of the fault according to the preset fault type, wherein the severity levels include level one fault, level two fault and level three fault from high to low; if the fault is a level one fault, sending a fault signal in real time through an output port, embedding the fault information in the data stream output by the chip for output, and adjusting the state of the chip to a stop-flow safety state; if the fault is a level two fault, embedding the fault information in the data stream output by the chip for output, and maintaining the normal working state of the chip; if the fault is a level three fault, not outputting the fault signal and the fault information, and maintaining the normal working state of the chip. By judging the severity level of the fault according to the fault signal and selecting the output path of the fault signal according to the severity level, it is possible to ensure that serious fault information can be effectively output while preventing other fault information from occupying too many resources, thereby effectively improving the fault handling efficiency; by judging the severity level of the fault according to the fault signal and adjusting the state of the chip according to the severity level, it is possible to ensure that the chip immediately stops flowing when a serious fault occurs, thereby effectively improving the safety of the chip operation and solving the problem of imperfect mechanisms of existing chip fault handling methods. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Figure 1 A flowchart of the chip self-test method provided in this embodiment; Figure 2 A logic diagram of the chip self-check method provided in this embodiment; Figure 3 A structural block diagram of the chip provided in this embodiment; Figure 4 A schematic diagram of the application structure of the chip provided in this embodiment. DETAILED DESCRIPTION
[0018] The chip self-test method and chip proposed in the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the accompanying drawings is often a part of the actual structure. In particular, the emphasis of each accompanying drawing is different, and sometimes different proportions are used.
[0019] It should be noted that the terms "first", "second", etc. in the specification, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that the structures used in this way can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0020] This embodiment provides a chip self-test method, such as Figure 1 As shown, including: S1, fault detection of internal functions of the chip; S2, determine whether the chip is faulty; S3, if the chip fails, a fault signal is generated; S4, extracting the fault type from the fault signal, and judging the severity level of the fault according to the preset fault type, wherein the severity levels include level one fault, level two fault and level three fault from high to low; S5, if the fault is a first-level fault, a fault signal is sent in real time through the output port, and the fault information is embedded in the data stream output by the chip and output, and the state of the chip is adjusted to a stop-flow safety state; if the fault is a second-level fault, the fault information is embedded in the data stream output by the chip and output, and the normal working state of the chip is maintained; if the fault is a third-level fault, the fault signal and fault information are not output, and the normal working state of the chip is maintained.
[0021] The chip self-check method provided in this embodiment determines the severity level of the fault according to the fault signal and selects the output path of the fault signal according to the severity level, thereby ensuring that serious fault information can be effectively output while preventing other fault information from occupying too many resources, thereby effectively improving the fault handling efficiency; by determining the severity level of the fault according to the fault signal and adjusting the state of the chip according to the severity level, it is possible to ensure that the chip immediately stops flowing when a serious fault occurs, thereby effectively improving the safety of the chip operation and solving the problem of imperfect mechanism of existing chip fault handling methods.
[0022] The chip fault processing method provided in this embodiment is applicable to various types of chips, including but not limited to image sensor chips, automotive chips, etc.
[0023] Specifically, in this embodiment, step S1, a fault detection is performed on the internal functions of the chip, wherein the fault detection includes but is not limited to power-on self-test, analog function test, digital function test, etc. The power-on self-test is mainly used to detect faults such as logic self-test errors and memory self-test errors, the analog function test is mainly used to detect faults such as voltage exceeding a threshold value and temperature exceeding a threshold value, and the digital function test is mainly used to detect faults such as data processing errors, data transmission errors, and register write errors.
[0024] In practical applications, multiple fault detection items can be set according to the actual use of the chip. For example, when the chip integrates multiple functional circuits, fault detection can be performed on each functional circuit to ensure that each functional circuit of the chip can operate normally.
[0025] Furthermore, in this embodiment, step S2 determines whether the chip fails.
[0026] Specifically, if a function test result shows failure, or the function test cannot be performed, it indicates that the chip fails during the function test. In practical applications, those skilled in the art can obtain specific methods and means for determining whether a chip fails based on existing known technologies, and this application will not go into details.
[0027] And, in this embodiment, in step S3, if a chip fails, a fault signal is generated.
[0028] Specifically, in this embodiment, when a chip fails during a certain functional test, the generated fault signal corresponds to the functional test item, that is, different faults correspond to different faults, so that the cause of the chip failure can be confirmed based on the fault signal.
[0029] Preferably, in order to ensure that the fault signal can be read correctly and accurately, a digital signal can be used as the fault signal, and at the reading end of the fault signal, filtering and denoising can be performed before reading the fault signal.
[0030] Furthermore, in this embodiment, step S4 extracts the fault type from the fault signal, and determines the severity level of the fault according to the preset fault type, wherein the severity levels include level one fault, level two fault and level three fault from high to low.
[0031] Specifically, in this embodiment, first, the fault type is extracted from the fault signal, for example, whether the fault belongs to a fault occurring in a power-on self-test, a fault occurring in an analog function test, or a fault occurring in a digital function test, and the possible consequences of the fault, such as chip burnout, data loss, inefficient chip operation, or normal chip operation. Then, according to the preset fault type, the severity level of the fault is determined, for example, multiple faults that cause chip burnout and data loss are classified as the same fault type, and the severity level of this fault type is defined as a first-level fault, multiple faults that cause inefficient chip operation are classified as the same fault type, and the severity level of this fault type is defined as a second-level fault, and multiple faults that do not affect the normal operation of the chip are classified as the same fault type, and the severity level of this fault type is defined as a third-level fault.
[0032] In a specific embodiment, all fault signals generated by the detection can be statistically analyzed to obtain historical fault information; then, according to the historical fault information, fault differentiation conditions are set to classify the severity level of the fault according to the fault differentiation conditions. In this way, the historical fault information includes various types of fault conditions that may occur and have occurred in the chip, and the consequences corresponding to the fault conditions can be obtained, so that the severity level of the fault can be classified by using the historical fault information, so that each fault signal can have its own corresponding severity level, which is convenient for the subsequent processing of the fault signal.
[0033] In practical applications, all possible faults can be counted in a list format to obtain a comparison table of fault content, fault signal and severity level.
[0034] Of course, in other embodiments, faults may be divided into more different severity levels according to actual needs, so as to achieve a more detailed fault handling management process, and this application does not impose any restrictions on this.
[0035] Preferably, in order to ensure that the fault information in the fault signal can be effectively read and avoid chip fault processing omissions caused by the failure to output the fault normally, in this embodiment, the fault information can also be extracted from the fault signal; then, according to the fault type, the fault information is stored in a designated storage space.
[0036] Specifically, since each fault signal corresponds to a fault, the fault content can be confirmed by reading the fault signal. At the same time, the time when the fault signal is sent, that is, the time when the fault occurs, can be obtained. In this way, the fault content and the fault occurrence time are extracted as fault information and saved according to the fault type. This is beneficial for the staff to directly read the fault information stored in the storage space through the external interface to confirm the fault, ensuring that the fault information can be read in a timely and effective manner, thereby improving the safety of chip operation.
[0037] In actual applications, two storage spaces can be set in the chip, where: one storage space only stores the fault information generated by the current functional test, that is, when the next functional test starts, the fault information stored last time will be replaced by the fault information of the new functional test. When the staff reads the fault information in the storage space through the external interface, they can obtain in real time whether there is a fault in the current functional test and the content of the fault; the other storage space stores all the fault information of the chip, that is, each fault information generated will be stored in the corresponding position of the storage space. Only by resetting the storage space can all the stored fault information be cleared. When the staff reads the fault information in the storage space through the external interface, all the historical fault information up to the time of reading can be obtained.
[0038] Further, in this embodiment, in step S5, if the fault is a first-level fault, a fault signal is sent in real time through the output port, and the fault information is embedded in the data stream output by the chip and output, and the state of the chip is adjusted to a stop-flow safety state; if the fault is a second-level fault, the fault information is embedded in the data stream output by the chip and output, and the normal working state of the chip is maintained; if the fault is a third-level fault, the fault signal and fault information are not output, and the normal working state of the chip is maintained.
[0039] In this way, when the fault is a level 1 fault (serious fault), the fault signal is output through two channels, thereby ensuring that the fault information can be received in a timely and effective manner, and the accuracy of the fault signal can be judged by comparing the two fault signals, thereby improving the efficiency of fault confirmation and processing. At the same time, the chip status is adjusted in time according to the fault signal, thereby improving the safety of the chip. For level 2 faults (ordinary faults) that do not affect the normal operation of the chip, they are output by embedding the data stream, and for level 3 faults (minor faults), they can be not output, thereby minimizing the complexity and power consumption of data transmission.
[0040] Preferably, in order to accurately control the output and path of fault signals corresponding to different faults, in this embodiment, an alarm enable signal is set. The alarm enable signal can flexibly control whether the fault signal is output according to the chip function and usage scenario, thereby ensuring that the fault can be effectively output while reducing the complexity and power consumption of signal transmission as much as possible.
[0041] Specifically, in the present embodiment, an alarm enable signal is generated; if the fault is a level one fault or a level two fault, the alarm enable signal is valid, and the fault signal and fault information are controlled to be output, wherein, in actual applications, the alarm enable signal can be in two valid states, corresponding to level one faults and level two faults, respectively, so that the alarm enable signal can be used to select the path for outputting the fault signal; if the fault is a level three fault, the alarm enable signal is invalid, and the fault signal and fault information are controlled not to be output.
[0042] The following, combined Figure 2 , illustrating the processing process of the chip self-check method provided in this embodiment in practical application.
[0043] First, the internal functions of the chip are detected for faults. If the chip fails, a fault signal is generated. Then, the fault information carried by the fault signal is stored. Specifically, two different storage spaces can be used to store the fault information respectively, so as to ensure that the fault information can be effectively stored and read. Next, the severity of the fault is determined, wherein the alarm enable signal can be used to select different output paths for fault signals of different severity levels. If it is a first-level fault, the alarm enable signal controls the fault signal to send the fault signal in real time through the output port, and embeds the fault information into the data stream output by the chip for output; if it is a second-level fault, the alarm enable signal controls the fault signal to be embedded into the data stream output by the chip for output; if it is a third-level fault, the fault signal and fault information are not output, which is equivalent to no fault. At the same time, when a first-level fault occurs, the state of the chip is adjusted to a stop-flow safety state; when a second-level fault or a third-level fault occurs, the state of the chip remains in a normal working state.
[0044] In this way, all fault information is saved to ensure that all fault information can be effectively read; different signal output paths are selected for faults of different severity levels to ensure that serious faults can be handled in a timely and effective manner, and the complexity and power consumption of data transmission can be reduced; the chip status is adjusted accordingly for faults of different severity levels to improve the safety of chip operation.
[0045] This embodiment also provides a chip for implementing the chip self-test method as described above. Figure 3 As shown, the chip includes: A fault detection module is used to perform function detection on each functional module in the chip to determine whether the chip has a fault and generate a fault signal when the chip has a fault; A fault management module is used to obtain a fault signal, analyze and process the fault signal to obtain the severity level of the fault, and select an output path of the fault signal according to the severity level of the fault; The chip control module is used to adjust the state of the chip according to the severity level of the fault.
[0046] The chip provided in this embodiment performs function detection and generates fault signals through a fault detection module, determines the severity of the fault according to the fault signal through a fault management module, and selects the output path of the fault signal according to the severity level, thereby ensuring that serious fault information can be effectively output while preventing other fault information from occupying too many resources, thereby effectively improving the fault handling efficiency; the chip control module determines the severity of the fault according to the fault signal, and adjusts the state of the chip according to the severity level, thereby ensuring that the chip stops immediately when a serious fault occurs, effectively improving the safety of the chip operation, and solving the problem of imperfect mechanisms of existing chip fault handling methods.
[0047] Specifically, in this embodiment, the fault detection module may include multiple fault detection units such as a power-on self-test unit, an analog function detection unit, and a digital function detection unit to detect various types of faults occurring in the chip in real time. Among them, the power-on self-test unit can detect faults such as logic self-test errors and memory self-test errors; the analog function detection unit can detect faults such as voltage exceeding a threshold value and temperature exceeding a threshold value; the digital function detection unit can detect faults such as image processing errors, data transmission errors, and register write errors. When a fault is detected, the fault detection module transmits the corresponding fault signal to the fault management module.
[0048] Of course, in practical applications, the type of fault detection unit specifically included in the fault detection module can be designed according to the functional circuit inside the chip to ensure that each functional circuit of the chip can be effectively detected, and this application does not impose any restrictions on this.
[0049] Furthermore, in this embodiment, if Figure 4 As shown, the fault management module includes: a current fault information storage unit, which is used to store the fault signal generated by the current function detection and is updated when the next function detection generates a fault signal; a historical fault information storage unit, which is used to store all fault signals generated by the function detection and is cleared after reset; a fault classification unit, which is used to judge the severity level of the fault according to the fault signal, and select the output path of the fault signal according to the severity level of the fault.
[0050] Specifically, in this embodiment, the current fault information storage unit includes a plurality of single-field registers and a multi-field register. Each of the single-field registers corresponds to a fault signal, and when the fault signal occurs, the corresponding single-field register is assigned a value of 1; each field of the multi-field register corresponds to a fault signal, and when the fault signal occurs, the corresponding field is assigned a value of 1.
[0051] The number of single-field registers needs to meet the type of fault signals, and the number of fields of multi-field registers needs to meet the type of fault signals, thereby ensuring that each fault signal is stored in a specially designated register or field.
[0052] In actual applications, the fault information stored in the single-field register will be replaced and changed according to the process of functional detection. Taking the image sensor chip as an example, the fault information stored in the single-field register changes once per frame. If the fault corresponding to the single-field register is cleared in the next frame, the single-field register is assigned a value of 0. The fault information stored in the single-field register can be manually read out through the external interface.
[0053] And, in practical applications, multi-field registers are used to quickly identify and locate faults, and the fault information stored in the multi-field registers will also be replaced and changed according to the process of functional detection. Taking the image sensor chip as an example, the fault information stored in the multi-field register changes once per frame. If the fault corresponding to a field is cleared in the next frame, the field is assigned a value of 0. The fault information stored in the multi-field register can be embedded in the data stream output by the chip, for example, embedded at the end of each frame of picture information and output with the image data stream.
[0054] Furthermore, in this embodiment, the historical fault information storage unit includes a plurality of single-field registers; each of the single-field registers corresponds to a fault signal, and when the fault signal occurs, the corresponding single-field register is assigned a value of 1.
[0055] In actual applications, unlike the single-field register in the current fault information storage unit, the single-field register in the historical fault information storage unit is assigned a value of 1 as long as the corresponding fault has occurred. Even if the subsequent fault is cleared, the single-field register is still assigned a value of 1. Only after the chip is reset, the fault information stored in the single-field register in the historical fault information storage unit will be cleared. In this way, if there is a problem with the fault output mechanism of the chip, the values of these single-field registers can be read through the bus to query the historical fault information, avoiding the loss of fault information due to the failure of the fault output mechanism.
[0056] Furthermore, in this embodiment, the fault classification unit determines the severity level of the fault according to the fault signal, and selects an output path of the fault signal according to the severity level of the fault.
[0057] Specifically, the fault classification unit classifies faults into level one faults, level two faults, and level three faults according to the severity level from high to low, and when a level one fault occurs, a fault signal is sent in real time through the output port (I / O output), and the fault information is embedded in the data stream output by the chip for output; when a level two fault occurs, the fault information is embedded in the data stream output by the chip for output; when a level three fault occurs, no fault signal is output.
[0058] At the same time, the fault classification unit also reports the classification result (severity level) of the current fault signal to the chip control module through the bus, and the chip control module adjusts the chip status according to the classification result (severity level) of the fault signal: when a level 1 fault occurs, the chip status is adjusted to a stop-flow safety state; when a level 2 or level 3 fault occurs, the chip maintains its normal working state.
[0059] Preferably, in order to flexibly control the items of function detection and the output of fault signals, in this embodiment, Figure 4 As shown, the fault management module also includes an enable control unit, which is used to generate a detection enable signal and an alarm enable signal. The detection enable signal is used to control the functional detection items performed by the fault detection module, and the alarm enable signal is used to control the output of the fault signal according to the severity level of the fault.
[0060] Specifically, in this embodiment, the enabling control unit includes a detection control register group and an alarm control register group.
[0061] The detection control register group includes a plurality of detection control registers, each detection control register corresponds to a function test, and when a detection control register is assigned a value of 1, the fault detection module is controlled to perform the function test corresponding to the detection control register. In this way, the function test items to be performed can be flexibly adjusted by changing the value of the detection control register.
[0062] Furthermore, the alarm control register group includes a plurality of alarm control registers, each of which corresponds to a fault signal. When a certain alarm control register is assigned a value of 1, if the fault detection module generates a fault signal corresponding to the alarm control register, the fault signal is output. In this way, the fault signal of the alarm to be performed can be flexibly adjusted by changing the value of the alarm control register, thereby shielding unimportant fault information, reducing the amount of data transmission, and reducing system power consumption.
[0063] Furthermore, in this embodiment, the chip control module is used to receive information output by the fault classification unit, and control the adjustment of the chip state according to the severity level of the fault, so as to ensure the safety of the chip operation.
[0064] In addition, in practical applications, an electronic controller (ECU) can also be used to obtain fault signals. The fault information can be read through the I / O interface or the embedded fault information can be read through the data stream. This ensures that the fault information is effectively read and processed in a timely manner, thus improving the chip fault processing mechanism.
[0065] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other. In addition, the different parts between the various embodiments can also be used in combination with each other, and the present invention is not limited to this.
[0066] The chip self-check method and chip provided in this embodiment include: performing fault detection on the internal functions of the chip; judging whether the chip fails; generating a fault signal if the chip fails; extracting the fault type from the fault signal, and judging the severity level of the fault according to the preset fault type, wherein the severity levels include level 1 fault, level 2 fault and level 3 fault from high to low; if the fault is a level 1 fault, sending a fault signal in real time through the output port, embedding the fault information in the data stream output by the chip for output, and adjusting the state of the chip to a stop-flow safety state; if the fault is a level 2 fault, embedding the fault information in the data stream output by the chip for output, and maintaining the normal working state of the chip; if the fault is a level 3 fault, not outputting the fault signal and fault information, and maintaining the normal working state of the chip. By judging the severity level of the fault according to the fault signal and selecting the output path of the fault signal according to the severity level, it is possible to ensure that serious fault information can be effectively output while preventing other fault information from occupying too many resources, thereby effectively improving the fault handling efficiency; by judging the severity level of the fault according to the fault signal and adjusting the state of the chip according to the severity level, it is possible to ensure that the chip immediately stops flowing when a serious fault occurs, thereby effectively improving the safety of the chip operation and solving the problem of imperfect mechanisms of existing chip fault handling methods.
[0067] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A chip self-test method, characterized in that: include: Perform fault detection on the internal functions of the chip; Determine whether the chip is faulty; If the chip fails, a fault signal is generated; Extracting the fault type from the fault signal, and judging the severity level of the fault according to the preset fault type, wherein the severity levels include level one fault, level two fault and level three fault from high to low; If the fault is a primary fault, a fault signal is sent in real time through the output port, and the fault information is embedded in the data stream output by the chip for output, and the state of the chip is adjusted to a stop-flow safety state; If the fault is a secondary fault, the fault information is embedded in the data stream output by the chip and the normal working state of the chip is maintained; If the fault is a level 3 fault, no fault signal and fault information are output, and the chip maintains its normal working state.
2. The chip self-checking method according to claim 1, characterized in that: The chip self-test method further comprises: Fault information is extracted from the fault signal and stored in a designated storage space according to the fault type.
3. The chip self-checking method according to claim 1, characterized in that: The chip self-test method further comprises: generating an alarm enable signal; If the fault is a primary fault or a secondary fault, the alarm enable signal is valid, and the fault signal and fault information output are controlled; If the fault is a level 3 fault, the alarm enable signal is invalid, and the control fault signal and fault information are not output.
4. The chip self-checking method according to claim 1, characterized in that: The chip self-test method further comprises: Statistically detect all fault signals generated to obtain historical fault information; According to the historical fault information, the fault differentiation conditions are set to classify the severity level of the fault according to the fault differentiation conditions.
5. A chip, used to implement the chip self-checking method according to any one of claims 1 to 4, characterized in that: The chip comprises: A fault detection module is used to perform function detection on each functional module in the chip to determine whether the chip has a fault and generate a fault signal when the chip has a fault; A fault management module is used to obtain a fault signal, analyze and process the fault signal to obtain the severity level of the fault, and select an output path of the fault signal according to the severity level of the fault; The chip control module is used to adjust the state of the chip according to the severity level of the fault.
6. The chip according to claim 5, characterized in that: The fault management module comprises: A current fault information storage unit, used to store a fault signal generated by the current function test, and updated when a fault signal is generated by the next function test; A historical fault information storage unit is used to store all fault signals generated by the function detection and is cleared after reset; The fault classification unit is used to determine the severity level of the fault according to the fault signal, and select an output path of the fault signal according to the severity level of the fault.
7. The chip according to claim 6, characterized in that: The current fault information storage unit includes multiple single-field registers and one multi-field register; each of the single-field registers corresponds to a fault signal, and when the fault signal occurs, the corresponding single-field register is assigned a value of 1; each field of the multi-field register corresponds to a fault signal, and when the fault signal occurs, the corresponding field is assigned a value of 1.
8. The chip according to claim 6, characterized in that: The historical fault information storage unit includes a plurality of single-field registers; each of the single-field registers corresponds to a fault signal, and when the fault signal occurs, the corresponding single-field register is assigned a value of 1.
9. The chip according to claim 6, characterized in that: The fault management module also includes an enable control unit, which is used to generate a detection enable signal and an alarm enable signal. The detection enable signal is used to control the functional detection items performed by the fault detection module, and the alarm enable signal is used to control the output of the fault signal according to the severity level of the fault.
10. The chip according to claim 9, characterized in that: The enable control unit includes a detection control register group and an alarm control register group; the detection control register group includes multiple detection control registers, each of which corresponds to a function detection, and when a detection control register is assigned a value of 1, the fault detection module is controlled to perform the function detection corresponding to the detection control register; the alarm control register group includes multiple alarm control registers, each of which corresponds to a fault signal, and when a certain alarm control register is assigned a value of 1, if the fault detection module generates a fault signal corresponding to the alarm control register, the fault signal is output.