Method for preparing chip packaging structure

Abstract

The present application discloses a method for preparing a chip packaging structure, which is applicable to the field of semiconductor technology. The preparation method includes sequentially forming a stacked first mask layer and a second mask layer on a wafer. A conductive via is formed, which penetrates the second mask layer and the first mask layer and extends into the wafer. The conductive via includes a first sub-via located in the second mask layer. The first sub-via includes a first opening close to the wafer and a second opening away from the wafer. The area of ​​the second opening is larger than the area of ​​the first opening. A conductive structure is formed in the conductive via, and the conductive structure includes a first portion located in the first sub-via. The second mask layer is removed to expose the first portion of the conductive structure. The first portion of the conductive structure is removed. The technical solution of the present application achieves an improvement in the electrical performance of the chip packaging structure.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular, relates to a method for preparing a chip packaging structure. Background Art

[0002] At present, advanced packaging processes all require the use of Through Silicon Via (TSV) to achieve electrical interconnection between stacked chips, so TSV is a key structure in advanced packaging.

[0003] However, in the process of forming TSV, a "funnel-shaped" morphological defect is prone to appear on the top of the TSV, resulting in a TSV short circuit, which affects the electrical performance of the chip packaging structure. Summary of the invention

[0004] The present application provides a method for preparing a chip packaging structure, aiming to improve the electrical performance of the chip packaging structure.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0006] A method for preparing a chip packaging structure is provided, the method comprising: sequentially forming a first mask layer and a second mask layer stacked on a wafer. Forming a conductive via, the conductive via penetrating the second mask layer and the first mask layer and extending into the wafer, the conductive via comprising a first sub-via located in the second mask layer, the first sub-via comprising a first opening close to the wafer and a second opening away from the wafer, the area of ​​the second opening being larger than the area of ​​the first opening. Forming a conductive structure in the conductive via, the conductive structure comprising a first portion located in the first sub-via. Removing the second mask layer to expose the first portion of the conductive structure. Removing the first portion of the conductive structure.

[0007] The method for preparing a chip packaging structure provided in an embodiment of the present application sequentially forms a stacked first mask layer and a second mask layer on a wafer, and then forms a conductive via. The first sub-via of the conductive via located in the second mask layer has a second opening area away from the wafer that is larger than the first opening area close to the wafer. It can be understood that only the first sub-via located in the second mask layer has a "trumpet-mouth" morphological defect, and the conductive via located in the first mask layer is a normal via. Then, a conductive structure is formed in the conductive via, the second mask layer is removed, the first part of the conductive structure located in the first sub-via is exposed, and the first part is removed, that is, the conductive structure with morphological defects in the first sub-via is removed, and the conductive structure located in the first mask layer is retained. The above preparation method improves the morphological defects of the conductive structure, avoids TSV short circuits caused by the "trumpet-mouth", and thus improves the electrical performance of the chip packaging structure finally prepared.

[0008] In some embodiments, a remote plasma-assisted dry etching process is used to remove the second mask layer.

[0009] In some embodiments, an etching selectivity ratio of the second mask layer to the first mask layer is greater than 50.

[0010] In some embodiments, the material of the first mask layer includes Si3N4, and the material of the second mask layer includes SiO2. A fluorine-containing gas and a hydrogen-containing gas are used to form a plasma, and an alcohol is used as a solvent for the plasma to obtain an etching gas. The etching gas is used to react with the second mask layer to generate volatile byproducts, and the volatile byproducts are removed by heating to remove the second mask layer.

[0011] In some embodiments, NF3 and H2 are used to form plasma, and CH3OH is used as a solvent of the plasma to obtain an etching gas. The etching gas is used to react with SiO2 to generate (NH4)2SiF6, and the (NH4)2SiF6 is removed by heating to remove the second mask layer.

[0012] In some embodiments, the gas ratio of NF3 to H2 is in the range of 1:3 to 1:5.

[0013] In some embodiments, the gas ratio of the sum of NF3 and H2 to CH3OH is in the range of 1:3 to 1:5.

[0014] In some embodiments, the dry etching process has a pressure of 200 m Torr, a process temperature in the range of 0 to 60° C., and a duration of 3 min to 20 min.

[0015] In some embodiments, removing the first portion of the conductive structure includes grinding the first portion of the conductive structure using a chemical mechanical polishing process.

[0016] In some embodiments, during the grinding of the first portion of the conductive structure, the surface of the first mask layer away from the wafer is also ground. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0018] Figure 1 A flowchart of the chip packaging structure provided in the embodiment of the present application;

[0019] Figure 2~Figure 7 for Figure 1 A diagram of each step of the preparation process;

[0020] Figure 8 A schematic diagram of the principle of the etching process steps provided in the embodiment of the present application;

[0021] Figure 9~Figure 12 This is a comparative experimental data chart of various process parameters provided in the examples of this application. DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0023] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0024] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0025] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0026] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0027] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0028] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0029] Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0030] At present, advanced packaging is mainly divided into two forms: 2.5D and 3D. On the Fab side, 2.5D is mainly for the production of silicon adapters, and 3D is mainly for wafer to wafer fusion or hybrid bonding (Wafer to Wafer Fusion / Hybrid Bonding). Both involve the production of through-silicon vias. The etching of through-silicon vias is more difficult, mainly because of their high aspect ratio. At the same time, the etched film layer involves factors such as the switching of dielectric layers (silicon oxide, silicon nitride, silicon carbonitride, etc.) and different types of silicon. Therefore, after the through-silicon via etching is completed, obtaining TSV holes with high verticality and smooth sidewalls places high demands on the etching process and the integration of the previous and subsequent processes.

[0031] In the process of forming TSV in 3D stacked wafers, after TSV silicon etching (Si ETCH) is completed, the bottom dielectric layer and Liner Oxide (insulating oxide layer) need to be etched in sequence. In the process of etching silicon with the hard mask as a barrier, the surface of the hard mask will have an uneven morphology, especially the raised position at the edge of the TSV hole is easy to attract charges and be etched away first. At the same time, the top hard mask layer and the bottom dielectric layer and Liner Oxide are similar in material, all of which are mainly silicon oxide (SiO2), so the etching rate is similar. While the bottom material is being etched, a large part of the top hard mask layer will also be etched, and finally a trumpet-shaped etching morphology will appear.

[0032] In the process of forming TSV in 2.5D Si Interposer, due to the large depth-width ratio of the entire Si, the depth is usually above 100um. Even if there is a large selectivity between etching silicon and dielectric layers, the amount of etched silicon is large, and the loss of the top hard mask layer is also large. In addition, the above-mentioned hole surface is directly subjected to Litho process, and the dielectric layer and silicon etching are completed in one step using Si Etch Chamber. Since the etching of the dielectric layer will be more difficult due to the parameters such as gas and ratio for Si etching, the top dielectric layer will not be etched, that is, a trumpet-mouth morphology will appear.

[0033] When a trumpet-shaped morphology appears on the top of the TSV, the overall morphology of the TSV will change, and the distance between the TSVs will be shortened, and the electrical performance will be different from the original design. When the distance between the TSV and the design is close enough and the trumpet-shaped morphology is expanded to a certain extent, the two hole interfaces will contact each other, and eventually the TSV short circuit will occur, which will affect the electrical performance of the chip packaging structure prepared subsequently.

[0034] Moreover, due to the inclined morphology of the trumpet mouth, the linear insulating oxide layer located on the side wall of the cavity is subsequently etched away during the etching process, so that most of the side wall is not protected by the insulating layer, causing the copper in the TSV to diffuse in the silicon, affecting the electrical performance of the wafer and even causing a short circuit in the TSV.

[0035] In order to solve the above problems, the embodiments of the present application provide a method for preparing a chip packaging structure. Figure 1 A flowchart of the chip packaging structure provided in the embodiment of the present application; Figure 2~Figure 7 for Figure 1 The steps of the preparation process are shown in Figure 2. Figure 1 As shown, the preparation method includes the following steps S1 to S5:

[0036] Step S1: Figure 2 As shown, a stacked first mask layer 11 and a second mask layer 12 are sequentially formed on the wafer 1, and along the direction Z, the thickness of the first mask layer 11 is less than that of the second mask layer 12. Since the TSV to be prepared is deep and wide, in order to ensure the final etching effect, the embodiment provided in the present application uses the first mask layer 11 and the second mask layer 12 of different materials together as a hard mask. Exemplarily, the material of the first mask layer 11 is Si3N4, and the material of the second mask layer 12 is SiO2. The wafer 1 can be a Si Interposer or a stacked silicon-based wafer. A dielectric film layer 10 is also formed between the first mask layer 11 and the wafer 1.

[0037] Step S2: Figure 3As shown, a conductive via 13 is formed. Exemplarily, the conductive via 13 is formed by etching. The conductive via 13 penetrates the second mask layer 12 and the first mask layer 11, and extends into the wafer 1. The conductive via 13 formed using the relevant process has a trumpet-shaped morphology at the top of the conductive via 13 along the direction Z. The conductive via 13 includes a first sub-via 14 located in the second mask layer 12. The first sub-via 14 includes a first opening 141 close to the wafer 1, and a second opening 142 away from the wafer 1. Due to the large thickness of the second mask layer 12, the area of ​​the second opening 142 of the first sub-via 14 is larger than the area of ​​the first opening 141, that is, the trumpet is completely located in the second mask layer 12.

[0038] Step S3: Figure 4 As shown, barrier and seed layer deposition (Barrier & Seed, B&S) and electrochemical plating (Electrochemical Plating, ECP) ​​processes are performed to form a conductive structure 15 in the conductive via 13. For example, the conductive structure 15 is copper (Cu), and then Figure 5 As shown, a Cu chemical mechanical polishing (CMP) process is performed to completely remove the copper on the surface of the wafer 1 . The conductive structure 15 includes a first portion 151 located in the first sub-via 14 .

[0039] Step S4: Figure 6 As shown, the second mask layer 12 is removed to expose the first portion 151 of the conductive structure 15 .

[0040] In some embodiments, the material of the first mask layer 11 includes Si3N4, and the material of the second mask layer 12 includes SiO2. A fluorine-containing gas and a hydrogen-containing gas are used to form a plasma, and an alcohol is used as a solvent for the plasma to obtain an etching gas. The etching gas is used to react with the second mask layer 12 to generate volatile byproducts, and the volatile byproducts are removed by heating to remove the second mask layer 12.

[0041] Figure 8 A schematic diagram of the principles of the etching process steps provided in an embodiment of the present application.

[0042] For example, Figure 8 As shown, a substrate a made of a silicon-based material is provided, on which a thicker silicon oxide layer b is disposed.

[0043] In the reaction stage, a remote plasma-assisted dry etching process is used, NF3 and H2 are used to form a plasma as the HF source, and CH3OH (methanol) is used as the solvent of the plasma to obtain an etching gas including HF ions. In order to minimize the F radicals generated when NF3 dissociates in the plasma (which will cause spontaneous etching of silicon-based materials), the H2 / NF3 gas is transported to the remote plasma area, and methanol is injected into the processing area outside the plasma discharge area. In addition, a double-layer grid is set between the discharge area and the processing area to block ions from the discharge area. Then, the etching gas containing HF ions is used to react with the part of the silicon oxide layer b away from the substrate a to generate a byproduct layer c, the component of the byproduct layer c is volatile (NH4)2SiF6.

[0044] In the removal stage, the side of the substrate a away from the silicon oxide layer b is placed on a heating tray d, and the temperature of the heating tray d is 150°C. The byproduct layer ((NH4)2SiF6) c can be removed by heating, thereby thinning the silicon oxide layer b. This is a cycle until the silicon oxide layer b of the desired thickness is obtained. In the embodiment provided in the present application, the above stages are repeated until the second mask layer 12 located at the "bell mouth" portion is completely removed.

[0045] The reaction equations involved in the above process are as follows:

[0046] 2HF+M (such as CH3OH)→HF- 2+MH +

[0047] For SiO2: Si-O + 2HF-2 → SiF4 (ads), SiF4 + 2NH3 + 2HF → (NH4)2SiF6ΔH = -256KJ / mol

[0048] For Si3N4: Si-N+ 2HF- 2+ MH + →SiF4(ads)+NH3(ads)+M→(NH4)2SiF6

[0049] ΔH=-33.2KJ / mol

[0050] From the above reaction enthalpy change, it can be seen that the reaction rate of SiO2 is much greater than that of Si3N4. Therefore, the embodiment provided in this application removes SiO2 by plasma active group attachment. Ordinary plasma etching has strong directionality, but the etching by plasma active group attachment is isotropic. Therefore, Figure 6 The second mask layer (SiO 2 ) 12 in the region between the first opening 141 and the second opening 142 can also be removed smoothly.

[0051] In some embodiments, the etching selectivity ratio of the second mask layer 12 to the first mask layer 11 is greater than 50, that is, the etching effect of the plasma on the second mask layer 12 is much greater than the etching effect of the plasma on the first mask layer 11, so as to achieve selective removal of the second mask layer 12.

[0052] For example, the etching characteristics of SiO2 can be measured according to the gas ratio, pressure, temperature and process time, and the etching selectivity of SiO2 to polysilicon can be compared. In addition, the etching mechanism can be studied by analyzing plasma, surface composition, etc., so as to obtain the result that the etching selectivity ratio of the second mask layer 12 to the first mask layer 11 is greater than 50. Figure 9~Figure 12 This is a comparative experimental data chart of various process parameters provided in the examples of this application.

[0053] like Fig. 9 As shown in the figure, in this control experiment, the process pressure is 200 mTorr, NF3:H2=1:3, the substrate temperature is 20°C, and the reaction time of each cycle is 20 minutes. Fig. 9 It can be seen that when the gas ratio of plasma (the sum of NF3 and H2) to CH3OH (Methanol) is in the range of 1:3 to 1:5, the etching selectivity of the second mask layer (SiO2) 12 to the first mask layer (Si3N4) 11 is greater than 50, and the expected etching effect can be achieved.

[0054] like Fig.10 As shown in the figure, in this control experiment, the process pressure is 200mTorr, the gas ratio of plasma (the sum of NF3 and H2) and CH3OH methanol is 1:1, the substrate temperature is 20°C, and the reaction time of each cycle is 20 minutes. Fig.10 It can be seen that when the gas ratio range of the sum of NF3 and H2 to CH3OH is 1:1, as the proportion of H2 in the mixed gas of NF3 and H2 increases, the etching selectivity ratio also continues to increase. When the gas ratio range of NF3 and H2 reaches 1:3, the etching selectivity ratio no longer increases significantly. Therefore, when the gas ratio range of NF3 and H2 is 1:3~1:5, the expected etching effect can be achieved.

[0055] like Fig.11 As shown, in this control experiment, the process pressure is 200mTorr, NF3:H2=1:3, the gas ratio of plasma (the sum of NF3 and H2) and CH3OH methanol is 1:3, and the reaction time of each cycle is 20 minutes. Fig.11It can be seen that when the process temperature ranges from 0 to 60° C., the etching selectivity ratio (Etch Selectivity) of the second mask layer (SiO2) 12 to the first mask layer (Si3N4) 11 is greater than 50, which can achieve the expected etching effect.

[0056] like Fig.12 As shown, in this control experiment, the process pressure is 200mTorr, NF3:H2=1:3, the gas ratio of plasma (the sum of NF3 and H2) and CH3OH methanol is 1:3, and the process temperature is 0°C. Fig.12 It can be seen that when the process time is 3min~20min, the etching selectivity ratio (EtchSelectivity) of the second mask layer (SiO2) 12 and the first mask layer (Si3N4) 11 is greater than 50, which can achieve the expected etching effect. Figure 9~Figure 12 As shown, when the pressure of the dry etching process is 200 mTorr, the expected etching effect can be achieved.

[0057] The processes used in the embodiments of this application are all common processes. The process parameters (recipe) of the entire TSV Loop do not put forward higher requirements and are not much different from the original recipe. The newly added remote plasma-assisted dry etching process also uses a common ICP machine, and it also belongs to the film layer etching of the planar structure, and does not involve the etching of the three-dimensional structure. The difficulty of recipe debugging is low. This solution is easy to implement in terms of both the machine and the recipe, and can be quickly put into mass production to complete the manufacture of high-verticality TSV through-holes.

[0058] Step S5: Figure 7 As shown, the first portion 151 located in the first sub-via 14 is removed to complete the fabrication of the TSV hole (Loop), so as to obtain a chip packaging structure 2 having a TSV hole with high top verticality.

[0059] In some embodiments, removing the first portion 151 of the conductive structure 15 includes grinding the first portion 151 of the conductive structure 15 using a chemical mechanical polishing process.

[0060] In some embodiments, since the surface of the first mask layer 11 away from the wafer 1 is damaged to a certain extent during the process of removing the second mask layer 12, resulting in a certain loss of the first mask layer 11, during the process of grinding the first portion 151 of the conductive structure 15, the surface of the first mask layer 11 away from the wafer 1 is also ground to a certain extent (overpolish), and the damaged portion of the first mask layer 11 is ground off to ensure the final flatness of the first mask layer 11.

[0061] The preparation method of the chip packaging structure 2 provided in the embodiment of the present application sequentially forms a stacked first mask layer 11 and a second mask layer 12 on a wafer 1, and then forms a conductive via 13. The conductive via 13 has a first sub-via 14 located in the second mask layer 12, and its area away from the wafer 1 is larger than the area of ​​the first opening 141 close to the wafer 1. It can be understood that only the first sub-via 14 located in the second mask layer 12 has a "funnel" morphology defect, and the conductive via 13 located in the first mask layer 11 is a normal via. Then, a conductive structure 15 is formed in the conductive via 13, and the second mask layer 12 is removed to expose the first portion 151 of the conductive structure 15 located in the first sub-via 14, and the first portion 151 is removed, that is, the conductive structure 15 with morphological defects in the first sub-via 14 is removed, and the conductive structure 15 located in the first mask layer 11 is retained. The above preparation method improves the morphological defects of the conductive structure 15, avoids TSV short-circuiting caused by the "bell mouth", and thus improves the electrical performance of the chip packaging structure 2 finally prepared.

[0062] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for preparing a chip packaging structure, characterized in that: include: sequentially forming a first mask layer and a second mask layer stacked on the wafer; forming a conductive via, the conductive via penetrating the second mask layer and the first mask layer and extending into the wafer; the conductive via comprises a first sub-via located in the second mask layer, the first sub-via comprises a first opening close to the wafer and a second opening away from the wafer, the area of ​​the second opening being larger than the area of ​​the first opening; forming a conductive structure in the conductive via, the conductive structure comprising a first portion located in the first sub-via; removing the second mask layer to expose the first portion of the conductive structure; The first portion of the conductive structure is removed.

2. The preparation method according to claim 1, characterized in that: The second mask layer is removed by using a remote plasma assisted dry etching process.

3. The preparation method according to claim 2, characterized in that: An etching selection ratio between the second mask layer and the first mask layer is greater than 50.

4. The preparation method according to claim 2, characterized in that: The material of the first mask layer includes Si3N4, and the material of the second mask layer includes SiO2; Using fluorine-containing gas and hydrogen-containing gas to form plasma, and using alcohol as a solvent for the plasma to obtain etching gas; The etching gas is reacted with the second mask layer to generate volatile by-products, and the volatile by-products are removed by heating to remove the second mask layer.

5. The preparation method according to claim 4, characterized in that: NF3 and H2 are used to form plasma, and CH3OH is used as a solvent of the plasma to obtain an etching gas; The etching gas is reacted with SiO2 to generate (NH4)2SiF6, and the (NH4)2SiF6 is removed by heating to remove the second mask layer.

6. The preparation method according to claim 5, characterized in that: The gas ratio of NF3 to H2 ranges from 1:3 to 1:

5.

7. The preparation method according to claim 5, characterized in that: The gas ratio of NF3 and H2 to CH3OH is in the range of 1:3~1:

5.

8. The preparation method according to claim 2, characterized in that: The pressure of the dry etching process is 200 mTorr, the process temperature ranges from 0 to 60° C., and the duration is 3 min to 20 min.

9. The preparation method according to claim 1, characterized in that: Removing the first portion of the conductive structure includes: The first portion of the conductive structure is ground using a chemical mechanical grinding process.

10. The preparation method according to claim 9, characterized in that: During the process of grinding the first portion of the conductive structure, the surface of the first mask layer away from the wafer is also ground.

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