Sensor pixel unit, signal processing device and electronic equipment

Abstract

The embodiment of the invention discloses a sensor pixel unit, a signal processing device and electronic equipment. The sensor pixel unit comprises a photodiode, a charge buffer module, a first output module and a second output module, the photodiode is used for receiving an optical signal in an exposure duration to generate photoelectric charges; the charge cache module is used for storing photoelectric charges generated by the photodiode when exposure duration is reached, and inputting the stored photoelectric charges into the first output module according to control of an external signal; the first output module is used for generating a first signal according to the photoelectric charge received from the charge buffer module and outputting the first signal; and the second output module is used for outputting a second signal in response to the condition that the photoelectric charge quantity generated in the photodiode reaches the exposure threshold. According to the embodiment of the invention, the dynamic range of the image sensor is widened on the premise that the number of the photodiodes is not increased.

Description

Technical Field

[0001] The present disclosure relates to the field of sensor technology, and in particular to a sensor pixel unit, a signal processing device and an electronic device. Background Art

[0002] Image sensors have been widely used in digital cameras, mobile phones, medical treatment, automobiles, drones, machine recognition and other fields. In particular, the rapid development of complementary metal oxide semiconductor (CMOS) image sensor technology has led to higher requirements for the output image quality of image sensors. CMOS image sensors can be divided into two categories based on the signal acquisition method: one method is to set the exposure time of the pixel and then measure the change in the voltage signal; the second method is to set the voltage change of the pixel and then measure the exposure time. This type of image sensor is called a pulse sequence image sensor. During the operation of the pixel, each reset of the pixel will bring random reset noise, and the transmission path of the pixel signal from the pixel readout to the column circuit will also introduce noise and errors. Summary of the invention

[0003] Embodiments of the present disclosure provide a sensor pixel unit, a signal processing device, and an electronic device.

[0004] In one aspect of an embodiment of the present disclosure, a sensor pixel unit is provided, comprising: a photodiode, a charge buffer module, a first output module and a second output module;

[0005] The photodiode is used to receive light signals during the exposure time to generate photoelectric charges;

[0006] The charge buffer module is used to store the photoelectric charge generated by the photodiode when the exposure time is reached, and input the stored photoelectric charge into the first output module according to the control of the row selection signal;

[0007] The first output module is used to generate and output a first signal according to the photoelectric charge received from the charge buffer module;

[0008] The second output module is used to output a second signal in response to the amount of photoelectric charge generated in the photodiode reaching an exposure threshold.

[0009] Optionally, the charge buffer module includes a first capacitor, a second capacitor, a first switch transistor and a second switch transistor;

[0010] The first capacitor is connected to the photodiode through the first switch transistor, and in response to the first switch transistor being turned on according to the control of the first switch signal, the first capacitor receives and stores the photoelectric charge;

[0011] The second capacitor is connected to the first capacitor through the second switch transistor, and in response to the second switch transistor being turned on according to the control of the second switch signal, the photoelectric charge stored in the first capacitor is read to the second capacitor.

[0012] Optionally, it further includes: a reset transistor;

[0013] The source terminal and the drain terminal of the reset transistor are respectively connected to the power supply signal and the second capacitor. When the reset transistor is turned on according to the reset signal received by the gate terminal, the photodiode is controlled to perform reset.

[0014] Optionally, the first output module includes: a source follower transistor and a readout transistor;

[0015] The source follower transistor has a source terminal connected to a power supply signal, a drain terminal connected to the readout transistor, and a gate terminal connected to the charge buffer module, and is used to follow the change in the photoelectric charge stored in the charge buffer module to obtain a first signal;

[0016] The drain terminal of the readout transistor is connected to the drain terminal of the source follower transistor, the source terminal serves as the first output terminal of the pixel unit, the gate terminal receives a row selection signal, and in response to the readout transistor being turned on according to the control of the row selection signal, the first signal is output through the first output terminal.

[0017] Optionally, the second output module includes a mode control transistor, a comparator and a pulse readout control circuit;

[0018] The mode control transistor is used to connect the photodiode and the comparator, and is turned on according to the control of the mode control signal;

[0019] The comparator is used to determine whether the photoelectric charge amount reaches the exposure threshold, and in response to the photoelectric charge amount reaching the exposure threshold, trigger the output signal of the comparator to perform flipping, and input the flipped output signal into the pulse readout control circuit;

[0020] The pulse readout control circuit sends a pulse request signal to the external arbitration module according to the inverted output signal, and outputs the second signal in response to a high-level enable signal fed back by the external arbitration module.

[0021] Optionally, the pulse readout control circuit includes: a first logic circuit, a second logic circuit and a third switch transistor;

[0022] The first logic circuit is used to receive the output signal of the comparator and the enable signal, and output a third signal to the third switch transistor and the second logic circuit to control whether the third switch transistor is turned on;

[0023] The source terminal of the third switch transistor is connected to the power supply signal, the drain terminal is used as the request output terminal, and the gate terminal receives the third signal; in response to the third signal being at a low level, the third switch transistor is turned on and outputs a high level pulse request signal through the request output terminal;

[0024] The second logic circuit is used to receive the third signal and the enable signal, and output the second signal in response to the enable signal being at a high level and the third signal being at a high level.

[0025] Optionally, the first logic circuit includes: a NOT gate, a first NAND gate, a second NAND gate and a third NAND gate;

[0026] The input end of the NOT gate receives the enabling signal, and the output end of the NOT gate is connected to the second input end of the second NAND gate;

[0027] The first input end of the first NAND gate receives the output signal of the comparator, the second input end of the first NAND gate is connected to the output end of the second NAND gate, and the output end of the first NAND gate is connected to the first input end of the second NAND gate and the second input end of the third NAND gate;

[0028] The first input terminal of the third NAND gate receives the output signal of the comparator, and the output terminal outputs the third signal.

[0029] Optionally, the second logic circuit includes: a fourth NAND gate, a fifth NAND gate and a fourth switch transistor;

[0030] The first input terminal of the fourth NAND gate receives the third signal, the second input terminal of the fourth NAND gate is connected to the output terminal of the fifth NAND gate, and the output terminal of the fourth NAND gate is connected to the first input terminal of the fifth NAND gate and the drain terminal of the fourth switch transistor;

[0031] The second input terminal of the fifth NAND gate receives the enabling signal;

[0032] The gate terminal of the fourth switch transistor receives the enable signal, and the source terminal of the fourth switch transistor serves as the output terminal of the second logic circuit. In response to the enable signal being at a high level, the second signal is output through the source terminal of the fourth switch transistor.

[0033] Optionally, the photodiode, the charge buffer module and the first output module are prepared on a first chip, and the second output module is prepared on a second chip; the first chip is arranged on an upper layer of the second chip, and the first chip and the second chip are copper interconnected.

[0034] Another aspect of the embodiments of the present disclosure provides a signal processing device, comprising: a pixel array composed of n columns and m rows of sensor pixel units according to any one of the above embodiments, a timed exposure circuit, a pulse coding circuit, and a dual-mode data fusion module; m and n are integers greater than 1 respectively;

[0035] The pixel array is used to output the first signal row by row according to the control of the timing exposure circuit;

[0036] The timing exposure circuit is used to control the sensor pixel units in the pixel array to output the first signal row by row according to an exposure period, and process the first signal into a first coded signal and then input it into the dual-mode data fusion module;

[0037] The pulse coding circuit is used to record and process the row address information, column address information and exposure time information of the sensor pixel unit that reaches the exposure threshold when the accumulated photoelectric charge in the sensor pixel unit reaches the exposure threshold during the exposure period, and input the processed pixel address code and pulse coding signal into the dual-mode data fusion module;

[0038] The dual-mode data fusion module is used to determine the image information corresponding to the pixel array based on the first coding signal, the pixel address coding and the pulse coding signal.

[0039] Optionally, the timed exposure circuit is arranged at a first position on the second chip, and the pulse encoding circuit and the dual-mode data fusion module are arranged at a second position on the second chip; and the distance between the first position and the second position is greater than a preset distance.

[0040] Optionally, the timed exposure circuit is arranged on a second chip, and the pulse encoding circuit and the dual-mode data fusion module are arranged on a third chip.

[0041] Optionally, the timed exposure circuit includes a row drive control module, a column readout module and a first encoding module;

[0042] The row drive control module is used to provide row selection signals, second switch signals and reset signals to the sensor pixel units in the pixel array row by row, and to provide the first switch signal and mode control signal to the pixel array;

[0043] The column readout module is used to read and process the first signal output row by row by the pixel array, and send the obtained fourth signal to the first encoding module;

[0044] The first encoding module is used to encode the fourth signal to obtain the first encoded signal.

[0045] Optionally, the pulse encoding circuit includes a row arbitration module, a column address encoder, a row address encoder and a second encoding module;

[0046] The row arbitration module receives the pulse request signal sent row by row by the sensor pixel unit in the pixel array, and feeds back the permission signal according to the priority corresponding to the sensor pixel unit, and the sensor pixel unit outputs the second signal according to the permission signal;

[0047] The column address encoder records and encodes the column address information of the sensor pixel unit that sends the second signal according to the received second signal to obtain a column address code;

[0048] The row address encoder records and encodes the row address information of the sensor pixel unit that receives the enable signal according to the enable signal sent by the row arbitration module to obtain the row address code, and records the time information of receiving the enable signal and sends it to the second encoding module;

[0049] The second encoding module is used to process the column address encoding and the row address encoding to obtain the pixel address encoding, and obtain the pulse encoding signal based on the time information.

[0050] Optionally, the dual-mode data fusion module caches the pixel address code and the pulse code signal into a cache space in response to the pulse code circuit outputting the pixel address code and the pulse code signal within one exposure period;

[0051] In response to the timing exposure circuit controlling the first row of sensor pixel units in the pixel array to output n first coded signals, k pulse coded signals corresponding to the first row of sensor pixel units are determined according to the row address information and the pixel address code corresponding to the n first coded signals; the first signal corresponding to the pixel address code is replaced by the k pulse coded signals, and a row of image information corresponding to the pixel array is determined based on the replaced pulse coded signals and the first coded signals that have not been replaced.

[0052] Optionally, the dual-mode data fusion module is further used to determine whether there is a sensor pixel unit that outputs the second signal in the first row of sensor pixels after the timing exposure circuit controls the first row of sensor pixel units in the pixel array to output n first coded signals; when there is a sensor pixel unit that outputs the second signal, replace the first coded signal corresponding to the sensor pixel unit with a pulse coded signal; and determine a row of image information corresponding to the pixel array based on the replaced pulse coded signal and the unreplaced first coded signal.

[0053] Another aspect of the embodiments of the present disclosure provides an electronic device, comprising: a processor, and a memory communicatively connected to the processor, and further comprising the sensor pixel unit described in any one of the above embodiments or the signal processing device described in any one of the above embodiments;

[0054] The memory stores computer-executable instructions;

[0055] The processor executes the computer-executable instructions stored in the memory to control the sensor pixel unit or the signal processing device.

[0056] Optionally, the electronic device is included in any one of the following: image data acquisition equipment, audio / video player, navigation equipment, entertainment equipment, communication equipment, roadside traffic facilities, equipment in motor vehicles, industrial inspection equipment, flight equipment, medical equipment, security equipment.

[0057] The sensor pixel unit, signal processing device and electronic device provided based on the above-mentioned embodiments of the present disclosure include: a photodiode, a charge buffer module, a first output module and a second output module; the photodiode is used to receive a light signal within the exposure time to generate a photoelectric charge; the charge buffer module is used to store the photoelectric charge generated by the photodiode when the exposure time is reached, and input the stored photoelectric charge into the first output module according to the control of an external signal; the first output module is used to generate and output a first signal according to the photoelectric charge received from the charge buffer module; the second output module is used to output a second signal in response to the amount of photoelectric charge generated in the photodiode reaching an exposure threshold. The sensor pixel unit provided in the embodiment of the present disclosure outputs a first signal through the first output module and outputs a second signal through the second output module, thereby combining pulse sequence imaging and global timed exposure imaging in one pixel unit, and broadening the dynamic range of the image sensor without increasing the number of photodiodes.

[0058] The technical solution of the present disclosure is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The accompanying drawings, which constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0060] The present disclosure may be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0061] Figure 1 is a schematic structural diagram of a sensor pixel unit provided by an exemplary embodiment of the present disclosure;

[0062] Figure 2 is a circuit diagram of a charge storage module in a sensor pixel unit provided by another exemplary embodiment of the present disclosure;

[0063] Figure 3 is a circuit diagram of a second output module in a sensor pixel unit provided by another exemplary embodiment of the present disclosure;

[0064] Figure 4 is a structural schematic diagram of a pulse readout control circuit in a sensor pixel unit provided by another exemplary embodiment of the present disclosure;

[0065] Figure 5 is a circuit diagram of a pulse readout control circuit in a sensor pixel unit provided by yet another exemplary embodiment of the present disclosure;

[0066] Figure 6 is a structural schematic diagram of a signal processing device provided by an exemplary embodiment of the present disclosure;

[0067] Figure 7 is a structural schematic diagram of a signal processing device provided by another exemplary embodiment of the present disclosure;

[0068] Figure 8 is a signal timing diagram corresponding to a signal processing device provided by an exemplary embodiment of the present disclosure;

[0069] Fig. 9 The figure is a schematic diagram of the structure of an application embodiment of the electronic device disclosed in the present invention. DETAILED DESCRIPTION

[0070] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless otherwise specifically stated.

[0071] Those skilled in the art can understand that the terms "first" and "second" in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and neither represent any specific technical meaning nor indicate the necessary logical order between them.

[0072] It should also be understood that in the embodiments of the present disclosure, “plurality” may refer to two or more than two, and “at least one” may refer to one, two, or more than two.

[0073] It should also be understood that any component, data or structure mentioned in the embodiments of the present disclosure can generally be understood as one or more, unless explicitly limited or otherwise indicated in the context.

[0074] In addition, the term "and / or" in the present disclosure is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present disclosure generally indicates that the associated objects before and after are in an "or" relationship.

[0075] It should also be understood that the description of the various embodiments in the present disclosure focuses on the differences between the various embodiments, and the same or similar aspects thereof can be referenced to each other, and for the sake of brevity, they will not be described one by one.

[0076] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0077] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the present disclosure, its application, or uses.

[0078] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0079] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0080] The embodiments of the present disclosure can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate with many other general or special computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, servers, etc. include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, large computer systems, and distributed cloud computing technology environments including any of the above systems, etc.

[0081] Electronic devices such as terminal devices, computer systems, servers, etc. can be described in the general context of computer system executable instructions (such as program modules) executed by computer systems. Generally, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0082] Conventional image sensors reflect the intensity of light by recording the cumulative value of photoelectric signals at a fixed time. The light intensity range between the maximum light intensity and the minimum light intensity that the sensor can distinguish is the dynamic range of the sensor. In the process of realizing the present disclosure, the inventors found that the main ways to broaden the dynamic range of image sensors include increasing the number of photodiodes to achieve separate photosensitization of strong and weak light; or by adjusting the exposure time, exposing weak light signals for a longer time and strong light signals for a shorter time; or adding multiple signal conversion readout channels to achieve different gains for strong and weak signals. These methods all require increasing the hardware cost to improve the dynamic range, and the improvement effect of the dynamic range is directly related to the hardware cost. For example, if the dynamic range is to be increased tenfold, the exposure time needs to be extended tenfold, or the photosensitive area needs to be increased tenfold, which results in a large hardware cost and a decrease in frame rate. In response to the above problems, the present disclosure provides a sensor pixel unit to achieve the goal of broadening the dynamic range of image sensors without increasing hardware.

[0083] Figure 1 is a schematic diagram of the structure of a sensor pixel unit provided by an exemplary embodiment of the present disclosure. Figure 1 As shown, the sensor pixel unit (hereinafter referred to as pixel unit) of this embodiment includes: a photodiode 11 , a charge buffer module 12 , a first output module 13 and a second output module 14 .

[0084] The photodiode 11 is used to receive light signals within the exposure time to generate photoelectric charges.

[0085] Optionally, the photodiode provided in this embodiment may be a pinned photodiode (PPD).

[0086] The charge buffer module 12 is used to store the photoelectric charge generated by the photodiode 11 when the exposure time is reached, and input the stored photoelectric charge to the first output module according to the control of the row selection signal RS.

[0087] In this embodiment, the charge buffer module is used to store the photoelectric charges that have not reached the exposure threshold within the exposure time. When the exposure time is reached, all the photoelectric charges accumulated within the exposure time are input into the first output module according to the control of the row selection signal RS to generate a first signal corresponding to the timed exposure.

[0088] The first output module 13 is used to generate and output a first signal according to the photoelectric charges received from the charge buffer module 12 .

[0089] In this embodiment, the first output module 13 implements the timed exposure output of the pixel unit, so as to better collect image information in a weak light environment.

[0090] The second output module 14 is configured to output a second signal in response to the amount of photoelectric charge generated in the photodiode reaching an exposure threshold.

[0091] This embodiment realizes quantitative exposure of the pixel unit through the second output module, and reflects the light intensity by recording the time when the accumulated photoelectric charge in the photodiode reaches the exposure threshold, which can accurately reflect the strong light information received by the pixel unit.

[0092] Therefore, the present application realizes through the first output module and the second output module that the same pixel unit can not only ensure the imaging performance of dark light, but also accurately reflect the strong light information received by the pixel unit, thereby broadening the dynamic range of the image sensor using the pixel unit of the embodiment of the present disclosure.

[0093] The sensor pixel unit provided in the above embodiment of the present disclosure includes: a photodiode, a charge buffer module, a first output module and a second output module; the photodiode is used to receive a light signal within an exposure time to generate a photoelectric charge; the charge buffer module is used to store the photoelectric charge generated by the photodiode when the exposure time is reached, and input the stored photoelectric charge into the first output module according to the control of an external signal; the first output module is used to generate and output a first signal according to the photoelectric charge received from the charge buffer module; the second output module is used to output a second signal in response to the amount of photoelectric charge generated in the photodiode reaching an exposure threshold. The sensor pixel unit provided in the embodiment of the present disclosure outputs a first signal through the first output module and outputs a second signal through the second output module, thereby combining pulse sequence imaging and global timed exposure imaging in one pixel unit, and broadening the dynamic range of the image sensor without increasing the number of photodiodes.

[0094] Figure 2 FIG. 1 is a circuit diagram of a charge storage module in a sensor pixel unit provided by another exemplary embodiment of the present disclosure. Figure 2As shown, the charge buffer module 12 includes a first capacitor 121 , a second capacitor 122 , a first switch transistor 123 and a second switch transistor 124 .

[0095] The first capacitor 121 is connected to the photodiode 11 through the first switch transistor 123. In response to the first switch transistor 123 being turned on according to the control of the first switch signal GS, the first capacitor 121 receives and stores the photoelectric charge. Optionally, when the first switch signal GS is at a high level, the first switch transistor 123 is turned on; when the first switch signal GS is at a low level, the first switch transistor 123 is turned off.

[0096] The second capacitor 122 is connected to the first capacitor 121 through the second switch transistor 124, and in response to the second switch transistor 124 being turned on according to the control of the second switch signal TX, the photoelectric charge stored in the first capacitor 121 is read to the second capacitor 122. Optionally, when the second switch signal TX is at a high level, the second switch transistor 124 is turned on; when the second switch signal TX is at a low level, the second switch transistor 124 is turned off.

[0097] In this embodiment, the first switching transistor 123 implements global exposure control. When performing global timed exposure, it is turned on according to the control of the first switching signal GS, and all photoelectric charges accumulated in the photodiode during the exposure period are transferred to the first capacitor 121 for storage. In addition, the timing of the first switching signal GS corresponding to all pixel units in the pixel array composed of the pixel units provided in this embodiment is unified, that is, when the exposure period is reached, a high-level first switching signal GS is provided to all pixel units in the pixel array, so that the photoelectric charges in all photodiodes in the pixel array are transferred to the corresponding first capacitor for storage. When outputting by row, a high-level signal is provided row by row according to the second switching signal TX, so that the pixel units in the pixel array output the first signal row by row.

[0098] like Figure 2 As shown, the pixel unit provided in this embodiment may further include: a reset transistor 15;

[0099] The source terminal and the drain terminal of the reset transistor 15 are connected to the power supply signal Vdd and the second capacitor 122 respectively. When the reset transistor 15 is turned on according to the reset signal received at the gate terminal, the photodiode 11 is controlled to be reset.

[0100] Optionally, when the reset signal RST is at a high level, the reset transistor 15 is turned on, and the pixel unit is in a reset stage. At this time, the first switch signal and the second switch signal simultaneously control the first switch transistor and the second switch transistor to be turned on, and the reset transistor, the first switch transistor and the second switch transistor jointly turn on the path between the photodiode and the power supply signal Vdd, so that all the photoelectric charges in the photodiode are transferred to the power supply end, thereby realizing the reset of the photodiode.

[0101] like Figure 2 As shown, the first output module 13 in the pixel unit provided in this embodiment includes: a source follower transistor 131 and a readout transistor 132 .

[0102] The source follower transistor 131 has a source terminal connected to the power signal Vdd, a drain terminal connected to the readout transistor 132 , and a gate terminal connected to the charge buffer module 12 , and is used to follow the change in the photoelectric charge stored in the charge buffer module 12 to obtain a first signal.

[0103] The drain terminal of the readout transistor 132 is connected to the drain terminal of the source follower transistor, the source terminal serves as the first output terminal of the pixel unit, the gate terminal receives the row selection signal, and in response to the readout transistor being turned on according to the control of the row selection signal, the first signal Vout is output through the first output terminal.

[0104] The functions, connections and implementations of the source follower transistor and the readout transistor in this embodiment are the same as those in the existing 3T pixel unit, and are not described in detail here.

[0105] Figure 3 FIG. 1 is a circuit diagram of a second output module in a sensor pixel unit provided by another exemplary embodiment of the present disclosure. Figure 3 As shown, the second output module 14 includes a mode control transistor 141 , a comparator 142 and a pulse readout control circuit 143 .

[0106] The mode control transistor 141 is used to connect the photodiode 11 and the comparator 142 , and is turned on according to the control of the mode control signal SS.

[0107] In this embodiment, the timing of the mode control signal SS always maintains a high level in the pulse imaging stage, so that the photoelectric charge accumulated by the photodiode can be output to the comparator 142 through the mode control transistor 141 at any time including the threshold value in the pulse imaging stage.

[0108] The comparator 142 is used to determine whether the photoelectric charge amount reaches the exposure threshold. In response to the photoelectric charge amount reaching the exposure threshold, the output signal of the comparator 142 is triggered to perform a flip, and the flipped output signal is input into the pulse readout control circuit.

[0109] The pulse readout control circuit 143 sends a pulse request signal to the external arbitration module according to the inverted output signal, and outputs a second signal in response to a high-level enable signal fed back by the external arbitration module.

[0110] Optionally, the source terminal of the mode control transistor 141 is connected to the photodiode, the drain terminal of the mode control transistor 141 is connected to the negative input terminal of the comparator 142, and the gate terminal of the mode control transistor 141 receives the mode control signal SS. The negative input terminal of the comparator 142 is connected to the drain terminal of the mode control transistor 141, and the positive input terminal of the comparator 142 receives the reference signal Vth. The signal output by the output terminal of the comparator 142 is determined according to the comparison result between the signal output by the photodiode through the mode control transistor and the reference signal. After the photodiode is reset, the output signal is the power supply voltage (high level). As the photoelectric charge accumulates, the output signal gradually decreases. When the exposure threshold is reached, the output signal is less than the reference signal Vth. Therefore, it can be seen that in this embodiment, when the photodiode is reset, the reference signal Vth (for example, set to 1 / 2 of the power supply signal) is less than the power supply signal. At this time, the signal at the positive input terminal of the comparator is less than the signal at the negative input terminal, and a low-level signal is output; when the accumulated photoelectric charge of the photodiode reaches the exposure threshold, the signal input to the negative input terminal of the comparator is less than the reference signal. At this time, the signal output by the comparator is flipped and a high-level signal is output.

[0111] Figure 4 FIG. 1 is a schematic diagram of a pulse readout control circuit in a sensor pixel unit provided by another exemplary embodiment of the present disclosure. Figure 4 As shown, the pulse readout control circuit 143 includes: a first logic circuit 41 , a second logic circuit 42 and a third switch transistor 43 .

[0112] The first logic circuit 41 is used for receiving the output signal COMP OUT of the comparator 142 and the enable signal ACK, and outputting the third signal Z to the third switch transistor 43 and the second logic circuit 42 to control whether the third switch transistor 43 is turned on.

[0113] In this embodiment, the first logic circuit outputs a high-level third signal Z when the output signal COMP OUT and the enable signal ACK are both low-level; in the pulse request stage, the output signal COMP OUT is high-level and the enable signal ACK is low-level, and outputs a low-level third signal Z (controls the third switch transistor 43 to be turned on and sends out a pulse request signal); in the request permission stage, the high-level enable signal ACK is received, and the output signal COMP OUT is also high-level, and the high-level third signal Z is output at this time; when the pulse readout control circuit 143 completes outputting the second signal, the output signal COMPOUT is high-level, the enable signal is low-level, and the third signal Z is high-level. That is, the embodiment of the present application implements the low-level signal only when the pulse readout control circuit 143 executes the pulse request stage through the first logic circuit 41, so that the third switch transistor 43 is turned on and sends out a pulse request signal.

[0114] The source terminal of the third switch transistor 43 is connected to the power signal VDD, the drain terminal serves as the request output terminal, and the gate terminal receives the third signal Z; in response to the third signal Z being at a low level, the third switch transistor 43 is turned on and outputs a high level pulse request signal REQ through the request output terminal.

[0115] The second logic circuit 42 is used for receiving the third signal Z and the enable signal ACK, and outputting the second signal Vspike in response to the enable signal being at a high level and the third signal being at a high level.

[0116] The second logic circuit 42 in this embodiment outputs the high-level second signal Vspike only when the third signal Z and the enable signal ACK are both at high levels.

[0117] Figure 5 FIG. 1 is a circuit diagram of a pulse readout control circuit in a sensor pixel unit provided by another exemplary embodiment of the present disclosure. Figure 5 As shown, the first logic circuit 41 in the pulse readout control circuit 143 includes a NOT gate 411 , a first NAND gate 412 , a second NAND gate 413 and a third NAND gate 414 .

[0118] An input terminal of the NOT gate 411 receives the enable signal ACK, and an output terminal of the NOT gate 411 is connected to a second input terminal of the second NAND gate 413 .

[0119] The first input terminal of the first NAND gate 412 receives the output signal COMP OUT of the comparator, the second input terminal of the first NAND gate 412 is connected to the output terminal of the second NAND gate 413, and the output terminal of the first NAND gate 412 is connected to the first input terminal of the second NAND gate 413 and the second input terminal of the third NAND gate 414.

[0120] Optionally, the output signal of the first NAND gate 412 may be recorded as Q1.

[0121] A first input terminal of the third NAND gate 414 receives the output signal COMP OUT of the comparator, and an output terminal thereof outputs the third signal Z.

[0122] like Figure 5 As shown, the second logic circuit 42 includes: a fourth NAND gate 421, a fifth NAND gate 422 and a fourth switch transistor 423;

[0123] The first input terminal of the fourth NAND gate 421 receives the third signal Z, the second input terminal of the fourth NAND gate 421 is connected to the output terminal of the fifth NAND gate 422, and the output terminal of the fourth NAND gate 421 is connected to the first input terminal of the fifth NAND gate 422 and the drain terminal of the fourth switch transistor 423.

[0124] Optionally, the output signal of the fourth NAND gate 421 may be recorded as Q2.

[0125] A second input terminal of the fifth NAND gate 422 receives the enable signal ACK.

[0126] The gate terminal of the fourth switch transistor 423 receives the enable signal ACK, and the source terminal of the fourth switch transistor 423 serves as the output terminal of the second logic circuit. In response to the enable signal ACK being at a high level, the second signal Vspike is output through the source terminal of the fourth switch transistor 423 .

[0127] COMP OUT ACK Q1 Z REQ Q2 Vspike Reset 0 0 1 1 0 0 0 Pulse Request 1 0 1 0 1 1 0 Request permission 1 1 0 1 0 1 1 Output end 1 0 0 1 0 0 0

[0128] Table 1

[0129] Table 1 shows the true value of the pulse readout control circuit at each stage during operation. First, after the pixel unit is reset, the voltage Vpd on the photodiode is a higher potential close to the power supply voltage VDD, the output signal COMPOUT of the comparator is low, and the requested permission signal ACK is also low. According to the circuit logic, the signal Q1 obtained by COMP OUT through a NAND gate is high, the obtained third signal Z is high, the third switch transistor is disconnected, and the pulse request signal REQ is low. When Vpd reaches the preset threshold during the exposure process, COMP OUT will flip to a high level. Before receiving the permission signal ACK, Q1 remains high, the third signal Z will be converted to a low level to turn on the third switch transistor, and the pulse request signal REQ becomes high, sending a high-level pulse request signal REQ to the peripheral circuit. At the same time, Q2 becomes high, and the second signal Vspike (pulse signal) can be output when waiting for the permission signal ACK to arrive. When the pulse request signal REQ is allowed, the enable signal ACK is converted to a high level, Q1 becomes a low level, the third signal Z becomes a high level, the third switch transistor is disconnected, and the pulse request signal REQ is no longer issued. The enable signal ACK controls the conduction of the fourth switch transistor, and the second signal Vspike is a high level. When the output is completed, the pulse request signal REQ is converted to a low level. Before the pixel is reset, the output signal COMP OUT will remain at a high level, thereby ensuring that Q1 remains at a low level and the third signal Z remains at a high level. The pixel unit will no longer issue a pulse request signal REQ before the next reset. Before the next pixel unit reset, Q2 will also remain at a low level, so that even if other pixel units in the same row output later, the output of this pixel unit will still be a low level, avoiding repeated output of pulse signals.

[0130] In some optional embodiments, the photodiode 11, the charge buffer module 12 and the first output module 13 are prepared on a first chip, and the second output module 14 is prepared on a second chip; the first chip is arranged on an upper layer of the second chip, and the first chip and the second chip are copper interconnected.

[0131] The mode control transistor 141 in the second output module 14 can also be prepared in the first chip. In this embodiment, the light-sensitive part in the pixel unit is prepared in the first chip of the upper layer, so as to meet the light-sensitive requirements of the pixel unit, and the chip integration is improved through the chip stacking technology, and the area occupied by the pixel array in the sensor is compressed.

[0132] Optionally, the pixel unit can be divided into two main parts: a photosensitive unit (including a photodiode 11, a charge buffer module 12, a first output module 13 and a mode control transistor 141) and a pulse generation and readout control unit (including a comparator and a pulse readout control circuit), wherein the photosensitive unit is prepared on a top wafer (top chip), and the pulse generation and readout unit is prepared on a bottom wafer (bottom chip), and the two wafers are stacked by a copper interconnect hybrid bonding process, so that two working modes can be realized on a limited pixel area.

[0133] Figure 6 FIG. 1 is a schematic diagram of a signal processing device provided by an exemplary embodiment of the present disclosure. Figure 6 As shown, the device provided in this embodiment includes: a pixel array 61 composed of n columns and m rows of sensor pixel units (hereinafter referred to as pixel units) provided in any of the above embodiments, a timed exposure circuit 62, a pulse coding circuit 63 and a dual-mode data fusion module 64. m and n are integers greater than 1 respectively.

[0134] The pixel array 61 is used to output the first signal row by row according to the control of the timing exposure circuit.

[0135] The structure of the pixel units included in the pixel array in this embodiment can refer to any of the above embodiments. Optionally, when the photosensitive unit and the pulse generation and readout control unit in the pixel unit are prepared on different wafers respectively, the pixel array is distributed on two wafers, and the photosensitive unit of each pixel unit in the pixel array is prepared on the upper wafer, and the pulse generation and readout control unit of each pixel unit in the pixel array is prepared on the lower wafer.

[0136] The timing exposure circuit 62 is used to control the sensor pixel units in the pixel array 61 to output the first signal row by row according to the exposure period, and process the first signal into a first coded signal and then output or input it to the dual-mode data fusion module 64.

[0137] In this embodiment, the timed exposure circuit receives n first signals output by the pixel units in the pixel array row by row according to the exposure period, and after encoding the n first signals read out each time, the first encoded signal can be output as image information obtained by the timed exposure, or the n first encoded signals can be input into the dual-mode data fusion module.

[0138] The pulse coding circuit 63 is used to record and process the row address information row addr, column address information coladdr and exposure time information timestamp of the sensor pixel unit that reaches the exposure threshold when the accumulated photoelectric charge in the sensor pixel unit reaches the exposure threshold during the exposure period, and output or input the processed pixel address code and pulse coding signal to the dual-mode data fusion module 64.

[0139] In this embodiment, the asynchronous reading of the pixel unit is realized by the pulse coding circuit, and the exposure time information indicates the time from the reset moment of the pixel unit to the moment when the photoelectric charge reaches the exposure threshold. The intensity of the light intensity can be indicated by the exposure time information. The stronger the light intensity, the shorter the exposure time, and the weaker the light intensity, the longer the exposure time. After obtaining the pulse coding signal and the pixel address coding, this embodiment can directly output it as an output signal, which can reflect the image information collected in a strong light environment. Alternatively, the pixel address coding and pulse coding signals are input into the dual-mode data fusion module.

[0140] The dual-mode data fusion module 64 is used to determine the image information of the corresponding pixel array based on the first coding signal, the pixel address coding and the pulse coding signal.

[0141] Optionally, the dual-mode data fusion module outputs the above image information through a chip digital signal interface provided on the chip.

[0142] In this embodiment, within one exposure cycle, pulse imaging data (generated by the pulse coding circuit) and global timed exposure data (generated by the timed exposure circuit) are generated successively. The pulse coding circuit and the timed exposure circuit can directly input the generated signals to the outside of the chip, or input the generated signals to the dual-mode data fusion module. The dual-mode data fusion module combines the signals output by the timed exposure circuit and the pulse coding circuit, so that on the basis of the global timed exposure data, the strong light information that can be more accurately expressed by the pulse data is integrated, and a high-dynamic image is synthesized for output. This embodiment retains two data output modes of independent and separate dual-mode data output and fused output. The amount of data output by the independent and separate dual-mode data is relatively large, and the amount of data output by the fused output is relatively small. It is a standard image output data format, and has better compatibility with subsequent data processing chips.

[0143] In some optional embodiments, the timing exposure circuit 62 is disposed at a first position on the second chip, and the pulse encoding circuit 63 and the dual-mode data fusion module 64 are disposed at a second position on the second chip.

[0144] In this embodiment, most of the circuits included in the timed exposure circuit 62 work in the analog voltage domain. The analog circuit has high requirements for signal accuracy. Therefore, in order to avoid the signal of the digital circuit module disturbing the analog circuit signal, the distance between the first position and the second position is greater than the preset distance; for example, the first position is the lower left corner of the second chip, and the second position is the upper right corner of the second chip. This ensures that the physical distance from the chip interface to the module circuit is reduced as much as possible, avoids crossing with the digital circuit, ensures the accuracy of the analog signal, and further ensures the imaging performance of the global timed exposure mode for dark light.

[0145] Optionally, the pulse generation and readout control unit in each pixel unit in the pixel array is prepared in the middle of the second chip, and the photosensitive unit in each pixel unit in the pixel array is prepared on the first chip. The scale of the array formed by the pulse generation and readout control unit is consistent with the scale of the photosensitive unit array. When the chips are stacked, the two arrays are located at the same horizontal position, and each photosensitive unit in the array and the pulse generation and readout control unit at the corresponding position are connected one by one through the inter-chip copper interconnection process. The first chip stack is set on the upper layer of the second chip. The chip integration is improved through chip stacking, and the area occupied by the chip is compressed, which can further reduce the size of the image sensor and make it more portable.

[0146] In some other optional embodiments, the timed exposure circuit 62 is disposed on the second chip, and the pulse encoding circuit 63 and the dual-mode data fusion module 64 are disposed on the third chip.

[0147] In order to prevent the signal of the digital circuit module from disturbing the analog circuit signal, this embodiment sets the timing exposure circuit, the pulse coding circuit and the dual-mode data fusion module on different chips. At this time, the pixel array is still set on the first chip and the second chip. By preparing the analog circuit and the digital circuit on different chips, the intersection of the analog circuit and the digital circuit is avoided, thereby ensuring the accuracy of the analog signal.

[0148] Figure 7 FIG. 1 is a schematic diagram of a signal processing device provided by another exemplary embodiment of the present disclosure. Figure 7 As shown, the timed exposure circuit 62 in the device provided in this embodiment includes a row drive control module 621 , a column readout module 622 and a first encoding module 623 .

[0149] The row driving control module 621 is used to provide row selection signals RS, second switch signals TX and reset signals RST to the sensor pixel units in the pixel array 61 row by row, and provide the first switch signal GS and mode control signal SS to the pixel array.

[0150] The column readout module 622 is used to read and process the first signal output row by row by the pixel array 61, and send the obtained fourth signal to the first encoding module.

[0151] The first encoding module 623 is used to encode the fourth signal to obtain a first encoded signal.

[0152] Optionally, the first coded signal may be a digital signal or a pulse signal, etc.

[0153] The photosensitive unit array in the pixel array in this embodiment is used to receive light signals and convert them into electrical signals. The control signals required are all provided by the row drive control module. These control signals may include but are not limited to: reset signal RST, second switch signal TX (to realize the control of charge transfer), first switch signal (to realize the control of global exposure) GS, mode control signal SS and row selection signal RS. In addition, since the timing exposure circuit is arranged in the lower chip (second chip), it is transmitted to the corresponding position on the first chip through the copper interconnection between chips (between the second chip and the first chip), wherein the first switch signal GS and mode control signal SS are global signals of the pixel array, and all rows are controlled by the same signal, while the row selection signal RS, the second switch signal TX and the reset signal RST are independent control signals for each row. A low dropout regulator (LDO) and a charge pump may also be deployed around the row drive control module 621. The main function of the low dropout linear regulator is to provide a stable and low-noise power supply signal for analog circuit modules such as the photosensitive unit array. The main function of the charge pump is to provide a voltage signal higher than the power supply voltage and a negative voltage signal lower than the ground. The high voltage signal is mainly used to improve the transfer efficiency of the photogenerated charge in the photosensitive unit, and the negative voltage signal is mainly used to suppress the leakage current in the photosensitive unit. The output signals of the low-voltage difference linear regulator and the charge pump are also connected to the photosensitive unit array through the inter-chip copper interconnection line. Since the low-voltage difference linear regulator and the charge pump are common structures in sensor devices in the prior art, their specific structures are not described in detail in the embodiments of this application.

[0154] In the global timed exposure mode, the first signal Vout generated by the photosensitive unit after the timed exposure will be output row by row under the control of the row drive control module. The selected Vout signal is first output to the bottom of the photosensitive unit array in the first chip, and then output to the column readout circuit module on the second chip through the copper interconnection line between the chips. The main function of the column readout circuit module is to convert the first signal Vout into a digital signal and output it to the first encoding module through the parallel-serial conversion circuit. A reference voltage and bias voltage generation module and a ramp voltage generation module are also deployed around the column readout circuit module. The reference voltage generation module mainly uses the principle of the bandgap reference to generate a number of voltage signals and current signals that are approximately independent of temperature for use by the bias voltage generation module and the ramp voltage generation module. Among them, the bandgap reference (Bandgap voltage reference) is a circuit for providing a stable reference voltage or current. It uses the characteristics of semiconductor materials and realizes a stable reference voltage output by designing a suitable circuit structure. Based on the characteristics of the bandgap reference, it is possible to provide a voltage signal and a current signal that are approximately independent of temperature.

[0155] The bias voltage generation module mainly uses the reference current signal to generate the column readout bias voltage for use by the column readout circuit module to ensure that the column readout signal is obtained under a fixed current bias. The ramp voltage generation module is mainly used to generate a signal voltage that increases linearly with a fixed slope over time within a fixed period. This signal voltage is required for realizing single-slope ADC analog-to-digital conversion. The above-mentioned row drive control module, low-dropout linear regulator, charge pump, reference voltage and bias voltage generation module, ramp voltage generation module, and the column readout circuit except the parallel-to-serial conversion circuit are all analog circuit modules working in the analog power supply voltage domain.

[0156] like Figure 7 As shown, the pulse encoding circuit 63 in the device provided in this embodiment includes a row arbitration module 631 , a column address encoder 632 , a row address encoder 633 and a second encoding module 634 .

[0157] The row arbitration module 631 receives the pulse request signals sent row by row by the sensor pixel units in the pixel array 61 and feeds back an enable signal according to the priority corresponding to the sensor pixel unit. The sensor pixel unit outputs a second signal according to the enable signal ACK.

[0158] The column address encoder 632 records and encodes the column address information of the sensor pixel unit that sends the second signal according to the received second signal to obtain the column address code col addr.

[0159] The row address encoder 633 records and encodes the row address information of the sensor pixel unit receiving the enable signal ACK according to the enable signal ACK sent by the row arbitration module 631, obtains the row address code row addr, records the time information timestamp of receiving the enable signal ACK and sends it to the second encoding module.

[0160] In this embodiment, the column address encoder can determine the column address corresponding to the pixel unit that reaches the exposure threshold during the exposure period, and the row address encoder can determine the row address corresponding to the pixel unit that reaches the exposure threshold during the exposure period. The specific pixel unit that reaches the exposure threshold can be located based on the row address and the column address, and the light intensity information of the corresponding position of the pixel unit is represented based on the exposure time information, thereby improving the intensity of the maximum light intensity that the sensor can distinguish and expanding the dynamic range of the sensor.

[0161] The second encoding module 634 is used to process the column address encoding and the row address encoding to obtain the pixel address encoding, and obtain the pulse encoding signal based on the time information.

[0162] In this embodiment, the pulse generation and readout control unit in the pixel unit is used to detect the pixel exposure signal in real time during the pulse imaging stage. When it is detected that the exposure signal of the corresponding pixel unit reaches the set threshold, the pulse generation and readout control unit will send a pulse request signal REQ to the row arbitration module. After receiving the pulse request signal REQ, the row arbitration module will determine which row's pulse request signal REQ has the highest current priority (the priority is determined based on the time sequence, and the pulse request signal REQ sent first has a higher priority), and then send an enable signal ACK to the row of pixel units with the highest priority. The row arbitration module will determine the priority according to the time sequence of the pulse request signal REQ. In most cases, only one row of pixel units in the pixel array will output the pulse request signal REQ within a certain period of time. In this case, the only row that outputs the pulse request signal REQ has the highest current priority. If more than one row of pixel units in the pixel array outputs the pulse request signal REQ within a certain period of time, the row with the earliest output time has the highest priority. After the reading of the row with the highest priority is completed, the row with the second earliest output time has the highest priority, and so on. When a row of pixel units sends a pulse request signal REQ and receives a permission signal, all pixels in the row will output their second signal Vspike to the column cache. Some of these pixel units have reached the exposure threshold, and the second signal Vspike output by these pixel units is high level; some pixel units have not reached the exposure threshold, and the second signal Vspike output by these pixel units is low level.

[0163] After the second signal Vspike is input to the column cache, the column address encoder detects which column's second signal Vspike is at a high level, and encodes the address information of these columns and outputs it to the second encoding module. At the same time, the row address encoder will also encode the row address that currently receives the permission signal and output it to the second encoding module. The clock will record the moment when the row arbitration module sends the permission signal and output it to the second encoding module. The second encoding module can accurately reflect the strong light information received by the pixel array based on the timestamp of the pulse, the row address code and the column address code.

[0164] In some optional embodiments, the dual-mode data fusion module 64 caches the pixel address code and the pulse code signal into the cache space in response to the pulse coding circuit 63 outputting the pixel address code and the pulse code signal within one exposure period.

[0165] In response to the timing exposure circuit 62 controlling the first row of sensor pixel units in the pixel array to output n first coded signals, the corresponding column address information is determined according to the row address information and the pixel address code corresponding to the n first coded signals, the corresponding pulse coded signal is determined based on the column address information and the row address information, and k pulse coded signals corresponding to the first row of sensor pixel units are determined; the first signal corresponding to the pixel address code is replaced by the k pulse coded signals, and based on the replaced pulse coded signal and the unreplaced first coded signal, a row of image information corresponding to the pixel array is determined.

[0166] In this embodiment, when the light intensity at the position corresponding to some pixel units is strong, a pulse coding signal is generated by a pulse coding circuit, and the pixel address code corresponding to the pixel unit is stored. After the exposure cycle is reached, all pixel units in the pixel array output a first signal. The first signal is a timed exposure, which can collect more details in a weak light environment, but cannot correctly express the light intensity signal for parts with strong light intensity. Therefore, this embodiment replaces the first signal corresponding to the pixel address code with a pulse coding signal, so that the dynamic range of the obtained image information is larger, and it has better effects for both weak light and strong light. After completing the exposure of the two modes within one exposure cycle, the sensor provided in the embodiment of the present application performs fusion coding processing on the dual-mode data, thereby realizing single-frame high dynamic range imaging.

[0167] In some other optional embodiments, the dual-mode data fusion module 64 is also used to determine whether there are sensor pixel units that output the second signal in the first row of sensor pixels after the timing exposure circuit controls the first row of sensor pixel units in the pixel array to output n first coded signals; when there are sensor pixel units that output the second signal, replace the first coded signal corresponding to the sensor pixel unit with a pulse coded signal; and determine a row of image information corresponding to the pixel array based on the replaced pulse coded signal and the unreplaced first coded signal.

[0168] In this embodiment, first, in the pulse imaging stage, the second encoding module encodes and caches the pulse signal (corresponding to the second signal) generated in real time, and records the row and column address and time information of each pulse signal. In the pulse imaging stage, the timing exposure circuit and the dual-mode data fusion module are in standby state. After the pulse imaging stage and the global exposure is completed, the global exposure signal (corresponding to the first signal) of the pixel unit is read out row by row. Each row of global exposure signal is first input to the first encoding module after analog-to-digital conversion (ADC). The first encoding module will determine whether there is an overexposed signal in this row of signals, that is, the signal code value reaches the upper limit (for example, 0-255 represents the image brightness, and the brightness greater than 255 cannot be represented by the first signal). If there is an overexposed signal, the pulse encoding circuit is queried to see whether the address of the pixel unit corresponding to the overexposed signal has generated a pulse signal in the pulse imaging stage of the same frame exposure cycle. If a pulse signal is queried, the dual-mode data fusion module calculates the actual light intensity information based on the pulse signal and replaces it with the original overexposed first signal. After the replacement is completed, the dual-mode data fusion module outputs a row of fused and encoded signals. If there is no overexposure signal in the row signal, the global exposure signal can be directly used to express the light intensity information and output. After the processing and output of one row of signals are completed, the next row of signals is processed in the same way, and the cycle is repeated. Together with the column readout circuit of the chip, a pipelined signal output form is formed, and there is no need to integrate a cache unit for the entire frame of data on the chip, which improves the system efficiency of the chip.

[0169] Figure 8 is a signal timing diagram corresponding to a signal processing device provided by an exemplary embodiment of the present disclosure. Figure 8 As shown, an exposure cycle of the signal device provided in this embodiment is mainly divided into five working stages: a first reset stage, a pulse imaging stage, a second reset stage, a global timing exposure stage and a global exposure signal line-by-line readout stage.

[0170] In the first reset stage, all reset signals RST in the pixel array are all high level, and all second switch signals TX are all high level, the first switch signal GS is high level, and the mode control signal SS is high level. At this time, the reset transistor, the first switch transistor and the second switch transistor are all turned on, and the reset signal can be connected to the photodiode through these transistors to reset the photodiode. After the reset is completed, the reset signal RST, the second switch signal TX and the first switch signal GS are all changed to low level, and the mode control signal SS remains high level (maintains high level in the pulse imaging stage), and enters the pulse imaging stage. At this time, the photodiode of the photosensitive unit is only connected to its corresponding comparator. During the exposure process, the voltage on the photodiode gradually decreases with the accumulation of photoelectric charge, and when it drops to the preset threshold, the comparator is triggered to flip. According to the description of the logic function of the pulse readout control circuit in the above embodiment, it can be seen that the pixel unit of the trigger pulse will first send a pulse request signal REQ to the row arbitration module, and the row arbitration module will send an enable signal ACK to the row after confirming the request. At the same time, the row and column address encoder of the chip will record the row address information of the pixel unit of the trigger pulse, and the clock in the chip will record the moment of the trigger pulse. Figure 8The REQ, ACK, timestamp, rowaddr, and col addr shown in are only examples of a pulse trigger. In the pulse imaging stage, depending on the actual light intensity information, the pixel units at different positions will trigger pulses at different times, and these pulse information are output and recorded according to the above logic. After the pulse imaging stage lasts for a period of time, the mode control signal SS drops to a low level, and the pulse imaging stage ends (for example, at a frame rate of 60 frames per second, the duration of the pulse imaging stage can be set to 1 millisecond), and then enters the second reset stage. All reset signals RST in the pixel array are high, and all second switch signals TX are high, all row selection signals RS are high, and the first switch signal GS is high. The photodiode is reset to clear the photoelectric charge accumulated on the photodiode during the pulse imaging stage. After the reset is completed, the reset signal RST, the second switch signal TX, the row selection signal RS, and the first switch signal GS all become low levels, and all pixel units simultaneously enter the global timed exposure stage. During the exposure time of the global exposure, the photodiode continues to collect photogenerated charges. After the global exposure time is reached, the exposure signal is output row by row. First, the first switch signal GS becomes high, and the photoelectric charges collected by all pixel units during the exposure time are transferred to the first capacitor. Then, the pixel signals are correlated double sampling row by row. In the process of correlated double sampling, for each row of pixel units, the reset signal RST and the row selection signal RS of the pixel unit of the row are first started, the second capacitor is reset, and its reset signal is read out to the timing exposure circuit (column readout module), and then the reset signal of the pixel unit of the row is controlled to be low, and the second switch signal TX of the pixel unit of the row is started, and the photoelectric charges collected during exposure are transferred from the first capacitor to the second capacitor, and then the voltage signal converted from the photoelectric charges in the second capacitor is read out to the timing exposure circuit (column readout module). In the column readout module, the reset signal and the voltage signal obtained by exposure are first differentially operated to suppress the reset noise and the noise introduced in the column readout module, and then the column readout module performs analog-to-digital conversion on the differential result, and outputs the analog-to-digital conversion result of each row row by row (RnCm in the figure represents the analog-to-digital conversion result of the global exposure signal of the nth row and the mth column).

[0171] Optionally, after completing the exposure of the two modes within one exposure cycle, the signal processing device provided in the present application performs fusion encoding processing on the encoded signals output by the two modes through a dual-mode data fusion module, thereby realizing single-frame high dynamic range imaging.

[0172] The signal processing device provided in this embodiment realizes imaging processing with high dynamic range, global exposure and no motion blur. In the global timed exposure stage, all pixel units in the pixel array start exposure and end exposure at the same time, and all pixel units are exposed for the same length of time. After exposure, the exposure signal is converted into digital form by the column readout module row by row in a certain order. In the pulse imaging stage, all pixel units in the pixel array start exposure at the same time, and any pixel unit will send a pulse request signal to the row arbitration module when the exposure reaches a preset threshold, and output the second signal after receiving the permission signal fed back by the row arbitration module. The peripheral circuit (pulse encoding circuit) records the moment of the pulse request signal output by the pixel unit, and determines the address of the pixel unit generating the pulse according to the pulse request signal output by the pixel unit and the second signal. In the pulse imaging stage, the earlier the moment when the pixel unit outputs the pulse request signal, the stronger the light intensity received by the pixel unit. The pulse imaging stage is set with a maximum exposure time (the maximum exposure time can be determined according to the maximum light intensity that can be represented by the first signal output by the timed exposure circuit, and the maximum exposure time corresponds to the maximum light intensity). When the maximum exposure time is reached, the pulse imaging stage ends. Therefore, in the pulse imaging stage, only some pixel units that receive stronger light will trigger pulse output. In the signal processing device provided in this embodiment, the global timing exposure signal can accurately characterize the weaker dark light signal, while the pulse signal can quickly and accurately express the stronger strong light signal, thereby achieving high dynamic range imaging.

[0173] In addition, an embodiment of the present disclosure further provides an electronic device, including:

[0174] A processor, and a memory communicatively connected to the processor, further comprising the sensor pixel unit described in any one of the above embodiments or the signal processing device described in the above embodiments;

[0175] The memory stores computer-executable instructions;

[0176] The processor executes the computer-executable instructions stored in the memory to control the sensor pixel unit or the signal processing device.

[0177] The electronic device provided by the present disclosure can be included in any of the following: image data acquisition equipment, audio / video player, navigation equipment, entertainment equipment, communication equipment, roadside traffic facilities, equipment in motor vehicles, industrial inspection equipment, flight equipment, medical equipment, security equipment, etc.

[0178] The electronic device provided by the present disclosure can be applied to any of the following: image data acquisition equipment, audio / video players, navigation equipment, entertainment equipment, communication equipment, roadside traffic facilities, equipment in motor vehicles, industrial inspection equipment, flight equipment, medical equipment, security equipment, etc.

[0179] Fig. 9 This is a schematic diagram of the structure of an application embodiment of the electronic device disclosed in the present invention. Fig. 9 The electronic device according to the embodiment of the present disclosure is described. The electronic device may be any one or both of the first device and the second device, or a stand-alone device independent of them, and the stand-alone device may communicate with the first device and the second device to receive the collected input signals from them.

[0180] like Fig. 9 As shown, the electronic device includes one or more processors and memory.

[0181] The processor may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0182] The memory may store one or more computer program products, and the memory may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, a random access memory (RAM) and / or a cache memory (cache), etc. The non-volatile memory may include, for example, a read-only memory (ROM), a hard disk, a flash memory, etc. One or more computer program products may be stored on the computer-readable storage medium, and the processor may run the computer program product to implement the sensor pixel unit or signal processing device of each embodiment of the present disclosure described above and / or other desired functions.

[0183] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0184] In addition, the input device may also include, for example, a keyboard, a mouse, and the like.

[0185] The output device can output various information to the outside, including determined distance information, direction information, etc. The output device can include, for example, a display, a speaker, a printer, a communication network and a remote output device connected thereto, and the like.

[0186] Of course, to simplify, Fig. 9Only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device may further include any other appropriate components.

[0187] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the sensor pixel unit or signal processing device according to various embodiments of the present disclosure described in the above part of this specification.

[0188] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0189] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the sensor pixel unit or signal processing device according to various embodiments of the present disclosure described in the above part of this specification.

[0190] The computer readable storage medium can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0191] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0192] Each embodiment in this specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0193] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0194] The method and apparatus of the present disclosure may be implemented in many ways. For example, the method and apparatus of the present disclosure may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure may also be implemented as a program recorded in a recording medium, which includes machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

[0195] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0196] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0197] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A sensor pixel unit, characterized in that: include: A photodiode, a charge buffer module, a first output module and a second output module; The photodiode is used to receive light signals during the exposure time to generate photoelectric charges; The charge buffer module is used to store the photoelectric charge generated by the photodiode when the exposure time is reached, and input the stored photoelectric charge into the first output module according to the control of the row selection signal; The first output module is used to generate and output a first signal according to the photoelectric charge received from the charge buffer module; The second output module is used to output a second signal in response to the amount of photoelectric charge generated in the photodiode reaching an exposure threshold.

2. The pixel unit according to claim 1, characterized in that: The charge buffer module includes a first capacitor, a second capacitor, a first switch transistor and a second switch transistor; The first capacitor is connected to the photodiode through the first switch transistor, and in response to the first switch transistor being turned on according to the control of the first switch signal, the first capacitor receives and stores the photoelectric charge; The second capacitor is connected to the first capacitor through the second switch transistor, and in response to the second switch transistor being turned on according to the control of the second switch signal, the photoelectric charge stored in the first capacitor is read to the second capacitor.

3. The pixel unit according to claim 2, characterized in that: Also includes: Reset transistor; The source terminal and the drain terminal of the reset transistor are respectively connected to the power supply signal and the second capacitor. When the reset transistor is turned on according to the reset signal received by the gate terminal, the photodiode is controlled to perform reset.

4. The pixel unit according to any one of claims 1 to 3, characterized in that: The first output module includes: a source follower transistor and a readout transistor; The source follower transistor has a source terminal connected to a power supply signal, a drain terminal connected to the readout transistor, and a gate terminal connected to the charge buffer module, and is used to follow the change in the photoelectric charge stored in the charge buffer module to obtain a first signal; The drain terminal of the readout transistor is connected to the drain terminal of the source follower transistor, the source terminal serves as the first output terminal of the pixel unit, the gate terminal receives a row selection signal, and in response to the readout transistor being turned on according to the control of the row selection signal, the first signal is output through the first output terminal.

5. The pixel unit according to any one of claims 1 to 4, characterized in that: The second output module includes a mode control transistor, a comparator and a pulse readout control circuit; The mode control transistor is used to connect the photodiode and the comparator, and is turned on according to the control of the mode control signal; The comparator is used to determine whether the photoelectric charge amount reaches the exposure threshold, and in response to the photoelectric charge amount reaching the exposure threshold, trigger the output signal of the comparator to perform flipping, and input the flipped output signal into the pulse readout control circuit; The pulse readout control circuit sends a pulse request signal to the external arbitration module according to the inverted output signal, and outputs the second signal in response to a high-level enable signal fed back by the external arbitration module.

6. The pixel unit according to claim 5, characterized in that: The pulse readout control circuit includes: a first logic circuit, a second logic circuit and a third switch transistor; The first logic circuit is used to receive the output signal of the comparator and the enable signal, and output a third signal to the third switch transistor and the second logic circuit to control whether the third switch transistor is turned on; The source terminal of the third switch transistor is connected to the power supply signal, the drain terminal is used as the request output terminal, and the gate terminal receives the third signal; in response to the third signal being at a low level, the third switch transistor is turned on and outputs a high level pulse request signal through the request output terminal; The second logic circuit is used to receive the third signal and the enable signal, and output the second signal in response to the enable signal being at a high level and the third signal being at a high level.

7. The pixel unit according to claim 6, characterized in that: The first logic circuit includes: a NOT gate, a first NAND gate, a second NAND gate and a third NAND gate; The input end of the NOT gate receives the enabling signal, and the output end of the NOT gate is connected to the second input end of the second NAND gate; The first input end of the first NAND gate receives the output signal of the comparator, the second input end of the first NAND gate is connected to the output end of the second NAND gate, and the output end of the first NAND gate is connected to the first input end of the second NAND gate and the second input end of the third NAND gate; The first input terminal of the third NAND gate receives the output signal of the comparator, and the output terminal outputs the third signal.

8. The pixel unit according to claim 6 or 7, characterized in that: The second logic circuit includes: a fourth NAND gate, a fifth NAND gate and a fourth switch transistor; The first input terminal of the fourth NAND gate receives the third signal, the second input terminal of the fourth NAND gate is connected to the output terminal of the fifth NAND gate, and the output terminal of the fourth NAND gate is connected to the first input terminal of the fifth NAND gate and the drain terminal of the fourth switch transistor; The second input terminal of the fifth NAND gate receives the enabling signal; The gate terminal of the fourth switch transistor receives the enable signal, and the source terminal of the fourth switch transistor serves as the output terminal of the second logic circuit. In response to the enable signal being at a high level, the second signal is output through the source terminal of the fourth switch transistor.

9. The pixel unit according to any one of claims 1 to 8, characterized in that: The photodiode, the charge buffer module and the first output module are prepared on a first chip, and the second output module is prepared on a second chip; the first chip is arranged on an upper layer of the second chip, and the first chip and the second chip are copper interconnected.

10. A signal processing device, characterized in that: include: A pixel array consisting of n columns and m rows of sensor pixel units according to any one of claims 1 to 9, a timed exposure circuit, a pulse coding circuit, and a dual-mode data fusion module; m and n are integers greater than 1 respectively; The pixel array is used to output the first signal row by row according to the control of the timing exposure circuit; The timing exposure circuit is used to control the sensor pixel units in the pixel array to output the first signal row by row according to an exposure period, and process the first signal into a first coded signal and then input it into the dual-mode data fusion module; The pulse coding circuit is used to record and process the row address information, column address information and exposure time information of the sensor pixel unit that reaches the exposure threshold when the accumulated photoelectric charge in the sensor pixel unit reaches the exposure threshold during the exposure period, and input the processed pixel address code and pulse coding signal into the dual-mode data fusion module; The dual-mode data fusion module is used to determine the image information corresponding to the pixel array based on the first coding signal, the pixel address coding and the pulse coding signal.

11. The device according to claim 10, characterized in that The timed exposure circuit includes a row drive control module, a column readout module and a first encoding module; The row drive control module is used to provide row selection signals, second switch signals and reset signals to the sensor pixel units in the pixel array row by row, and to provide the first switch signal and mode control signal to the pixel array; The column readout module is used to read and process the first signal output row by row by the pixel array, and send the obtained fourth signal to the first encoding module; The first encoding module is used to encode the fourth signal to obtain the first encoded signal.

12. The device according to any one of claims 10-11, characterized in that: The pulse encoding circuit includes a row arbitration module, a column address encoder, a row address encoder and a second encoding module; The row arbitration module receives the pulse request signal sent row by row by the sensor pixel unit in the pixel array, and feeds back the permission signal according to the priority corresponding to the sensor pixel unit, and the sensor pixel unit outputs the second signal according to the permission signal; The column address encoder records and encodes the column address information of the sensor pixel unit that sends the second signal according to the received second signal to obtain a column address code; The row address encoder records and encodes the row address information of the sensor pixel unit that receives the enable signal according to the enable signal sent by the row arbitration module to obtain the row address code, and records the time information of receiving the enable signal and sends it to the second encoding module; The second encoding module is used to process the column address encoding and the row address encoding to obtain the pixel address encoding, and obtain the pulse encoding signal based on the time information.

13. The device according to any one of claims 10 to 12, characterized in that: The dual-mode data fusion module caches the pixel address code and the pulse code signal in a cache space in response to the pulse code circuit outputting the pixel address code and the pulse code signal within one exposure cycle; In response to the timing exposure circuit controlling the first row of sensor pixel units in the pixel array to output n first coded signals, k pulse coded signals corresponding to the first row of sensor pixel units are determined according to the row address information and the pixel address code corresponding to the n first coded signals; the first signal corresponding to the pixel address code is replaced by the k pulse coded signals, and a row of image information corresponding to the pixel array is determined based on the replaced pulse coded signals and the first coded signals that have not been replaced.

14. An electronic device, characterized in that: The method comprises: a processor, and a memory connected to the processor in communication, and further comprises the sensor pixel unit according to any one of claims 1 to 9 or the signal processing device according to any one of claims 10 to 13; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to control the sensor pixel unit or the signal processing device.

15. The device according to claim 14, characterized in that The electronic device is included in any of the following: image data acquisition equipment, audio / video player, navigation equipment, entertainment equipment, communication equipment, roadside traffic facilities, equipment in motor vehicles, industrial testing equipment, flight equipment, medical equipment, and security equipment.

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