Semiconductor structure, manufacturing method thereof and memory

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a memory. The semiconductor structure comprises a lower group of conducting layers and an upper group of conducting layers located on the lower group of conducting layers, the two groups of conducting layers have the same number of layers, and each conducting layer is provided with a common connection area and a storage unit area located on at least one side of the common connection area; the through holes are formed in the common connection area and are arranged at intervals in the extension direction of the common connection area, the through holes penetrate through the conductive layers, and the number of the through holes is equal to the number of the conductive layers of the lower group; the conductive columns are arranged in the through holes in a one-to-one correspondence mode, each conductive column comprises a lower conductive section and an upper conductive section which are separated by an insulating section, the lower conductive sections are electrically connected with the lower group of conductive layers in a one-to-one correspondence mode, and the upper conductive sections are electrically connected with the upper group of conductive layers in a one-to-one correspondence mode. According to the invention, the common bit line or the common word line can be connected to devices below and above the memory cell array at the same time.

Description

Technical Field

[0001] The present application relates to but is not limited to semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof, and a memory. Background Art

[0002] After the three-dimensional memory increases the storage density through multi-layer stacking, the number of sense amplifiers (SA) and sub-word line drivers (SWD) in the peripheral circuit will also increase accordingly. At present, in the common bit line storage device structure, a large number of SAs need to be set on the bonding chip. However, as the number of three-dimensional stacking layers increases, the number of SAs will also increase, which puts higher requirements on the placement and integration of SAs and SWDs on the bonding chip. Summary of the invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of this application.

[0004] In one aspect, an exemplary embodiment of the present application provides a semiconductor structure, comprising:

[0005] a lower set of conductive layers, comprising a plurality of conductive layers stacked vertically in an interspaced relationship;

[0006] An upper conductive layer group, which is located above the lower conductive layer group and includes a plurality of conductive layers stacked vertically and spaced apart from each other, the upper conductive layer group and the lower conductive layer group have the same number of layers, and each conductive layer has a common connection area and a storage cell area located at least on one side of the common connection area;

[0007] A plurality of through holes are arranged in the common connection area and spaced apart along the extension direction of the common connection area, the through holes penetrate the upper conductive layer and the lower conductive layer, and the number of the through holes is equal to the number of layers of the lower conductive layer;

[0008] A plurality of conductive pillars are disposed in each of the through holes in a one-to-one manner, each conductive pillar comprises a lower conductive segment and an upper conductive segment separated by an insulating segment, each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers in a one-to-one manner, and each of the upper conductive segments is electrically connected to each of the conductive layers in the upper group of conductive layers in a one-to-one manner.

[0009] In an exemplary embodiment, it also includes a plurality of lower insulating rings and a plurality of upper insulating rings, each of the lower insulating rings is arranged in a one-to-one correspondence in each of the through holes and surrounds the corresponding lower conductive segment, and the height of each of the lower insulating rings is less than the height of the conductive layer electrically connected to the corresponding lower conductive segment and is greater than the height of the next conductive layer adjacent to the conductive layer electrically connected to the corresponding lower conductive segment; each of the upper insulating rings is arranged in a one-to-one correspondence in each of the through holes and surrounds the corresponding upper conductive segment, and one end of each of the upper insulating rings close to the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer.

[0010] In an exemplary embodiment, along the extension direction of the common connection area, the height of the lower conductive segment in each of the through holes gradually increases, while the height of the upper conductive segment gradually decreases; or, the height of the lower conductive segment in each of the through holes gradually decreases, while the height of the upper conductive segment gradually increases.

[0011] In an exemplary embodiment, along the extension direction of the common connection area, the distances between adjacent through holes are the same.

[0012] In another aspect, an exemplary embodiment of the present application provides a memory, comprising:

[0013] a substrate on which a plurality of first devices are disposed;

[0014] a lower conductive layer group located on the substrate and comprising a plurality of conductive layers stacked vertically in an interspaced relationship;

[0015] an upper conductive layer group, which is located above the lower conductive layer group and includes a plurality of conductive layers stacked vertically and spaced apart from each other, wherein the upper conductive layer group and the lower conductive layer group have the same number of conductive layers, and each conductive layer has a common connection area and a storage cell area located at least on one side of the common connection area;

[0016] A binding chip, which is located on the upper conductive layer and is provided with a plurality of second devices;

[0017] A plurality of through holes, which are arranged in the common connection area and spaced apart along the extension direction of the common connection area, the through holes penetrate the plurality of conductive layers, and the number of the through holes is equal to the number of layers of the lower group of conductive layers;

[0018] A plurality of conductive pillars are disposed in each of the through holes in a one-to-one manner, each conductive pillar comprising a lower conductive segment and an upper conductive segment separated by an insulating segment, an end of each of the lower conductive segments away from the substrate being electrically connected in a one-to-one manner to each of the conductive layers in the lower group of conductive layers, and an end close to the substrate being electrically connected in a one-to-one manner to each of the first devices; an end of each of the upper conductive segments away from the binding chip being electrically connected in a one-to-one manner to each of the conductive layers in the upper group of conductive layers, and an end close to the binding chip being electrically connected in a one-to-one manner to each of the second devices.

[0019] In an exemplary embodiment, the common connection region is a common bit line region and the first device and the second device are both sense amplifiers, or the common connection region is a common word line region and the first device and the second device are both sub word line drivers.

[0020] In an exemplary embodiment, it also includes a plurality of lower insulating rings and a plurality of upper insulating rings, each of the lower insulating rings is arranged in a one-to-one correspondence in each of the through holes and surrounds the corresponding lower conductive segment, and the height of each of the lower insulating rings is less than the height of the conductive layer electrically connected to the corresponding lower conductive segment and greater than the height of the next conductive layer adjacent to the conductive layer electrically connected to the corresponding lower conductive segment; each of the upper insulating rings is arranged in a one-to-one correspondence in each of the through holes and surrounds the corresponding upper conductive segment, and one end of each of the upper insulating rings close to the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent previous conductive layer; the height of the lower conductive segment is greater than the height of the conductive layer electrically connected to it and less than the height of the previous conductive layer adjacent to the conductive layer electrically connected to it; and one end of the upper conductive segment close to the substrate is located between the conductive layer electrically connected to it and the adjacent next conductive layer.

[0021] In yet another aspect, an exemplary embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising:

[0022] Forming a stacked structure on a substrate, the stacked structure comprising a lower group of sacrificial layers and an upper group of sacrificial layers located above the lower group of sacrificial layers, the lower group of sacrificial layers comprising a plurality of sacrificial layers stacked vertically at intervals, the upper group of sacrificial layers comprising a plurality of sacrificial layers stacked vertically at intervals, the upper group of sacrificial layers and the lower group of sacrificial layers having the same number of layers, each of the sacrificial layers having a preset common connection area and a preset storage unit area located at least on one side of the preset common connection area;

[0023] A plurality of through holes are formed in the preset common connection area and along the extension direction of the preset common connection area, and are arranged at intervals, wherein the through holes penetrate the stacked structure, and the number of the through holes is equal to the number of layers of the lower group of sacrificial layers;

[0024] forming a conductive column and an insulating ring surrounding the conductive column in each through hole;

[0025] Patterning the stacked structure so that the preset common connection region forms a common connection region and the preset memory cell region forms a memory cell region;

[0026] Replacing the material of each sacrificial layer with a conductive material to form a corresponding lower conductive layer group and an upper conductive layer group;

[0027] Conductive columns and insulating rings with different heights are formed in each through hole to form a lower conductive segment and a lower insulating ring, and each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers in a one-to-one correspondence;

[0028] forming the insulating segment on each of the lower conductive segments;

[0029] Conductive columns and insulating rings of different heights are formed on the insulating segments to form upper conductive segments and upper insulating rings, and each upper conductive segment is electrically connected to each conductive layer in the upper conductive layer group in a one-to-one correspondence.

[0030] In an exemplary embodiment,

[0031] The forming of conductive pillars and insulating rings with different heights in each through hole to form a lower conductive segment and a lower insulating ring, and each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers in a one-to-one correspondence, comprises:

[0032] Depositing an insulating layer film on the inner sidewall and bottom surface of each through hole;

[0033] Removing the insulating film on the bottom surface of the through hole to form an insulating ring located on the inner side wall of the through hole;

[0034] Depositing a conductive material in each of the through holes to form a conductive column;

[0035] Removing part of the material of the insulating ring and the conductive pillar in the through hole to the same height, so that the height of the insulating ring and the conductive pillar in each through hole is less than the height of the conductive layer to be electrically connected to each lower conductive segment and is higher than the height of the next conductive layer adjacent to the conductive layer to be electrically connected to each lower conductive segment, so as to form each lower insulating ring and each preset lower conductive segment, and form empty grooves of different heights in each through hole;

[0036] Depositing conductive material into each empty slot until each empty slot is filled;

[0037] Part of the conductive material in each of the empty slots is removed so that the height of each of the preset lower conductive segments is greater than the height of the conductive layer to be electrically connected and less than the height of the upper conductive layer adjacent to the electrically connected conductive layer, so as to form each of the lower conductive segments, and each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers in a one-to-one correspondence.

[0038] In an exemplary embodiment,

[0039] The conductive pillars and insulating rings of different heights are formed on the insulating segments to form upper conductive segments and upper insulating rings, and each upper conductive segment is electrically connected to each conductive layer in the upper conductive layer group in a one-to-one correspondence, including:

[0040] Depositing an insulating layer film above the insulating segment in each of the through holes, and removing the insulating layer film on the top of each of the insulating segments to form each of the upper insulating rings; wherein one end of each of the insulating rings close to the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer;

[0041] Removing part of the insulating segments in each of the through holes, so that an end of each of the insulating segments away from the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent next conductive layer;

[0042] Conductive material is deposited in each of the empty grooves to form each of the upper conductive segments, and each of the upper conductive segments is electrically connected to each of the conductive layers in the upper group of conductive layers in a one-to-one correspondence.

[0043] The present application forms lower conductive segment structures of different heights on a substrate side below the memory array in a through-hole structure located in a common connection area of ​​the memory array, so that each lower conductive segment structure is electrically connected to each lower conductive layer of the corresponding memory array; at the same time, upper conductive segment structures of different heights are formed on a chip side above the memory array, so that each upper conductive segment structure is electrically connected to each upper conductive layer of the corresponding memory array, thereby being able to connect downwardly to the device (such as a sense amplifier SA or a sub-word line driver SWD) located on the substrate below the memory array, and being able to connect upwardly to the device (such as a sense amplifier SA or a sub-word line driver SWD) located on the binding chip above the memory array. The invention can also connect the memory cells on both sides of the common connection area, thereby realizing that multiple SA and SWD devices can be placed in a distributed manner, and these devices can be placed more evenly on the chip below the memory array or on the bound chip above the memory array, thereby alleviating the pressure on the bound chip and significantly reducing the manufacturing difficulty and process cost of the three-dimensional device; or the number of peripheral devices placed on the chip below the memory array or on the bound chip above the memory array can be reasonably allocated as needed, thereby making the manufacturing process more flexible and enhancing the design flexibility and adaptability of the three-dimensional device product.

[0044] The semiconductor structure provided by the present application is particularly suitable for a planar channel all around (PCAA) device structure of a three-dimensional DRAM.

[0045] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0047] Figure 1A A schematic perspective view of a semiconductor structure provided for an exemplary embodiment of the present application;

[0048] Figure 1B for Figure 1A A vertical cross-sectional schematic diagram of the structure shown taken along a plane parallel to the first direction;

[0049] Figure 2 A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction;

[0050] Figure 3AA horizontal cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a sacrificial layer;

[0051] Figure 3B for Figure 3A A vertical cross-sectional schematic diagram of the intermediate product shown is taken along a plane parallel to the first direction;

[0052] Figure 4 A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction;

[0053] Figure 5 A horizontal cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a sacrificial layer;

[0054] Fig. 6A A schematic horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a conductive layer;

[0055] Figure 6B for Fig. 6A A vertical cross-sectional schematic diagram of the intermediate product shown is taken along a plane parallel to the first direction;

[0056] Figure 7 A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction;

[0057] Figure 8 A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction;

[0058] Fig. 9 A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction;

[0059] Fig.10 A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction;

[0060] Fig.11A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction;

[0061] Fig.12 A vertical cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided for an exemplary embodiment of the present application, taken along a plane parallel to a first direction; and

[0062] Fig.13 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction. DETAILED DESCRIPTION

[0063] In order to make the purpose, technical solution and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0064] The embodiments herein can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the implementation and content can be transformed into various forms without departing from the purpose and scope of the present application. Therefore, the present application should not be interpreted as being limited to the contents recorded in the following embodiments. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0065] The proportions of the drawings in this application can be used as a reference in the actual process, but are not limited to this. For example, the aspect ratio of the semiconductor layer, the thickness and spacing of each film layer can be adjusted according to actual needs. The drawings described in this application are only schematic diagrams of the structure, and one embodiment of this application is not limited to the shapes or values ​​shown in the drawings.

[0066] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation on this application. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification and can be appropriately replaced according to the situation.

[0067] In this specification, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For those skilled in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0068] In the description of the present application, ordinal numbers such as "first" and "second" are provided to avoid confusion among constituent elements rather than to limit the quantity.

[0069] In this specification, "film" and "layer" may be interchanged. For example, "metal layer" may be replaced with "metal film" in some cases.

[0070] The sense amplifier SA is usually coupled to a column of memory cells (e.g., a bit line) to detect the current or voltage flowing through the memory cells as part of a read operation. A large number of SAs are placed on the bonded chip, and the number of SAs increases with the number of stacked layers, which places higher requirements on the placement and integration of SAs and SWDs on the bonded chip. However, the inventors of the present application have found that in order to increase the integration of the memory cells, the SA is set to be shunted, that is, the SA is set below the transistor array, so that the bit line will be located above the SA, and the connection between the SA and the bit line cannot be achieved.

[0071] Therefore, the present application provides a semiconductor structure, including a lower conductive layer, which includes a plurality of conductive layers stacked vertically at intervals; an upper conductive layer, which is located above the lower conductive layer and includes a plurality of conductive layers stacked vertically at intervals, the upper conductive layer and the lower conductive layer have the same number of layers, each conductive layer has a common connection area and a storage unit area located on at least one side of the common connection area; a plurality of through holes, which are arranged in the common connection area and are arranged at intervals along the extension direction of the common connection area, the through holes penetrate the upper conductive layer and the lower conductive layer, and the number of the through holes is equal to the number of layers of the lower conductive layer; a plurality of conductive columns, each of the conductive columns is arranged in each of the through holes in a one-to-one manner, each conductive column includes a lower conductive segment and an upper conductive segment separated by an insulating segment, each of the lower conductive segments is electrically connected to each of the conductive layers in the lower conductive layer in a one-to-one manner, and each of the upper conductive segments is electrically connected to each of the conductive layers in the upper conductive layer in a one-to-one manner.

[0072] The semiconductor structure provided by the exemplary embodiment of the present application may include a lower group of conductive layers and an upper group of conductive layers located above the lower group of conductive layers, each group of conductive layers may include a plurality of conductive layers stacked vertically at intervals, and the upper group of conductive layers and the lower group of conductive layers have the same number of layers.

[0073] As used in this application, the term "first direction" X is defined as a direction parallel to the through-hole arrangement direction; the term "second direction" Y is defined as a direction intersecting the first direction X; the term "third direction" Z is defined as a direction perpendicular to the plane where the substrate is located; the plane formed by the first direction X and the second direction Y is parallel to the substrate. The "first direction" X, the "second direction" Y and the "third direction" Z can be as follows Figure 1A As shown in the following table.

[0074] Figure 1A A schematic perspective view of a semiconductor structure provided for an exemplary embodiment of the present application; Figure 1B for Figure 1A The structure shown is a vertical cross-sectional schematic diagram taken along a plane parallel to the first direction. Figure 1A and 1B As shown, the lower conductive layer group may include a first lower conductive layer 61, a second lower conductive layer 62, a third lower conductive layer 63, a fourth lower conductive layer 64 and a fifth lower conductive layer 65, for a total of 5 layers. The upper conductive layer group may include a first upper conductive layer 71, a second upper conductive layer 72, a third upper conductive layer 73, a fourth upper conductive layer 74 and a fifth upper conductive layer 75, for a total of 5 layers. That is, the number of layers of the lower conductive layer group and the upper conductive layer group is the same.

[0075] Each conductive layer may have a common bit line extending along a first direction X and at least two memory cells located on both sides of the common bit line and extending along a second direction Y. For 1T1C and 2T0C memory cells, the drain of each memory cell may be connected to the common bit line.

[0076] Continue to refer Figure 1B The semiconductor structure provided by the present application may include five through holes arranged in the common bit line region and arranged in sequence along the extension direction of the common connection region, each through hole passing through the lower conductive layer and the upper conductive layer. The number of through holes is the same as the number of layers of the lower conductive layer and the upper conductive layer.

[0077] Each through hole may include a conductive pillar and an insulating ring. Figure 1B It shows that the first through hole may include the first lower conductive segment 21, the first insulating segment 31 and the first upper conductive segment 41; the second through hole may include the second lower conductive segment 22, the second insulating segment 32 and the second upper conductive segment 42; the third through hole may include the third lower conductive segment 23, the third insulating segment 33 and the third upper conductive segment 43; the fourth through hole may include the fourth lower conductive segment 24, the fourth insulating segment 34 and the fourth upper conductive segment 44; and the fifth through hole may include the fifth lower conductive segment 25, the fifth insulating segment 35 and the fifth upper conductive segment 45.

[0078] Figure 1BIt also shows that the first lower conductive segment 21 is only electrically connected to the first lower conductive layer 61; the second lower conductive segment 22 is only electrically connected to the second lower conductive layer 62; the third lower conductive segment 23 is only electrically connected to the third lower conductive layer 63; the fourth lower conductive segment 24 is only electrically connected to the fourth lower conductive layer 64 and the fifth lower conductive segment 25 is only electrically connected to the fifth lower conductive layer 65, that is, the lower conductive segments in each through hole are only electrically connected to one lower conductive layer and are electrically insulated from the other lower conductive layers by their own lower insulating rings.

[0079] Figure 1B It also shows that the first upper conductive segment 41 is electrically connected only to the first upper conductive layer 71, the second upper conductive segment 42 is electrically connected only to the second upper conductive layer 72, the third upper conductive segment 43 is electrically connected only to the third upper conductive layer 73, the fourth upper conductive segment 44 is electrically connected only to the fourth upper conductive layer 74, and the fifth upper conductive segment 45 is electrically connected only to the fifth upper conductive layer 75, that is, the upper conductive segment in each through hole is electrically connected only to one upper conductive layer and is electrically insulated from the other upper conductive layers by their own upper insulating rings.

[0080] Figure 1B It also shows that the height of the first lower conductive segment 21 is greater than the height of the first conductive layer 61 to which it is electrically connected and less than the height of the upper conductive layer 62 adjacent to the conductive layer 61 to which it is electrically connected; the height of the second lower conductive segment 22 is greater than the height of the second conductive layer 62 to which it is electrically connected and less than the height of the upper conductive layer 63 adjacent to the conductive layer 62 to which it is electrically connected; the height of the third lower conductive segment 23 is greater than the height of the third conductive layer 63 to which it is electrically connected and less than the height of the upper conductive layer 64 adjacent to the conductive layer 63 to which it is electrically connected; the height of the fourth lower conductive segment 24 is greater than the height of the fourth conductive layer 64 to which it is electrically connected and less than the height of the upper conductive layer 65 adjacent to the conductive layer 64 to which it is electrically connected; and the height of the fifth lower conductive segment 25 is greater than the height of the fifth conductive layer 65 to which it is electrically connected and the height of the first upper conductive layer 71.

[0081] Taking the bonded chip as the height reference plane, Figure 1BIt is also shown that the height of the first upper conductive segment 41 is greater than the height of the upper conductive layer 71 to which it is electrically connected and less than the height of the next lower conductive layer 65 adjacent to the upper conductive layer 71 to which it is electrically connected; the height of the second upper conductive segment 42 is greater than the height of the upper conductive layer 72 to which it is electrically connected and less than the height of the next upper conductive layer 71 adjacent to the upper conductive layer 72 to which it is electrically connected; the height of the third upper conductive segment 43 is greater than the height of the upper conductive layer 73 to which it is electrically connected and less than the height of the next upper conductive layer 72 adjacent to the upper conductive layer 73 to which it is electrically connected; the height of the fourth upper conductive segment 44 is greater than the height of the upper conductive layer 74 to which it is electrically connected and less than the height of the next upper conductive layer 73 adjacent to the upper conductive layer 74 to which it is electrically connected; and the height of the fifth upper conductive segment 45 is greater than the height of the upper conductive layer 75 to which it is electrically connected and less than the height of the next upper conductive layer 74 adjacent to the upper conductive layer 75 to which it is electrically connected.

[0082] As used in this application, when referring to the lower conductive segments and the lower insulating ring, the term "height" means the distance between the side of each lower conductive segment away from the substrate and the side of each lower insulating ring away from the substrate and the upper surface of the substrate. When referring to the upper conductive segments and the upper insulating ring, the term "height" means the distance between the side of each upper conductive segment close to the substrate and the side of each upper insulating ring close to the substrate and the upper surface of the stacked structure (i.e., the side where the bonded chip is located).

[0083] Figure 1B It is also shown that the heights of the first to fifth lower conductive segments gradually increase, while the heights of the first to fifth upper conductive segments gradually decrease along the first direction X. However, in other exemplary embodiments, the heights of the first to fifth lower conductive segments may gradually decrease, while the heights of the first to fifth upper conductive segments may gradually increase along the first direction X.

[0084] In an exemplary embodiment, the common connection region may be a common bit line region or a common word line region.

[0085] In an exemplary embodiment, the memory cell may be a 1T1C memory cell, a 2T0C memory cell, or a 2T1C memory cell.

[0086] Therefore, the present application is particularly suitable for connecting the common bit lines of each layer of the three-dimensional memory to both the device below the three-dimensional memory (such as a memory chip) and the corresponding sense amplifiers in the device above the three-dimensional memory (such as a binding chip).

[0087] The technical solution of the present application is further explained below by the manufacturing process of the semiconductor structure according to the exemplary embodiment of the present application. The "patterning process" mentioned in the exemplary embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which is a mature manufacturing process in the relevant technology. The "photolithography process" mentioned in the exemplary embodiment includes coating of film layer, mask exposure and development, which is a mature manufacturing process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of the exemplary embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" also requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0088] The manufacturing method of the present application is explained below by taking a manufacturing process of a semiconductor structure for connecting a bit line of a three-dimensional memory to a sense amplifier (SA) disposed below and above the bit line as an example.

[0089] The exemplary manufacturing method may include the following steps:

[0090] S100: A stacked structure is formed on a substrate, wherein the stacked structure includes, stacked in sequence from bottom to top, a 1st lower insulating layer and a 1st lower sacrificial layer; a 2nd lower insulating layer and a 2nd lower sacrificial layer; ...; an nth lower insulating layer and an nth lower sacrificial layer; an isolation insulating layer; a 1st upper insulating layer and a 1st upper sacrificial layer; a 2nd upper insulating layer and a 2nd upper sacrificial layer; ...; and an nth upper insulating layer and an nth upper sacrificial layer, where n is a positive integer; the stacked structure has a preset common connection area and a preset storage unit area located on at least one side of the preset common connection area.

[0091] An exemplary step may include: alternately depositing insulating layer films and sacrificial layer films on a substrate 2 to form a stacked structure 1, wherein the stacked structure 1 includes, from bottom to top, a first lower insulating layer 101 and a first lower sacrificial layer 121, a second lower insulating layer 102 and a second lower sacrificial layer 122, a third lower insulating layer 103 and a third lower sacrificial layer 123, a fourth lower insulating layer 104 and a fourth lower sacrificial layer 124, a fifth lower insulating layer 105 and a fifth lower sacrificial layer 125, an insulating layer 106 and a second lower sacrificial layer 126, an insulating layer 107 and a second lower sacrificial layer 127, an insulating layer 108 and a second lower sacrificial layer 128, an insulating layer 109 and a second lower sacrificial layer 130, an insulating layer 110 and a second lower sacrificial layer 131, an insulating layer 111 and a second lower sacrificial layer 132, an insulating layer 112 and a second lower sacrificial layer 133, an insulating layer 113 and a second lower sacrificial layer 134, an insulating layer 114 and a second lower sacrificial layer 135, an insulating layer 115 and a second lower sacrificial layer 136, an insulating layer 116 and a second lower sacrificial layer 137, an insulating layer 117 and a second lower sacrificial layer 138, an insulating layer 118 and a second lower sacrificial layer 139, an insulating layer 129 and a second lower sacrificial layer 140, an insulating layer 12 The stacked structure 1 comprises a first upper insulating layer 106, a first upper sacrificial layer 126, a second upper insulating layer 108 and a second upper sacrificial layer 127, a third upper insulating layer 109 and a third upper sacrificial layer 128, a fourth upper insulating layer 110 and a fourth upper sacrificial layer 129, and a fifth upper insulating layer 111 and a fifth upper sacrificial layer 130; the stacked structure 1 comprises a preset common bit line region 100 and preset memory cell regions 200 and 300 located at both sides of the preset common bit line region 100, as shown in FIG. Figure 2 shown. Figure 2 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction.

[0092] In an exemplary embodiment, each insulating layer film and the sacrificial layer film may be deposited by chemical vapor deposition, plasma enhanced chemical vapor deposition, atomic layer deposition (ALD), or the like.

[0093] In an exemplary embodiment, each insulating layer may be made of an oxide insulating material, such as silicon dioxide (eg, SiO 2 ), which is convenient for large-area deposition.

[0094] In an exemplary embodiment, each sacrificial layer may employ a nitride material, such as silicon nitride (SiN).

[0095] S200: forming a through hole.

[0096] An exemplary step may include: in the preset common bit line region 100, five through holes are formed at equal intervals along the extension direction Y of the preset common bit line region by photolithography, namely, the first through hole K1, the second through hole K2, the third through hole K3, the fourth through hole K4 and the fifth through hole K5, the number of through holes being the same as the number of layers of the upper conductive layer or the lower conductive layer to be formed subsequently, such as Figure 3A and 3B shown. Figure 3A A horizontal cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a sacrificial layer; Figure 3B for Figure 3AThe intermediate product shown is a vertical cross-sectional schematic diagram taken along a plane parallel to the first direction.

[0097] In an exemplary embodiment, the orthographic projection of each through hole on a plane parallel to the substrate 2 may be in a circular, elliptical, square, rectangular or other shape.

[0098] S300: forming a conductive column and an insulating ring.

[0099] Exemplary steps may include: depositing an insulating layer film around the inner sidewall and bottom of each through hole by atomic layer deposition, anisotropically etching the insulating layer at the bottom and retaining only the insulating layer on the inner sidewall of the through hole; continuing to deposit metal in each through hole by ALD; and finally making the upper surface of the stacked structure flush by CMP to form five conductive pillars 10 and five insulating rings 20, such as Figure 4 shown. Figure 4 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction.

[0100] In an exemplary embodiment, each conductive pillar may be made of a metal material such as tungsten.

[0101] In an exemplary embodiment, each insulating ring may be made of HfO 2 or Al 2 O 3 And other materials.

[0102] S400: Patterning a stacked structure, forming a second sub-stacked structure extending along the second direction in the preset common bit line area, forming a plurality of first sub-stacked structures extending along the first direction and terminating at the second sub-stacked structure in the preset memory cell area, and the plurality of first sub-stacked structures are arranged at intervals in the second direction.

[0103] An exemplary step may include: etching the stacked structure by photolithography, forming a second sub-stacked structure 1000 extending along the second direction Y in the preset common bit line region 100, forming a plurality of first sub-stacked structures 2000 and 3000 extending along the first direction X and terminating at the second sub-stacked structure 1000 in the preset memory cell regions 200 and 300, wherein the plurality of first sub-stacked structures 2000 and 3000 are arranged at intervals in the second direction Y, as shown in FIG. Figure 5 shown. Figure 5 A horizontal cross-sectional schematic diagram of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a sacrificial layer.

[0104] S500: replacing the material of each sacrificial layer in the stacked structure with a conductive material to form n conductive layers, so as to form a memory cell region of each layer in the first sub-stacked structure and a common bit line region of each layer in the second sub-stacked structure;

[0105] Exemplary steps may include: removing each sacrificial layer by etching to form a plurality of grooves; depositing a metal conductive material into the plurality of grooves, etching away the metal on the sidewalls of the insulating layer, leaving only the metal between adjacent insulating layers, completing the replacement of the sacrificial layer material, and forming 10 conductive layers, namely, a first lower conductive layer 61, a second lower conductive layer 62, a third lower conductive layer 63, a fourth lower conductive layer 64, and a fifth lower conductive layer 65; a first upper conductive layer 71, a second upper conductive layer 72, a third upper conductive layer 73, a fourth upper conductive layer 74, and a fifth upper conductive layer 75, such as Fig. 6A and 6B shown. Fig. 6A A schematic horizontal cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a conductive layer; Figure 6B for Fig. 6A The intermediate product shown is a vertical cross-sectional schematic diagram taken along a plane parallel to the first direction.

[0106] S600: removing a portion of each of the conductive pillars and each of the insulating rings.

[0107] An exemplary step may include: removing a portion of the material of the conductive pillar and the insulating ring by etching, so that the conductive pillar and the insulating ring in each through hole have the same height, but the conductive pillars and the insulating rings in different through holes have different heights, the heights of the conductive pillars and the insulating rings in through holes K1 to K5 gradually increase, and the upper part of the conductive pillar and the insulating ring in each through hole is empty, such as Figure 7 shown. Figure 7 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction.

[0108] S700: An exemplary step may include: depositing the same material as the conductive pillar into each through hole by an ALD process, and then making the upper surface of the stacked structure flush by a CMP process, such as Figure 8 shown. Figure 8 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction.

[0109] S800: forming lower insulating rings and lower conductive segments.

[0110] Exemplary steps may include: etching the conductive pillars in each through hole to different heights through a staircase process, so that the first lower insulating ring 11 in the through hole K1 has a height T1 and the first lower conductive segment 21 has a height H1; by analogy, the second lower insulating ring 12 in the through hole K2 has a height T2 and the second lower conductive segment 22 has a height H2; the third lower insulating ring 13 in the through hole K3 has a height T3 and the third lower conductive segment 23 has a height H3; the fourth lower insulating ring 14 in the through hole K4 has a height T4 and the fourth lower conductive segment 24 has a height H4; and the fifth lower insulating ring 15 in the through hole K5 has a height T5 and the fifth lower conductive segment 25 has a height H5, as shown in FIG. Fig. 9 shown. Fig. 9 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction.

[0111] Fig. 9 It is shown that the height H1 to the height H5 gradually increases, and the height T1 to the height T5 gradually increases. However, in other exemplary embodiments, the height H1 to the height H5 may also gradually decrease, and the height T1 to the height T5 may also gradually decrease; or, the height H3 is the largest and gradually decreases toward both sides, that is, H3 to H1 gradually decreases and H3 to H5 gradually decreases; similarly, T3 to T1 gradually decreases and T3 to T5 gradually decreases.

[0112] Fig. 9 It also shows that the first lower conductive segment 21 is only electrically connected to the first lower conductive layer 61, the second lower conductive segment 22 is only electrically connected to the second lower conductive layer 62, the third lower conductive segment 23 is only electrically connected to the third lower conductive layer 63, the fourth lower conductive segment 24 is only electrically connected to the fourth lower conductive layer 64, and the fifth lower conductive segment 25 is only electrically connected to the fifth lower conductive layer 65, that is, the lower conductive segments in each through hole are only electrically connected to one lower conductive layer and are electrically insulated from the other lower conductive layers by their own lower insulating rings, thereby realizing the electrical connection of the common bit lines of each layer with the corresponding sensing amplifiers below.

[0113] S900: An exemplary step may include: depositing an insulating material film to fill each through hole, and then leveling the upper surface of the stacked structure by a CMP process, such as Fig.10 shown. Fig.10 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction.

[0114] In an exemplary embodiment, each insulating material may be HfO 2 or Al 2 O3 And other materials.

[0115] S1000: forming each insulating segment.

[0116] An exemplary step may include: using a step process to etch the insulating layer in each through hole to different depths to form a first insulating segment 31, a second insulating segment 32, a third insulating segment 33, a fourth insulating segment 34 and a fifth insulating segment 35, such as Fig.11 shown. Fig.11 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction.

[0117] S1100: forming upper insulating rings.

[0118] Exemplary steps may include: depositing an insulating layer film around the inner sidewall and bottom of each through hole by ALD method, anisotropically etching the insulating layer at the bottom and retaining only the insulating layer on the inner sidewall of the through hole; etching the insulating layer to expose the metal cross section to be connected, forming a first upper insulating ring 51, a second upper insulating ring 52, a third upper insulating ring 53, a fourth upper insulating ring 54 and a fifth upper insulating ring 55, such as Fig.12 shown. Fig.12 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction.

[0119] S1200: forming upper conductive segments.

[0120] An exemplary step may include: continuing to deposit metal conductive material on the metal cross-section exposed in each through hole in the aforementioned step, and making the upper surface of the stacked structure flush by a CMP process to form a first upper conductive segment 41, a second upper conductive segment 42, a third upper conductive segment 43, a fourth upper conductive segment 44, and a fifth upper conductive segment 45, such as Fig.13 shown. Fig.13 A schematic vertical cross-sectional view of an intermediate product obtained in an intermediate step of a method for manufacturing a semiconductor structure provided in an exemplary embodiment of the present application, taken along a plane parallel to a first direction.

[0121] Fig.13It shows that the first upper conductive segment 41 is electrically connected only to the first upper conductive layer 71, the second upper conductive segment 42 is electrically connected only to the second upper conductive layer 72, the third upper conductive segment 43 is electrically connected only to the third upper conductive layer 73, the fourth upper conductive segment 44 is electrically connected only to the fourth upper conductive layer 74, and the fifth upper conductive segment 45 is electrically connected only to the fifth upper conductive layer 75, that is, the upper conductive segments in each through hole are electrically connected to only one upper conductive layer and are electrically insulated from the other upper conductive layers by their own upper insulating rings, thereby realizing electrical connection between the common bit lines of each layer and the corresponding sensing amplifiers above the bit lines.

[0122] The method of the present application can enable the common bit line in the memory cell array to be connected to both the device below the memory cell array, such as the SA on the memory array chip, and the device above the memory cell array, such as the SA in the binding chip.

[0123] The exemplary embodiment of the present application also provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0124] S1000: forming a stacked structure on a substrate, the stacked structure comprising a lower group of sacrificial layers and an upper group of sacrificial layers located above the lower group of sacrificial layers, the lower group of sacrificial layers comprising a plurality of sacrificial layers stacked vertically at intervals, the upper group of sacrificial layers comprising a plurality of sacrificial layers stacked vertically at intervals, the upper group of sacrificial layers and the lower group of sacrificial layers having the same number of layers, each sacrificial layer having a preset common connection region and a preset storage unit region located at least on one side of the preset common connection region;

[0125] S1100: forming a plurality of through holes arranged at intervals in the preset common connection area and along an extension direction of the preset common connection area, wherein the through holes penetrate the stacked structure, and the number of the through holes is equal to the number of layers of the lower group of sacrificial layers;

[0126] S1200: forming a conductive column and an insulating ring surrounding the conductive column in each through hole;

[0127] S1300: patterning the stacked structure so that the preset common connection region forms a common connection region and the preset memory cell region forms a memory cell region;

[0128] S1400: replacing the material of each sacrificial layer with a conductive material to form a corresponding lower conductive layer group and an upper conductive layer group;

[0129] S1500: forming conductive pillars and insulating rings with different heights in each through hole to form a lower conductive segment and a lower insulating ring, and each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers in a one-to-one correspondence;

[0130] S1600: forming the insulating segment on each of the lower conductive segments;

[0131] S1700: Conductive pillars and insulating rings of different heights are formed on the insulating segments to form upper conductive segments and upper insulating rings, and each upper conductive segment is electrically connected to each conductive layer in the upper group of conductive layers in a one-to-one correspondence.

[0132] In an exemplary embodiment, step S1500 may include:

[0133] S1510: depositing an insulating layer thin film on the inner sidewall and bottom surface of each of the through holes;

[0134] S1520: removing the insulating film on the bottom surface of the through hole to form an insulating ring located on the inner side wall of the through hole;

[0135] S1530: depositing a conductive material in each of the through holes to form a conductive column;

[0136] S1540: removing part of the material of the insulating ring and the conductive pillar in the through hole to the same height, so that the height of the insulating ring and the conductive pillar in each through hole is less than the height of the conductive layer to be electrically connected to each lower conductive segment and is higher than the height of the next conductive layer adjacent to the conductive layer to be electrically connected to each lower conductive segment, so as to form each lower insulating ring and each preset lower conductive segment, and form empty grooves of different heights in each through hole;

[0137] S1550: depositing conductive material into each empty slot until each empty slot is filled;

[0138] S1560: removing part of the conductive material in each of the empty slots, so that the height of each of the preset lower conductive segments is greater than the height of the conductive layer to be electrically connected and less than the height of the upper conductive layer adjacent to the electrically connected conductive layer, so as to form each of the lower conductive segments, and each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers one by one.

[0139] In an exemplary embodiment, step S1700 may include:

[0140] S1710: depositing an insulating layer film above the insulating segment in each of the through holes, and removing the insulating layer film on the top of each of the insulating segments to form each of the upper insulating rings; wherein one end of each of the insulating rings close to the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer;

[0141] S1720: removing a portion of the insulating segments in each of the through holes, so that an end of each of the insulating segments away from the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent next conductive layer;

[0142] S1730: depositing a conductive material in each of the empty grooves to form each of the upper conductive segments, and each of the upper conductive segments is electrically connected to each of the conductive layers in the upper group of conductive layers in a one-to-one correspondence.

[0143] The exemplary embodiment of the present application further provides a memory, including:

[0144] a substrate on which a plurality of first devices are disposed;

[0145] a lower conductive layer group located on the substrate and comprising a plurality of conductive layers stacked vertically in an interspaced relationship;

[0146] an upper conductive layer group, which is located above the lower conductive layer group and includes a plurality of conductive layers stacked vertically and spaced apart from each other, wherein the upper conductive layer group and the lower conductive layer group have the same number of conductive layers, and each conductive layer has a common connection area and a storage cell area located at least on one side of the common connection area;

[0147] A binding chip, which is located on the upper conductive layer and is provided with a plurality of second devices;

[0148] A plurality of through holes, which are arranged in the common connection area and spaced apart along the extension direction of the common connection area, the through holes penetrate the plurality of conductive layers, and the number of the through holes is equal to the number of layers of the lower group of conductive layers;

[0149] A plurality of conductive pillars are disposed in each of the through holes in a one-to-one manner, each conductive pillar comprising a lower conductive segment and an upper conductive segment separated by an insulating segment, an end of each of the lower conductive segments away from the substrate being electrically connected in a one-to-one manner to each of the conductive layers in the lower group of conductive layers, and an end close to the substrate being electrically connected in a one-to-one manner to each of the first devices; an end of each of the upper conductive segments away from the binding chip being electrically connected in a one-to-one manner to each of the conductive layers in the upper group of conductive layers, and an end close to the binding chip being electrically connected in a one-to-one manner to each of the second devices.

[0150] In an exemplary embodiment, the common connection region is a common bit line region and the first device and the second device are both sense amplifiers, or the common connection region is a common word line region and the first device and the second device are both sub word line drivers.

[0151] In an exemplary embodiment, the memory further includes a plurality of lower insulating rings and a plurality of upper insulating rings, each of the lower insulating rings being arranged in a one-to-one correspondence in each of the through holes and surrounding the corresponding lower conductive segment, and a height of each of the lower insulating rings being less than a height of the conductive layer electrically connected to the corresponding lower conductive segment and being greater than a height of a next conductive layer adjacent to the conductive layer electrically connected to the corresponding lower conductive segment; each of the upper insulating rings being arranged in a one-to-one correspondence in each of the through holes and surrounding the corresponding upper conductive segment, and an end of each of the upper insulating rings close to the substrate being located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent previous conductive layer; the height of the lower conductive segment being greater than a height of the conductive layer electrically connected to it and less than a height of the previous conductive layer adjacent to the conductive layer electrically connected to it; and an end of the upper conductive segment close to the substrate being located between the conductive layer electrically connected to it and the adjacent next conductive layer.

[0152] Although the embodiments disclosed in this application are as above, the contents are only embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any technician in the field to which this application belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in this application, but the scope of protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: a lower set of conductive layers, comprising a plurality of conductive layers stacked vertically in an interspaced relationship; An upper conductive layer group, which is located above the lower conductive layer group and includes a plurality of conductive layers stacked vertically and spaced apart from each other, the upper conductive layer group and the lower conductive layer group have the same number of layers, and each conductive layer has a common connection area and a storage cell area located at least on one side of the common connection area; A plurality of through holes are arranged in the common connection area and spaced apart along the extension direction of the common connection area, the through holes penetrate the upper conductive layer and the lower conductive layer, and the number of the through holes is equal to the number of layers of the lower conductive layer; A plurality of conductive pillars are disposed in each of the through holes in a one-to-one manner, each conductive pillar comprises a lower conductive segment and an upper conductive segment separated by an insulating segment, each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers in a one-to-one manner, and each of the upper conductive segments is electrically connected to each of the conductive layers in the upper group of conductive layers in a one-to-one manner.

2. The semiconductor structure according to claim 1, characterized in that: It also includes a plurality of lower insulating rings and a plurality of upper insulating rings, wherein each of the lower insulating rings is arranged in a one-to-one correspondence in each of the through holes and surrounds the corresponding lower conductive segment, and the height of each of the lower insulating rings is less than the height of the conductive layer electrically connected to the corresponding lower conductive segment and is greater than the height of the next conductive layer adjacent to the conductive layer electrically connected to the corresponding lower conductive segment; each of the upper insulating rings is arranged in a one-to-one correspondence in each of the through holes and surrounds the corresponding upper conductive segment, and one end of each of the upper insulating rings close to the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer.

3. The semiconductor structure according to claim 1, characterized in that: Along the extension direction of the common connection area, the height of the lower conductive segment in each through hole gradually increases, while the height of the upper conductive segment gradually decreases; or, the height of the lower conductive segment in each through hole gradually decreases, while the height of the upper conductive segment gradually increases.

4. The semiconductor structure according to claim 1, characterized in that: Along the extension direction of the common connection area, the distances between adjacent through holes are the same.

5. A memory, characterized in that: include: a substrate on which a plurality of first devices are disposed; a lower conductive layer group located on the substrate and comprising a plurality of conductive layers stacked vertically in an interspaced relationship; an upper conductive layer group, which is located above the lower conductive layer group and includes a plurality of conductive layers stacked vertically and spaced apart from each other, wherein the upper conductive layer group and the lower conductive layer group have the same number of conductive layers, and each conductive layer has a common connection area and a storage cell area located at least on one side of the common connection area; A binding chip, which is located on the upper conductive layer and is provided with a plurality of second devices; A plurality of through holes, which are arranged in the common connection area and spaced apart along the extension direction of the common connection area, the through holes penetrate the plurality of conductive layers, and the number of the through holes is equal to the number of layers of the lower group of conductive layers; A plurality of conductive pillars are disposed in each of the through holes in a one-to-one manner, each conductive pillar comprising a lower conductive segment and an upper conductive segment separated by an insulating segment, an end of each of the lower conductive segments away from the substrate being electrically connected in a one-to-one manner to each of the conductive layers in the lower group of conductive layers, and an end close to the substrate being electrically connected in a one-to-one manner to each of the first devices; an end of each of the upper conductive segments away from the binding chip being electrically connected in a one-to-one manner to each of the conductive layers in the upper group of conductive layers, and an end close to the binding chip being electrically connected in a one-to-one manner to each of the second devices.

6. The memory according to claim 5, characterized in that: The common connection region is a common bit line region and the first device and the second device are both sense amplifiers, or the common connection region is a common word line region and the first device and the second device are both sub word line drivers.

7. The memory according to claim 5, characterized in that: It also includes a plurality of lower insulating rings and a plurality of upper insulating rings, wherein each of the lower insulating rings is arranged in a one-to-one correspondence in each of the through holes and surrounds the corresponding lower conductive segment, and the height of each of the lower insulating rings is less than the height of the conductive layer electrically connected to the corresponding lower conductive segment and greater than the height of the next conductive layer adjacent to the conductive layer electrically connected to the corresponding lower conductive segment; each of the upper insulating rings is arranged in a one-to-one correspondence in each of the through holes and surrounds the corresponding upper conductive segment, and one end of each of the upper insulating rings close to the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent previous conductive layer; the height of the lower conductive segment is greater than the height of the conductive layer electrically connected to it and less than the height of the previous conductive layer adjacent to the conductive layer electrically connected to it; and one end of the upper conductive segment close to the substrate is located between the conductive layer electrically connected to it and the adjacent next conductive layer.

8. A method for manufacturing a semiconductor structure, characterized in that: include: Forming a stacked structure on a substrate, the stacked structure comprising a lower group of sacrificial layers and an upper group of sacrificial layers located above the lower group of sacrificial layers, the lower group of sacrificial layers comprising a plurality of sacrificial layers stacked vertically at intervals, the upper group of sacrificial layers comprising a plurality of sacrificial layers stacked vertically at intervals, the upper group of sacrificial layers and the lower group of sacrificial layers having the same number of layers, each of the sacrificial layers having a preset common connection area and a preset storage unit area located at least on one side of the preset common connection area; A plurality of through holes are formed in the preset common connection area and along the extension direction of the preset common connection area. The through holes penetrate the stacked structure, and the number of the through holes is equal to the number of layers of the lower group of sacrificial layers. forming a conductive column and an insulating ring surrounding the conductive column in each through hole; Patterning the stacked structure so that the preset common connection region forms a common connection region and the preset memory cell region forms a memory cell region; Replacing the material of each sacrificial layer with a conductive material to form a corresponding lower conductive layer group and an upper conductive layer group; Conductive columns and insulating rings with different heights are formed in each through hole to form a lower conductive segment and a lower insulating ring, and each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers in a one-to-one correspondence; forming the insulating segment on each of the lower conductive segments; Conductive columns and insulating rings of different heights are formed on the insulating segments to form upper conductive segments and upper insulating rings, and each upper conductive segment is electrically connected to each conductive layer in the upper conductive layer group in a one-to-one correspondence.

9. The manufacturing method according to claim 8, characterized in that: The forming of conductive pillars and insulating rings with different heights in each through hole to form a lower conductive segment and a lower insulating ring, and each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers in a one-to-one correspondence, comprises: Depositing an insulating film on the inner sidewall and bottom surface of each through hole; Removing the insulating film on the bottom surface of the through hole to form an insulating ring located on the inner side wall of the through hole; Depositing a conductive material in each of the through holes to form a conductive column; Removing part of the material of the insulating ring and the conductive pillar in the through hole to the same height, so that the height of the insulating ring and the conductive pillar in each through hole is less than the height of the conductive layer to be electrically connected to each lower conductive segment and is higher than the height of the next conductive layer adjacent to the conductive layer to be electrically connected to each lower conductive segment, so as to form each lower insulating ring and each preset lower conductive segment, and form empty grooves of different heights in each through hole; Depositing conductive material into each empty slot until each empty slot is filled; Part of the conductive material in each of the empty slots is removed so that the height of each of the preset lower conductive segments is greater than the height of the conductive layer to be electrically connected and less than the height of the upper conductive layer adjacent to the electrically connected conductive layer, so as to form each of the lower conductive segments, and each of the lower conductive segments is electrically connected to each of the conductive layers in the lower group of conductive layers in a one-to-one correspondence.

10. The manufacturing method according to claim 9, characterized in that: The conductive pillars and insulating rings of different heights are formed on the insulating segments to form upper conductive segments and upper insulating rings, and each upper conductive segment is electrically connected to each conductive layer in the upper conductive layer group in a one-to-one correspondence, including: Depositing an insulating layer film above the insulating segment in each of the through holes, and removing the insulating layer film on the top of each of the insulating segments to form each of the upper insulating rings; wherein one end of each of the insulating rings close to the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent upper conductive layer; Removing part of the insulating segments in each of the through holes, so that an end of each of the insulating segments away from the substrate is located between the conductive layer electrically connected to the corresponding upper conductive segment and the adjacent next conductive layer; Conductive material is deposited in each of the empty grooves to form each of the upper conductive segments, and each of the upper conductive segments is electrically connected to each of the conductive layers in the upper group of conductive layers in a one-to-one correspondence.

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