Semiconductor structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor structures, and discloses a semiconductor structure and a preparation method thereof. The polycrystalline silicon layer is located on the surface of one side of the semiconductor substrate layer; the first buried oxide layer is located on the surface of the side, away from the semiconductor substrate layer, of the polycrystalline silicon layer; the graphic structure layer is located on the surface of the side, away from the polycrystalline silicon layer, of the first buried oxide layer, the graphic structure layer comprises a plurality of conductive structures and a plurality of insulator structures, the conductive structures and the insulator structures are alternately arranged in the preset direction, and one sides of the adjacent conductive structures and insulator structures abut against each other; the second buried oxide layer is located on the surface of the side, away from the first buried oxide layer, of the graphic structure layer; the active layer is located on the surface of the side, away from the graphic structure layer, of the second buried oxide layer. The threshold voltage of the semiconductor device can be adjusted, and the electrical performance of the semiconductor device can be flexibly optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor structures, and in particular to a semiconductor structure and a preparation method thereof. Background Art

[0002] Silicon on Insulator (SOI) adds a buried oxide layer (BOX) between the top silicon and the substrate. This structure electrically isolates the top silicon and the substrate, which can reduce the parasitic capacitance between transistors, reduce the delay in signal transmission, and increase the operating speed of the circuit. It also reduces the leakage current from the substrate to the top silicon device and reduces the power consumption of the circuit.

[0003] However, in the Partially Depleted Silicon on Insulator (PDSOI) process, since the silicon body layer is partially depleted and not connected to the substrate or the source, the silicon body layer becomes a floating potential region, making it impossible for the charge in the silicon body layer to be effectively released or fixed through an external path, thereby causing a floating body effect and affecting the electrical performance of semiconductor devices formed by SOI. Summary of the invention

[0004] In view of this, the present invention provides a semiconductor structure and a method for preparing the same, so as to improve the problem of poor electrical performance of semiconductor devices formed by SOI.

[0005] In a first aspect, the present invention provides a semiconductor structure, comprising: a semiconductor substrate layer; a polysilicon layer, located on one side surface of the semiconductor substrate layer; a first buried oxide layer, located on one side surface of the polysilicon layer away from the semiconductor substrate layer; a graphic structure layer, located on one side surface of the first buried oxide layer away from the polysilicon layer, the graphic structure layer comprising a plurality of conductive structures and a plurality of insulator structures, the plurality of conductive structures and the plurality of insulator structures being alternately arranged along a preset direction, and one side of adjacent conductive structures and insulator structures being abutted; a second buried oxide layer, located on one side surface of the graphic structure layer away from the first buried oxide layer; and an active layer, located on one side surface of the second buried oxide layer away from the graphic structure layer.

[0006] The semiconductor structure provided in this embodiment sets a graphic structure layer in the buried oxide layer, which is equivalent to introducing a back gate in the SOI structure. The back gate can reduce the parasitic capacitance of the semiconductor device and improve the maximum operating frequency and gain-bandwidth product of the semiconductor device. Secondly, it can optimize the linear characteristics of the semiconductor device and reduce distortion. Thirdly, it can enhance the anti-interference ability of the semiconductor device to external signals. Fourthly, it can effectively absorb and conduct the heat generated by the device, improve thermal management, and improve the reliability of the semiconductor device. Fifthly, it can flexibly optimize the key RF performance indicators of the semiconductor device, such as gain, noise and linearity.

[0007] In an optional implementation, the width of the conductive structure is less than or equal to the width of the insulator structure.

[0008] In an optional implementation, the widths of the plurality of conductive structures and the widths of the plurality of insulator structures vary according to a preset rule.

[0009] In this embodiment, if the width of the conductive structure gradually increases, the gate capacitance of the corresponding switch unit increases successively, and the conduction speed gradually decreases, so that the corresponding switch units can be turned on or off one by one, avoiding the synchronous on / off of all units, thereby reducing the peak value of the transient current, helping to smoothly control the switching of the signal and reduce the power supply fluctuation or electromagnetic interference caused by the transient current. If the width of the conductive structure gradually decreases, the parasitic capacitance of adjacent units can be reduced, the crosstalk between signals can be suppressed, and the isolation effect can be improved especially under high-frequency conditions.

[0010] In an optional implementation, the width of the conductive structure ranges from 20 nm to 1000 μm, and the width of the insulator structure ranges from 20 nm to 1000 μm.

[0011] In an optional embodiment, the thickness of the graphic structure layer ranges from to

[0012] In an optional implementation, the material of the conductive structure is at least one of amorphous silicon, polycrystalline silicon and metal, and the material of the insulator structure is silicon oxide or silicon dioxide.

[0013] In an optional embodiment, the thickness of the first buried oxide layer ranges from to The thickness of the second buried oxide layer ranges from to

[0014] In an optional implementation, the thickness of the polysilicon layer ranges from 0.5 μm to 5 μm.

[0015] In an optional embodiment, the thickness of the active layer ranges from to

[0016] In an optional implementation, the resistance of the semiconductor substrate layer ranges from 5000Ω to 20000Ω.

[0017] In a second aspect, the present invention provides a method for preparing a semiconductor structure, the method comprising: providing a first substrate sheet for forming an active layer and a second substrate sheet for forming a semiconductor substrate layer; based on a thermal oxidation process, growing oxide on a side surface of the first substrate sheet to form a second buried oxide layer; forming a graphic structure layer and a first buried oxide layer on a side surface of the second buried oxide layer away from the first substrate sheet, the graphic structure layer and the first buried oxide layer are stacked from bottom to top, the graphic structure layer comprises a plurality of conductive structures and a plurality of insulator structures, the plurality of conductive structures and the plurality of insulator structures are alternately arranged along a preset direction, and one side of adjacent conductive structures and insulator structures are abutted; performing ion implantation treatment on a side surface of the first buried oxide layer away from the graphic structure layer; depositing polysilicon on a side surface of the second substrate sheet to form a polysilicon layer; performing bonding treatment on a side surface of the polysilicon layer away from the second substrate sheet and a surface after the ion implantation treatment of the first buried oxide layer to obtain the semiconductor structure of the above-mentioned first aspect or any corresponding embodiment thereof.

[0018] In an optional embodiment, a graphic structure layer and a first buried oxide layer are formed on a surface of the second buried oxide layer away from the first substrate sheet, including: depositing a conductive material on a surface of the second buried oxide layer away from the first substrate sheet; etching the conductive material to form a plurality of conductive structures; and filling silicon oxide between the plurality of conductive structures to form a graphic structure layer and a first buried oxide layer.

[0019] In an optional embodiment, after bonding the surface of the polysilicon layer on one side away from the second substrate sheet and the surface after the ion implantation treatment of the first buried oxide layer, the method further comprises: performing a thermal annealing treatment on the semiconductor structure in an argon environment or in a mixed gas environment of argon and hydrogen, so that the surface roughness of the semiconductor structure is less than or equal to 0.5 nm, wherein the percentage of hydrogen is less than 5%.

[0020] In an optional implementation, the process parameters of the thermal annealing treatment include: a temperature range of 1000° C. to 1300° C., and a time range of 10 s to 600 s.

[0021] In an optional embodiment, the process parameters of the ion implantation process include: the implanted ions are hydrogen ions and / or helium ions, and the implantation dose is in the range of 1E15atom / cm 2 To 1E17atom / cm 2.

[0022] In an optional embodiment, the temperature of the thermal oxidation process ranges from 900°C to 1200°C.

[0023] In an optional implementation, the process parameters of the bonding process include: a temperature value range of 400° C. to 600° C., and a time value range of 1 min to 60 min. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0026] Figure 2 is a schematic diagram of another semiconductor structure according to an embodiment of the present invention;

[0027] Figure 3 is a schematic diagram of another semiconductor structure according to an embodiment of the present invention;

[0028] Figure 4 is a schematic structural diagram of forming a second buried oxide layer on a first substrate according to an embodiment of the present invention;

[0029] Figure 5 is a schematic diagram of a structure in which a conductive material is formed on a second buried oxide layer according to an embodiment of the present invention;

[0030] Figure 6 is a schematic structural diagram of forming a plurality of conductive structures on the second buried oxide layer according to an embodiment of the present invention;

[0031] Figure 7 is a schematic structural diagram of forming an image structure layer and a first buried oxide layer on a second buried oxide layer according to an embodiment of the present invention;

[0032] Figure 8 According to an embodiment of the present invention Figure 7 A schematic diagram of a structure for ion implantation based on the invention;

[0033] Fig. 9 is a schematic structural diagram of forming a polysilicon layer on a second substrate layer according to an embodiment of the present invention;

[0034] Fig.10 According to an embodiment of the present invention Figure 8 and Fig. 9 Schematic diagram of the structure after bonding treatment;

[0035] Fig.11 According to an embodiment of the present invention Fig.10 Schematic diagram of the structure after heating treatment.

[0036] Figure numerals: 10, semiconductor substrate layer; 20, polysilicon layer; 30, first buried oxide layer; 40, graphic structure layer; 41, conductive structure; 42, insulator structure; 50, second buried oxide layer; 60, active layer; 70, first substrate sheet; 71, injection layer; 80, conductive material; 90, second substrate sheet. DETAILED DESCRIPTION

[0037] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0038] In the following description, the description of known structures and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified for the purpose of clear expression, and some details may be omitted. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships between them are only exemplary, and may be deviated due to manufacturing tolerances or technical limitations in practice, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be a middle layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element.

[0039] SOI wafers are usually composed of top silicon (Device Layer), buried oxide layer (BOX) and substrate layer (Substrate). The top silicon is the silicon layer that eventually forms the semiconductor device. The buried oxide layer is generally a silicon dioxide (SiO2) layer, which plays the role of electrical isolation and reduces the parasitic effects of the device. The buried oxide layer can also be called an insulating layer. The substrate layer is usually a silicon base, which plays the role of mechanical support.

[0040] In the PDSOI metal oxide semiconductor field effect transistor (MOSFET) formed by the above-mentioned SOI wafer, a floating body region is easily formed between the drain region and the substrate, and the floating body region will accumulate charges to form a floating body voltage (also known as the floating body effect), which affects the electrical performance of the PDSOI MOSFET. Among them, MOSFET can be referred to as MOS tube.

[0041] Specifically, the floating voltage affects the threshold voltage of the MOS tube. For example, a positive floating voltage will reduce the threshold voltage, thereby increasing the leakage current, and a negative floating voltage will increase the threshold voltage. The floating voltage will also change dynamically with the change of the device working state, resulting in an unstable threshold voltage.

[0042] Moreover, the change of floating body voltage will also cause parasitic bipolar transistor effect, further affecting the threshold voltage of the device. In addition, floating body voltage will reduce the subthreshold swing of the device, affect the switching speed or switching ratio, and cause unstable operating current. The floating body voltage will also cause heat to be generated in the floating channel area, causing the device temperature to rise, further deteriorating the operating current characteristics of the device.

[0043] In view of this, the present invention provides a semiconductor structure, which can adjust the threshold voltage of the semiconductor device and flexibly optimize key radio frequency (RF) performance indicators such as gain, noise and linearity of the semiconductor device by setting a graphic structure layer of alternating conductive structures and insulator structures in the buried oxide layer.

[0044] It should be understood that the above-mentioned semiconductor device is a semiconductor device formed based on the semiconductor structure provided by the present invention.

[0045] The semiconductor structure provided by the present invention can be used to form a PDSOI MOS tube or other semiconductor devices, and the formed semiconductor devices can be applied in the RF field. The semiconductor structure provided by the present invention is described below in conjunction with the accompanying drawings.

[0046] like Figure 1 As shown, the semiconductor structure provided by the present invention includes a semiconductor substrate layer 10 , a polysilicon layer 20 , a first buried oxide layer 30 , a pattern structure layer 40 , a second buried oxide layer 50 and an active layer 60 .

[0047] Among them, the polysilicon layer 20 is located on one side surface of the semiconductor substrate layer 10, the first buried oxide layer 30 is located on the side surface of the polysilicon layer 20 away from the semiconductor substrate layer 10, the graphic structure layer 40 is located on the side surface of the first buried oxide layer 30 away from the polysilicon layer 20, the second buried oxide layer 50 is located on the side surface of the graphic structure layer 40 away from the first buried oxide layer 30, and the active layer 60 is located on the side surface of the second buried oxide layer 50 away from the graphic structure layer 40.

[0048] That is, in Figure 1 In the perspective (side perspective), the semiconductor substrate layer 10, the polysilicon layer 20, the first buried oxide layer 30, the pattern structure layer 40, the second buried oxide layer 50 and the active layer 60 are stacked from bottom to top.

[0049] Specifically, the semiconductor substrate layer 10 may be a conventional semiconductor substrate such as silicon (Si) or germanium (Ge), and may have a certain type of doping. The semiconductor substrate layer 10 may also be a high-resistance substrate having a resistance greater than or equal to 5000Ω. In one example, the resistance of the semiconductor substrate layer 10 may range from 5000Ω to 20000Ω. For example, the resistance of the semiconductor substrate layer 10 may be 5000Ω, 5500Ω, 6000Ω, 6500Ω, 7000Ω, 8000Ω, 9000Ω, 10000Ω, 12000Ω, 18000Ω or 20000Ω, etc.

[0050] In RF devices, low parasitic capacitance is essential for achieving high-frequency operation. The semiconductor substrate layer 10 has a high resistivity, which can effectively reduce parasitic capacitance and leakage current, and provide better insulation performance, prevent charge leakage between different layers, and ensure the normal operation of semiconductor devices. Limiting the resistance of the semiconductor substrate layer 10 to between 5000Ω and 20000Ω can give full play to the advantages of the high-resistance silicon substrate while taking into account the difficulty of the manufacturing process, avoiding increased difficulty of the manufacturing process and increased costs.

[0051] The material of the polysilicon layer 20 may be polysilicon, the materials of the first buried oxide layer 30 and the second buried oxide layer 50 may be silicon dioxide (SiO2), and the active layer 60 may be formed based on single crystal silicon to form a semiconductor device.

[0052] Exemplarily, the material of the active layer 60 may also be one or more of silicon germanium alloy (SiGe), III-V materials (such as gallium arsenide (GaAs) or indium phosphide (InP)), aluminum nitride (AlN), gallium nitride (GaN) or silicon carbide (SiC).

[0053] Specifically, silicon germanium alloys are used for strain engineering, optimizing electron mobility, and can be used to form complementary metal oxide semiconductor (CMOS) devices or radio frequency (RF) devices. III-V materials are used to achieve high-speed electronic or optoelectronic properties, and can be used to form optoelectronic devices (such as lasers, light emitting diodes (LEDs)) or high-frequency devices, which require buffer layers or special treatments when there is lattice mismatch.

[0054] Aluminum nitride or gallium nitride is used in high electron mobility transistors (HEMTs), which are particularly suitable for high-power and high-frequency applications. Aluminum nitride or gallium nitride can be used to form power amplifiers or 5G communication base stations, which need to overcome differences in thermal expansion coefficients and lattice mismatch. Silicon carbide is used in high-power and high-temperature resistant applications and can be used to form power devices (such as MOS tubes, insulated gate bipolar transistors (IGBT), etc.), and the cost of silicon carbide epitaxy is relatively high.

[0055] When epitaxially growing the active layer 60, the mismatch rate needs to be controlled to avoid dislocations. Due to the difference in thermal expansion coefficients, the stress during material heating and cooling also needs to be controlled when epitaxially growing the active layer 60. Moreover, the defect density and quality of the interface are crucial to device performance, so the interface quality also needs to be controlled.

[0056] The graphic structure layer 40 includes a plurality of conductive structures 41 and a plurality of insulating structures 42, wherein the plurality of conductive structures 41 and the plurality of insulating structures 42 are alternately arranged along a preset direction, and one side of adjacent conductive structures 41 and insulating structures 42 abuts against each other. The preset direction may be a horizontal direction, and the thickness of the conductive structure 41 and the thickness of the insulating structure 42 may be the same or different.

[0057] Specifically, a plurality of conductive structures 41 may be arranged horizontally and spaced apart on the upper surface of the first buried oxide layer 30, and a plurality of insulator structures 42 may be arranged in the interval between two adjacent conductive structures 41, and there is no interval between the insulator structure 42 and the conductive structure 41. Figure 1 As shown, the right end surface of the first conductive structure 41 is connected to the left end surface of the first insulator structure 42 , and the left end surface of the second conductive structure 41 is connected to the right end surface of the first insulator structure 42 .

[0058] The present invention does not limit the specific materials of the conductive structure 41 and the insulating structure 42, as long as the conductive structure 41 meets the conductive requirements and the insulating structure 42 meets the insulating requirements. For example, the material of the conductive structure 41 can be at least one of amorphous silicon, polycrystalline silicon and metal, and the material of the insulating structure 42 can be an insulating material such as silicon oxide or silicon dioxide.

[0059] The semiconductor structure provided in this embodiment has a graphic structure layer 40 arranged in the buried oxide layer, which is equivalent to introducing a back gate into the SOI structure. By adjusting the back gate voltage, the electrical performance of the semiconductor device can be adjusted more flexibly, so that the SOI structure can meet different application requirements.

[0060] After the back gate is introduced, firstly, the parasitic capacitance of the semiconductor device can be reduced, and the maximum operating frequency and gain bandwidth product (GBW) of the semiconductor device can be improved.

[0061] Specifically, the charge distribution of the silicon body layer in the semiconductor device can be actively controlled through the back gate, further reducing the capacitance effect between the positive gate and the body layer, and increasing the cutoff frequency of the device, thereby improving the maximum operating frequency and gain-bandwidth product of the semiconductor device.

[0062] The relationship between the cut-off frequency and the parasitic capacitance can be expressed as follows:

[0063]

[0064] In formula (1), f T represents the cut-off frequency, g m Indicates the transconductance of the MOS tube, the unit is A / V, C gs It represents the gate-source parasitic capacitance, that is, the parasitic capacitance between the gate and source of the MOS tube, C gd It represents the gate-drain parasitic capacitance, that is, the parasitic capacitance between the gate and drain of the MOS tube, C gs +C gd Represents the total gate parasitic capacitance.

[0065] It can be seen from the above formula (1) that the parasitic capacitance of the semiconductor device is inversely proportional to the cut-off frequency. The smaller the parasitic capacitance, the higher the cut-off frequency, that is, the semiconductor device can operate at a higher frequency. Therefore, after reducing the parasitic capacitance of the semiconductor device through the back gate, the cut-off frequency of the device can be increased, thereby increasing the maximum operating frequency of the semiconductor device.

[0066] The relationship between the gain-bandwidth product and the parasitic capacitance can be expressed as formula (2):

[0067]

[0068] In formula (2), GBW represents the gain-bandwidth product, which represents the product of the amplifier's gain and bandwidth. L Represents the load capacitance, which includes the parasitic capacitance of semiconductor devices and external capacitance.

[0069] It can be seen from the above formula (2) that the parasitic capacitance of the semiconductor device is inversely proportional to the gain-bandwidth product. When the parasitic capacitance increases, the gain-bandwidth product decreases, and when the parasitic capacitance decreases, the gain-bandwidth product increases. Therefore, after reducing the parasitic capacitance of the semiconductor device through the back gate, the gain-bandwidth product can be improved.

[0070] Specifically, lower parasitic capacitance reduces signal delay and charge accumulation time, enabling devices to respond quickly at higher frequencies while reducing high-frequency losses and improving the performance of RF switching devices.

[0071] Secondly, the linear characteristics of semiconductor devices can be optimized and distortion can be reduced. Specifically, through the coordinated operation of the front gate and the back gate, the potential of the body layer can be controlled, so that the charge distribution in the channel is more uniform, and the threshold voltage drift and on-current change caused by the body layer potential fluctuation can be reduced, thereby reducing the nonlinear effect, improving the linearity of the device and reducing distortion.

[0072] The nonlinearity of semiconductor devices means that the relationship between the input signal and the output signal of the semiconductor device is not linear, that is, the output signal is no longer a simple multiple relationship. If the semiconductor device has nonlinear effects, the output signal will contain multiple harmonic components of the input signal frequency, resulting in signal distortion and harmonic distortion.

[0073] Thirdly, the anti-interference ability of semiconductor devices to external signals can be enhanced. Specifically, after the back gate is introduced, the back gate can play the role of shielding and regulating the body layer potential, thereby suppressing the floating of the body layer and enhancing the anti-interference ability of the semiconductor device. That is, the back gate can stabilize the body layer potential by applying an appropriate bias, so that the device has better robustness when facing external interference signals, reduces the impact of noise on signal processing, and thus improves the signal integrity of the device.

[0074] Fourthly, it can effectively absorb and conduct the heat generated by the device, improve thermal management, and enhance the reliability of semiconductor devices. Specifically, the back gate can provide a new heat dissipation path for semiconductor devices, and the back gate is close to the body layer, which can absorb the heat caused by high-speed switching and high current, and transfer the heat through the thermal conductive material, thereby improving thermal management, reducing the operating temperature of the device, and improving the reliability and stability of the device.

[0075] Fifthly, key RF performance indicators such as gain, noise and linearity of semiconductor devices can be flexibly optimized. Specifically, different characteristics of semiconductor devices can be regulated by the coordinated work of the front gate and the back gate. For example, the on-current and threshold voltage of the semiconductor device can be controlled by the front gate, and the body layer potential can be further adjusted by the back gate, thereby affecting the charge distribution of the channel, so that designers can flexibly adjust the gain of semiconductor devices according to different application requirements.

[0076] Through the coordinated work of the front gate and the back gate, the gain and response characteristics of the semiconductor device can be dynamically optimized according to the frequency and amplitude of the input signal to obtain the best signal amplification performance. At the same time, unnecessary noise and distortion can be reduced through back gate regulation, further enhancing the high-frequency performance of the semiconductor device.

[0077] The present invention does not limit the specific shape and size of the conductive structure 41 and the insulating structure 42, as long as the image structure layer 40 is disposed in the buried oxide layer. For example, for the convenience of processing, the conductive structure 41 and the insulating structure 42 can be rectangular.

[0078] The width of the conductive structure 41 may be greater than or equal to the width of the insulating structure 42, or the width of the conductive structure 41 may be less than the width of the insulating structure 42. The widths of the plurality of conductive structures 41 may be the same or different. Accordingly, the widths of the plurality of insulating structures 42 may also be the same or different.

[0079] Among them, Figure 1 As shown, the width of the conductive structure 41 refers to the length L1 of the conductive structure 41 in the horizontal direction, and the width of the insulator structure 42 refers to the length L2 of the insulator structure 42 in the horizontal direction.

[0080] The width of the conductive structure 41 and the width of the insulator structure 42 can be determined by the designer according to the process requirements. In one example, the width of the conductive structure 41 can range from 20nm to 1000μm, and the width of the insulator structure 42 can range from 20nm to 1000μm.

[0081] That is, the width of the conductive structure 41 may be any value between 20 nm and 1000 μm, for example, the width of the conductive structure 41 may be 20 nm, 28 nm, 30 nm, 36 nm, 50 nm, 80 nm, 100 nm, 10 μm, 100 μm, 500 μm or 1000 μm, etc. The width of the insulator structure 42 may be any value between 20 nm and 1000 μm, for example, the width of the insulator structure 42 may be 20 nm, 28 nm, 40 nm, 60 nm, 80 nm, 100 nm, 1 μm, 10 μm, 100 μm, 800 μm or 1000 μm, etc.

[0082] In some embodiments, the width of the conductive structure 41 is less than or equal to the width of the insulator structure 42 .

[0083] Specifically, conductive structures 41 of different widths can provide different degrees of back-gate effect, thereby flexibly adjusting the threshold voltage of the semiconductor device. A narrower conductive structure 41 may generate a stronger electric field and have a more significant effect on adjusting the threshold voltage, while a wider conductive structure 41 may reduce leakage current and provide a better electric field shielding effect.

[0084] Limiting the width of the conductive structure 41 to between 20 nm and 1000 μm can better optimize the electrical performance with a lower manufacturing process difficulty.

[0085] The width of the insulator structure 42 affects the capacitive coupling between the back gate and the channel. A narrower insulator structure 42 width may increase the capacitive coupling, making the back gate more sensitive to the channel, and helping to achieve higher gain and better subthreshold characteristics. A wider insulator structure can provide better insulation performance, reduce the generation of leakage current, and improve the performance and stability of semiconductor devices.

[0086] By limiting the width of the insulator structure 42 to between 20 nm and 1000 μm, the electrical performance of the semiconductor device can be better optimized with a lower difficulty of the manufacturing process, so that the semiconductor structure can meet the requirements of different applications.

[0087] Exemplarily, the widths of the plurality of conductive structures 41 and the widths of the plurality of insulator structures 42 are changed according to a preset rule, wherein the preset rule can be determined by a designer according to process requirements.

[0088] For example, Figure 2 As shown, the widths of the plurality of conductive structures 41 and the plurality of insulating structures 42 increase (or decrease) from left to right, that is, the difference in width between two adjacent conductive structures 41 is equal, and the difference in width between two adjacent insulating structures 42 is equal.

[0089] For example, Figure 3 As shown, the widths of the plurality of conductive structures 41 vary gradually from left to right, that is, the width differences of two adjacent conductive structures 41 are not equal.

[0090] Specifically, the width of each conductive structure 41 changes, affecting the gate capacitance and on-resistance of the corresponding semiconductor device. If the width of each conductive structure 41 is different, the on-speed of the semiconductor device corresponding to each conductive structure 41 is correspondingly different.

[0091] In this embodiment, if the width of the conductive structure 41 gradually increases, the gate capacitance of the corresponding switch unit increases successively, and the conduction speed gradually decreases, so that the corresponding switch units can be turned on or off one by one, avoiding the synchronous on / off of all units, thereby reducing the peak value of the transient current, helping to smooth the control signal switching, and reducing the power supply fluctuation or electromagnetic interference (EMI) caused by the transient current.

[0092] At the same time, by gradually changing the width of the conductive structure 41, the capacitive coupling between adjacent switch units can be reduced to a certain extent. Specifically, if the width of the conductive structure 41 is gradually reduced, the parasitic capacitance of adjacent units can be reduced, the crosstalk between signals can be suppressed, and the isolation effect can be improved especially under high frequency conditions.

[0093] For example, the thickness of the graphic structure layer 40 may range from to That is to say, the thickness of the graphic structure layer 40 can be to For example, the thickness of the graphic structure layer 40 can be or wait.

[0094] Specifically, back gates of different thicknesses can generate electric fields of different strengths, thereby flexibly regulating the carrier concentration and conductivity in the channel. A thinner back gate can generate a stronger electric field, which is more sensitive to carrier control and helps achieve higher switching speeds and lower power consumption. A thicker back gate can provide a more uniform electric field, reduce carrier scattering, and thus improve carrier mobility.

[0095] The present invention does not specifically limit the thicknesses of the polysilicon layer 20 , the first buried oxide layer 30 , the second buried oxide layer 50 and the active layer 60 , and the thicknesses can be set by designers according to application scenarios and design requirements.

[0096] In one example, the thickness of the polysilicon layer 20 may range from 0.5 μm to 5 μm. That is, the thickness of the polysilicon layer 20 may be any value between 0.5 μm and 5 μm. For example, the thickness of the polysilicon layer 20 may be 0.5 μm, 0.8 μm, 1 μm, 1.2 μm, 1.8 μm, 2 μm, 3 μm, 3.5 μm, 4 μm, or 5 μm.

[0097] Specifically, the polysilicon layer 20 can be used as a back gate electrode. By adjusting the back gate voltage, the threshold voltage of the semiconductor device and the carrier concentration in the channel can be controlled. The polysilicon layer can also play a shielding role, reducing the parasitic capacitance between the buried oxide layer and the substrate layer, thereby improving the switching speed and power consumption of the semiconductor device.

[0098] A thicker polysilicon layer can provide a stronger back gate effect, thereby more effectively adjusting the threshold voltage, and a thinner polysilicon layer can reduce parasitic capacitance. Moreover, a thinner polysilicon layer 20 may cause non-uniformity and defects in the manufacturing process, while an overly thick polysilicon layer 20 may increase process difficulty and cost.

[0099] In this embodiment, the thickness of the polysilicon layer 20 is limited to between 0.5 μm and 5 μm, which can achieve a balance between reducing parasitic capacitance and ensuring the performance of the back gate electrode while ensuring the feasibility and stability of the manufacturing process.

[0100] For example, the thickness of the first buried oxide layer 30 may range from to The thickness of the second buried oxide layer 50 can range from to For example, the thickness of the first buried oxide layer 30 may be or The thickness of the second buried oxide layer 50 can be or wait.

[0101] Specifically, the thickness of the first buried oxide layer is limited to to The back gate and the semiconductor substrate layer 10 can be completely separated to provide a stronger insulation isolation effect, thereby reducing the electrical interference of the semiconductor substrate layer on the back gate. Moreover, it can provide a certain mechanical support for the upper graphic structure layer 40, the second buried oxide layer 50 and the active layer 60, thereby reducing the structural deformation caused by external stress or process.

[0102] The thickness of the second buried oxide layer is limited to to It can provide effective insulation isolation while enhancing the capacitive coupling between the back gate and the upper conductive structure, making the back gate more sensitive to the control of the upper channel.

[0103] Exemplarily, the thickness of the active layer 60 may range from to That is, the thickness of the active layer 60 may be to For example, the thickness of the active layer 60 may be

[0104] or wait.

[0105] Specifically, the thickness of the active layer 60 also affects the threshold voltage of the semiconductor device. By adjusting the thickness of the active layer 60, the electric field distribution and carrier concentration in the channel can be changed, thereby adjusting the magnitude of the threshold voltage.

[0106] like Figures 4 to 11 As shown, an embodiment of the present invention further provides a method for preparing a semiconductor structure, and the method includes but is not limited to steps S101 to S106.

[0107] Step S101 , providing a first substrate sheet for forming an active layer and a second substrate sheet for forming a semiconductor substrate layer.

[0108] Exemplarily, the first substrate sheet may be a silicon substrate sheet having a resistivity of 0 ohm-cm to 100 ohm-cm, and the second substrate sheet may be a high-resistance silicon substrate sheet having a resistivity greater than 1000 ohm-cm.

[0109] Step S102: Based on a thermal oxidation process, oxide is grown on a surface of one side of the first substrate to form a second buried oxide layer.

[0110] Specifically, the cleaned first substrate is placed in a high temperature oxidation furnace, and the temperature of the high temperature oxidation furnace is controlled at 900° C. to 1200° C. At high temperature, oxygen reacts chemically with the first substrate, such as Figure 4 As shown, silicon dioxide is grown on one side surface (such as the upper surface) of the first substrate sheet 70 to form a second buried oxide layer 50 .

[0111] Before performing subsequent processes, the first substrate sheet is cleaned to remove impurities and contaminants present in the first substrate sheet, thereby ensuring the quality and reliability of subsequent processes.

[0112] In one example, the thickness of the second buried oxide layer 50 may be to

[0113] Step S103, forming a pattern structure layer and a first buried oxide layer on a surface of the second buried oxide layer away from the first substrate.

[0114] Specifically, the above step S103 includes steps S1031 to S1033:

[0115] Step S1031 , depositing a conductive material on a surface of the second buried oxide layer that is away from the first substrate.

[0116] For example, the deposition method may be chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0117] Specifically, Figure 5 As shown, after the second buried oxide layer 50 is formed, a conductive material 80 may be deposited on the upper surface of the second buried oxide layer 50 by CVD.

[0118] Step S1032, etching the conductive material to form a plurality of conductive structures.

[0119] For example, in forming Figure 5 After the structure shown in FIG. 1 is formed, step S1032 may specifically include: forming a photoresist layer on the upper surface of the conductive material; exposing the photoresist layer; after the exposure, developing the photoresist layer; after the development of the photoresist layer, etching the conductive material using the remaining photoresist of the photoresist layer as a mask; removing the photoresist on the conductive material to obtain a conductive film as shown in FIG. Figure 6 A plurality of conductive structures 41 are shown.

[0120] In one example, the thickness of the plurality of conductive structures 41 may be to

[0121] Step S1033, filling silicon oxide between the plurality of conductive structures to form a graphic structure layer and a first buried oxide layer.

[0122] Specifically, in forming Figure 6 After the structure shown in FIG. 1 is formed, silicon oxide is filled between the plurality of conductive structures by a CVD process, and the spaces between the plurality of conductive structures 41 are filled with silicon oxide, forming a structure as shown in FIG. Figure 7 The pattern structure layer 40 and the first buried oxide layer 30 are shown.

[0123] For example, when the thickness of the first buried oxide layer 30 is greater than the preset thickness, part of the silicon oxide can be removed by chemical mechanical polishing (CMP) to make the thickness of the first buried oxide layer 30 the preset thickness. The preset thickness can be determined by the designer based on the process requirements. For example, the thickness of the first buried oxide layer 30 can be to

[0124] like Figure 7As shown, the graphic structure layer 40 and the first buried oxide layer 30 are stacked from bottom to top, and the graphic structure layer 40 includes a plurality of conductive structures 41 and a plurality of insulating structures 42. The plurality of conductive structures 41 and the plurality of insulating structures 42 are alternately arranged along a preset direction, and one side of adjacent conductive structures 41 and insulating structures 42 is abutted.

[0125] Step S104, performing ion implantation treatment on a surface of the first buried oxide layer away from the pattern structure layer.

[0126] Specifically, in forming Figure 7 After the structure shown in Figure 8 As shown, an ion implantation machine is used to perform ion implantation on the upper surface of the first buried oxide layer 30 to form an implantation layer 71 in the first substrate sheet.

[0127] The implanted ion type may include hydrogen ions and / or helium ions, that is, the implanted ion type may be hydrogen ions or helium ions, or may be hydrogen ions and helium ions, and the implanted dose may range from 1E15atom / cm 2 To 1E17atom / cm 2 For example, the implantation dose can be 1E15atom / cm 2 、1E16atom / cm 2 or 1E15atom / cm 2 In addition, the implantation depth can be determined based on the thickness of the active layer. When the implanted ions include hydrogen ions and helium ions, the hydrogen ions and helium ions are implanted sequentially.

[0128] Step S105 , depositing polysilicon on one side surface of the second substrate to form a polysilicon layer.

[0129] Specifically, Fig. 9 As shown, polysilicon can be deposited on the upper surface of the second substrate sheet 90 by a CVD process to form a polysilicon layer 20. The thickness of the polysilicon layer 20 can be 0.5 μm to 5 μm, and the temperature during the deposition process can be 900° C. to 1200° C. The second substrate sheet 90 forms a semiconductor substrate layer 10.

[0130] Step S106 , bonding the surface of the polysilicon layer away from the second substrate and the surface of the first buried oxide layer after the ion implantation to obtain a semiconductor structure.

[0131] Specifically, when obtaining Fig. 9 After the structure shown in FIG. 1 is formed, the upper surface of the polysilicon layer 20 and the first buried oxide layer 30 are bonded to each other. Figure 8 The structure shown and Fig. 9 The structures shown are combined together to obtain Fig.10The initial SOI structure is then placed in a heating furnace to separate the first substrate sheet 70 at the implantation layer 71 to obtain the initial SOI structure shown in FIG. Fig.11 The SOI structure shown.

[0132] The temperature during the bonding process may be 400° C. to 600° C., and the bonding process time may be 1 min to 60 min.

[0133] In some optional embodiments, after the bonding process is performed, the method for preparing the semiconductor structure further includes: performing a thermal annealing process on the semiconductor structure in an argon environment or in a mixed gas environment of argon and hydrogen, so that the surface roughness of the semiconductor structure is less than or equal to 0.5 nm. Specifically, in the mixed gas environment of argon and hydrogen, the percentage of hydrogen is less than 5%.

[0134] The temperature of the thermal annealing treatment may be 1000° C. to 1300° C., and the time of the thermal annealing treatment may be 10s to 600s. For example, the temperature of the thermal annealing treatment may be 1000° C., 1200° C., 1250° C., or 1300° C., and the time of the thermal annealing treatment may be 10s, 30s, 100s, 200s, 300s, 360s, 500s, or 600s.

[0135] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0136] In the description of this specification, the description with reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples, unless otherwise clearly and specifically defined. In addition, the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0137] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0138] The above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described above, and that various obvious changes, readjustments, combinations and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present invention, and the scope of protection of the present invention is determined by the attached scope of protection.

Claims

1. A semiconductor structure, characterized in that: The semiconductor structure comprises: Semiconductor substrate layer; A polysilicon layer, located on one side surface of the semiconductor substrate layer; A first buried oxide layer is located on a surface of the polysilicon layer on a side away from the semiconductor substrate layer; A graphic structure layer is located on a surface of the first buried oxide layer away from the polysilicon layer, the graphic structure layer includes a plurality of conductive structures and a plurality of insulating structures, the plurality of conductive structures and the plurality of insulating structures are alternately arranged along a preset direction, and one side of adjacent conductive structures and insulating structures abuts against each other; A second buried oxide layer is located on a surface of the pattern structure layer away from the first buried oxide layer; The active layer is located on a surface of the second buried oxide layer away from the pattern structure layer.

2. The semiconductor structure according to claim 1, characterized in that: The width of the conductive structure is less than or equal to the width of the insulator structure.

3. The semiconductor structure according to claim 1, characterized in that: The widths of the plurality of conductive structures and the widths of the plurality of insulator structures vary according to a preset rule.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The width of the conductive structure ranges from 20 nm to 1000 μm, and the width of the insulator structure ranges from 20 nm to 1000 μm.

5. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The thickness of the graphic structure layer ranges from to 6. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The material of the conductive structure is at least one of amorphous silicon, polycrystalline silicon and metal, and the material of the insulator structure is silicon oxide or silicon dioxide.

7. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The thickness of the first buried oxide layer ranges from to The thickness of the second buried oxide layer ranges from to 8. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The thickness of the polysilicon layer ranges from 0.5 μm to 5 μm.

9. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The thickness of the active layer ranges from to 10. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The resistance of the semiconductor substrate layer ranges from 5000Ω to 20000Ω.

11. A method for preparing a semiconductor structure, characterized in that: The method comprises: Providing a first substrate sheet forming an active layer and a second substrate sheet forming a semiconductor substrate layer; Based on a thermal oxidation process, an oxide is grown on a surface of one side of the first substrate to form a second buried oxide layer; A graphic structure layer and a first buried oxide layer are formed on a surface of the second buried oxide layer away from the first substrate, wherein the graphic structure layer and the first buried oxide layer are stacked from bottom to top, and the graphic structure layer includes a plurality of conductive structures and a plurality of insulator structures, wherein the plurality of conductive structures and the plurality of insulator structures are alternately arranged along a preset direction, and one side of adjacent conductive structures and insulator structures abuts against each other; Performing ion implantation on a surface of the first buried oxide layer away from the graphic structure layer; Depositing polysilicon on one side surface of the second substrate to form a polysilicon layer; A bonding process is performed on a surface of the polysilicon layer on one side away from the second substrate and a surface of the first buried oxide layer after ion implantation to obtain a semiconductor structure as claimed in any one of claims 1 to 10.

12. The method according to claim 11, characterized in that A pattern structure layer and a first buried oxide layer are formed on a surface of the second buried oxide layer away from the first substrate, comprising: Depositing a conductive material on a surface of the second buried oxide layer away from the first substrate; Etching the conductive material to form a plurality of conductive structures; Silicon oxide is filled between the plurality of conductive structures to form the graphic structure layer and the first buried oxide layer.

13. The method according to claim 11, characterized in that After bonding the surface of the polysilicon layer away from the second substrate and the surface of the first buried oxide layer after the ion implantation, the method further includes: The semiconductor structure is subjected to thermal annealing in an argon environment or in a mixed gas environment of argon and hydrogen, so that the surface roughness of the semiconductor structure is less than or equal to 0.5 nm, wherein the percentage of the hydrogen is less than 5%.

14. The method according to claim 13, characterized in that The process parameters of the thermal annealing treatment include: a temperature value range of 1000° C. to 1300° C., and a time value range of 10s to 600s.

15. The method according to any one of claims 11 to 14, characterized in that The process parameters of the ion implantation process include: the implanted ions are hydrogen ions and / or helium ions, and the implanted dose is in the range of 1E15atom / cm 2 To 1E17atom / cm 2 .

16. The method according to any one of claims 11 to 14, characterized in that The temperature of the thermal oxidation process ranges from 900°C to 1200°C.

17. The method according to any one of claims 11 to 14, characterized in that The process parameters of the bonding process include: a temperature range of 400° C. to 600° C., and a time range of 1 min to 60 min.

Images