Chip preparation method based on reverse molding process, chip and three-dimensional packaging structure
Through the chip preparation method based on the inverted mold process, the bonding glue and temporary substrate technology is used to solve the problem of easy damage to the hidden cutting film after the water washing step, and the effect of protecting the hidden cutting film and improving the utilization rate of the wafer layer is achieved.
Patent Information
- Application Number
- CN202411800134.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-09
- Publication Date
- 2025-03-28
AI Technical Summary
The hidden cutting film of the semiconductor structure is prone to wrinkles and damage after washing steps, which affects the subsequent process.
The chip preparation method based on the mold reversing process is adopted, and the bonding glue and temporary substrate are used to avoid damage to the cryptic film by the water washing step, and the bonding film is removed by laser or other means.
The hidden cutting film is protected from the influence of steps such as water washing, avoiding damage to the hidden cutting film and subsequent processes, and improving the utilization rate of the wafer layer.
Smart Images
Figure CN119725157A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of integrated circuit technology, and in particular to a chip preparation method based on a reverse molding process, a chip, and a three-dimensional packaging structure. Background Art
[0002] The debonding process of semiconductor structures often includes laser irradiation, removal of temporary substrates, multiple water washings to remove impurities, removal of residues, debonding, plasma cleaning and other steps. During this process, the wafer is usually placed on a kerf film. After a series of steps such as water washing, the kerf film is prone to wrinkles and damage, which in turn affects the subsequent kerf process and vacuum adsorption process of the wafer.
[0003] Therefore, how to optimize the debonding process has become a technical problem that needs to be solved urgently. Summary of the invention
[0004] Based on this, it is necessary to provide a chip preparation method, chip and three-dimensional packaging structure based on the reverse molding process to address the problem that the hidden cutting film in the prior art may be damaged.
[0005] In order to achieve the above object, on the one hand, a chip preparation method based on a reverse molding process is provided, comprising:
[0006] Providing an incoming material structure, the incoming material structure comprising a wafer layer, a bonding adhesive and a first temporary substrate, the bonding adhesive being located between the wafer layer and the first temporary substrate, the wafer layer having a second surface and a first surface that are oppositely disposed, the first surface facing the bonding adhesive and having solder balls;
[0007] removing the bonding glue and the first temporary substrate, and forming a first bonding film and a second temporary substrate on the first surface;
[0008] attaching the wafer layer to the hidden cutting film through the second surface;
[0009] removing the first bonding film and the second temporary substrate;
[0010] The wafer layer is diced based on the hidden cutting film to form a plurality of chips.
[0011] In one embodiment, removing the first bonding film and the second temporary substrate includes:
[0012] irradiating the first bonding film with a preset light;
[0013] The first bonding film is peeled off, and the second temporary substrate is removed.
[0014] In one embodiment, removing the bonding glue and the first temporary substrate and forming a first bonding film and a second temporary substrate on the first surface includes:
[0015] forming a second bonding film and a third temporary substrate on the second surface;
[0016] removing the bonding glue and the first temporary substrate to expose the first surface and the solder balls;
[0017] forming the first bonding film and the second temporary substrate on the first surface;
[0018] The second bonding film and the third temporary substrate are removed.
[0019] In one embodiment, before removing the bonding glue and the first temporary substrate to expose the first surface and the solder balls, the method includes:
[0020] attaching a side of the third temporary substrate facing away from the second bonding film to the first fixing layer;
[0021] After removing the bonding glue and the first temporary substrate to expose the first surface and the solder balls, the method includes:
[0022] The first fixing layer is removed.
[0023] In one embodiment, before removing the second bonding film and the third temporary substrate, the method includes:
[0024] Attaching the second temporary substrate, with the side facing away from the first bonding film, to the second fixing layer;
[0025] After removing the second bonding film and the third temporary substrate, the method further comprises:
[0026] The second fixing layer is removed.
[0027] In one embodiment, providing the incoming material structure includes:
[0028] Providing a wafer initial structure, the wafer initial structure comprising a wafer initial layer and a conductive through-hole structure, and the wafer initial structure having a first initial surface and a second initial surface, the first initial surface having the solder ball, the conductive through-hole structure connecting the solder ball and extending in the wafer initial layer, and the conductive through-hole structure and the second initial surface being spaced apart;
[0029] Bonding the first initial surface of the wafer initial structure to the first temporary substrate by means of the bonding adhesive;
[0030] The wafer initial layer is ground and thinned from the second initial surface to expose the conductive through-hole structure and form a wafer layer from the wafer initial structure.
[0031] In one embodiment, the step of grinding and thinning the wafer initial layer from the second initial surface to expose the conductive via structure and form the wafer initial structure into a wafer layer includes:
[0032] Performing a first grinding on the initial layer of the wafer from the second initial surface to expose the conductive via structure;
[0033] Etching the wafer initial layer so that the conductive via structure protrudes from the wafer initial layer;
[0034] The protruding conductive via structure is subjected to a second grinding so that the wafer initial structure forms a wafer layer.
[0035] In one embodiment, before bonding the first initial surface of the wafer initial structure to the first temporary substrate by bonding adhesive, the method further includes:
[0036] The wafer initial structure is circularly cut from the first initial surface to form a circular cutting space.
[0037] On the one hand, a chip is also provided, wherein the chip is prepared using the chip preparation method based on the reverse molding process as described in any of the above.
[0038] On the one hand, a three-dimensional packaging structure is also provided, wherein the three-dimensional packaging structure is formed by stacking a plurality of chips prepared by the chip preparation method based on the reverse molding process as described in any one of the above.
[0039] The chip preparation method, chip and three-dimensional packaging structure based on the reverse molding process of the present application have the following beneficial effects: First, a first bonding film and a first temporary substrate are formed on the first surface, so that the first bonding film can be removed by laser or other methods, without the need to set up water washing, drug washing and other steps, thereby protecting the hidden cutting film from being damaged by water washing and other steps. Moreover, the bonding adhesive used in the present application is used to bond the wafer layer and the first temporary substrate, thereby avoiding the movement of the wafer layer in the previous steps (for example, grinding, etc.). BRIEF DESCRIPTION OF THE DRAWINGS
[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0041] Figures 1 to 11 It is a schematic diagram of the structure obtained by the traditional technology;
[0042] Fig.12 It is a flow chart of a chip preparation method based on a reverse molding process provided in an embodiment;
[0043] Figures 13 to 22 It is a schematic diagram of an intermediate structure obtained in a chip preparation method based on a reverse molding process provided in an embodiment.
[0044] Explanation of the reference numerals: incoming material structure-100; wafer layer-110; solder ball-111; conductive via structure-112; bonding glue-120; first temporary substrate-121; first bonding film-130; second temporary substrate-131; hidden cutting film-140; patch ring-141; chip-150; protective layer-160; second bonding film-170; third temporary substrate-171; first fixed layer-180; second fixed layer-181.
[0045] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood. DETAILED DESCRIPTION
[0046] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.
[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.
[0048] In each embodiment, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in each embodiment can be understood according to the specific situation.
[0049] It should be understood that when an element or layer is referred to as being "on, adjacent to, or connected to other elements or layers, it may be directly on, adjacent to, or connected to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, or directly connected to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present embodiment, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part.
[0050] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0051] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0052] Embodiments of the present specification are described herein with reference to cross-sectional views that are schematic representations of ideal embodiments (and intermediate structures) of the present specification, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present specification should not be limited to the specific shapes of the regions shown herein, but include deviations in shapes due to, for example, manufacturing techniques. The regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the embodiments of the present specification.
[0053] As mentioned in the background art, the semiconductor structure's hidden cut film is prone to wrinkles, damage, etc. after a series of steps such as water washing, which affects the semiconductor structure's subsequent steps. For details, please refer to Figures 1 to 11 In the conventional technology, firstly, the original structure of the incoming material is obtained 10 ( Figure 1 ), the incoming material original structure 10 includes a wafer original layer 11 and an original substrate 12, wherein a conductive through-hole structure 13 is provided in the wafer original layer. Then, the wafer original layer 11 is ring-cut ( Figure 2 ), forming a wafer layer 14, and forming a first bonding adhesive 15 and a first temporary substrate 16 on the side of the wafer layer 14 away from the original substrate 10 ( Figure 3 ). The obtained structure is flipped based on the first temporary substrate 16 so that the original substrate 12 is facing upward and then the original substrate 12 is removed ( Figure 4 Then, the surface of the wafer layer 14 may be etched to expose the conductive via structure 13 ( Figure 5 Then, a protective material layer 17 is formed to cover the conductive via structure 13 and the wafer layer 14 ( Figure 6 The protective material layer 17 is ground to form a protective layer 18 and expose the conductive through-hole structure 13 ( Figure 7 Then, a solder ball 19 may be formed on the side of the conductive via structure 13 away from the first temporary substrate 16 ( Figure 8 ) and a second bonding adhesive 20 covering the solder balls 19 and a second temporary substrate 21 ( Fig. 9 The obtained structure is flipped over so that the second temporary substrate 21 is at the bottom and the first temporary substrate 16 is at the top, and the first bonding adhesive 15 and the first temporary substrate 16 are removed to expose the wafer layer 14 ( Fig.10 Finally, the wafer layer 14 is placed on the hidden cutting film 22, and the second bonding glue 20 and the second temporary substrate 21 are removed ( Fig.11 ). The inventors found that in the process of removing the second bonding glue 20 and the second temporary substrate 21, it is necessary to perform laser irradiation, water washing (drug washing), removal of residual layer, adhesive removal washing, plasma cleaning, water washing and other steps. In this process, the hidden cutting film 22 will be wrinkled, damaged, etc., which affects the vacuum adsorption of the subsequent hidden cutting process.
[0054] Based on this, in one embodiment, see Fig.12 , this embodiment provides a method for preparing a chip 150 based on a reverse molding process. Figures 13 to 22 Schematic diagram of the intermediate structure obtained in the method. Specifically, the method for preparing the chip 150 based on the reverse molding process includes the following steps:
[0055] Step S100: Provide 100, 100 includes a wafer layer 110, a bonding glue 120 and a first temporary substrate 121, the bonding glue 120 is located between the wafer layer 110 and the first temporary substrate 121, the wafer layer 110 has a second surface and a first surface that are relatively arranged, the first surface faces the bonding glue 120 and has a solder ball 111.
[0056] Step S200 : removing the bonding glue 120 and the first temporary substrate 121 , and forming a first bonding film 130 and a second temporary substrate 131 on the first surface.
[0057] Step S300 : attaching the wafer layer 110 to the hidden cutting film 140 through the second surface.
[0058] Step S400 : removing the first bonding film 130 and the second temporary substrate 131 .
[0059] Step S500 : dicing the wafer layer 110 based on the hidden cutting film 140 to form a plurality of chips 150 .
[0060] In step S100, refer to Fig.13 , the wafer layer 110 may have a second surface and a first surface that are arranged opposite to each other, and the first surface of the wafer layer 110 has a solder ball 111. As an example, the material of the solder ball 111 may include tin, etc. The wafer layer 110 may include a dielectric layer and a conductive via structure 112. In addition, the wafer layer 110 may also include a routing layer, etc. As an example, the material of the conductive via structure 112 may include metal materials such as cobalt, nickel, titanium, tungsten, copper and aluminum. At this time, the solder ball 111 may be electrically connected to the connecting column, or may be electrically connected to the routing layer. The dielectric layer may be used to isolate adjacent routing layers, that is, the dielectric layer and the routing layer may be stacked and alternately arranged. In addition, a film layer such as a protective layer 160 may also be provided on the second surface of the wafer layer 110. The material of the protective layer 160 includes but is not limited to silicon oxide, silicon nitride, aluminum oxide or silicon oxynitride.
[0061] The bonding glue 120 is located between the wafer layer 110 and the first temporary substrate 121, and the bonding glue 120 can be used to bond the wafer layer 110 and the first temporary substrate 121. Specifically, the first surface of the wafer layer 110 faces the bonding glue 120 and the first surface has a solder ball 111. At this time, the thickness of the bonding glue 120 is greater than the height of the solder ball 111. This embodiment does not limit the specific material of the bonding glue 120.
[0062] The first temporary substrate 121 may be a glass substrate, etc. The first temporary substrate 121 is used to carry the wafer layer 110 and the bonding adhesive 120. As an example, when 100 is provided, in the direction of gravity, the wafer layer 110, the bonding adhesive 120, and the first temporary substrate 121 may be arranged in sequence, and at this time, the second surface of the wafer layer 110 faces away from the direction of gravity.
[0063] In step S200, as an example, the bonding glue 120 can be first irradiated with a laser and the first temporary substrate 121 can be removed. Thereafter, water washing, descumming to remove the residual layer, descum washing, plasma cleaning, water washing and other steps are sequentially performed to remove the bonding glue 120.
[0064] Of course, a water washing agent may be added during the water washing process. This embodiment does not limit the specific type of the water washing agent.
[0065] See also Fig.19 After removing the bonding glue 120 and the first temporary substrate 121, the wafer layer 110 can form a first bonding film 130 and a second temporary substrate 131 on the first surface. It can be understood that at this time, the second surface of the wafer layer 110 is exposed. Of course, the thickness of the bonding glue 120 can be greater than the height of the solder ball 111. Further, in the direction of gravity, the wafer layer 110, the first bonding film 130, and the second temporary substrate 131 can be arranged in sequence, and at this time, the second surface of the wafer layer 110 faces the direction away from gravity.
[0066] The present embodiment does not limit the specific materials of the first bonding film 130 and the second temporary substrate 131. As an example, the second temporary substrate 131 may be a glass substrate. Furthermore, the second temporary substrate 131 may be the same substrate as the first temporary substrate 121.
[0067] In step S300, refer to Fig. 20 , the wafer layer 110 formed with the first bonding film 130 and the second temporary substrate 131 can be turned over so that the second surface of the wafer layer 110 faces the direction of gravity (downward). After that, the structure can be placed on the invisible cutting film 140, so that the second surface of the wafer layer 110 can be attached to the invisible cutting film 140. At this time, in the direction of gravity, the structure formed with the invisible cutting film 140 can sequentially include the second temporary substrate 131, the first bonding film 130, the wafer layer 110 and the invisible cutting film 140. It can be understood that the invisible cutting film 140 can be a film layer for invisible cutting, and the present embodiment does not limit the specific material composition of the invisible cutting film 140.
[0068] In addition, a patch ring 141 may be formed around the circumference of the hidden cutting film 140. The patch ring 141 may cover the hidden cutting film 140, thereby fixing the hidden cutting film 140.
[0069] In step S400, as an example, see Fig.21 , the first bonding film 130 and the second temporary substrate 131 can be removed by irradiating with a preset light or the like. Specifically, ultraviolet (UV) irradiation, laser irradiation, etc. can be performed in sequence, so that the second temporary substrate 131 can be removed and the first bonding film 130 can be peeled off. This embodiment does not limit parameters such as the wavelength of the light.
[0070] After removing the first bonding film 130 and the second temporary substrate 131 , the remaining structure is the wafer layer 110 and the hidden cutting film 140 , and the hidden cutting film 140 covers the second surface.
[0071] In step S500, at this time, refer to Fig. 22 , the wafer layer 110 is diced to form a plurality of independent chips 150. As an example, in this process, laser invisible cutting technology can be used. Specifically, a laser can be used to penetrate the surface of the wafer layer 110 and focus on the inside of the wafer layer 110 to form a modified layer at a required depth, and then a certain external force is applied to achieve dicing. In the process of using the laser invisible cutting technology, the invisible cutting technology will not produce the problems caused by the blade or laser ablation technology, and there will be no debris or debris (chipping), so there is no need to set up cleaning steps. Moreover, the cutting path of the invisible cutting technology is narrow, and the number of chips 150 formed can also be increased, thereby improving the utilization rate of the wafer layer 110.
[0072] In addition, the present embodiment may also use laser ablation cutting, mechanical diamond blade cutting, thermal laser separation and other technologies to slice the wafer layer 110 .
[0073] In this embodiment, first, a first bonding film 130 and a first temporary substrate 121 are formed on the first surface, so that the first bonding film 130 can be removed by laser or other methods, and there is no need to set water washing, chemical washing and other steps, thereby protecting the hidden cutting film 140 from being damaged by the water washing and other steps. Moreover, the 100 in this embodiment uses a bonding glue 120 to bond the wafer layer 110 and the first temporary substrate 121, thereby preventing the wafer layer 110 from moving in the previous steps (for example, grinding, etc.) and increasing the offset.
[0074] In one embodiment, step S200 includes:
[0075] Step S220: forming a second bonding film 170 and a third temporary substrate 171 on the second surface.
[0076] Step S240 : removing the bonding adhesive 120 and the first temporary substrate 121 to expose the first surface and the solder balls 111 .
[0077] Step S260: forming a first bonding film 130 and a second temporary substrate 131 on the first surface.
[0078] Step S280 : removing the second bonding film 170 and the third temporary substrate 171 .
[0079] In step S220, refer to Fig.14 The second surface of the wafer layer 110 may face the direction away from gravity (upward), and a second bonding film 170 and a third temporary substrate 171 are sequentially formed on the second surface. As an example, the material of the second bonding film 170 may be consistent with the material of the first bonding film 130. The third temporary substrate 171 may include a glass substrate.
[0080] In step S240, the structure formed in step S220 may be turned over so that the first temporary substrate 121 faces upward. At this time, the third temporary substrate 171 is used to support the formed structure. Fig.15 The bonding glue 120 and the first temporary substrate 121 can be removed by water washing, chemical washing, etc. After the bonding glue 120 and the first temporary substrate 121 are removed, the first surface and the solder balls 111 are exposed.
[0081] In step S260, refer to Fig.16 , a first bonding film 130 and a second temporary substrate 131 may be sequentially formed on the first surface.
[0082] In step S280, refer to Fig.17 The structure formed in step S260 can be flipped again so that the third temporary substrate 171 is facing upward, and the second temporary substrate 131 is used to support the formed structure. Afterwards, the second bonding film 170 and the third temporary substrate 171 can be removed by UV irradiation, laser irradiation, etc., so as to obtain a structure in which the wafer layer 110, the first bonding film 130 and the second temporary substrate 131 are stacked.
[0083] In this embodiment, the second bonding film 170 and the third temporary substrate 171 are formed on the second surface, so that the third temporary substrate 171 and the second bonding film 170 can provide support during the process of flipping the obtained structure to prevent the wafer layer 110 from being damaged. Moreover, in this embodiment, the second bonding film 170 is used to bond the third temporary substrate 171 and the wafer layer 110, so that the second bonding film 170 and the third temporary substrate 171 can be quickly peeled off without using steps such as water washing, further reducing the possibility of damage to the wafer layer 110 and simplifying the preparation steps of the chip 150.
[0084] In a possible example, before step S240, the following steps are included:
[0085] Step S230 : forming a first fixing layer 180 on a side of the third temporary substrate 171 away from the second bonding film 170 .
[0086] And, after step S240, the following steps are included:
[0087] Step S250 : removing the first fixing layer 180 .
[0088] Accordingly, in another possible example, before step S280, the following steps are included:
[0089] Step S270 : forming a second fixing layer 181 on a side of the second temporary substrate 131 away from the first bonding film 130 .
[0090] And, after step S280, the following steps are included:
[0091] Step S290 : removing the second fixing layer 181 .
[0092] In step S230, refer to Fig.15 As an example, the structure obtained in step S220 can be flipped and placed on the first fixed layer 180. As an example, the third temporary substrate 171, the second bonding film 170, the wafer layer 110, the bonding glue 120 and the first temporary substrate 121 can be sequentially formed on the first fixed layer 180.
[0093] In step S250 , the first fixing layer 180 may be peeled off. After the first fixing layer 180 is peeled off, the remaining structures are the third temporary substrate 171 , the second bonding film 170 , and the wafer layer 110 .
[0094] In step S270, after forming the first bonding film 130 and the second temporary substrate 131 on the first surface, the resulting structure is the second temporary substrate 131, the first bonding film 130, the wafer layer 110, the second bonding film 170 and the third temporary substrate 171. At this time, please refer to Fig.17 and Fig.18 , the second temporary substrate 131 can be placed with the side away from the second bonding film 170 facing downward, and the structure can be placed on the second fixed layer 181, and then step S280 can be performed.
[0095] In step S290, refer to Fig.19 , the second fixing layer 181 can be peeled off. After the second fixing layer 181 is peeled off, the remaining structure is the second temporary substrate 131, the first bonding film 130, and the wafer layer 110.
[0096] Furthermore, the material of the first fixing layer 180 and / or the second fixing layer 181 may be consistent with the material of the hidden cutting film. For example, the first fixing layer 180 and / or the second fixing layer 181 may include the hidden cutting film. Of course, one of the first fixing layer 180 and the second fixing layer 181 may also be other fixing films, which is not specifically limited in this embodiment.
[0097] In this example, first, the first fixing layer 180 and the second fixing layer 181 are used to fix the corresponding structure, so as to prevent the corresponding structure from moving and affecting the process operation. In addition, in this example, the first fixing layer 180 and the second fixing layer 181 are also peeled off, so that even if the first fixing layer 180 or the second fixing layer 181 is damaged by washing in steps S220 to S280, the first fixing layer 180 and the second fixing layer 181 will be peeled off and will not appear in the final chip 150.
[0098] In one embodiment, step S100 includes:
[0099] Step S120: Provide a wafer initial structure, the wafer initial structure includes a wafer initial layer and a conductive through-hole structure 112, and the wafer initial structure has a first initial surface and a second initial surface, the first initial surface has a solder ball 111, the conductive through-hole structure 112 connects the solder ball and extends in the wafer initial layer, and the conductive through-hole structure 112 is spaced apart from the second initial surface.
[0100] Step S140 : bonding the first initial surface of the wafer initial structure to the first temporary substrate 121 by means of bonding adhesive 120 .
[0101] Step S160 : grinding and thinning the wafer initial layer from the second initial surface to expose the conductive via structure 112 and make the wafer initial structure form the wafer layer 110 .
[0102] In step S120, the wafer initial layer may be relatively thick, and the first initial surface of the wafer initial layer has a solder ball 111, and the conductive via structure 112 is located on a side close to the solder ball 111. At this time, no structure may be provided on the side of the wafer initial layer away from the solder ball 111. For example, a silicon structure may be provided between the conductive via structure 112 and the second initial surface.
[0103] In step S140 , the first initial surface of the wafer initial structure may be facing downward and bonded to the first temporary substrate 121 by bonding adhesive 120 .
[0104] In step S160, the wafer initial layer may be ground and thinned from the second initial surface by mechanical grinding or chemical mechanical grinding to remove the silicon structure between the conductive via structure 112 and the second initial surface until the conductive via structure 112 is exposed. At this time, the remaining wafer initial structure may form the wafer layer 110. It is understood that the conductive via structure 112 may penetrate the wafer layer 110, the exposed second initial surface forms the second surface, and the first initial surface forms the first surface.
[0105] Of course, thereafter, a pad may be formed on the second surface of the wafer layer 110 . The pad may be electrically connected to the conductive via structure 112 .
[0106] Specifically, step S160 may include:
[0107] Step S161 : performing a first grinding on the initial layer of the wafer from the second initial surface to expose the conductive via structure 112 .
[0108] Step S162 : etching the wafer initial layer so that the conductive via structure 112 protrudes from the wafer initial layer.
[0109] Step S163 : performing a second grinding on the protruding conductive via structure 112 , so that the wafer initial structure forms a wafer layer 110 .
[0110] In step S161 to step S163, the initial structure of the wafer can be thinned by step-by-step grinding, so as to more accurately obtain the required thickness of the wafer layer 110. As an example, the first grinding can include mechanical grinding and chemical mechanical grinding, and the second grinding can include chemical mechanical grinding. Of course, before step S163, a protective material layer covering the protruding conductive via structure 112 and the surface can also be formed, and in step S163, part of the protective material layer is ground away, and the remaining protective material layer forms a protective layer.
[0111] In this embodiment, the bonding glue 120 has strong adhesion. By using the bonding glue 120 to bond the first temporary substrate 121 and the initial structure of the wafer, the first temporary substrate 121 and the initial structure of the wafer can be more firmly fixed, thereby better fixing the initial structure of the wafer during multiple grinding processes, thereby reducing the offset of the initial structure of the wafer.
[0112] In one embodiment, before step S140, the following steps are included:
[0113] Step S130: performing circular cutting on the initial structure of the wafer from the first initial surface to form a circular cutting space.
[0114] In step S130, part of the material on the periphery of the initial layer of the wafer may be removed to form an annular space, and the remaining initial layer of the wafer forms the wafer layer 110. The specific size of the annular space is not limited in this embodiment. As an example, a photoresist may be used to cover the middle surface of the initial layer of the wafer, and then the periphery of the initial layer of the wafer may be etched by wet etching or the like, and then the photoresist may be removed to form the wafer layer 110.
[0115] In this embodiment, by forming a ring-cut structure, the bonding adhesive 120 can enter the ring-cut structure, so that the wafer layer 110 and the first temporary substrate 121 can be better bonded to form a more solid structure.
[0116] In addition, it can be understood that in this embodiment, when the bonding film is peeled off, the bonding film remains less on the temporary substrate, so that the first temporary substrate 121, the second temporary substrate 131 and the third temporary substrate 171 can be reused. When the bonding glue 120 is used, the residue of the bonding glue 120 is not easy to clean and is difficult to reuse.
[0117] It should be understood that although Fig.12 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Fig.12 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.
[0118] Based on the same inventive concept, in one embodiment, a chip 150 is provided, and the chip 150 is obtained by using a chip 150 preparation method formed by any one of the above embodiments or a combination of multiple embodiments. Specifically, the chip 150 may include a chip 150 body and a hidden cutting film 140. The chip 150 body may include a conductive through-hole structure 112, a solder ball 111, and a pad, etc. It can be understood that the hidden cutting film 140 may be a film layer for hidden cutting, and this embodiment does not limit the specific material composition of the hidden cutting film 140.
[0119] The hidden cut film 140 of the chip 150 provided in this embodiment is relatively complete, so that the vacuum adsorption and other steps can be continued.
[0120] In one embodiment, a three-dimensional packaging structure is provided. The three-dimensional packaging structure may include a plurality of chips 150 obtained by a chip 150 preparation method based on a reverse molding process as formed by any one of the above embodiments or a combination of multiple embodiments. The plurality of chips 150 may form a three-dimensional packaging structure in a 3D stacking manner. As an example, the three-dimensional packaging structure may include 8 layers of chips 150. Furthermore, a pad may be provided on one side of each chip 150, and the chips 150 in the three-dimensional packaging structure may be electrically connected through the pad and the gold wire.
[0121] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that "this embodiment" or "one embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification may not necessarily refer to the same embodiment.
[0122] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0123] The embodiments described above only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all fall within the scope of protection of the present application. Therefore, the scope of protection of the patent of the present application shall be subject to the attached claims. The above description is only a preferred implementation method of the present disclosure, and does not limit the scope of the patent of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure specification and drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the scope of protection of the patent of the present disclosure.
Claims
1. A chip preparation method based on a reverse molding process, characterized in that: include: Providing an incoming material structure, the incoming material structure comprising a wafer layer, a bonding adhesive and a first temporary substrate, the bonding adhesive being located between the wafer layer and the first temporary substrate, the wafer layer having a second surface and a first surface that are oppositely disposed, the first surface facing the bonding adhesive and having solder balls; removing the bonding glue and the first temporary substrate, and forming a first bonding film and a second temporary substrate on the first surface; attaching the wafer layer to the hidden cutting film through the second surface; removing the first bonding film and the second temporary substrate; The wafer layer is diced based on the hidden cutting film to form a plurality of chips.
2. The chip preparation method based on the reverse molding process according to claim 1, characterized in that: The removing the first bonding film and the second temporary substrate comprises: irradiating the first bonding film with a preset light; The first bonding film is peeled off, and the second temporary substrate is removed.
3. The chip preparation method based on the reverse molding process according to claim 1, characterized in that: The step of removing the bonding glue and the first temporary substrate and forming a first bonding film and a second temporary substrate on the first surface includes: forming a second bonding film and a third temporary substrate on the second surface; removing the bonding glue and the first temporary substrate to expose the first surface and the solder balls; forming the first bonding film and the second temporary substrate on the first surface; The second bonding film and the third temporary substrate are removed.
4. The chip preparation method based on the reverse molding process according to claim 3 is characterized in that: Before removing the bonding glue and the first temporary substrate to expose the first surface and the solder balls, the method includes: attaching a side of the third temporary substrate facing away from the second bonding film to the first fixing layer; After removing the bonding glue and the first temporary substrate to expose the first surface and the solder balls, the method includes: The first fixing layer is removed.
5. The chip preparation method based on the reverse molding process according to claim 3, characterized in that: Before removing the second bonding film and the third temporary substrate, the method includes: Attaching the second temporary substrate, with the side facing away from the first bonding film, to the second fixing layer; After removing the second bonding film and the third temporary substrate, the method further comprises: The second fixing layer is removed.
6. The chip preparation method based on the reverse molding process according to claim 1, characterized in that: The structure of providing incoming materials includes: Providing a wafer initial structure, the wafer initial structure comprising a wafer initial layer and a conductive through-hole structure, and the wafer initial structure having a first initial surface and a second initial surface, the first initial surface having the solder ball, the conductive through-hole structure connecting the solder ball and extending in the wafer initial layer, and the conductive through-hole structure and the second initial surface being spaced apart; Bonding the first initial surface of the wafer initial structure to the first temporary substrate by means of the bonding adhesive; The wafer initial layer is ground and thinned from the second initial surface to expose the conductive through-hole structure and form a wafer layer from the wafer initial structure.
7. The chip preparation method based on the reverse molding process according to claim 6, characterized in that: The step of grinding and thinning the wafer initial layer from the second initial surface to expose the conductive through-hole structure and form the wafer initial structure into a wafer layer includes: Performing a first grinding on the initial layer of the wafer from the second initial surface to expose the conductive via structure; Etching the wafer initial layer so that the conductive via structure protrudes from the wafer initial layer; The protruding conductive via structure is subjected to a second grinding so that the wafer initial structure forms a wafer layer.
8. The chip preparation method based on the reverse molding process according to claim 6, characterized in that: Before bonding the first initial surface of the wafer initial structure to the first temporary substrate by bonding adhesive, the method further includes: The wafer initial structure is circularly cut from the first initial surface to form a circular cutting space.
9. A chip, characterized in that: The chip is prepared using the chip preparation method based on the reverse molding process as described in any one of claims 1 to 8.
10. A three-dimensional packaging structure, characterized in that: The three-dimensional packaging structure is formed by stacking a plurality of chips prepared by the chip preparation method based on the reverse molding process as described in any one of claims 1 to 8.