Power tube driving circuit for three-phase motor

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to a power pre-driving circuit for a three-phase motor. According to the circuit, firstly, a simple logic circuit is used for guaranteeing that high and low sides in the pre-driving circuit are not directly connected, then 0-5V low-voltage signals are converted into VCC-VG high-voltage signals, level shifting work is completed in the pre-driving circuit, charging and discharging work of a grid electrode of a half-bridge power tube is controlled through two LDMOSs, and the voltage of the half-bridge power tube is controlled to be larger than or equal to 5V. The target of driving the three-phase motor power tube is achieved. And compared with a traditional pre-drive circuit, the circuit has the advantages of smaller transmission delay, faster response time and higher universality.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a power tube driving circuit for a three-phase motor. Background Art

[0002] In a three-phase motor drive circuit that does not use a bootstrap capacitor structure, there will be multiple power rails. Specifically, the first is a low-voltage power rail output by the internal logic, the second is a sub-high-voltage power rail provided by an external power supply, and the third is a high-voltage power rail generated by an internal charge pump. Due to the large area of ​​the power tube, its gate parasitic capacitance is large, and a separate pre-drive circuit is required to transmit the control signal to the gate of the power tube. At the same time, since the high-side power tube of the half-bridge in the three-phase motor drive circuit requires a high voltage to turn on, the drive circuit also needs to convert the low-voltage power rail output by the internal logic into a high-voltage power rail. Traditional pre-drive circuits often use an inverter cascade structure. This structure has a large number of inverters and will result in a long transmission delay. In addition, the size of each inverter tube needs to be designed separately according to different circuits, which is not universal. Summary of the invention

[0003] In view of the above problems, the present invention provides a power tube driving circuit for a three-phase motor, which can meet the needs of driving the power tube of the three-phase motor.

[0004] The technical solution of the present invention is:

[0005] A power tube driving circuit for a three-phase motor, used for driving the power tube of a half-bridge of the three-phase motor, characterized in that it comprises a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a first PMOS tube M5, a second PMOS tube M6, a third PMOS tube M7, a fourth PMOS tube M8, a first N-type LDMOS tube M9, a second N-type LDMOS tube M10, a third N-type LDMOS tube M11, a fourth N-type LDMOS tube M12, a fifth N-type LDMOS tube M13, a first P-type LDMOS tube M14, a second P-type LDMOS tube M15, a third P-type LDMOS tube M16, a fourth PMOS tube M17, a first N-type LDMOS tube M18, a second N-type LDMOS tube M19, a third N-type LDMOS tube M20, a fourth N-type LDMOS tube M21, a fifth N-type LDMOS tube M22, a first P-type LDMOS tube M23, a second P-type LDMOS tube M24, a third P-type LDMOS tube M25, a fourth P-type LDMOS tube M26 MOS tube M16, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2, a first Zener diode Z1, a second Zener diode Z2, a third Zener diode Z3, a first NAND gate nand1, a first inverter inv1, a second inverter inv2, a third inverter inv3, a fourth inverter inv4, a fifth inverter inv5, a sixth inverter inv6, a seventh inverter inv7, an eighth inverter inv8, a ninth inverter inv9, a tenth inverter inv10, an eleventh inverter inv11, and a twelfth inverter inv12.

[0006] Among them, the input end of the first inverter inv1 is connected to the IN1 node, the node inputs the high-side drive signal, and the output end is connected to the B node; the input end of the second inverter inv2 is connected to the output end of the first inverter inv1, and the output end is connected to the C node; the input end inv3 of the third inverter is connected to the IN2 node, the node inputs the low-side drive signal, and the output end is connected to the D node; the input end of the fourth inverter inv4 is connected to the output end of the third inverter inv3, and the output end is connected to the A node; the input end of the first NAND gate nand1 is connected to the output ends of the second inverter inv2 and the third inverter inv3, and the output end is connected to the DOWN node; the gate of the first NMOS tube M1 is connected to the A node The gate of the second NMOS tube M2 is connected to the B node, the drain is connected to the drain of the first PMOS tube M5, and the source is connected to the GND node; the gate of the third NMOS tube M3 is connected to the D node, the drain is connected to the source of the fourth NMOS tube M4, and the source is connected to the GND node; the gate of the fourth NMOS tube M4 is connected to the C node, the drain is connected to the drain of the second PMOS tube M6, and the source is connected to the drain of the third NMOS tube M3; the gate of the first PMOS tube M5 is connected to the VCC node, the drain is connected to the drain of the first NMOS tube M1, and the source is connected to the E node; the gate of the second PMOS tube M6 is connected to the V CC node, the drain is connected to the drain of the fourth NMOS tube M4, and the source is connected to the F node; the gate of the third PMOS tube M7 is connected to the F node, the drain is connected to the E node, and the source is connected to the power supply VG; the gate of the fourth PMOS tube M8 is connected to the E node, the drain is connected to the F node, and the source is connected to the power supply VG; one end of the first resistor R1 is connected to the F node, and the other end is connected to the power supply VG; one end of the second resistor R2 is connected to the first capacitor C1, and the other end is connected to the drain of the MOS tube in the fifth inverter inv5; one end of the third resistor R3 is connected to the second capacitor C2, and the other end is connected to the drain of the MOS tube in the ninth inverter inv9; one end of the fourth resistor R4 is connected to the first P-type LDMOS One end of the fifth resistor R5 is connected to the drain of the fifth N-type LDMOS tube M13, and the other end is connected to the output terminal OUT node; one end of the sixth resistor R6 is connected to the gate of the fifth N-type LDMOS tube M13, and the other end is connected to the SW node; one end of the first capacitor C1 is connected to one end of the second resistor R2 and the output end of the fifth inverter inv5, and the other end is connected to the VCC node; one end of the second capacitor C2 is connected to one end of the third resistor R3 and the output end of the ninth inverter inv9, and the other end is connected to the GND node; the input end of the fifth inverter inv5 is connected to the F node, and the output end is connected to the input end of the sixth inverter inv6;The input end of the sixth inverter inv6 is connected to the output end of the fifth inverter inv5, and the output end is connected to the input end of the seventh inverter inv7; the input end of the seventh inverter inv7 is connected to the output end of the sixth inverter inv6, and the output end is connected to the input end of the eighth inverter inv8; the input end of the eighth inverter inv8 is connected to the output end of the seventh inverter inv7, and the output end is connected to the gate of the first P-type LDMOS tube M14; the input end of the ninth inverter inv5 is connected to the DOWN node, and the output end is connected to the input end of the tenth inverter inv10; the input end of the tenth inverter inv10 is connected to the output end of the ninth inverter inv9, and the output end is connected to the eleventh inverter. The input end of the eleventh inverter inv11 is connected to the output end of the tenth inverter inv10, and the output end is connected to the input end of the twelfth inverter inv12 and the gate of the first N-type LDMOS tube M9; the input end of the twelfth inverter inv12 is connected to the output end of the eleventh inverter inv11, and the output end is connected to the gate of the second N-type LDMOS tube M10; the gate of the first N-type LDMOS tube M9 is connected to the output end of the eleventh inverter inv11, the drain is connected to the drain of the second P-type LDMOS tube M15, and the source is connected to the gate of the third N-type LDMOS tube M11; the gate of the second N-type LDMOS tube M10 is connected to the output end of the twelfth inverter inv11 The output end of the phase converter inv12 has a drain connected to the drain of the third P-type LDMOS tube M16, and a source connected to the drain of the fourth N-type LDMOS tube M12; the gate of the third N-type LDMOS tube M11 is connected to the VBIAS node, the drain is connected to the source of the first N-type LDMOS tube M9, and the source is connected to the GND node; the gate of the fourth N-type LDMOS tube M12 is connected to the VBIAS node, the drain is connected to the source of the second N-type LDMOS tube M10, and the source is connected to the GND node; the gate of the fifth N-type LDMOS tube M13 is connected to one end of the sixth resistor R6, the drain is connected to one end of the fifth resistor R5, and the source is connected to the SW node; the first P-type LDMOS tube M The gate of the second P-type LDMOS tube M15 is connected to the gate of the third P-type LDMOS tube M16, the drain is connected to the drain of the first N-type LDMOS tube M9, and the source is connected to the power supply VG; the gate of the third P-type LDMOS tube M16 is connected to the gate of the second P-type LDMOS tube M15, the drain is connected to the drain of the second N-type LDMOS tube M10, and the source is connected to the power supply VG; one end of the first Zener diode Z1 is connected to the E node, and the other end is connected to the VCC node; one end of the second Zener diode Z2 is connected to the F node, and the other end is connected to the VCC node;One end of the third Zener diode Z3 is connected to the gate of the fifth N-type LDMOS tube M13, and the other end is connected to the SW node. The connection point between the fourth resistor R4 and the fifth resistor R5 mentioned above is the output terminal OUT node of the driving circuit, which is connected to the gate of the external power tube. ;

[0007] The beneficial effects of the present invention are as follows: compared with the traditional power pre-drive circuit, the present invention achieves the goal of driving the power tube to turn on and off by controlling the charging and discharging of the power tube gate, while effectively reducing the transmission delay of the overall pre-drive circuit and improving the speed and performance of the three-phase motor drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a power pre-driver module architecture diagram proposed by the present invention;

[0009] Figure 2 The present invention provides a power pre-driving circuit diagram for a three-phase motor. DETAILED DESCRIPTION

[0010] The present invention will be described in detail below with reference to the accompanying drawings.

[0011] Figure 1 This is the architecture diagram of the power pre-driver module. Its specific workflow is as follows:

[0012] First, before inputting the control signal, the dead time is added to the input PWM control signal, and then the PWM control signal is divided into two signals for driving the high side and the low side. The high side signal needs to be controlled after the level shift circuit is level-converted because the pre-driver power rail to be controlled is from VG to SW; the low side power tube does not have a floating rail, so there is no need for special signal processing, but it is necessary to consider the matching with the high side signal and the possible dV / dt caused by the lower side tube mis-starting problem.

[0013] Figure 2 This is a power pre-drive circuit diagram for a three-phase motor proposed by the present invention. It can be roughly divided into four parts: CONTROL LOGIC module, LEVEL SHIFT module, DELAY MATCH module, and PRE DRIVER module. Specifically, its working principle is:

[0014] The CONTROL LOGIC module consists of the first NAND gate nand1, the first inverter inv1, the second inverter inv2, the third inverter inv3, and the fourth inverter inv4. Among them: the external input high-side drive signal and low-side drive signal, only when the low-side power tube is turned off, the high-side tube will be turned on to ensure that there will be no erroneous logic, causing the upper and lower tubes to be turned on at the same time. When the low-side drive signal is low, the high-side logic is normally input to the second-level LEVEL SHIFT module.

[0015] The LEVEL SHIFT module consists of a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a first PMOS tube M5, a second PMOS tube M6, a third PMOS tube M7, a fourth PMOS tube M8, a first Zener diode Z1, and a second Zener diode Z2. Among them: M2 and M4 are high-side signal input pairs, and M1 and M3 are control tubes for low-side output feedback. In order to ensure the matching of the input side, it is necessary to ensure that the width-to-length ratio of M3 and M4 tubes is twice that of M1 and M2. M5 and M6 are output swing clamps, which limit the output swing between VCC+Vgs6 and VG. Resistor R1 sets the initial state of the high-side tube to ensure that the high-side tube is in the off state during initial startup.

[0016] The DELAY MATCH module consists of the fifth inverter inv5, the sixth inverter inv6, the seventh inverter inv7, the eighth inverter inv8, the ninth inverter inv9, the tenth inverter inv10, the eleventh inverter inv11, the twelfth inverter inv12, the first resistor R1, the second resistor R2, the first capacitor C1, and the second capacitor C2. It has two functions: first, this structure increases the swing of the control logic, changing the control signal from the input VCC+Vgs6 to VG to the swing of VCC to VG; second, by setting the delay through RC, the switching timing of the switches M13 and M14 is controlled to ensure that the two are not turned on at the same time, avoiding power loss during direct pass.

[0017] The PRE DRIVER module is composed of a first N-type LDMOS tube M9, a second N-type LDMOS tube M10, a third N-type LDMOS tube M11, a fourth N-type LDMOS tube M12, a fifth N-type LDMOS tube M13, a first P-type LDMOS tube M14, a second P-type LDMOS tube M15, a third P-type LDMOS tube M16, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a third Zener diode Z3. Among them, M13 and M14 are respectively the discharge and charging tubes of the power MOS gate, and R4 and R5 control the size of the charge and discharge current: when the M14 tube is turned on, the current flows through VG through R4 to charge the gate of the power tube; when the M13 tube is turned on, the gate charge of the power tube flows into the SW terminal through R5. Since the source of the M14 tube is connected to VG, its switch can be directly controlled by the high-end output of the DELAY MATCH module. However, for the M13 tube, since its source is connected to the SW node, when the power tube is working, the potential of the SW node is in a floating state, so an additional loop is required to control the switch of the M13 tube. This circuit uses the current mirror charging and discharging method to control the switch of the M13 tube. Its working principle is as follows: when the DOWN signal input is high, M9 is closed and M10 is opened, and the M11 tube copies the current of the M12 tube and flows into the gate of the M13 tube, where the ratio of M11 to M12 is 2:1 to reduce the charging delay.

[0018] In summary, the circuit of the present invention first uses a simple logic circuit to ensure that there is no direct high-low side connection inside the pre-drive circuit, and then converts the low-voltage signal of 0 to 5V into a high-voltage signal of VCC to VG, completes the level shift work inside the pre-drive circuit, and controls the charging and discharging work of the gate of the half-bridge power tube through two LDMOS, thereby achieving the goal of driving the power tube of the three-phase motor. Compared with the traditional pre-drive circuit, this circuit has smaller transmission delay, faster response time and stronger versatility.

Claims

1. A power tube driving circuit for a three-phase motor, used to drive the power tube of a half-bridge of a three-phase motor, characterized in that: The device includes a first NMOS tube M1, a second NMOS tube M2, a third NMOS tube M3, a fourth NMOS tube M4, a first PMOS tube M5, a second PMOS tube M6, a third PMOS tube M7, a fourth PMOS tube M8, a first N-type LDMOS tube M9, a second N-type LDMOS tube M10, a third N-type LDMOS tube M11, a fourth N-type LDMOS tube M12, a fifth N-type LDMOS tube M13, a first P-type LDMOS tube M14, a second P-type LDMOS tube M15, a third P-type LDMOS tube M16, a first resistor R1, and a second resistor R2. R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first capacitor C1, a second capacitor C2, a first Zener diode Z1, a second Zener diode Z2, a third Zener diode Z3, a first NAND gate nand1, a first inverter inv1, a second inverter inv2, a third inverter inv3, a fourth inverter inv4, a fifth inverter inv5, a sixth inverter inv6, a seventh inverter inv7, an eighth inverter inv8, a ninth inverter inv9, a tenth inverter inv10, an eleventh inverter inv11, and a twelfth inverter inv12. Among them, the input end of the first inverter inv1 is connected to the IN1 node, the node inputs the high-side drive signal, and the output end is connected to the B node; the input end of the second inverter inv2 is connected to the output end of the first inverter inv1, and the output end is connected to the C node; the input end inv3 of the third inverter is connected to the IN2 node, the node inputs the low-side drive signal, and the output end is connected to the D node; the input end of the fourth inverter inv4 is connected to the output end of the third inverter inv3, and the output end is connected to the A node; the input end of the first NAND gate nand1 is connected to the output ends of the second inverter inv2 and the third inverter inv3, and the output end is connected to the DOWN node; the gate of the first NMOS tube M1 is connected to the A node The gate of the second NMOS tube M2 is connected to the B node, the drain is connected to the drain of the first PMOS tube M5, and the source is connected to the GND node; the gate of the third NMOS tube M3 is connected to the D node, the drain is connected to the source of the fourth NMOS tube M4, and the source is connected to the GND node; the gate of the fourth NMOS tube M4 is connected to the C node, the drain is connected to the drain of the second PMOS tube M6, and the source is connected to the drain of the third NMOS tube M3; the gate of the first PMOS tube M5 is connected to the VCC node, the drain is connected to the drain of the first NMOS tube M1, and the source is connected to the E node; the gate of the second PMOS tube M6 is connected to the V CC node, the drain is connected to the drain of the fourth NMOS tube M4, and the source is connected to the F node; the gate of the third PMOS tube M7 is connected to the F node, the drain is connected to the E node, and the source is connected to the power supply VG; the gate of the fourth PMOS tube M8 is connected to the E node, the drain is connected to the F node, and the source is connected to the power supply VG; one end of the first resistor R1 is connected to the F node, and the other end is connected to the power supply VG; one end of the second resistor R2 is connected to the first capacitor C1, and the other end is connected to the drain of the MOS tube in the fifth inverter inv5; one end of the third resistor R3 is connected to the second capacitor C2, and the other end is connected to the drain of the MOS tube in the ninth inverter inv9; one end of the fourth resistor R4 is connected to the first P-type LDMOS One end of the fifth resistor R5 is connected to the drain of the fifth N-type LDMOS tube M13, and the other end is connected to the output terminal OUT node; one end of the sixth resistor R6 is connected to the gate of the fifth N-type LDMOS tube M13, and the other end is connected to the SW node; one end of the first capacitor C1 is connected to one end of the second resistor R2 and the output end of the fifth inverter inv5, and the other end is connected to the VCC node; one end of the second capacitor C2 is connected to one end of the third resistor R3 and the output end of the ninth inverter inv9, and the other end is connected to the GND node; the input end of the fifth inverter inv5 is connected to the F node, and the output end is connected to the input end of the sixth inverter inv6;The input end of the sixth inverter inv6 is connected to the output end of the fifth inverter inv5, and the output end is connected to the input end of the seventh inverter inv7; the input end of the seventh inverter inv7 is connected to the output end of the sixth inverter inv6, and the output end is connected to the input end of the eighth inverter inv8; the input end of the eighth inverter inv8 is connected to the output end of the seventh inverter inv7, and the output end is connected to the gate of the first P-type LDMOS tube M14; the input end of the ninth inverter inv5 is connected to the DOWN node, and the output end is connected to the input end of the tenth inverter inv10; the input end of the tenth inverter inv10 is connected to the output end of the ninth inverter inv9, and the output end is connected to the eleventh inverter. The input end of the eleventh inverter inv11 is connected to the output end of the tenth inverter inv10, and the output end is connected to the input end of the twelfth inverter inv12 and the gate of the first N-type LDMOS tube M9; the input end of the twelfth inverter inv12 is connected to the output end of the eleventh inverter inv11, and the output end is connected to the gate of the second N-type LDMOS tube M10; the gate of the first N-type LDMOS tube M9 is connected to the output end of the eleventh inverter inv11, the drain is connected to the drain of the second P-type LDMOS tube M15, and the source is connected to the gate of the third N-type LDMOS tube M11; the gate of the second N-type LDMOS tube M10 is connected to the output end of the twelfth inverter inv11 The output end of the phase converter inv12 has a drain connected to the drain of the third P-type LDMOS tube M16, and a source connected to the drain of the fourth N-type LDMOS tube M12; the gate of the third N-type LDMOS tube M11 is connected to the VBIAS node, the drain is connected to the source of the first N-type LDMOS tube M9, and the source is connected to the GND node; the gate of the fourth N-type LDMOS tube M12 is connected to the VBIAS node, the drain is connected to the source of the second N-type LDMOS tube M10, and the source is connected to the GND node; the gate of the fifth N-type LDMOS tube M13 is connected to one end of the sixth resistor R6, the drain is connected to one end of the fifth resistor R5, and the source is connected to the SW node; the first P-type LDMOS tube M The gate of the second P-type LDMOS tube M15 is connected to the gate of the third P-type LDMOS tube M16, the drain is connected to the drain of the first N-type LDMOS tube M9, and the source is connected to the power supply VG; the gate of the third P-type LDMOS tube M16 is connected to the gate of the second P-type LDMOS tube M15, the drain is connected to the drain of the second N-type LDMOS tube M10, and the source is connected to the power supply VG; one end of the first Zener diode Z1 is connected to the E node, and the other end is connected to the VCC node; one end of the second Zener diode Z2 is connected to the F node, and the other end is connected to the VCC node;One end of the third Zener diode Z3 is connected to the gate of the fifth N-type LDMOS tube M13, and the other end is connected to the SW node. The connection point between the fourth resistor R4 and the fifth resistor R5 mentioned above is the output terminal OUT node of the driving circuit, which is connected to the gate of the external power tube. ;

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