MEMS resonator, manufacturing method thereof and electrical product

Abstract

The embodiment of the invention provides an MEMS resonator, a manufacturing method thereof and an electrical product. The MEMS resonator comprises a device structure which comprises a substrate layer, a first cavity located in the substrate layer or on the upper side of the substrate layer, a device layer located on the upper side of the substrate layer, a piezoelectric layer located on the upper side of the device layer and a first electrode layer located on the upper side of the piezoelectric layer; wherein the lower side of the substrate layer is provided with a pin, and the pin is electrically connected with the first electrode layer through a conductive hole penetrating through the substrate layer and an island-shaped structure penetrating through the device layer. According to the embodiment of the invention, the size of a chip can be reduced.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a MEMS resonator and a manufacturing method thereof, and an electrical product. Background Art

[0002] Currently, the MEMS oscillator technology with electrostatically driven silicon-based MEMS (Microelectromechanical Systems) resonators as core devices is becoming increasingly mature and is expected to become a substitute for traditional quartz oscillators, thus having smaller size, lower manufacturing cost and higher reliability.

[0003] With the development of piezoelectric thin film materials, compared with electrostatically driven silicon-based MEMS resonators, piezoelectrically driven silicon-based MEMS resonators exhibit lower motional impedance and higher electromechanical coupling coefficient, which is beneficial to reducing the power consumption and phase noise of the oscillator.

[0004] Piezoelectrically driven silicon-based MEMS resonators do not require an electrostatic bias voltage, thereby reducing the error term on the output signal caused by power supply jitter. At the same time, piezoelectrically driven silicon-based MEMS resonators do not require the formation of sub-micron silicon layer slits during processing, which reduces the difficulty of the process, is beneficial to improving the device yield, and is also conducive to further miniaturization of the device. Summary of the invention

[0005] However, the inventors have found that in the current MEMS resonator structure, the signal pin of the upper electrode layer needs to include two parts, one for probe contact during device testing, and the other for bonding with the silicon cap layer; therefore, it is not conducive to reducing the chip size.

[0006] In order to solve at least one of the above problems or other similar problems, the embodiments of the present application provide a MEMS resonator and a manufacturing method thereof, and an electrical product.

[0007] According to a first aspect of an embodiment of the present application, a MEMS resonator is provided, including:

[0008] A device structure, comprising a substrate layer, a first cavity located inside or on the upper side of the substrate layer, a device layer located on the upper side of the substrate layer, a piezoelectric layer located on the upper side of the device layer, and a first electrode layer located on the upper side of the piezoelectric layer; wherein a pin is provided on the lower side of the substrate layer, and the pin is electrically connected to the first electrode layer via a conductive hole penetrating the substrate layer and an island structure penetrating the device layer.

[0009] According to a second aspect of the embodiment of the present application, the MEMS resonator further includes:

[0010] A cap structure includes a second cavity, wherein the cap structure is bonded to the device structure on an upper side of the first electrode layer, and the first cavity and the second cavity at least partially overlap in a thickness direction.

[0011] According to a third aspect of the embodiment of the present application, the device layer is a doped silicon layer, and the doping concentration of at least part of the doped silicon layer is greater than 10 19 cm -3 .

[0012] According to a fourth aspect of the embodiment of the present application, the doping concentration of at least part of the doped silicon layer is greater than 10 20 cm -3 .

[0013] According to a fifth aspect of the embodiment of the present application, the substrate layer has a conductive hole penetrating the substrate layer in the thickness direction, the conductive hole has a first conductive structure insulated from the substrate layer, the device layer has an island structure, the island structure is a part of the device layer and is insulated from other parts of the device layer;

[0014] One end of the first conductive structure is electrically connected to the pin, and the other end is electrically connected to one end of the island structure. The other end of the island structure is electrically connected to the first electrode layer via the second conductive structure.

[0015] According to a sixth aspect of the embodiments of the present application, the first conductive structure includes polycrystalline silicon or single crystal silicon, and the resistivity of the polycrystalline silicon or single crystal silicon is lower than 0.05Ω·cm.

[0016] According to a seventh aspect of the embodiment of the present application, there is a first insulating layer between the substrate layer and the device layer, and there is also the first insulating layer between the first conductive structure in the conductive hole and the substrate layer.

[0017] According to an eighth aspect of the embodiments of the present application, there is also a first metal layer between the device layer and the substrate layer, and a portion of the first metal layer is electrically connected to the first conductive structure as part of the island structure.

[0018] According to a ninth aspect of the embodiments of the present application, a second metal layer is further provided between the device layer and the first metal layer, and a portion of the second metal layer is in contact with a portion of the first metal layer as part of the island structure.

[0019] According to a tenth aspect of the embodiment of the present application, a second insulating layer is provided between the second metal layer and the device layer, and the second metal layer and the device layer are at least partially in electrical contact.

[0020] According to an eleventh aspect of the embodiment of the present application, there is also a second electrode layer between the device layer and the piezoelectric layer.

[0021] According to a twelfth aspect of the embodiment of the present application, a portion of the second electrode layer is electrically connected to the second conductive structure as part of the island structure.

[0022] According to a thirteenth aspect of the embodiment of the present application, there is a third insulating layer between the island structure and the device layer.

[0023] According to the fourteenth aspect of the embodiment of the present application, the third insulating layer at least covers a portion of the side wall and / or a portion of the upper surface of the piezoelectric layer.

[0024] According to the fifteenth aspect of the embodiment of the present application, the third insulating layer is at least partially located in the first metal layer and / or the second metal layer, and the portion of the first metal layer is insulated from other portions and / or the portion of the second metal layer is insulated from other portions.

[0025] According to a sixteenth aspect of the embodiment of the present application, a groove penetrating the device layer and the piezoelectric layer is provided between the first cavity and the second cavity.

[0026] According to the seventeenth aspect of the embodiment of the present application, the pins include at least one first pin for a driving end, and at least one first pin is electrically connected to the first electrode layer.

[0027] According to the eighteenth aspect of the embodiment of the present application, the pins include at least two first pins for driving ends, and at least two of the first pins are electrically connected to two parts of electrodes of the first electrode layer respectively.

[0028] According to the nineteenth aspect of the embodiment of the present application, the device structure further comprises a second pin, and the second pin is electrically connected to the device layer.

[0029] According to the twentieth aspect of the embodiment of the present application, the second pin is grounded.

[0030] According to a twenty-first aspect of an embodiment of the present application, a method for manufacturing a MEMS resonator is provided, comprising:

[0031] A device structure is formed, the device structure comprising a substrate layer, a first cavity located inside or on the upper side of the substrate layer, a device layer located on the upper side of the substrate layer, a piezoelectric layer located on the upper side of the device layer, and a first electrode layer located on the upper side of the piezoelectric layer; wherein a pin is provided on the lower side of the substrate layer, the pin being electrically connected to the first electrode layer via a conductive hole penetrating the substrate layer and an island structure penetrating the device layer.

[0032] According to the twenty-second aspect of the embodiment of the present application, the method further includes:

[0033] forming a cap structure, the cap structure comprising a second cavity;

[0034] The cap structure is bonded to the device structure on the upper side of the first electrode layer, and the first cavity and the second cavity at least partially overlap in the thickness direction.

[0035] According to a twenty-third aspect of the embodiment of the present application, forming a device structure includes:

[0036] forming a first conductive structure in a substrate layer; and

[0037] A first metal layer is formed on the substrate layer; wherein the first metal layer is electrically connected to the first conductive structure.

[0038] According to a twenty-fourth aspect of the embodiment of the present application, forming a device structure includes:

[0039] forming the first cavity inside or on the upper side of the substrate layer; and

[0040] The device layer is formed on the first metal layer by metal layer bonding.

[0041] According to a twenty-fifth aspect of the embodiment of the present application, forming a device structure includes:

[0042] forming a second metal layer under the device layer; and

[0043] The first metal layer is bonded to the second metal layer.

[0044] According to a twenty-sixth aspect of the embodiment of the present application, forming a device structure includes:

[0045] forming the piezoelectric layer on the device layer; and

[0046] The island structure is formed in the device layer, and the island structure is insulated from other parts of the device layer and the piezoelectric layer.

[0047] According to the twenty-seventh aspect of the embodiment of the present application, a portion of the first metal layer is electrically connected to the first conductive structure as part of the island-like structure, and / or a portion of the second metal layer is in contact with a portion of the first metal layer as part of the island-like structure.

[0048] According to a twenty-eighth aspect of the embodiment of the present application, forming a device structure includes:

[0049] forming the first electrode layer on the upper side of the piezoelectric layer; and

[0050] The first electrode layer is electrically connected to the other end of the island structure via a second conductive structure.

[0051] According to a twenty-ninth aspect of the embodiment of the present application, forming a device structure includes:

[0052] forming leads on a lower side of the substrate layer; and

[0053] The pin is electrically connected to one end of the island structure.

[0054] According to the thirtieth aspect of the embodiment of the present application, there is provided an electrical product, wherein the electrical product has a MEMS resonator as described in any one of the first to twentieth aspects above.

[0055] One of the beneficial effects of the embodiments of the present application is that the signal pins are led out from one side (lower side) of the substrate layer, and the pins in the first electrode layer (upper electrode) only need to include the part that is contacted by the probe during device testing, and do not need to include the part bonded to the silicon cap. The conductive holes and pins for signal lead-out can be located directly below the upper electrode pins, or have a certain overlap with the upper electrode pins, thereby reducing the chip size.

[0056] With reference to the following description and accompanying drawings, the embodiments of the present application are disclosed in detail. It should be understood that the embodiments of the present application are not limited in scope. Within the spirit and scope of the appended claims, the embodiments of the present application include many changes, modifications and equivalents.

[0057] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0058] It should be emphasized that the terms “include / comprises / has” when used herein refer to the existence of a feature, an integer, or a component, but do not exclude the existence or addition of one or more other features, integers, or components. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] The above and other objects, features and advantages of the embodiments of the present application will become more apparent from the following detailed description in conjunction with the accompanying drawings, in which:

[0060] Figure 1 is a schematic diagram of a MEMS resonator;

[0061] Figure 2 is a schematic diagram of a MEMS resonator according to an embodiment of the present application;

[0062] Figure 3 is another schematic diagram of a MEMS resonator according to an embodiment of the present application;

[0063] Figure 4is another schematic diagram of a MEMS resonator according to an embodiment of the present application;

[0064] Figure 5A is a schematic diagram of a method for manufacturing a MEMS resonator according to an embodiment of the present application;

[0065] Figure 5B is a schematic diagram of a device structure formed in an embodiment of the present application;

[0066] Figure 6 is an exemplary diagram of a device structure formed in an embodiment of the present application;

[0067] Figure 7 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0068] Figure 8 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0069] Fig. 9 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0070] Fig.10 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0071] Fig.11 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0072] Fig.12 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0073] Fig.13 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0074] Fig.14 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0075] Fig.15 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0076] Fig.16 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0077] Fig.17 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0078] Fig.18 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0079] Fig.19 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0080] Fig. 20 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0081] Fig.21 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0082] Fig. 22 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0083] Fig.23 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0084] Fig.24 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0085] Fig.25 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0086] Fig.26 is an exemplary diagram of manufacturing a MEMS resonator according to an embodiment of the present application;

[0087] Fig. 27 is another exemplary diagram of manufacturing a MEMS resonator according to an embodiment of the present application;

[0088] Fig.28 is another exemplary diagram of manufacturing a MEMS resonator according to an embodiment of the present application;

[0089] Fig.29 is another exemplary diagram of manufacturing a MEMS resonator according to an embodiment of the present application;

[0090] Fig.30 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0091] Fig.31 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0092] Fig.32 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0093] Fig.33 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0094] Fig.34 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0095] Fig.35 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0096] Fig.36 yes Fig.35 A top view of

[0097] Fig.37 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0098] Fig.38 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0099] Fig.39 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0100] Fig.40 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0101] Fig.41 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0102] Fig.42 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0103] Fig.43 is another exemplary diagram of a device structure formed according to an embodiment of the present application;

[0104] Fig.44 is another exemplary diagram of forming a device structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0105] With reference to the accompanying drawings, the above and other features of the present application will become apparent through the following description. In the description and the accompanying drawings, specific embodiments of the present application are specifically disclosed, which show some embodiments in which the principles of the present application can be adopted. It should be understood that the present application is not limited to the described embodiments. On the contrary, the present application includes all modifications, variations and equivalents falling within the scope of the attached claims.

[0106] In the embodiments of the present application, the term "and / or" includes any one and all combinations of one or more of the associated listed terms. The terms "include", "comprises", "has", etc. refer to the existence of the stated features, elements, components or components, but do not exclude the existence or addition of one or more other features, elements, components or components.

[0107] In the embodiments of the present application, the singular forms "a", "the", etc. may include plural forms, and should be broadly understood as "a kind" or "a type" rather than being limited to the meaning of "one"; in addition, the term "said" should be understood to include both singular and plural forms, unless the context clearly indicates otherwise. In addition, the term "according to" should be understood as "at least partially based on...", and the term "based on" should be understood as "at least partially based on...", unless the context clearly indicates otherwise. In addition, the terms "close to" and "far away" in this application are only used to illustrate the relative positional relationship of the components, and do not indicate the size or specific degree of distance. For example, "far away" can also be referred to as "deviate from", etc.

[0108] In addition, in the following description of the present application, for the convenience of explanation, one side of the substrate (also referred to as a base or substrate) is referred to as the lower side or the lower side, the side opposite to the substrate is referred to as the upper side or the upper side, the side close to the center of the resonator is referred to as the inner side, and the side away from the center of the resonator is referred to as the outer side. However, it is worth noting that these are only for the convenience of explanation and do not limit the orientation of the MEMS resonator of the embodiment of the present application during manufacture and use.

[0109] Figure 1 FIG. 1 is a schematic diagram of a MEMS resonator according to an embodiment of the present application, showing the structure of a piezoelectrically driven silicon-based MEMS resonator. Figure 1 As shown, 1101 is the substrate layer, 1102 is the lower cavity (close to the device layer side), 1201 is the device layer, 1202 is the piezoelectric layer, 1203 is the upper electrode layer, 1204 is the silicon dioxide bonding layer, 1301 is the silicon cap layer, 1302 is the upper cavity (close to the piezoelectric layer side), 1303 is the metal bonding layer, 1304 is the conductive hole, and 1305 is the external pin.

[0110] like Figure 1 As shown, there is a cavity 1102 located in the substrate layer 1101 below the device layer 1201, and a bonded silicon cap layer 1301 is located above the piezoelectric layer 1202, and there is a conductive hole 1304 for leading out the signal in the silicon cap layer 1301. In this structure, because the surface metal of the pin part that contacts the probe will be damaged, this pin part can no longer be reused for bonding, so the signal pin located in the upper electrode layer 1203 needs to include two parts, one for the probe contact during device testing, and the other for bonding with the silicon cap layer 1301. Therefore, Figure 1 The structure shown is not conducive to chip size reduction.

[0111] The implementation of the embodiments of the present application will be described below with reference to the accompanying drawings.

[0112] The present application provides a MEMS resonator. Figure 2 Schematic diagram of a MEMS resonator according to an embodiment of the present application. Figure 2 As shown, the MEMS resonator comprises:

[0113] The device structure 200 includes a substrate layer 101, a first cavity 102 located inside the substrate layer 101 or on the upper side of the substrate layer 101, a device layer 201 located on the upper side of the substrate layer 101, a piezoelectric layer 202 located on the upper side of the device layer 201, and a first electrode layer 203 located on the upper side of the piezoelectric layer 202; wherein a pin 108 is provided on the lower side of the substrate layer 101, and the pin 108 is electrically connected to the first electrode layer 203 via a conductive hole 103 penetrating the substrate layer 101 and an island structure 2011 penetrating the device layer 201.

[0114] In some embodiments, Figure 2 As shown, the MEMS resonator also includes:

[0115] The cap structure 300 includes a second cavity 302 . The cap structure 300 is bonded to the device structure 200 on the upper side of the first electrode layer 203 . The first cavity 102 and the second cavity 302 at least partially overlap in the thickness direction.

[0116] In some embodiments, the device layer is a doped silicon layer, and the doping concentration of at least a portion of the doped silicon layer is greater than 10 19 cm -3 For another example, the doping concentration of at least a portion of the doped silicon layer is greater than 10 20 cm -3 The present application is not limited thereto, and the doping concentration can be adjusted according to specific requirements.

[0117] In the embodiments of the present application, "electrical connection" can be understood as electrical connection or electrical conduction connection through conductive materials, that is, the two electrically connected components can be electrically connected, but it does not limit whether voltage has been applied or whether current is flowing. Those skilled in the art can understand that electrical connection (electrical conduction) is independent of voltage or current status.

[0118] In some embodiments, Figure 2 As shown, the substrate layer 101 has a conductive hole 103 penetrating the substrate layer 101 in the thickness direction, the conductive hole 103 has a first conductive structure 105 insulated from the substrate layer 101, and the device layer 201 has an island structure 2011, and the island structure 2011 is a part of the device layer 201 and is insulated from other parts of the device layer 201;

[0119] One end of the first conductive structure 105 is electrically connected to the pin 108 , and the other end is electrically connected to one end of the island structure 2011 . The other end of the island structure 2011 is electrically connected to the first electrode layer 203 via the second conductive structure 208 .

[0120] In some embodiments, the substrate layer 101 is a single crystal silicon substrate. The first conductive structure includes polycrystalline silicon. For example, the resistivity of the polycrystalline silicon is lower than 0.05Ω·cm. The present application is not limited thereto, and the conductivity may also be other values.

[0121] In some embodiments, the substrate layer 101 is a single crystal silicon substrate, and the first conductive structure includes single crystal silicon, that is, the first conductive structure and the substrate layer can be made of the same material and have the same resistivity. For example, the resistivity of the single crystal silicon is lower than 0.05Ω·cm. The present application is not limited thereto, and the conductivity can also be other values.

[0122] For example, the single crystal silicon or polycrystalline silicon may be doped with B (boron), P (phosphorus), or As (arsenic), and its resistivity may be 0.01 Ω·cm, 0.05 Ω·cm, 0.001 Ω·cm, 0.005 Ω·cm, or the like.

[0123] In some embodiments, Figure 2 As shown, there is a first insulating layer 104 between the substrate layer 101 and the device layer 201 , and there is also a first insulating layer 104 between the first conductive structure 105 in the conductive hole 103 and the substrate layer 101 .

[0124] In some embodiments, Figure 2 As shown, a first metal layer 106 is further provided between the device layer 201 and the substrate layer 101 , and a portion of the first metal layer 106 is electrically connected to the first conductive structure 105 as part of the island structure 2011 .

[0125] In some embodiments, Figure 2 As shown, there is a third insulating layer 207 between the island structure 2011 and the device layer 201. The third insulating layer 207 at least covers a portion of the sidewall and / or a portion of the upper surface of the piezoelectric layer 202.

[0126] In some embodiments, Figure 2 As shown, the third insulating layer 207 is at least partially located in the first metal layer 106 to insulate the portion of the first metal layer 106 from other portions.

[0127] In some embodiments, Figure 2As shown, a groove 209 penetrating the device layer 201 and the piezoelectric layer 202 is provided between the first cavity 102 and the second cavity 302 .

[0128] In some embodiments, the pins include at least one first pin for a driving end, and at least one first pin is electrically connected to the first electrode layer.

[0129] In some embodiments, the pins include at least two first pins for driving ends, and the at least two first pins are electrically connected to two electrodes of the first electrode layer respectively. Figure 2 As shown, the pin 108 includes at least two first pins 1081 for driving ends, and the first pins 1081 are electrically connected to two parts of the first electrode layer 203 respectively.

[0130] In some embodiments, Figure 2 As shown, the device structure 200 also has a second pin 1082, and the second pin is electrically connected to the device layer. For example, the second pin is grounded and is a ground pin. Figure 2 As shown, the second pin 1082 is electrically connected to the device layer 201 via the second conductive hole (grounding hole) 401. However, the present application is not limited thereto, for example, the second pin can also be used for driving, for example, the first pin and the second pin form a pair of driving ends.

[0131] like Figure 2 As shown, the device structure 200 may further include an insulating layer 107 , and the cap structure 300 may further include a substrate 301 , a getter layer 306 , and the like. Figure 2 The structure of the MEMS resonator of the embodiment of the present application is exemplarily shown, but the present application is not limited thereto, and for example, other components may also be included.

[0132] Figure 3 is another schematic diagram of the MEMS resonator of the embodiment of the present application, and Figure 2 The same contents will not be repeated. Figure 2 As shown, there is a second metal layer 205 between the device layer 201 and the first metal layer 106 , and a portion of the second metal layer 205 is in contact with a portion of the first metal layer 106 as part of the island structure 2011 .

[0133] In some embodiments, Figure 3 As shown, there is a second insulating layer 206 between the second metal layer 205 and the device layer 201 , and the second metal layer 205 and the device layer 201 are at least partially in electrical contact.

[0134] In some embodiments, Figure 3As shown, the third insulating layer 207 is at least partially located in the first metal layer 106 and / or the second metal layer 205, insulating the portion of the first metal layer 106 from other portions, and / or insulating the portion of the second metal layer 205 from other portions.

[0135] In some embodiments, Figure 3 As shown, there is also a second electrode layer 210 between the device layer 201 and the piezoelectric layer 202. Figure 3 As shown, a portion of the second electrode layer 210 serves as part of the island structure 2011 and is electrically connected to the second conductive structure 208 .

[0136] For example, the second conductive structure 208 may be made of the same material as the second electrode layer 210; alternatively, the second conductive structure 208 may be implemented by the second electrode layer 210, for example, may be formed by etching a portion of the second electrode layer 210. The present application is not limited thereto, and the second conductive structure 208 may also be other metal layers or doped polysilicon materials different from the second electrode layer 210.

[0137] Figure 4 is another schematic diagram of the MEMS resonator of the embodiment of the present application, and Figure 2 , Figure 3 The same contents will not be repeated. Figure 4 As shown, there is also a second electrode layer 210 between the device layer 201 and the piezoelectric layer 202. Figure 4 As shown, the island structure 2011 does not include a portion of the second electrode layer 210 .

[0138] The above describes the structure of the embodiment of the present application, but the present application is not limited thereto. The specific contents of each device or component can also refer to the relevant technology; in addition, Figures 1 to 4 Devices or components not shown, or reduced Figures 1 to 4 One or more devices or components.

[0139] In an embodiment of the present application, signal pins are led out from one side (lower side) of the substrate layer, and the pins in the first electrode layer (upper electrode) only need to include the part that is contacted by the probe during device testing, and do not need to include the part bonded to the silicon cap. The conductive holes and pins for signal lead-out can be located directly below the upper electrode pins, or have a certain overlap with the upper electrode pins, thereby reducing the chip size.

[0140] The following further describes the method for manufacturing the MEMS resonator according to the embodiment of the present application.

[0141] Figure 5A is a schematic diagram of a method for manufacturing a MEMS resonator according to an embodiment of the present application. Figure 5A As shown, the manufacturing method comprises:

[0142] 501. Form a device structure, the device structure comprising a substrate layer, a first cavity located inside the substrate layer or on the upper side of the substrate layer, a device layer located on the upper side of the substrate layer, a piezoelectric layer located on the upper side of the device layer, and a first electrode layer located on the upper side of the piezoelectric layer; wherein a pin is provided on the lower side of the substrate layer, and the pin is electrically connected to the first electrode layer via a conductive hole penetrating the substrate layer and an island structure penetrating the device layer.

[0143] In some embodiments, Figure 5A As shown, the manufacturing method also includes:

[0144] 502, forming a cap structure, wherein the cap structure includes a second cavity;

[0145] 503 , bonding the cap structure to the device structure on the upper side of the first electrode layer, wherein the first cavity and the second cavity at least partially overlap in a thickness direction.

[0146] It is worth noting that the above Figure 5A The embodiments of the present application are only schematically described, but the present application is not limited thereto. For example, the execution order of the various steps can be appropriately adjusted, and other steps can be added or some steps can be reduced. Those skilled in the art can make appropriate modifications based on the above content, and are not limited to the above attached. Figure 5A Records of.

[0147] Figure 5B FIG. 1 is a schematic diagram of forming a device structure according to an embodiment of the present application, and exemplarily shows a part of the process of forming a device structure according to an embodiment of the present application. Figure 5B As shown, the method includes:

[0148] 5011, forming a first conductive structure in a substrate layer; and

[0149] 5012. Form a first metal layer on the substrate layer; wherein the first metal layer is electrically connected to the first conductive structure.

[0150] For example, there is a first insulating layer between the first conductive structure and the substrate layer, and the first insulating layer also covers the substrate surface area outside the first conductive structure.

[0151] like Figure 5B As shown, the method also includes:

[0152] 5013, forming a first cavity inside or on the upper side of the substrate layer; and

[0153] 5014 , forming a device layer on the first metal layer by metal layer bonding.

[0154] like Figure 5B As shown, the method also includes:

[0155] 5015, forming the piezoelectric layer on the device layer; and

[0156] 5016. Form the island structure in the device layer, wherein the island structure is insulated from other parts of the device layer and the piezoelectric layer.

[0157] For example, etching is performed in the device layer to form an island structure, and the insulating layer is used to fill at least the gap between the island structure and the remaining devices. The insulating layer can also fill the gap between the bonding metal layer and other parts under the island structure.

[0158] like Figure 5B As shown, the method also includes:

[0159] 5017, forming the first electrode layer on the upper side of the piezoelectric layer; and

[0160] 5018. Electrically connect the first electrode layer to the other end of the island structure via a second conductive structure.

[0161] For example, a piezoelectric layer and a top electrode are formed above the device layer, and the top electrode is electrically connected to the island structure after crossing the insulating layer.

[0162] like Figure 5B As shown, the method also includes:

[0163] 5019, forming pins on the lower side of the substrate layer; and

[0164] 5020, electrically connecting the pin to one end of the island structure.

[0165] For example, the back side of the substrate layer can be thinned to expose the first conductive structure, and an insulating layer can be further deposited. The insulating layer is etched to expose the first conductive structure, and a metal pin structure is formed, so that the metal pin is electrically connected to the first conductive structure, thereby electrically connecting the pin to the island structure.

[0166] It is worth noting that the above Figure 5B The embodiments of the present application are only schematically described, but the present application is not limited thereto. For example, the execution order of the various steps can be appropriately adjusted, and other steps can be added or some steps can be reduced. Those skilled in the art can make appropriate modifications based on the above content, and are not limited to the above attached. Figure 5B Records of.

[0167] Figure 6 FIG. 1 is an example diagram of a device structure formed in an embodiment of the present application. Figure 6 As shown, firstly, a conductive hole 103 for leading out a signal is formed by etching on the silicon substrate layer 101, and the depth of the conductive hole 103 is generally above 50 um, for example above 100 um, but is not limited to the depth mentioned above.

[0168] The cross-sectional shape of the conductive hole can be any shape such as circular, elliptical, polygonal or a combination thereof, and the number of the conductive holes is generally the same as the number of signal ports. For example, there can be three positive drive terminals, negative drive terminals, and ground terminals, or there can be two drive terminals and ground terminals, or the number can be greater than the number of signal ports, for example: there can be multiple ground terminals, or multiple signal terminals.

[0169] In some embodiments, a first insulating layer is formed between the substrate layer and the device layer, and the first insulating layer is also formed between the first conductive structure in the conductive hole and the substrate layer.

[0170] Figure 7 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Figure 7 As shown, a uniform and dense silicon dioxide layer (first insulating layer 104) is formed on the substrate layer 101 by thermal oxidation (eg dry thermal oxidation or wet thermal oxidation), and its thickness is generally less than 2 um, for example, 500 nm or 1 um, but not limited thereto.

[0171] It is worth noting that Figure 7 The silicon dioxide layers illustrated on the left and right sides include the silicon dioxide layers formed on the outer edge of the entire wafer, rather than the silicon dioxide layers formed on the edge of a single chip. There will be multiple chips distributed continuously on the entire wafer.

[0172] Figure 8 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Figure 8 As shown, a doped polysilicon layer (first conductive structure 105) is grown on one side of the etched hole on the substrate layer 101, so that the polysilicon completely fills the conductive hole 103. The dopant of polysilicon can be phosphorus P, arsenic As, boron B and other elements, and the doping type can be N-type or P-type, and the doping concentration is generally greater than 10 18 cm -3 , for example, greater than 10 19 cm -3 , so that its resistivity is lower than 0.01Ω·cm.

[0173] Fig. 9 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig. 9As shown, the polysilicon layer on the surface of the substrate layer 101 can be removed by dry etching and / or chemical mechanical polishing (CMP) or the like. Optionally, the silicon dioxide layer on the surface is removed so that the polysilicon layer is left only in the conductive hole 103, and the surface of the polysilicon layer is flush or substantially flush with the silicon dioxide layer at the edge. For example, the surface of the polysilicon in the conductive hole may be slightly convex or concave, but its edge is flush with the silicon dioxide layer.

[0174] In some embodiments, a first metal layer is formed between the device layer and the substrate layer, and a portion of the first metal layer serves as part of the island structure and is electrically connected to the first conductive structure.

[0175] Fig.10 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.10 As shown, a metal layer (first metal layer 106) can be deposited on the surface of the above-mentioned substrate layer 101. The metal layer can be gold, aluminum, germanium, tin, copper and other metals for subsequent metal-silicon bonding or metal-metal bonding. The metal layer can also be a composite layer of multiple layers of metal materials, and can also include at least one layer of adhesion layer or barrier layer material, such as: Ti, TiW, Cr and other materials.

[0176] Fig.11 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.11 As shown, a cavity (first cavity 102) can be etched on the surface of the substrate layer 101, for example, the metal layer, the oxide layer and the silicon substrate material at the position of the first cavity 102 are etched away in sequence.

[0177] When the resonator works in an out-of-plane vibration mode, i.e., a large vibration amplitude is generated in the thickness direction, a cavity needs to be formed in the substrate layer 101, and its depth can be set according to the vibration amplitude of the resonator, for example, greater than 10um, or greater than 25um, or greater than 50um. Fig.11 As shown, the first cavity 102 may be located in the substrate layer 101 .

[0178] Fig.12 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.12 As shown, a cavity (first cavity 102) may be etched on the surface of the substrate layer 101, for example, the metal layer and the oxide layer at the position of the first cavity 102 are etched away in sequence.

[0179] When the resonator operates in the in-plane vibration mode, that is, the vibration mainly occurs in the horizontal direction, and no large vibration amplitude is generated in the thickness direction, at this time, the cavity can be formed only by etching the metal layer and the oxide layer. Fig.12As shown, the first cavity 102 may be located on the upper side of the substrate layer 101 .

[0180] Fig.13 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.13 As shown, another silicon wafer (device layer 201) can be bonded to the substrate layer 101, for example, by metal-silicon bonding. The silicon wafer is preferably a highly doped silicon material, so that the resonator has better frequency and temperature stability. For example, the dopant is phosphorus (P) or arsenic (As), the doping type is N-type, or the dopant is boron (B), the doping type is P-type, and the doping concentration is 10 19 cm -3 Above, further doping concentration is 10 20 cm -3 above.

[0181] In addition, the metal layer for bonding can be patterned before bonding.

[0182] Fig.14 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.14 As shown, the metal layer connected to the conductive via 103 can be patterned into discrete patterns.

[0183] Fig.15 is another exemplary diagram of a device structure formed according to an embodiment of the present application, showing a partial situation of a metal layer observed from above; Fig.16 FIG. 1 is another exemplary diagram of a device structure formed in an embodiment of the present application, showing a partial situation of observing a metal layer from above. Fig.15 and Fig.16 As shown, except for the metal layer connected to the signal terminal, the rest of the metal layer is connected to the grounding conductive hole, and the metal layer can also be patterned into any shape. For example, in each chip unit, the metal layer of the grounding part is at least connected to form a ring around the cavity.

[0184] In addition, the wafer involved in the above steps may also be replaced by an SOI wafer.

[0185] Fig.17 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.17 As shown, the wafer can be replaced with an SOI wafer, wherein 201 - 1 is the top silicon layer of the SOI wafer, 201 - 2 is the buried oxide layer of the SOI wafer, and 201 - 3 is the supporting silicon layer of the SOI wafer.

[0186] Generally speaking, the thickness of 201-1 is the same as the final target thickness of the device layer 201. Optionally, the thickness of 201-1 can be greater than the thickness of the device layer. After removing the supporting silicon layer 201-3 and the buried oxide layer 201-2, the thickness of 201-1 can be further thinned by dry etching or chemical mechanical polishing (CMP) to obtain the device layer.

[0187] Optionally, the thickness of 201-1 can be smaller than the thickness of the device layer 201. After removing the supporting silicon layer 201-3 and the buried oxide layer 201-2, the thickness of 201-1 can be further increased by epitaxially growing single crystal silicon or polycrystalline silicon and doping single crystal silicon or doped polycrystalline silicon, thereby obtaining the device layer 201.

[0188] Fig.18 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.18 As shown, the silicon wafer can be thinned to the thickness of the required device silicon layer by one or more of the methods such as wet etching, dry etching, grinding, chemical mechanical polishing, etc.

[0189] Optionally, after the silicon wafer is thinned to the target device layer thickness, phosphorus diffusion can be driven by heat, for example, by introducing POCl3 gas in a nitrogen environment at 1050°C, or by growing a layer of phosphate glass (PSG) material, i.e., a phosphorus-doped silicon oxide layer, on the surface, and then heating to diffuse the P in the device layer and then removing the surface silicon oxide layer, thereby further increasing the phosphorus doping concentration in the device layer, or obtaining a device layer with a doping concentration gradient varying along the thickness direction.

[0190] Optionally, after the silicon wafer is thinned to a thickness less than the target device layer thickness, the thickness is increased by epitaxially growing single crystal silicon or polycrystalline silicon and doping single crystal silicon or doped polycrystalline silicon to obtain a device layer. At this time, the doping concentration setting of the device layer can be more flexible.

[0191] Fig.19 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.19 As shown, the piezoelectric layer 202 and the top electrode (first electrode layer 203) can be formed in sequence, and the top electrode can be patterned.

[0192] The piezoelectric material may be: aluminum nitride, doped aluminum nitride, zinc oxide, PZT, lithium niobate, lithium tantalate, etc. It may be a single crystal piezoelectric material or a polycrystalline piezoelectric material. The doping element of doped aluminum nitride may be a rare earth element, such as scandium Sc, yttrium Y, etc.; the doping material may also be a II / XII group element, such as Ca, Mg, Sr, Zn, etc., or a IV / V group element, such as Ti, Zr, Hf, etc. The electrode layer material may be: molybdenum (Mo), aluminum (Al), copper (Cu), platinum (Pt), tantalum (Ta), tungsten (W), palladium (Pd), ruthenium (Ru), gold (Au), titanium (Ti), chromium (Cr), etc. and their alloys or composite stacks.

[0193] In addition, the electrode layer material can also be: doped polysilicon, the doping elements can be boron (B), phosphorus (P), arsenic (As), etc., and the doping concentration is generally greater than 10 19 cm -3 As mentioned above, the higher the doping concentration, the lower the sheet resistance of the electrode made of polysilicon will be, and the lower the electrical loss will be.

[0194] In some embodiments, a second electrode layer may be formed between the device layer and the piezoelectric layer. A portion of the second electrode layer may be electrically connected to the second conductive structure as part of the island structure.

[0195] For example, there may be a bottom electrode layer between the piezoelectric layer 202 and the device layer 201, and the bottom electrode layer may be a whole piece or may be patterned. Optionally, there may be an insulating layer between the bottom electrode layer and the piezoelectric layer, and the insulating layer material may be silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, tantalum pentoxide, etc. Optionally, there may be a passivation layer above the top electrode layer, such as dielectric materials such as aluminum nitride, silicon dioxide, silicon nitride, etc. Optionally, there may be a temperature compensation layer between any two adjacent layers and on the outermost side, such as silicon dioxide, doped silicon dioxide (e.g., fluorine doped), etc.

[0196] There are many kinds of planar structures of piezoelectrically driven silicon-based MEMS resonators, and the corresponding electrode arrangement structures are also different. There are also many kinds of vibration modes, such as in-plane flexural vibration mode, out-of-plane flexural vibration mode, width extensional mode (WE mode for short), length extensional mode (LE mode for short), Lamé mode, etc., but not limited to the above vibration modes. The resonant frequency that can be achieved can generally cover the range from tens of kHz to hundreds of MHz.

[0197] Fig. 20 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig. 20 As shown, the piezoelectric layer 202 at the position corresponding to the conductive hole can be etched to open a window. Fig. 20 There are three conductive holes, of which the one on the far right is a grounding hole. Fig. 20 In the embodiment shown, the grounding hole is connected to the device layer 201, but not to the top electrode layer (first electrode layer 203), so the piezoelectric layer 202 at the position corresponding to the grounding hole is not etched to open a window. In other solutions not shown, the grounding hole can also be omitted.

[0198] Fig.21 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.21 As shown, at the window position of the piezoelectric layer 202, the exposed device layer 201 is etched into an island structure 2011, that is, it is not connected to the surrounding device layers, and then the first metal layer 106 under the device layer 201 is also etched into the same shape. At this time, the boundary between the metal layer and the device silicon layer can be as shown in FIG. Fig.21 As shown flush, it may or may not be flush.

[0199] At this time, the island structure 2011 is electrically connected to the first conductive structure 105 in the conductive hole 103 corresponding to the signal end through the first metal layer 106, and the remaining device layer 201 is electrically connected to the first conductive structure 105 in the conductive hole 103 corresponding to the ground end through the first metal layer 106. Fig.14 In the case where the metal layer is patterned in advance, in this step, it is only necessary to etch the device layer 201 to form an island structure.

[0200] In some embodiments, a third insulating layer is formed between the island structure and the device layer.

[0201] Fig. 22 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig. 22 As shown, an insulating layer (third insulating layer 207) may be deposited so that the third insulating layer 207 completely fills the trench between the island structure 2011 and the rest of the device layer 201. The material of the third insulating layer 207 may be silicon dioxide, doped silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, tantalum pentoxide, etc., for example, silicon dioxide.

[0202] Fig.23 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.23As shown, the third insulating layer 207 above the electrode pin of the top electrode layer and the third insulating layer 207 above the island structure 2011 of the device layer 201 can be removed, and the corresponding top electrode is connected to the island structure through the metal layer (second conductive structure 208), thereby completing the electrical interconnection from the top electrode to the conductive hole.

[0203] Optionally, the metal layer (second conductive structure 208) also serves as the metal layer for subsequent bonding to the silicon cap; or the top electrode layer can be used as the metal layer for subsequent bonding to the silicon cap (not shown in the figure), or another metal layer can be deposited as the metal layer for subsequent bonding to the silicon cap (not shown in the figure).

[0204] Fig.24 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.24 As shown, the third insulating layer 207 retained after etching can at least cover the grooves between the island structures 2011 of the device layer 201 and the device layer surface under the metal layer (second conductive structure 208) that is not connected to the island structure, but the present application is not limited to this.

[0205] In addition, the passivation layer on the surface of the upper electrode layer can be formed before the third insulating layer 207 is formed, or can be formed after the third insulating layer 207 is formed, or the third insulating layer 207 can be used as the passivation layer. Fig.23 The situation shown.

[0206] In some embodiments, a trench penetrating the device layer and the piezoelectric layer is formed between the first cavity and the second cavity.

[0207] Fig.25 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.25 As shown, the third insulating layer 207, the piezoelectric layer 202, and the device layer 201 can be etched successively to form a groove structure, thereby defining the boundary of the suspended shape of the resonator. The layers to be etched successively are determined according to the actual stacking conditions.

[0208] The above exemplifies the situation where the device structure is formed, that is, the device side wafer is prepared.

[0209] Fig.26 FIG. 1 is an example diagram of manufacturing a MEMS resonator according to an embodiment of the present application. Fig.26 As shown, another silicon wafer may be used to make a silicon cap (cap structure 200 ), for example, a cavity (second cavity 302 ) is formed above each chip, and the second cavity 302 is generally larger than the first cavity 102 in lateral dimensions.

[0210] Optional, such as Fig.26As shown, a getter layer 306 may be formed in the second cavity 302, and the material of the getter layer 306 may be titanium (Ti) and titanium alloys, zirconium (Zr) and zirconium alloys, etc.

[0211] Fig. 27 FIG. 1 is another example diagram of manufacturing a MEMS resonator according to an embodiment of the present application. Fig. 27 As shown, optionally, there may be a silicon dioxide layer 307 formed by thermal oxidation on the surface of the silicon layer of the silicon cap.

[0212] Fig.28 FIG. 1 is another example diagram of manufacturing a MEMS resonator according to an embodiment of the present application. Fig.28 As shown, the thermal oxide layer on the back of the wafer (substrate layer 101) can be removed, and the wafer can be further thinned by a grinding method so that the conductive hole 103 is exposed on the surface of the wafer.

[0213] Fig.29 FIG. 1 is another example diagram of manufacturing a MEMS resonator according to an embodiment of the present application. Fig.29 As shown, an insulating layer 107 is formed on the back of the wafer, and a window is etched below the conductive hole 103 to expose the conductive hole 103. The insulating layer here can be a dielectric material, such as silicon dioxide, doped silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, tantalum pentoxide, etc., or an organic material, such as epoxy resin, polyimide, etc., but not limited to the listed materials.

[0214] like Figure 2 As shown, pins 108 can be finally formed, and pins 108 are electrically connected to the conductive holes through the openings of the insulating layer 107. Generally speaking, the material of the pins 108 is gold, copper, aluminum, and their alloys or their stacked combinations. Afterwards, the entire wafer is diced to form a number of single chips. If the chips are subsequently assembled by flip-chip, a ball implantation process step can also be performed on the pins 108 before dicing.

[0215] like Figure 2 As shown, the pin 108 includes at least two first pins 1081 for driving ends, and the first pins 1081 are respectively electrically connected to the first electrode layer 203. The device structure 200 also has a second pin 1082 for grounding ends, and the second pin 1082 is electrically connected to the device layer 201.

[0216] The above examples illustrate Figure 2 The fabrication process of the MEMS resonator is shown in Figure 3 or Figure 4 The manufacturing process of the MEMS resonator shown is similar. Figure 3 or Figure 4Part of the manufacturing process of the MEMS resonator shown is the same as that of the previous embodiment and is not described in detail. Only the differences are described below.

[0217] In some embodiments, forming the device structure further comprises: forming a second metal layer between the device layer and the first metal layer, a portion of the second metal layer being in contact with a portion of the first metal layer as part of the island structure.

[0218] In some embodiments, forming the device structure further comprises: forming a second insulating layer between the second metal layer and the device layer, the second metal layer and the device layer being in at least partial electrical contact.

[0219] Fig.30 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.30 As shown, when bonding the device layer 201 to the first metal layer 106, a metal layer (second metal layer 205) may be first formed on the side where the silicon wafer is bonded to the substrate layer, and patterned into a pattern corresponding to the first metal layer 106, thereby forming a metal bonding pair with the first metal layer 106. The material of the second metal layer 205 may be a metal such as gold, aluminum, germanium, tin, copper, etc., or a composite layer of multiple metal materials, and may also include at least one layer of adhesion layer or barrier layer material, such as Ti, TiW, Cr, etc.

[0220] Fig.31 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.31 As shown, an insulating layer (second insulation 206) can also be first formed on the side where the silicon wafer is bonded to the substrate layer. The insulating layer material can be silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, titanium oxide, tantalum pentoxide, etc., and the silicon layer corresponding to the conductive hole is patterned to expose the position, and then a second metal layer 205 is formed, and the second metal layer 205 is patterned into a pattern corresponding to the first metal layer 106, thereby forming a metal bonding pair with the first metal layer 106.

[0221] At this time, the second insulating layer 206 can, on the one hand, isolate the metal layer from the silicon layer, and on the other hand, when the insulating layer is made of silicon dioxide or doped silicon dioxide (the doping element can be F element), it can also play a role in temperature compensation of the resonator.

[0222] Fig.32 FIG. 1 is another example diagram of forming a device structure according to an embodiment of the present application. Fig.32As shown, the first metal layer 106 and / or the second metal layer 205 for bonding can be patterned separately before bonding, and the metal layer connected to the conductive hole can be patterned into a separate pattern. In the case of two layers of metal bonding, the effect formed after both are patterned and then bonded is similar to the effect of patterning one layer of metal. In addition, the patterns of the first metal layer 106 and the second metal layer 205 can be exactly the same, or the pattern on one side can be slightly smaller than the pattern on the other side, so that when there is a bonding alignment error, the corresponding layers are still guaranteed to be connected.

[0223] In the case of multiple layers, the etching is processed accordingly. Fig.31 In the case shown, the device layer 201, the second insulating layer 206, the second metal layer 205 and the first metal layer 106 need to be etched. The etching can be a one-step etching process or can be performed separately using different methods. Fig.32 In the illustrated case, the device layer 201 and the second insulating layer 206 need to be etched.

[0224] The above embodiments are merely exemplary of the embodiments of the present application, but the present application is not limited thereto, and appropriate modifications may be made based on the above embodiments. For example, the above embodiments may be used alone, or one or more of the above embodiments may be combined.

[0225] Some variations of the embodiments of the present application are described below.

[0226] Fig.33 is another exemplary diagram of a device structure formed in an embodiment of the present application, Fig.34 is another example diagram of a device structure formed in an embodiment of the present application; Fig. 9 The situation of modification.

[0227] like Fig.33 As shown, for example, the silicon dioxide layer on the surface can be completely removed by CMP. Fig.34 As shown, a first insulating layer 104 (generally silicon dioxide) can be further grown on the surface of the substrate layer 101, and a portion of the surface of the conductive hole 103 is etched to expose. When a metal bonding layer is subsequently deposited, the metal bonding layer is electrically connected to the exposed conductive hole 103.

[0228] In some embodiments, the first conductive structure may also be part of the substrate layer.

[0229] Fig.35 is another exemplary diagram of a device structure formed in an embodiment of the present application, Fig.36 yes Fig.35 A top view of Fig.37 is another exemplary diagram of a device structure formed in an embodiment of the present application, Fig.38is another exemplary diagram of a device structure formed in an embodiment of the present application, Fig.39 is another example diagram of a device structure formed in an embodiment of the present application; Figures 6 to 9 The situation of modification.

[0230] In some embodiments, the substrate layer 101 may be a low-resistance single-crystal silicon substrate, wherein the single-crystal silicon resistivity is lower than 0.05Ω·cm. Fig.35 and Fig.36 As shown, an isolation ring structure is etched on the substrate layer 101, so that a part of the conductive hole 103 is laterally isolated from the rest of the substrate. At this time, the material of the conductive hole 103 is the same as that of the substrate layer 101, both of which are single crystal silicon.

[0231] like Fig.37 As shown, a dielectric layer (insulating layer 107) can be further grown to fill the isolation ring structure. The dielectric layer can be a silicon dioxide layer grown by thermal oxidation or LPCVD-TEOS or other methods, or the dielectric layer can be a stack of two dielectric materials, for example, a silicon dioxide layer is first grown on the surface of the substrate, at which time the isolation ring structure is not completely filled, and then polysilicon is grown by LPCVD or other methods to completely fill the isolation ring structure.

[0232] like Fig.38 As shown, the dielectric layer on the surface of the substrate layer 101 can be removed by CMP or dry etching to expose the surface of the substrate layer 101 again. Fig.39 As shown, an insulating layer (generally silicon dioxide) can be grown on the surface of the substrate layer 101 and etched to expose a portion of the surface of the conductive hole 103 .

[0233] The following Figures 19 to 25 A variation of will be described below.

[0234] Fig.40 is another exemplary diagram of a device structure formed in an embodiment of the present application, Fig.41 is another exemplary diagram of a device structure formed in an embodiment of the present application, Fig.42 is another exemplary diagram of a device structure formed in an embodiment of the present application, Fig.43 is another exemplary diagram of a device structure formed in an embodiment of the present application, Fig.44 is another example diagram of a device structure formed in an embodiment of the present application; Figures 19 to 25 The situation of modification.

[0235] like Fig.40 As shown, after forming the device layer 201, the island structure can be formed by etching first, and the metal bonding layer below is also etched into a corresponding pattern. Fig.41As shown, the etched grooves can be filled with insulating material (generally silicon dioxide), and the insulating layer on the surface of the resonator can be etched away to expose the position of the piezoelectric layer to be grown (eg, aluminum nitride, doped aluminum nitride, PZT, etc.).

[0236] like Fig.42 As shown, the piezoelectric layer 202 can be grown and etched so that the piezoelectric layer 202 is at least partially located above the resonator active area. Fig.43 As shown, the insulating layer above the island structure in the device layer 201 can be etched to expose the surface of the island structure below. Then the first electrode layer 203 (top electrode layer) is grown and formed, and etched into a corresponding pattern. The top electrode layer is electrically connected to the corresponding island structure. Fig.44 As shown, a groove penetrating the device layer 201 and the piezoelectric layer 202 may be formed.

[0237] The embodiment of the present application also provides an electrical product, which has the MEMS resonator as described above. The electrical product includes, for example, a MEMS oscillator, or a communication device using the MEMS resonator, etc., but the present application is not limited thereto.

[0238] It is worth noting that the above is only an exemplary description of the embodiments of the present application, but the embodiments of the present application are not limited thereto, and appropriate modifications can be made on the basis of the above embodiments. In addition, the above is only an exemplary description of each component, but the embodiments of the present application are not limited thereto, and the specific content of each component can also refer to the relevant technology; in addition, components not shown in the figure can be added, or one or more components in the figure can be reduced.

[0239] The embodiments of the present application are described above in conjunction with specific implementation methods, but it should be clear to those skilled in the art that these descriptions are exemplary and are not intended to limit the scope of protection of the embodiments of the present application. Those skilled in the art can make various modifications and variations to the embodiments of the present application based on the spirit and principles of the embodiments of the present application, and these modifications and variations are also within the scope of the embodiments of the present application.

[0240] The preferred embodiments of the present application are described above with reference to the accompanying drawings. Many features and advantages of these embodiments are clear from this detailed description, and therefore the appended claims are intended to cover all such features and advantages of these embodiments that fall within their true spirit and scope. In addition, since many modifications and changes are easily conceivable to those skilled in the art, it is not intended to limit the embodiments of the present application to the precise structures and operations illustrated and described, but all suitable modifications and equivalents that fall within its scope may be covered.

Claims

1. A MEMS resonator, characterized in that: The MEMS resonator comprises: A device structure, comprising a substrate layer, a first cavity located inside or on the upper side of the substrate layer, a device layer located on the upper side of the substrate layer, a piezoelectric layer located on the upper side of the device layer, and a first electrode layer located on the upper side of the piezoelectric layer; wherein a pin is provided on the lower side of the substrate layer, and the pin is electrically connected to the first electrode layer via a conductive hole penetrating the substrate layer and an island structure penetrating the device layer.

2. The MEMS resonator according to claim 1, characterized in that: The MEMS resonator further comprises: A cap structure includes a second cavity, wherein the cap structure is bonded to the device structure on an upper side of the first electrode layer, and the first cavity and the second cavity at least partially overlap in a thickness direction.

3. The MEMS resonator according to claim 1, characterized in that: The device layer is a doped silicon layer, and the doping concentration of at least part of the doped silicon layer is greater than 10 19 cm -3 .

4. The MEMS resonator according to claim 3, characterized in that: The doping concentration of at least part of the doped silicon layer is greater than 10 20 cm -3 .

5. The MEMS resonator according to claim 1, characterized in that: The substrate layer has the conductive hole penetrating the substrate layer in the thickness direction, the conductive hole has the first conductive structure insulated from the substrate layer, the device layer has the island structure, the island structure is a part of the device layer and is insulated from other parts of the device layer; One end of the first conductive structure is electrically connected to the pin, and the other end is electrically connected to one end of the island structure. The other end of the island structure is electrically connected to the first electrode layer via the second conductive structure.

6. The MEMS resonator according to claim 5, characterized in that: The first conductive structure includes polycrystalline silicon or single crystal silicon, and the resistivity of the polycrystalline silicon or single crystal silicon is lower than 0.05Ω·cm.

7. The MEMS resonator according to claim 5, characterized in that: There is a first insulating layer between the substrate layer and the device layer, and there is also the first insulating layer between the first conductive structure in the conductive hole and the substrate layer.

8. The MEMS resonator according to claim 5, characterized in that: A first metal layer is further provided between the device layer and the substrate layer, and a portion of the first metal layer serves as part of the island structure and is electrically connected to the first conductive structure.

9. The MEMS resonator according to claim 8, characterized in that: A second metal layer is provided between the device layer and the first metal layer, and a portion of the second metal layer as a portion of the island structure contacts a portion of the first metal layer.

10. The MEMS resonator according to claim 9, characterized in that: A second insulating layer is provided between the second metal layer and the device layer, and the second metal layer and the device layer are in at least partial electrical contact.

11. The MEMS resonator according to claim 5, characterized in that: A second electrode layer is provided between the device layer and the piezoelectric layer.

12. The MEMS resonator according to claim 11, characterized in that: A portion of the second electrode layer serves as part of the island structure and is electrically connected to the second conductive structure.

13. The MEMS resonator according to claim 9, characterized in that: A third insulating layer is provided between the island structure and the device layer.

14. The MEMS resonator according to claim 13, characterized in that: The third insulating layer at least covers a portion of the side wall and / or a portion of the upper surface of the piezoelectric layer.

15. The MEMS resonator according to claim 13, characterized in that: The third insulating layer is at least partially located in the first metal layer and / or the second metal layer, wherein the portion of the first metal layer is insulated from other portions and / or the portion of the second metal layer is insulated from other portions.

16. The MEMS resonator according to claim 2, characterized in that: A groove penetrating the device layer and the piezoelectric layer is provided between the first cavity and the second cavity.

17. The MEMS resonator according to claim 1, characterized in that: The pins include at least one first pin for a driving end, and at least one first pin is electrically connected to the first electrode layer.

18. The MEMS resonator according to claim 1, characterized in that: The pins include at least two first pins for driving ends, and the at least two first pins are electrically connected to two parts of electrodes of the first electrode layer respectively.

19. The MEMS resonator according to claim 17 or 18, characterized in that: The device structure also has a second pin, and the second pin is electrically connected to the device layer.

20. The MEMS resonator according to claim 19, characterized in that The second pin is grounded.

21. A method for manufacturing a MEMS resonator, characterized in that: The manufacturing method comprises: A device structure is formed, the device structure comprising a substrate layer, a first cavity located inside or on the upper side of the substrate layer, a device layer located on the upper side of the substrate layer, a piezoelectric layer located on the upper side of the device layer, and a first electrode layer located on the upper side of the piezoelectric layer; wherein a pin is provided on the lower side of the substrate layer, the pin being electrically connected to the first electrode layer via a conductive hole penetrating the substrate layer and an island structure penetrating the device layer.

22. The method according to claim 21, characterized in that The manufacturing method further comprises: forming a cap structure, the cap structure comprising a second cavity; The cap structure is bonded to the device structure on the upper side of the first electrode layer, and the first cavity and the second cavity at least partially overlap in the thickness direction.

23. The method according to claim 21, characterized in that The forming of the device structure comprises: forming a first conductive structure in the substrate layer; and A first metal layer is formed on the substrate layer; wherein the first metal layer is electrically connected to the first conductive structure.

24. The method according to claim 23, characterized in that The forming of the device structure further comprises: forming the first cavity inside or on the upper side of the substrate layer; and The device layer is formed on the first metal layer by metal layer bonding.

25. The method according to claim 23, characterized in that The forming of the device structure further comprises: forming a second metal layer under the device layer; and The first metal layer is bonded to the second metal layer.

26. The method according to claim 24 or 25, characterized in that The forming of the device structure further comprises: forming the piezoelectric layer on the device layer; and The island structure is formed in the device layer, and the island structure is insulated from other parts of the device layer and the piezoelectric layer.

27. The method according to claim 26, characterized in that A portion of the first metal layer as a portion of the island structure is electrically connected to the first conductive structure, and / or a portion of the second metal layer as a portion of the island structure is in contact with a portion of the first metal layer.

28. The method according to claim 26, characterized in that The forming of the device structure further comprises: forming the first electrode layer on the upper side of the piezoelectric layer; and The first electrode layer is electrically connected to the other end of the island structure via a second conductive structure.

29. The method according to claim 28, characterized in that The forming of the device structure further comprises: forming leads on a lower side of the substrate layer; and The pin is electrically connected to one end of the island structure.

30. An electrical product, characterized in that: The electrical product comprises the MEMS resonator according to any one of claims 1 to 20.

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