Low-delay low-power-consumption level conversion circuit based on MVT transistor
By combining the conversion stage circuit based on MVT transistor and the latch circuit in the level converter, the problems of high delay and power consumption in the communication of different voltage domains are solved, and the level conversion effect of low delay and low power consumption is achieved.
Patent Information
- Application Number
- CN202411776063.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-05
- Publication Date
- 2025-03-28
AI Technical Summary
Existing level converters have high power consumption and delay problems, especially in communication between different voltage domains. Traditional LS structures such as current mirror structures, differential casubar structures and Wilson current mirror structures all have competition problems and output signal uncertainty.
Using a low-delay low-power level conversion circuit based on MVT transistor, the input voltage of the latch circuit is lowered by combining the conversion stage circuit based on MVT transistor and the latch circuit, and the rising and falling edges of the clock are used to pull down the input terminal voltage of the latch circuit, and the output level is flipped through the latch circuit to achieve stable level conversion.
A large level conversion range is achieved, reducing the delay and power consumption of the level conversion circuit, and has the advantages of lower delay and power consumption.
Smart Images
Figure CN119727694A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low-delay and low-power level conversion circuit based on an MVT transistor. Background Art
[0002] Modern integrated circuit technology mostly adopts multi-voltage power supply design to reduce chip power consumption. Level shifters (LS) are needed to connect modules in different voltage domains. In addition, the process of modern CMOS integrated circuits is getting smaller and smaller, and the power supply voltage of the processor is as low as 1V. At the same time, the power supply of peripheral devices is still 3V or even 5V. Therefore, in order to communicate between circuits in different voltage domains, a level shifter with a wide voltage conversion range is necessary. At this stage, the level shifters are mainly traditional LS based on current mirror structure, traditional LS based on differential cascode structure, and LS based on Wilson current mirror. However, the traditional LS based on current mirror structure has very high power consumption, and the traditional LS based on differential cascode structure has competition problems. The LS based on Wilson current mirror still has the problem of transistor competition, and it is more difficult to flip the output signal, which increases the uncertainty of the output signal of the circuit. Summary of the invention
[0003] In order to solve the above technical problems, the purpose of the present invention is to provide a low-delay and low-power level conversion circuit based on MVT transistors, which can reduce the delay of the level conversion circuit and reduce the power consumption of the level conversion circuit.
[0004] The technical solution adopted by the present invention is: a low-delay and low-power level conversion circuit based on an MVT transistor, comprising a conversion stage circuit based on an MVT tube and a latch circuit, wherein the output end of the conversion stage circuit based on the MVT tube is connected to the input end of the latch circuit, wherein:
[0005] The conversion stage circuit based on the MVT tube is used to pull down the voltages of the two input terminals of the corresponding pull-down latch circuit at the rising edge and the falling edge of the clock;
[0006] The latch circuit obtains the signal pulled down from the conversion stage circuit, flips the output level, and obtains a stable signal after conversion.
[0007] Furthermore, the MVT tube-based conversion stage circuit includes a switch control circuit and an MVT tube conversion circuit, and the output end of the switch control circuit is connected to the input end of the MVT tube conversion circuit, wherein:
[0008] The switch control circuit is used to select the input voltage and drive one of the branches of the MVT tube conversion circuit at the rising edge and the falling edge of the input clock respectively;
[0009] The MVT tube conversion circuit is used to pull down the voltages of the two input terminals of the corresponding latch circuit according to the branch selected by the switch control circuit.
[0010] Further, the switch control circuit includes an inverter, a transmission gate, a first switch tube, a second switch tube, a third switch tube and a fourth switch tube, wherein the inverter and the transmission gate are both composed of low-threshold CMOS transistors, the input end of the inverter and the input end of the transmission gate are both connected to the input voltage signal, the inverter is powered by VDDL, the two complementary control ends C of the transmission gate are connected to VDDL, and C is reversely connected to VSS, the first end of the second switch tube and the first end of the fourth switch tube are both grounded, the output end of the inverter is connected to the input end of the first switch tube, the output end of the transmission gate is connected to the input end of the third switch tube, the second end of the first switch tube is connected to the second end of the second switch tube and connected to the first input end of the MVT tube conversion circuit, and the second end of the third switch tube is connected to the second end of the fourth switch tube and connected to the second input end of the MVT tube conversion circuit.
[0011] Further, the first switch tube is composed of a first NMOS tube, the second switch tube is composed of a second NMOS tube, the third switch tube is composed of a third NMOS tube, and the fourth switch tube is composed of a fourth NMOS tube, wherein the drain of the first NMOS tube serves as the first end of the first switch tube, the source of the first NMOS tube serves as the second end of the first switch tube, the gate of the first NMOS tube is connected to the second output control signal, the drain of the second NMOS tube serves as the first end of the second switch tube, the source of the second NMOS tube serves as the second end of the second switch tube, the gate of the second NMOS tube is connected to the first output control signal, the drain of the third NMOS tube serves as the first end of the third switch tube, the source of the third NMOS tube serves as the second end of the third switch tube, the gate of the third NMOS tube is connected to the first output control signal, the drain of the fourth NMOS tube serves as the first end of the fourth switch tube, the source of the fourth NMOS tube serves as the second end of the fourth switch tube, and the gate of the fourth NMOS tube is connected to the second output control signal. Further, the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are all high threshold transistors.
[0012] Further, the MVT tube conversion circuit includes a first PMOS tube, a second PMOS tube, a first MVT tube, a second MVT tube and a first NMOS enabling tube, wherein the source of the first PMOS tube and the source of the second PMOS tube VDDH, the gate of the first PMOS tube, the drain of the first PMOS tube, and the drain of the first MVT tube are connected to the second input end of the latch circuit, the gate of the second PMOS tube, the drain of the second PMOS tube, and the drain of the second MVT tube are connected to the first input end of the latch circuit, the gate of the first MVT tube serves as the first input end of the MVT tube conversion circuit, the gate of the second MVT tube serves as the second input end of the MVT tube conversion circuit, the source of the first MVT tube, the source of the second MVT tube are connected to the drain of the first NMOS enabling tube, the source of the first NMOS enabling tube is grounded, and the gate of the first NMOS enabling tube is connected to the enable signal.
[0013] Furthermore, the first PMOS transistor, the second PMOS transistor and the first NMOS enabling transistor are all high threshold transistors, and the first MVT transistor and the second MVT transistor are both MVT NMOS transistors.
[0014] Further, the latch circuit includes a first NAND gate and a second NAND gate, the first input end of the first NAND gate serves as the first input end of the latch circuit, the second input end of the first NAND gate is connected to the output end of the second NAND gate and outputs a second output control signal, the second input end of the second NAND gate serves as the second input end of the latch circuit, the first input end of the second NAND gate is connected to the output end of the first NAND gate and outputs a first output control signal.
[0015] The beneficial effect of the circuit of the present invention is that the conversion stage circuit based on the MVT tube of the present invention pulls down the voltages of the two input terminals of the corresponding latch circuit at the rising edge and the falling edge of the clock; then the signal pulled down from the conversion stage circuit is obtained according to the latch circuit, the output level is flipped, and a stable signal after conversion is obtained. Relying on the low threshold voltage characteristics of the MVT transistor, a larger level conversion range can be achieved, the delay of the level conversion circuit can be reduced, and the power consumption of the level conversion circuit can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is a circuit schematic diagram of a low-delay and low-power level conversion circuit based on an MVT transistor of the present invention;
[0017] Figure 2 is a schematic diagram of a multi-voltage system provided by a specific embodiment of the present invention;
[0018] Figure 3 It is a structural schematic diagram of an existing current mirror-based level conversion circuit provided by a specific embodiment of the present invention;
[0019] Figure 4It is a structural schematic diagram of an existing differential cascode-based level conversion circuit provided by a specific embodiment of the present invention;
[0020] Figure 5 It is a structural schematic diagram of an existing level conversion circuit based on Wilson current mirror provided by a specific embodiment of the present invention;
[0021] Figure 6 It is a schematic diagram of voltage waveforms of each node when the level conversion circuit provided by a specific embodiment of the present invention is working;
[0022] Figure 7 It is a schematic diagram of the pre-simulation results of LS delay and power consumption based on MVT tube under multi-temperature and multi-process provided by a specific embodiment of the present invention;
[0023] Figure 8 It is a schematic diagram of post-simulation results of LS delay and power consumption based on MVT tube under multi-temperature and multi-process provided by a specific embodiment of the present invention. DETAILED DESCRIPTION
[0024] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only provided for the convenience of explanation and description, and the order between the steps is not limited in any way. The execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.
[0025] First of all, it should be noted that nowadays more and more electronic devices use multi-voltage systems to reduce system power consumption, such as Figure 2 It is a multi-voltage system that connects modules in different voltage domains by a level converter. The communication between modules in different voltage domains requires the use of a level converter. Modern CMOS integrated circuit process is getting smaller and smaller, and the power supply voltage of the processor is as low as 1V. At the same time, the power supply of peripheral devices is still 3V or even 5V, so a level converter with a wide voltage conversion range is necessary.
[0026] In the prior art, such as Figure 3 As shown in the figure, it is a traditional LS based on the current mirror structure. When VIN is high, both the upper and lower tubes NM1 and PM1 are turned on, resulting in very large power consumption of the LS structure. Figure 4 As shown in the figure, it is a traditional LS based on a differential common source and common gate structure. Due to the differential structure, the power consumption of the LS of this structure is not as large as that of the LS based on the current mirror. However, when VIN changes from low to high, due to the delay of the inverter, VINB has not yet changed to low, and Q2 is still low. At this time, the pull-up tube PM1 and the pull-down tube NM1 begin to compete, and it takes a longer time to charge the capacitor at the Q1 node, resulting in a longer delay. If the input voltage is relatively low, the driving capability of NM1 is weaker than that of PM1, and it may even fail to correctly pull down the voltage of the Q1 node; as shown in the figure, it is not as powerful as the conventional LS based on the differential common source and common gate structure. Figure 5 As shown, it is based on the Wilson current mirror. The addition of PM3 tube also makes the static current of this structure relatively small and the power consumption is not large. When VIN changes from high to low, NM1 is closed and NM2 is opened, trying to pull the Q2 node low. At the same time, PM3 is turned on, and the previous state of Q1 is low, so there will be a small transient current I1 to charge the Q1 node. This current is mirrored as I2, trying to pull the Q2 node high. It can be seen that there is still a competition problem between the pull-up transistor PM2 and the pull-down transistor NM2.
[0027] Based on this, in order to solve the problem of relatively large delay or high power consumption of LS with traditional structure, the present invention proposes a low-delay and low-power LS based on MVT transistor. The proposed LS has the characteristics of low delay and low power consumption, and the structure can achieve a wider voltage conversion range.
[0028] Reference Figure 1 The present invention provides a low-delay and low-power level conversion circuit based on an MVT transistor, comprising a conversion stage circuit based on an MVT tube and a latch circuit, wherein the output end of the conversion stage circuit based on the MVT tube is connected to the input end of the latch circuit, wherein:
[0029] The conversion stage circuit based on the MVT tube is used to pull down the voltages of the two input terminals of the corresponding latch circuit at the rising edge and the falling edge of the input clock;
[0030] Specifically, the conversion stage circuit based on the MVT tube includes a switch control circuit and an MVT tube conversion circuit, wherein the output end of the switch control circuit is connected to the input end of the MVT tube conversion circuit, wherein the switch control circuit is used to select an input voltage and drive one of the branches of the MVT tube conversion circuit at the rising edge and the falling edge of the input clock respectively; the MVT tube conversion circuit is used to pull down the two input terminal voltages of the corresponding latch circuit according to the branch selected by the switch control circuit.
[0031] It should be further explained that the switch control circuit includes an inverter INV, a transmission gate TG, a first switch tube S1, a second switch tube S2, a third switch tube S3 and a fourth switch tube S4, wherein the input end of the inverter and the input end of the transmission gate are both connected to the input voltage signal VIN, the inverter is powered by VDDL, the two complementary input ends of the transmission gate are connected to VSS and VDDL respectively, the low threshold NMOS tube gate inside the transmission gate is connected to VDDL, and the low threshold PMOS tube gate inside the transmission gate is connected to VSS, so that the transmission gate is always turned on. The input signal VIN passes through the inverter and the transmission gate to generate two clock signals VINN and VINB with opposite phases and similar delays. The first end of the second switch tube and the first end of the fourth switch tube are both grounded, the output end of the inverter is connected to the input end of the first switch tube, the output end VINN of the transmission gate is connected to the input end of the third switch tube, the second end of the first switch tube is connected to the second end of the second switch tube and connected to the first input end VC1 of the MVT tube conversion circuit, and the second end of the third switch tube is connected to the second end of the fourth switch tube and connected to the second input end VC2 of the MVT tube conversion circuit.
[0032] More specifically, the first switch tube is composed of a first NMOS tube, the second switch tube is composed of a second NMOS tube, the third switch tube is composed of a third NMOS tube, and the fourth switch tube is composed of a fourth NMOS tube, wherein the drain of the first NMOS tube serves as the first end of the first switch tube, the source of the first NMOS tube serves as the second end of the first switch tube, the gate of the first NMOS tube is connected to the second output control signal OUT_B, the drain of the second NMOS tube serves as the first end of the second switch tube, the source of the second NMOS tube serves as the second end of the second switch tube, the gate of the second NMOS tube is connected to the first output control signal OUT, the drain of the third NMOS tube serves as the first end of the third switch tube, the source of the third NMOS tube serves as the second end of the third switch tube, the gate of the third NMOS tube is connected to the first output control signal OUT, the drain of the fourth NMOS tube serves as the first end of the fourth switch tube, the source of the fourth NMOS tube serves as the second end of the fourth switch tube, and the gate of the fourth NMOS tube is connected to the second output control signal OUT_B.
[0033] Among them, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are all high threshold transistors,
[0034] It should be further explained that the MVT tube conversion circuit includes a first PMOS tube PM1, a second PMOS tube PM2, a first MVT tube MVT1, a second MVT tube MVT2 and a first NMOS enable tube N1, wherein the source of the first PMOS tube and the source of the second PMOS tube are connected to the VDDH voltage, the gate of the first PMOS tube, the drain of the first PMOS tube and the drain of the first MVT tube are connected to the second input terminal VQ of the latch circuit, the gate of the second PMOS tube, the drain of the second PMOS tube and the drain of the second MVT tube are connected to the first input terminal VP of the latch circuit, the gate of the first MVT tube serves as the first input terminal VC1 of the MVT tube conversion circuit, the gate of the second MVT tube serves as the second input terminal VC2 of the MVT tube conversion circuit, the source of the first MVT tube and the source of the second MVT tube are connected to the drain of the first NMOS enable tube, the source of the first NMOS enable tube is grounded, and the gate of the first NMOS enable tube is connected to the enable signal.
[0035] The first PMOS transistor, the second PMOS transistor and the first NMOS enabling transistor are all high threshold transistors, and the first MVT transistor and the second MVT transistor are both MVTNMOS transistors.
[0036] The latch circuit obtains the signal pulled down from the conversion stage circuit, flips the output level, and obtains a stable signal after conversion.
[0037] Specifically, the latch circuit includes a first NAND gate NAND1 and a second NAND gate NAND2, which constitute an SR latch, wherein the first input end of the first NAND gate serves as the first input end VP of the latch circuit, the second input end of the first NAND gate is connected to the output end OUT of the second NAND gate and outputs the second output control signal OUT_B, the second input end of the second NAND gate serves as the second input end VQ of the latch circuit, the first input end of the second NAND gate is connected to the output end OUT_B of the first NAND gate and outputs the first output control signal OUT. At the same time, the first output control signal OUT and the second output control signal OUT_B control the four switch tubes in the switch control circuit through a feedback loop.
[0038] In summary, the level conversion circuit in the embodiment of the present invention adopts a 0.18μm standard CMOS process, and the design of LS is completed by comparing the traditional LS structure and the structure proposed by the present invention. Under the condition of 25 degrees, tt process angle, the simulation results show that the delay of the traditional LS based on the current mirror structure is 1.43ns and the power consumption is 63.52μW; the delay of the traditional LS based on the differential cascode structure is 5.71ns and the power consumption is 6.57μW; while the delay of the LS proposed by the present invention is as low as 2.17ns, and the power consumption is only 0.54μW. It can be seen that the LS structure proposed by the present invention has lower power consumption than the current mirror structure, and smaller delay than the differential cascode structure, and has the advantages of delay and power consumption.
[0039] Further, the working principle of the level conversion circuit of the embodiment of the present invention is described:
[0040] When the enable EN is turned off, the entire circuit does not work, the output remains in the previous state, and the power consumption is only 43nW at room temperature and tt process corner.
[0041] When the enable EN is turned on, the circuit starts to work. After VIN passes through the permanently open transmission gate and inverter, it generates signals VINN and VINB with opposite phases, which control two relatively independent circuits, respectively, and control the latch output flipping at the rising edge of VIN and the latch output flipping at the falling edge of VIN. Voltage waveforms of each node when the circuit is working Figure 6 shown.
[0042] When the input VIN is low and remains stable, the output OUT is low, OUT_B is high, the switch tubes S1 and S4 are turned on, and S2 and S3 are turned off, so VC1 is equal to VINN is low, and VC2 is equal to VSS is low. The tubes of the conversion stage are in the off state as a whole, and the current is very small, so the static power consumption of the circuit is very small.
[0043] When the input changes from low to high, the output OUT remains low, OUT_B is high, the switch tubes S1 and S4 are turned on, and S2 and S3 are turned off, so VC1 equals VINN to VDDL, and VC2 equals VSS to low. VC1 can turn on the MVT1 tube, pull down the VP voltage, and the output of the latch flips, OUT is high, and OUT_B is low. Close S1 and S4, open S2 and S3, VC1 is VSS, VC2 is VINB is low, turn off the MVT1 tube, and VP returns to a high potential.
[0044] The circuit operation process when the input VIN maintains a high level and when VIN changes from a high level to a low level is similar to the above two processes.
[0045] Finally, a simulation experiment is performed on the level conversion circuit of the present invention to illustrate:
[0046] The simulation conditions are typical working conditions: the input clock signal VIN is a square wave signal with a frequency of 1MHz, a high level of VDDL and a low level of VSS, a rise time and a fall time of 1ns, and a duty cycle of 50%; VDDL is 0.6V, VDDH is 3V; based on a 0.18μm standard CMOS process. Power consumption and delay are two very important indicators of the level converter, and the simulation will focus on these two indicators.
[0047] The pre-simulation results of the LS delay and power consumption of the second MVT tube under multiple temperature and multiple process corners are as follows: Figure 7 As shown, the post-simulation results Figure 8 As shown. The power consumption is less than 1μW at most temperatures and process corners. Except for the extremely bad cases, the delay of the pre-simulation is mostly between 1-4ns, and the post-simulation is between 2-5ns. It can be seen that the delay is less affected by temperature. Only under the ss process corner, the threshold voltage of the MOS tube increases, causing the circuit to work slower and the delay to increase. The power consumption of the pre-simulation and post-simulation is also around 1μW in most cases, and the power consumption will increase at high temperatures. It can be seen that the performance is far better than the LS of the traditional structure.
[0048] The above is a specific description of the preferred implementation of the present invention, but the invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.
Claims
1. A low-latency and low-power level conversion circuit based on MVT transistors, characterized in that: It includes a conversion stage circuit based on an MVT tube and a latch circuit, wherein the output end of the conversion stage circuit based on the MVT tube is connected to the input end of the latch circuit, wherein: The conversion stage circuit based on the MVT tube is used to pull down the voltages of the two input terminals of the corresponding latch circuit at the rising edge and the falling edge of the input clock; The latch circuit obtains the signal pulled down from the conversion stage circuit, flips the output level, and obtains a stable signal after conversion.
2. A low-delay, low-power level conversion circuit based on an MVT transistor according to claim 1, characterized in that: The conversion stage circuit based on the MVT tube includes a switch control circuit and an MVT tube conversion circuit, wherein the output end of the switch control circuit is connected to the input end of the MVT tube conversion circuit, wherein: The switch control circuit is used to select the input voltage and drive one of the branches of the MVT tube conversion circuit at the rising edge and the falling edge of the input clock respectively; The MVT tube conversion circuit is used to pull down the voltages of the two input terminals of the corresponding latch circuit according to the branch selected by the switch control circuit.
3. A low-delay, low-power level conversion circuit based on an MVT transistor according to claim 2, characterized in that: The switch control circuit includes an inverter, a transmission gate, a first switch tube, a second switch tube, a third switch tube and a fourth switch tube, wherein the inverter and the transmission gate are both composed of low-threshold CMOS transistors, the input end of the inverter and the input end of the transmission gate are both connected to the input voltage signal, the inverter is powered by VDDL, two complementary control ends of the transmission gate are respectively connected to VDDL and VSS, so that the transmission gate is always turned on, the first end of the second switch tube and the first end of the fourth switch tube are both grounded, the output end of the inverter is connected to the input end of the first switch tube, the output end of the transmission gate is connected to the input end of the third switch tube, the second end of the first switch tube is connected to the second end of the second switch tube and connected to the first input end of the MVT tube conversion circuit, and the second end of the third switch tube is connected to the second end of the fourth switch tube and connected to the second input end of the MVT tube conversion circuit.
4. According to claim 2, a low-delay and low-power level conversion circuit based on an MVT transistor, characterized in that: The first switch tube is composed of a first NMOS tube, the second switch tube is composed of a second NMOS tube, the third switch tube is composed of a third NMOS tube, and the fourth switch tube is composed of a fourth NMOS tube, wherein the drain of the first NMOS tube serves as the first end of the first switch tube, the source of the first NMOS tube serves as the second end of the first switch tube, the gate of the first NMOS tube is connected to the second output control signal, the drain of the second NMOS tube serves as the first end of the second switch tube, the source of the second NMOS tube serves as the second end of the second switch tube, the gate of the second NMOS tube is connected to the first output control signal, the drain of the third NMOS tube serves as the first end of the third switch tube, the source of the third NMOS tube serves as the second end of the third switch tube, the gate of the third NMOS tube is connected to the first output control signal, the drain of the fourth NMOS tube serves as the first end of the fourth switch tube, the source of the fourth NMOS tube serves as the second end of the fourth switch tube, and the gate of the fourth NMOS tube is connected to the second output control signal.
5. A low-delay, low-power level conversion circuit based on an MVT transistor according to claim 4, characterized in that: The first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are all high threshold transistors.
6. The low-delay and low-power level conversion circuit based on MVT transistor according to claim 2, characterized in that: The MVT tube conversion circuit includes a first PMOS tube, a second PMOS tube, a first MVT tube, a second MVT tube and a first NMOS enabling tube, wherein the source of the first PMOS tube and the source of the second PMOS tube are connected to VDDH, the gate of the first PMOS tube, the drain of the first PMOS tube and the drain of the first MVT tube are connected to the second input end of the latch circuit, the gate of the second PMOS tube, the drain of the second PMOS tube and the drain of the second MVT tube are connected to the first input end of the latch circuit, the gate of the first MVT tube serves as the first input end of the MVT tube conversion circuit, the gate of the second MVT tube serves as the second input end of the MVT tube conversion circuit, the source of the first MVT tube and the source of the second MVT tube are connected to the drain of the first NMOS enabling tube, the source of the first NMOS enabling tube is grounded, and the gate of the first NMOS enabling tube is connected to the enabling signal.
7. A low-delay, low-power level conversion circuit based on an MVT transistor according to claim 6, characterized in that: The first PMOS transistor, the second PMOS transistor and the first NMOS enabling transistor are all high threshold transistors, and the first MVT transistor and the second MVT transistor are both MVT NMOS transistors.
8. The low-delay and low-power level conversion circuit based on MVT transistor according to claim 1, characterized in that: The latch circuit includes a first NAND gate and a second NAND gate, the first input end of the first NAND gate serves as the first input end of the latch circuit, the second input end of the first NAND gate is connected to the output end of the second NAND gate and outputs a second output control signal, the second input end of the second NAND gate serves as the second input end of the latch circuit, the first input end of the second NAND gate is connected to the output end of the first NAND gate and outputs a first output control signal.