Oxide semiconductor thin film transistor and preparation method thereof

Abstract

The invention discloses a preparation method of an oxide semiconductor thin film transistor, which comprises the following steps: selecting a substrate, cleaning the substrate, and sequentially forming a back gate electrode, a back gate medium, a channel material, a source electrode and a drain electrode on the selected substrate from bottom to top to prepare the oxide semiconductor thin film transistor, wherein the deposition of the back gate medium and the channel material adopts an atomic layer deposition process; and performing ozone pulse treatment on the oxide semiconductor thin film transistor for a preset time. The oxide semiconductor thin film transistor can solve the problem that the switching state of the oxide semiconductor thin film transistor is abnormal due to too high current carriers, the threshold voltage of the oxide semiconductor thin film transistor can be accurately regulated and controlled, and the problem that the contact resistance is increased due to a high-temperature long-time thermal annealing process is solved; therefore, the performance of the oxide semiconductor thin film transistor is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to an oxide semiconductor thin film transistor and a preparation method thereof. Background Art

[0002] Thin Film Transistor (TFT) is a special transistor, which is characterized by using thin layer technology to deposit semiconductor materials and other materials on a substrate to form a transistor. Thin film transistors are mainly used in the field of active matrix liquid crystal display (AMLCD) and are one of the core components of modern display technology. The development of thin film transistor technology has gone through amorphous silicon thin film transistors, low-temperature polycrystalline silicon thin film transistors, oxide semiconductor thin film transistors, etc. Among the many thin film transistor technologies, oxide semiconductor thin film transistors have been widely used in active matrix displays, three-dimensional monolithic integration of embedded memories, sensors, and in-memory computing due to their advantages such as low-temperature preparation process, high mobility and extremely low leakage current.

[0003] Existing oxide semiconductor thin-film transistors usually exhibit an amorphous structure during preparation, and have a large number of defects in their body and surface, such as oxygen vacancies, and when hydrogen impurities are used as donor impurities, a large number of electrons are provided, resulting in an abnormal switching state of the oxide semiconductor thin-film transistor, so that the oxide semiconductor thin-film transistor operates in depletion mode, that is, when the gate voltage is equal to zero, the oxide semiconductor thin-film transistor still has a source-drain current, resulting in high power consumption of the oxide semiconductor thin-film transistor when it is working, limiting its application in CMOS and three-dimensional monolithic integration scenarios.

[0004] In order to meet the application of oxide semiconductor thin film transistors in different electronic circuits, it is necessary to control the threshold voltage of oxide semiconductor thin film transistors, especially to control the threshold voltage to shift positively in order to achieve the enhanced working mode. The usual methods for controlling the threshold voltage of oxide semiconductors include changing the thickness of the channel material, using metals with different work functions as gate electrodes, changing the channel carrier concentration, etc. Annealing is a commonly used method for changing the carrier concentration of oxide channel materials, because annealing can inhibit the formation of oxygen vacancies in oxide semiconductor thin film transistors, thereby solving the problem of excessive carrier concentration in the device.

[0005] However, the traditional thermal annealing method has an annealing time measured in hours or minutes, which restricts the development of efficient preparation. In addition, since thermal annealing is a uniform heating of the device, it will cause the redistribution of impurities in the semiconductor material, and even cause the impurity elements in the gate dielectric or substrate to diffuse into the channel material, thereby affecting the performance of the device. In addition, the vacuum degree of the thermal annealing process equipment is insufficient, and the chamber atmosphere is easily polluted by the atmospheric environment, which in turn introduces unexpected impurity contamination during the annealing process. The most important thing is that traditional thermal annealing will have a trade-off between performance and threshold voltage. This is because the traditional thermal annealing time is generally long, and the oxygen vacancy defects in the area under the source and drain contacts will be passivated, resulting in an increase in contact resistance, thereby reducing the saturation output current of the device and affecting the performance of the device. Therefore, it is necessary to explore a new threshold control method suitable for oxide semiconductor thin film transistors.

[0006] The present invention designs an oxide semiconductor thin film transistor and a preparation method thereof, which can solve the problem of abnormal switching state of the oxide semiconductor thin film transistor caused by excessive carriers, and can accurately control the threshold voltage of the oxide semiconductor thin film transistor, and improve the problem of increased contact resistance caused by high-temperature and long-term thermal annealing process, thereby improving the performance of the oxide semiconductor thin film transistor. Summary of the invention

[0007] In view of the defects of the prior art and the need for improvement, the present invention provides an oxide semiconductor thin film transistor and a method for preparing the same, which can solve the problem of abnormal switching state of the oxide semiconductor thin film transistor caused by excessive carriers, and can accurately control the threshold voltage of the oxide semiconductor thin film transistor, and improve the problem of increased contact resistance caused by high-temperature and long-term thermal annealing process, thereby improving the performance of the oxide semiconductor thin film transistor.

[0008] In order to solve the above technical problems, the present invention provides a method for preparing an oxide semiconductor thin film transistor, the method comprising the following steps:

[0009] Step S11, selecting a substrate, cleaning the substrate, and sequentially forming a back gate electrode, a back gate dielectric, a channel material, a source electrode, and a drain electrode on the selected substrate from bottom to top to prepare the oxide semiconductor thin film transistor, wherein the back gate dielectric and the channel material are deposited by an atomic layer deposition process; and

[0010] Step S12, performing ozone pulse treatment for a predetermined time on the oxide semiconductor thin film transistor.

[0011] Optionally, the substrate includes a film and a base, the film is silicon dioxide, aluminum oxide, hafnium oxide or beryllium oxide, and the base is silicon-based, silicon carbide or sapphire.

[0012] The step S11 specifically includes:

[0013] Step S21, washing the substrate with deionized water and drying it with nitrogen, wherein the thickness of the substrate is 250-400 um;

[0014] Step S22, spin coating photoresist on the substrate, baking the photoresist, photolithography, development, evaporation deposition of metal, and stripping process to prepare a marking layer as a marker for alignment of the layout layer;

[0015] Step S23, preparing the back gate electrode by spin coating photoresist, baking, photolithography, development, evaporation deposition of metal, and stripping process, wherein the thickness of the back gate electrode is 10-40 nm;

[0016] Step S24, depositing the back gate dielectric by an atomic layer deposition process, wherein the thickness of the back gate dielectric is 3-20 nm;

[0017] Step S25, depositing the channel material by an atomic layer deposition process, wherein the thickness of the channel material is 2-4 nm;

[0018] Step S26, isolating the active area by spin coating photoresist, baking the photoresist, photolithography, and developing processes, wherein after developing, the active area is isolated by etching with a dilute hydrochloric acid solution; and

[0019] Step S27, preparing the source electrode and the drain electrode by spin coating photoresist, baking the photoresist, photolithography, development, evaporation deposition of metal, and stripping process, wherein the thickness of the source electrode and the drain electrode is 30-100 nm.

[0020] Optionally, the channel material is indium oxide, zinc oxide, tin oxide, gallium oxide, indium zinc oxide, indium gallium oxide, indium tin oxide, zinc tin oxide, zinc gallium oxide, indium gallium zinc oxide, gallium tin zinc oxide, indium aluminum zinc oxide, indium magnesium zinc oxide, indium silicon zinc oxide, indium titanium zinc oxide, indium germanium zinc oxide, or indium molybdenum zinc oxide.

[0021] Optionally, the back gate electrode, the source electrode and the drain electrode are metals of one or a combination of two of nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt or iron.

[0022] Optionally, the precursors for depositing the back gate dielectric are tetrakis(ethylmethylammonium)hafnium (TEMAHf) and ozone.

[0023] Optionally, the precursors for depositing the channel material are trimethylindium and water molecules.

[0024] Wherein, in the step S12, the time of the ozone pulse treatment is 0-100 seconds, and the temperature of the ozone pulse treatment is 50-300 degrees Celsius.

[0025] The present invention also provides an oxide semiconductor thin film transistor, which is prepared by the above preparation method.

[0026] The oxide semiconductor thin film transistor and its preparation method provided by the present invention can solve the problem of abnormal switching state of the oxide semiconductor thin film transistor caused by excessive carriers, and can accurately control the threshold voltage of the oxide semiconductor thin film transistor to improve the performance of the oxide semiconductor thin film transistor. It also avoids the problems of more time-consuming and higher temperature requirements under the traditional thermal annealing process, and greatly improves the performance of the metal oxide semiconductor thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1a-1e A schematic diagram of the process steps for preparing an oxide semiconductor thin film transistor according to an embodiment of the present invention;

[0028] Figure 2 A flow chart of a method for preparing an oxide semiconductor thin film transistor provided by an embodiment of the present invention;

[0029] Figure 3 In the flow chart of a method for preparing an oxide semiconductor thin film transistor provided in an embodiment of the present invention Figure 2 Detailed step diagram of step S11;

[0030] Figure 4 A schematic diagram of the relationship between the gate voltage and the source-drain current of the oxide semiconductor thin film transistor according to an embodiment of the present invention; and

[0031] Figure 5 The graph is a comparison of the gate voltage and source-drain current relationship of the oxide semiconductor thin film transistor according to the embodiment of the present invention and the gate voltage and source-drain current relationship of the oxide semiconductor thin film transistor processed by the conventional thermal annealing method. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0033] The invention provides a method for preparing an oxide semiconductor thin film transistor. Figure 1a-1e FIG. 1 is a schematic diagram showing the process steps for preparing an oxide semiconductor thin film transistor according to an embodiment of the present invention. Figure 1aAs shown, a substrate 1 is provided, wherein the substrate 1 includes a thin film 11 and a base 12, wherein the thin film 11 includes but is not limited to dielectric materials such as silicon dioxide, aluminum oxide, hafnium oxide, beryllium oxide, etc., and the base 12 includes but is not limited to silicon-based, silicon carbide, sapphire, etc., wherein the thickness of the substrate 1 is 250-400um. In one embodiment, the thin film 11 is a silicon dioxide layer with a thickness of 10-100nm, and the base 12 is a silicon-based.

[0034] like Figure 1b As shown, a back gate electrode 2 is prepared on the surface of the substrate 1. Specifically, the back gate electrode 2 is prepared by processes such as spin coating photoresist, baking, photolithography, development, evaporation deposition, and stripping, wherein the evaporated metal includes but is not limited to one or a combination of two of nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt or iron, and the deposition thickness may be but is not limited to 10-40nm. Preferably, when preparing the back gate electrode 2 in the present invention, the evaporated metal is 3nm nickel and 15nm platinum.

[0035] like Figure 1c As shown, a back gate dielectric 3 is deposited on the substrate 1 and the back gate electrode 2. The back gate dielectric 3 includes but is not limited to materials such as hafnium dioxide, and the thickness of the back gate dielectric includes but is not limited to 3-20nm. Specifically, the back gate dielectric 3 is made by, but is not limited to, an atomic layer deposition (ALD) process. In one embodiment, hafnium dioxide is deposited as the back gate dielectric 3 by an atomic layer deposition device, and the precursors are tetra(ethylmethylamine)hafnium (TEMAHf) and ozone (O3). The reaction temperature is set to 150-280 degrees Celsius. The reaction temperature here is only an example of the present invention and cannot be used as a limitation of the present invention.

[0036] Figure 1d As shown, a channel material 4 is deposited on the back gate dielectric 3. The channel material 4 includes, but is not limited to, indium oxide, zinc oxide, tin oxide, gallium oxide, indium zinc oxide, indium gallium oxide, indium tin oxide, zinc tin oxide, zinc gallium oxide, indium gallium zinc oxide, gallium tin zinc oxide, indium aluminum zinc oxide, indium magnesium zinc oxide, indium silicon zinc oxide, indium titanium zinc oxide, indium germanium zinc oxide, indium molybdenum zinc oxide and other materials, and the thickness of the channel material 4 is, but is not limited to, 2-4 nm. Specifically, the channel material 4 includes, but is not limited to, being made using an atomic layer deposition process. In one embodiment, indium oxide is deposited as the channel material 4 by an atomic layer deposition device, the precursors are trimethyl indium (TMIn) and water molecules (H2O), and the reaction temperature is set to 200-225 degrees Celsius. The reaction temperature here is only an example of the present invention and cannot be used as a limitation of the present invention.

[0037] Figure 1eAs shown, a source electrode 5 and a drain electrode 6 are prepared on a channel material 4. The source and drain metal layers include, but are not limited to, nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt or iron. Specifically, it is made by processes such as spin coating photoresist, baking, photolithography, development, evaporation deposition, and stripping. In particular, the source and drain metal layers can be deposited by evaporation, and the deposition thickness can include, but is not limited to, 30-100nm. Preferably, when preparing the source and drain in one embodiment of the present invention, the evaporated and deposited metal is 15nm of nickel and 25nm of gold.

[0038] like Figure 2 FIG. 1 is a flow chart of a method for manufacturing an oxide semiconductor thin film transistor according to an embodiment of the present invention. The method shows a method for manufacturing an oxide semiconductor thin film transistor, which specifically includes the following steps:

[0039] Step S11: selecting a substrate, cleaning the substrate, and sequentially forming a back gate electrode, a back gate dielectric, a channel material, a source electrode, and a drain electrode on the selected substrate from bottom to top to prepare an oxide semiconductor thin film transistor, wherein the back gate dielectric and the channel material are deposited by an atomic layer deposition process;

[0040] Step S12: The oxide semiconductor thin film transistor is subjected to ozone pulse treatment for a predetermined time. The specific process is that in step S11, the selected substrate can be made of a silicon wafer substrate or a glass substrate; the back gate electrode, source and drain are made by spin coating photoresist, baking glue, photolithography, development, evaporation deposition, stripping and other process flows; the back gate dielectric and channel material are deposited by atomic layer deposition technology or other technology processes; before preparing the back gate electrode, it also includes preparing a marking layer by spin coating photoresist, baking glue, photolithography, development, evaporation deposition, stripping and other processes, and preparing markers for aligning different layout layers on the substrate; and before preparing the source and drain, the active area is isolated by spin coating photoresist, baking glue, photolithography, development and other processes. In step S12, the prepared oxide semiconductor thin film transistor is placed in the atomic layer deposition chamber, and the device is subjected to ozone pulse treatment. Specifically, the temperature of ozone pulse treatment includes but is not limited to 50-300 degrees Celsius, the ozone pulse is designed to be in the form of a rectangular pulse, the rectangular pulse time includes but is not limited to 0-100 seconds, the interval between rectangular pulses is 5-20 seconds, and finally the device is rinsed with 10-40 ozone pulses respectively, where the rectangular pulse time, the interval between rectangular pulses and the number of ozone pulses are not limited to this.

[0041] In one embodiment, first, a silicide substrate is selected, for example, composed of a silicon base and silicon dioxide, and metal is evaporated and deposited on the silicide as a back gate electrode by processes such as spin coating photoresist, baking, photolithography, development, evaporation deposition, and stripping; secondly, hafnium dioxide is deposited as a back gate dielectric and oxide is deposited as a channel material by an atomic layer deposition device; then, metal is evaporated and deposited as a source and a drain by processes such as spin coating photoresist, baking, photolithography, development, evaporation deposition, and stripping.

[0042] Figure 3 In the flow chart of a method for preparing an oxide semiconductor thin film transistor provided in an embodiment of the present invention Figure 2 The detailed step diagram of step S11 in the embodiment specifically includes:

[0043] Step S21, using deionized water to clean the substrate, and blow dry with nitrogen, wherein the substrate thickness is 250-400um. In one embodiment, deionized water is prepared by deionized water and ammonia water in a ratio of 5:1. 150 ml of deionized water and 30 ml of ammonia water are selected and poured into a beaker, and then heated to 70°C on a hot plate, and then 30 ml of hydrogen peroxide is added, and the solution is heated to 110°C. After the solution bubbles, the silicon wafer is immersed in the solution, and taken out after heating for 10 minutes, and the surface of the silicon wafer is cleaned with deionized water, and then blow dried with a nitrogen gun. It should be understood by those skilled in the art that the amount of solution, heating temperature, time, etc. in this embodiment are for illustrating the present invention and cannot be used as a limitation of the present invention.

[0044] Step S22, spin-coating photoresist on the substrate, baking, photolithography, development, evaporation and deposition of metal, and stripping process to prepare a marking layer as a marker for alignment of the layout layer. In one embodiment, first, polymethyl methacrylate (PMMA A4) electron beam photoresist is dripped on the cleaned substrate to cover two-thirds of the substrate surface area, and the photoresist is spin-coated using a glue spreader at a speed of 3000 revolutions per minute for 60 seconds; then, the glue is baked on a hot plate at a temperature of 180 degrees Celsius for 90 seconds; secondly, an electron beam lithography device is used to expose the marking layer as the layout; a developer solution with a mass ratio of methyl isobutyl ketone (MIBK) to isopropyl alcohol (IPA) of 1:3 is selected, and the substrate is immersed in the developer for 50 seconds, taken out and cleaned with IPA for 30 seconds, and then washed with Blow dry with a nitrogen gun; when evaporating and depositing metal, use an electron beam evaporation device to deposit the metal, and the deposited metal includes but is not limited to one or a combination of two of nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt or iron, such as depositing 20nm of nickel and 40nm of gold; when stripping, immerse the substrate in an acetone solution at 50 degrees Celsius for 30 minutes and then rinse with a syringe to strip off the photoresist and metal in the unexposed area, use IPA to clean after stripping, and then blow dry with a nitrogen gun. Those skilled in the art should understand that the amount of solution, heating temperature, time, thickness of deposited metal, etc. in this embodiment are for illustrating the present invention and cannot be used as a limitation of the present invention.

[0045] Step S23, prepare a back gate electrode by spin coating photoresist, baking, photolithography, development, evaporation deposition of metal, and stripping process, wherein the thickness of the back gate electrode is 10-40nm. Specifically, the layout design of the back gate electrode is used in the photolithography step, and the evaporated deposited metal includes but is not limited to one or a combination of two of nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt or iron, such as depositing 3nm of nickel and 15nm of platinum.

[0046] Step S24, depositing a back gate dielectric by an atomic layer deposition process, wherein the thickness of the back gate dielectric is 3-20 nm. Specifically, an atomic layer deposition device is used to grow an oxide as the back gate dielectric. In one embodiment, the back gate dielectric is hafnium dioxide, the precursors are tetra(ethylmethylamine) hafnium (TEMAHf) and ozone (O3), and the reaction temperature is set to 150-280 degrees Celsius.

[0047] Step S25, depositing channel material by atomic layer deposition process, wherein the thickness of the channel material is 2-4nm. Specifically, an atomic layer deposition device is used to grow oxide as the channel material, and the channel material includes but is not limited to indium oxide, zinc oxide, tin oxide, gallium oxide, indium zinc oxide, indium gallium oxide, indium tin oxide, zinc tin oxide, zinc gallium oxide, indium gallium zinc oxide, gallium tin zinc oxide, indium aluminum zinc oxide, indium magnesium zinc oxide, indium silicon zinc oxide, indium titanium zinc oxide, indium germanium zinc oxide, indium molybdenum zinc oxide. In one embodiment, indium oxide is deposited as the channel material, the precursors are trimethyl indium (TMIn) and water molecules (H2O), and the reaction temperature is set to 200-225 degrees Celsius.

[0048] Step S26, isolate the active area by spin coating photoresist, baking, photolithography, and developing process, wherein after developing, a dilute hydrochloric acid solution is used to etch and isolate the active area. In one embodiment, a hydrochloric acid solution with a pH value of 1 is first configured, and the developed substrate is immersed in the hydrochloric acid solution with the front side facing down, taken out after soaking for 6 minutes, and the substrate is rinsed with deionized water for about 1 minute, and then blown dry with a nitrogen gun; secondly, after etching is completed, the substrate is immersed in an N-methylpyrrolidone (NMP) solution at a temperature of 120 degrees Celsius for 2 hours to remove the undeveloped photoresist, and then soaked and cleaned with isopropanol, and then blown dry with a nitrogen gun, wherein the layout used in the photolithography step is the layout layer for active area isolation. Those skilled in the art should understand that the solutions, heating temperatures, times, etc. listed in this embodiment are for illustrating the present invention and cannot be used as limitations of the present invention.

[0049] Step S27, preparing the source and drain by spin coating photoresist, baking, photolithography, development, evaporation deposition of metal, and stripping process, wherein the thickness of the source and drain is 30-100nm. The metals for evaporation deposition of the source and drain include but are not limited to one or a combination of two of nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt or iron, such as depositing 15nm of nickel and 25nm of gold, wherein the photolithography uses the layout design of the source and drain contact layer.

[0050] Specifically, the photoresist mentioned in the above preparation process includes traditional photoresist and electron beam photoresist; photolithography includes traditional photolithography and electron beam lithography; evaporation deposition includes thermal evaporation deposition and electron beam evaporation deposition.

[0051] Figure 4 FIG. 1 is a schematic diagram showing the relationship between the gate voltage and the source-drain current of the oxide semiconductor thin film transistor according to an embodiment of the present invention. Figure 4As shown, a comparison diagram of the relationship between the gate voltage and the source-drain current of the oxide semiconductor thin film transistor of the embodiment of the present invention after 10, 20, 30, and 40 cycles of ozone pulse treatment respectively. The transfer curve of the thin film transistor treated with 10 cycles of ozone pulse does not show good switching characteristics. When the gate voltage is 0V, the oxide semiconductor thin film transistor is in the on state, and there is an excessively high carrier concentration in the channel material at this time. When the number of ozone pulses continues to increase, the switching characteristics of the oxide semiconductor thin film transistor are gradually optimized, and the threshold voltage gradually shifts positively, indicating that the ozone pulse treatment effectively regulates the concentration of oxygen vacancy defects in the channel material, thereby controlling the carrier concentration range and realizing the switching characteristics of the oxide semiconductor thin film transistor. After 40 cycles of ozone pulse treatment, the device exhibits good switching characteristics, and the on-state current is only slightly reduced compared to other conditions, which reflects that the carrier concentration of the oxide semiconductor thin film transistor has decreased, indicating that the ozone pulse treatment has little effect on the on-state current of the device, and the ozone pulse treatment achieves a better balance between the performance and threshold voltage of the oxide semiconductor thin film transistor.

[0052] Figure 5 1 is a comparison diagram of the gate voltage and source-drain current relationship of the oxide semiconductor thin film transistor of the embodiment of the present invention and the gate voltage and source-drain current relationship of the oxide semiconductor thin film transistor processed by the conventional thermal annealing method. Figure 5 As shown, the traditional thermal annealing method can also improve the switching characteristics of the oxide semiconductor thin film transistor and realize the positive shift of the threshold voltage. Compared with the oxide semiconductor thin film transistor of the embodiment of the present invention, after 40 ozone pulse cycles and 10 minutes of traditional thermal annealing treatment, the transfer curve shows a similar threshold voltage, indicating that both treatments have achieved similar passivation effects, but compared with the time, the ozone pulse treatment is more efficient. In the embodiment disclosed in the present invention, the total effective time of the ozone pulse treatment is 100s, while the total effective time of the traditional thermal annealing is 600s; secondly, the temperature of the ozone pulse treatment is lower, the temperature of the ozone pulse treatment is 50-300 degrees Celsius, and the preferred temperature is 200-225 degrees Celsius, while the thermal annealing temperature is 300-500 degrees Celsius. Taking the metal oxide indium oxide used in the present invention as an example, the preferred thermal annealing temperature is 400 degrees Celsius. Finally, due to the long thermal annealing time, the area under the source-drain contact will also be passivated, thereby increasing the contact resistance. In other words, in order to achieve the switching characteristics of the oxide semiconductor thin-film transistor, part of the device performance is inevitably sacrificed. Moreover, some application scenarios require the oxide semiconductor thin-film transistor to have a more positive threshold voltage, which will inevitably require a longer annealing time, resulting in greater performance degradation. Compared with the traditional thermal annealing process, the high efficiency of ozone pulse treatment helps to solve the trade-off between high performance and threshold voltage, and can complete the passivation of the channel material before having a significant impact on the contact area.

[0053] The oxide semiconductor thin film transistor and its preparation method provided by the present invention can solve the problem of abnormal switching state of the oxide semiconductor thin film transistor caused by excessive carriers, and can accurately control the threshold voltage of the oxide semiconductor thin film transistor to improve the performance of the oxide semiconductor thin film transistor. It also avoids the problems of more time-consuming and higher temperature requirements under the traditional thermal annealing process, and greatly improves the performance of the metal oxide semiconductor thin film transistor.

[0054] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for preparing an oxide semiconductor thin film transistor, characterized in that: include: Step S11, selecting a substrate, cleaning the substrate, and sequentially forming a back gate electrode, a back gate dielectric, a channel material, a source electrode, and a drain electrode on the selected substrate from bottom to top to prepare the oxide semiconductor thin film transistor, wherein the back gate dielectric and the channel material are deposited by an atomic layer deposition process; as well as Step S12, performing ozone pulse treatment for a predetermined time on the oxide semiconductor thin film transistor.

2. The method for preparing an oxide semiconductor thin film transistor according to claim 1, characterized in that: The substrate comprises a film and a base, wherein the film is silicon dioxide, aluminum oxide, hafnium oxide or beryllium oxide, and the base is silicon-based, silicon carbide or sapphire.

3. The method for preparing an oxide semiconductor thin film transistor according to claim 1, characterized in that: The step S11 specifically includes: Step S21, washing the substrate with deionized water and drying it with nitrogen, wherein the thickness of the substrate is 250-400 um; Step S22, spin coating photoresist on the substrate, baking the photoresist, photolithography, development, evaporation deposition of metal, and stripping process to prepare a marking layer as a marker for alignment of the layout layer; Step S23, preparing the back gate electrode by spin coating photoresist, baking, photolithography, development, evaporation deposition of metal, and stripping process, wherein the thickness of the back gate electrode is 10-40 nm; Step S24, depositing the back gate dielectric by an atomic layer deposition process, wherein the thickness of the back gate dielectric is 3-20 nm; Step S25, depositing the channel material by an atomic layer deposition process, wherein the thickness of the channel material is 2-4 nm; Step S26, isolating the active area by spin coating photoresist, baking the photoresist, photolithography, and developing processes, wherein after developing, the active area is isolated by etching with a dilute hydrochloric acid solution; and Step S27, preparing the source electrode and the drain electrode by spin coating photoresist, baking the photoresist, photolithography, development, evaporation deposition of metal, and stripping process, wherein the thickness of the source electrode and the drain electrode is 30-100 nm.

4. The method for preparing an oxide semiconductor thin film transistor according to claim 3, characterized in that: The channel material is indium oxide, zinc oxide, tin oxide, gallium oxide, indium zinc oxide, indium gallium oxide, indium tin oxide, zinc tin oxide, zinc gallium oxide, indium gallium zinc oxide, gallium tin zinc oxide, indium aluminum zinc oxide, indium magnesium zinc oxide, indium silicon zinc oxide, indium titanium zinc oxide, indium germanium zinc oxide, and indium molybdenum zinc oxide.

5. The method for preparing an oxide semiconductor thin film transistor according to claim 3, characterized in that: in, The back gate electrode, the source electrode and the drain electrode are made of one or a combination of two of nickel, titanium, ruthenium, rhodium, palladium, silver, osmium, iridium, platinum, gold, titanium, aluminum, chromium, germanium, molybdenum, tungsten, copper, cobalt or iron.

6. The method for preparing an oxide semiconductor thin film transistor according to claim 3, characterized in that: in, The precursors for depositing the back gate dielectric are tetrakis(ethylmethylamine)hafnium (TEMAHf) and ozone.

7. The method for preparing an oxide semiconductor thin film transistor according to claim 4, characterized in that: in, The precursors for depositing the channel material are trimethylindium and water molecules.

8. The method for preparing an oxide semiconductor thin film transistor according to claim 1, characterized in that: In step S12, the duration of the ozone pulse treatment is 0-100 seconds.

9. The method for preparing an oxide semiconductor thin film transistor according to claim 8, characterized in that: In step S12, the temperature of the ozone pulse treatment is 50-300 degrees Celsius.

10. An oxide semiconductor thin film transistor, characterized in that: The oxide semiconductor thin film transistor is prepared by the method for preparing the oxide semiconductor thin film transistor as claimed in claim 1.

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