Planar power diode

Abstract

The invention relates to a planar power diode, and belongs to the field of semiconductor power devices. The diode comprises a substrate region; the drift region is positioned on the surface of the substrate region; a second electrode semiconductor region in the drift region; the terminal voltage-resistant regions are located in the drift region and distributed on the two sides of the second electrode semiconductor region; the lower part of the second electrode metal region is positioned on the upper surfaces of the second electrode semiconductor region and the terminal voltage-withstanding region; the second electrode metal region middle part is positioned on the upper surface of the second electrode metal region lower part; the second electrode metal area upper part is positioned on the upper surface of the second electrode metal area middle part; the first insulating passivation layers are positioned on the upper surfaces of the terminal voltage-resistant region and the drift region and are distributed on two sides of the lower part of the second electrode metal region; the second insulating passivation layers are positioned between the upper surface of the first insulating passivation layer and the upper part of the second electrode metal region and are distributed on two sides of the middle part of the second electrode metal region; and the first electrode metal region is positioned on the lower surface of the substrate region. The length of a packaging lead or a copper strip can be shortened, and occupied space is reduced.

Description

Technical Field

[0001] The invention belongs to the field of semiconductor power devices and relates to a planar power diode. Background Art

[0002] Power diodes are essential basic electronic components in power electronic systems and are one of the most widely used power semiconductor devices. Their main functions are rectification and freewheeling. In practical applications, power diodes can appear in single tube form or in module form. There is generally only one power diode chip in a single tube; while modules often include multiple chips, such as a single-phase full-bridge rectifier module containing 4 power diode chips; in some switching power modules, power diode chips and power switch tube chips are used together. Whether in a single tube or in a module, the electrodes on the surface of the power diode chip need to be connected to the electrodes of the remaining chips or the pins of the tube shell, and wires or copper strips are often used for bonding. Due to factors such as electrical isolation and process limitations, longer wires or copper strips will occupy a certain amount of space and will also introduce parasitic inductance, thereby affecting the switching speed and increasing switching losses. Therefore, advanced packaging technology reduces the device area and parasitic inductance by continuously shortening the length of the wires or copper strips. However, shortening the length of the wires or copper strips will affect the breakdown voltage of the chip.

[0003] Power diodes often need to withstand high voltages, so in addition to the active area for conduction in the power diode chip, a terminal withstand voltage area is generally set around the active area. The terminal withstand voltage area of ​​the power diode chip can be divided into two types in terms of structural morphology: table type and planar type. The planar terminal withstand voltage area has a simple process and is compatible with the active area process, and is more widely used. When the power diode chip is subjected to a reverse high voltage, the planar terminal withstand voltage area shares the high voltage distributed along the surface. This high voltage not only appears inside and on the surface of the chip, but also forms an electric field above the terminal withstand voltage area. Conductive materials such as metals (such as leads and copper strips) above the terminal withstand voltage area will affect the distribution of the electric field and ultimately affect the breakdown voltage of the chip. Therefore, when packaging and wiring, the leads or copper strips will be arc-shaped to keep a certain distance from the terminal withstand voltage area of ​​the chip to avoid affecting the breakdown voltage of the chip, but the arc-shaped leads or copper strips will increase the length, thereby occupying more space. Summary of the invention

[0004] In view of this, an object of the present invention is to provide a planar power diode, by setting a shielding structure on the terminal voltage-withstand area of ​​the chip, thereby avoiding affecting the terminal voltage-withstand area of ​​the power diode chip while shortening the length of the package lead or copper tape.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A planar power diode, comprising:

[0007] a substrate region of a first conductivity type;

[0008] A drift region of the first conductivity type located on the upper surface of the substrate region;

[0009] a second electrode semiconductor region of a second conductivity type located in the drift region;

[0010] A second conductivity type terminal withstand voltage region located in the drift region and distributed on both sides of the second electrode semiconductor region;

[0011] The lower part of the second electrode metal region is located on the upper surface of the second electrode semiconductor region and the terminal voltage-resistant region;

[0012] The middle part of the second electrode metal region is located on the upper surface of the lower part of the second electrode metal region;

[0013] An upper portion of the second electrode metal region located on an upper surface of a middle portion of the second electrode metal region;

[0014] A first insulating passivation layer located on the upper surface of the terminal voltage-withstanding region and the drift region and distributed on both sides of the lower portion of the second electrode metal region;

[0015] A second insulating passivation layer located between the upper surface of the first insulating passivation layer and the upper portion of the second electrode metal region and distributed on both sides of the middle portion of the second electrode metal region;

[0016] A first electrode metal region is located on the lower surface of the substrate region.

[0017] Furthermore, the upper portion of the second electrode metal region completely covers the top surface of the planar power diode, thereby forming an equipotential surface.

[0018] Furthermore, the middle portion of the second electrode metal region is rectangular or inverted trapezoidal.

[0019] Furthermore, the second electrode semiconductor region is an integral structure, or is a plurality of dispersed regions, and each region is separated by a drift region.

[0020] Furthermore, the terminal voltage-resistant region is an integral structure, or is a number of dispersed terminal rings, and each dispersed terminal ring is separated by a drift region.

[0021] The beneficial effect of the present invention is that the present invention can effectively eliminate the influence of the package lead or copper tape on the terminal withstand voltage area of ​​the power diode chip by introducing the second insulating passivation layer and the second electrode surface metal layer to form a metal shielding structure of the terminal withstand voltage area, thereby ensuring that the breakdown voltage of the chip is not disturbed. Compared with the conventional planar power diode structure, the present invention can further shorten the length of the package lead or copper tape, and even eliminate the need for wire bonding, thereby reducing the area occupied by the chip package lead and the parasitic inductance introduced by the lead. The planar power diode proposed by the present invention is particularly suitable for compact power electronic circuits and systems.

[0022] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0024] Figure 1 A schematic diagram of the planar power diode structure provided in Example 1 of the present invention;

[0025] Figure 2 A schematic diagram of the planar power diode structure provided by Embodiment 2 of the present invention;

[0026] Figure 3 A schematic diagram of the planar power diode structure provided in Example 3 of the present invention;

[0027] Figure 4 This is a schematic diagram of the planar power diode structure provided in Example 4 of the present invention.

[0028] Figure numerals: 1 - first electrode metal region; 2 - second electrode metal region; 3 - substrate region; 4 - drift region; 5 - second electrode semiconductor region; 6 - terminal withstand voltage region; 7 - first insulating passivation layer; 8 - second insulating passivation layer. DETAILED DESCRIPTION

[0029] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0030] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0031] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0032] The present invention provides a planar power diode structure, which can effectively eliminate the influence of package leads or copper strips on the terminal withstand voltage area of ​​a power diode chip through a terminal metal shielding technology, ensure that the breakdown voltage of the chip is not disturbed, and further shorten the length of the package leads or copper strips, or even eliminate the need for wire bonding, thereby reducing the volume occupied by the chip package leads and the parasitic inductance introduced by the leads. The planar power diode is described in detail below through several embodiments.

[0033] Example 1

[0034] like Figure 1 The planar power diode provided in this embodiment is shown, which includes:

[0035] A substrate region 3 heavily doped with a semiconductor of the first conductivity type;

[0036] A first electrode metal region 1 is located below the substrate region 3, and the first electrode metal region 1 is in contact with the substrate region 3;

[0037] A drift region 4 lightly doped with a semiconductor of the first conductivity type located on the substrate region 3, the drift region 4 being in contact with the substrate region 3;

[0038] A heavily doped second electrode semiconductor region 5 of the second conductivity type and a terminal withstand voltage region 6 of the second conductivity type are arranged inside the drift region 4, wherein the terminal withstand voltage region 6 is divided into two parts and is located on both sides of the second electrode semiconductor region 5, and the two parts are in contact with each other;

[0039] A second electrode metal region 2 located above the second electrode semiconductor region 5 and the terminal withstand voltage region 6, wherein the second electrode metal region 2 completely covers the upper surface of the second electrode semiconductor region 5 and partially covers the upper surfaces of the terminal withstand voltage regions 6 on both sides; wherein the second electrode metal region 2 is divided into three parts, namely, an upper part, a middle part and a lower part, and is in the shape of an inverted "I" as a whole; the upper part is the longer end of the "I" and completely covers the top of the diode device; the middle part is the vertical line in the middle of the "I"; the lower part is the shorter end of the "I" and completely covers the upper surface of the second electrode semiconductor region 5 and partially covers the upper surfaces of the terminal withstand voltage regions 6 on both sides;

[0040] A first insulating passivation layer 7 located on the upper surface of the terminal voltage-withstanding region 6 and the drift region 4 and distributed on both sides of the second electrode metal region 2, wherein the first insulating passivation layer 7 is embedded in the lower part of the second electrode metal region 2;

[0041] And a second insulating passivation layer 8 is located between the upper surface of the first insulating passivation layer 7 and below the upper part of the second electrode metal region 2 and distributed on both sides of the middle of the second electrode metal region 2. The second insulating passivation layer 8 is in contact with the second electrode metal region 2 and the first insulating passivation layer 7 respectively.

[0042] In this embodiment, by introducing a thicker second insulating passivation layer 8 into the planar power diode chip, thickening the second electrode metal region 2, and extending the second electrode metal region 2 to the entire chip surface, the chip surface is made into an equipotential surface, so that when the power diode is subjected to a reverse high voltage, the electric field above the chip terminal withstand voltage region 6 is confined in the insulating passivation layer and is determined by the thickness and dielectric constant of the insulating passivation layer. Based on the insulating passivation layer, the effect of the connecting metal wires (such as leads, copper strips, etc.) passing through the chip surface on the electric field in the terminal withstand voltage region 6 can be shielded to ensure that the breakdown voltage of the chip is not affected.

[0043] It should be noted that the thickness of the second insulating passivation layer 8 needs to be reasonably set to ensure that it is not broken down by the reverse high voltage, thereby maintaining safe and reliable operation.

[0044] In this embodiment, when the first conductivity type is N type, the second conductivity type is P type, the first electrode is a cathode, and the second electrode is an anode; when the first conductivity type is P type, the second conductivity type is N type, the first electrode is an anode, and the second electrode is a cathode.

[0045] In this embodiment, the semiconductor region may be made of silicon material, or may be made of germanium, gallium arsenide, gallium nitride, silicon carbide, gallium oxide, diamond, or aluminum nitride.

[0046] In this embodiment, the terminal voltage-withstanding region may be a floating field limiting ring, a junction terminal extension, a field plate, etc., or a combination structure of a floating field limiting ring, a junction terminal extension, and a field plate.

[0047] Example 2

[0048] In this embodiment, the middle portion of the second electrode metal region 2 is in an inverted trapezoidal shape. Figure 2 The vertex angle of the trapezoid needs to be reasonably set to avoid affecting the electric field distribution inside the second insulating passivation layer 8.

[0049] Example 3

[0050] In this embodiment, the second electrode semiconductor region 5 is configured as a plurality of dispersed regions distributed between the two terminal voltage-resistant regions 6, such as Figure 3 As shown, except for the second electrode semiconductor regions on both sides that are in contact with the terminal voltage-withstanding region, the remaining second electrode semiconductor regions are all surrounded by the drift region 4. In addition, the second electrode metal region 2 completely covers all the second electrode semiconductor regions.

[0051] Example 4

[0052] In this embodiment, the terminal voltage-withstanding region 6 is configured as a plurality of terminal rings of the second conductivity type distributed on both sides of the second electrode semiconductor region 5, such as Figure 4 As shown, except for the first ring as the main junction connected to the second electrode semiconductor region 5, the remaining terminal rings are surrounded by the drift region 4. Among them, a partial area of ​​the first ring as the main junction is covered by the second electrode metal region 2, and a partial area of ​​the first ring as the main junction and the remaining terminal rings are covered by the first insulating passivation layer 7.

[0053] It should be noted that the above embodiments are only used to illustrate the structure of the planar power diode proposed in the present invention, and should not be regarded as limiting the structure of the planar power diode. In addition to the above embodiments, the planar power diode proposed in the present invention can also be other structures. For example, in a specific embodiment of a planar power diode, the middle part of its second electrode metal region 2 is in an inverted trapezoidal shape, and its second electrode semiconductor region 5 is a plurality of dispersed regions distributed between two parts of the terminal withstand voltage region 6. For another example, in a specific embodiment of a planar power diode, the middle part of its second electrode metal region 2 is in an inverted trapezoidal shape, and its terminal withstand voltage region 6 is a plurality of terminal rings of the second conductivity type uniformly distributed on both sides of the second electrode semiconductor region 5. Alternatively, in a specific embodiment of a planar power diode, the second electrode semiconductor region 5 is a plurality of dispersed regions, and the terminal withstand voltage region 6 is a plurality of terminal rings of the second conductivity type distributed on both sides of the second electrode semiconductor region 5.

[0054] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A planar power diode, characterized in that: It includes: a substrate region of a first conductivity type; A drift region of the first conductivity type located on the upper surface of the substrate region; a second electrode semiconductor region of a second conductivity type located in the drift region; A terminal withstand voltage region of the second conductivity type located in the drift region and distributed on both sides of the second electrode semiconductor region; The lower part of the second electrode metal region is located on the upper surface of the second electrode semiconductor region and the terminal voltage-resistant region; A middle portion of the second electrode metal region located on the upper surface of the lower portion of the second electrode metal region; An upper portion of the second electrode metal region located on an upper surface of a middle portion of the second electrode metal region; A first insulating passivation layer located on the upper surfaces of the terminal voltage-withstanding region and the drift region and distributed on both sides of the lower portion of the second electrode metal region; A second insulating passivation layer located between the upper surface of the first insulating passivation layer and the upper portion of the second electrode metal region and distributed on both sides of the middle portion of the second electrode metal region; A first electrode metal region is located on the lower surface of the substrate region.

2. The planar power diode according to claim 1, characterized in that: The upper portion of the second electrode metal region completely covers the top surface of the planar power diode.

3. The planar power diode according to claim 1, characterized in that: The middle portion of the second electrode metal region is rectangular.

4. The planar power diode according to claim 1, characterized in that: The middle portion of the second electrode metal region is in an inverted trapezoidal shape.

5. The planar power diode according to claim 1, characterized in that: The second electrode semiconductor region is composed of a plurality of dispersed regions, and each region is separated by the drift region.

6. The planar power diode according to claim 1, characterized in that: The terminal voltage-resistant region is composed of a plurality of dispersed terminal rings, and each dispersed terminal ring is separated by the drift region.

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