Composite waveguide structure and preparation method thereof

Abstract

The embodiment of the invention provides a composite waveguide structure and a preparation method thereof, and relates to the technical field of electro-optical modulators, and the composite waveguide structure comprises a waveguide wafer which comprises a silicon substrate, a SiO2 layer arranged on the top surface of the silicon substrate, a waveguide structure and a metal electrode, the waveguide structures and the metal electrodes are arranged in the SiO2 layer, the layers of the waveguide structures are higher than the layers of the metal electrodes, and the two adjacent waveguide structures on the horizontal projection are arranged on the two sides of the metal electrodes; the groove structure is arranged in the SiO2 layer, and the groove structure is located above the waveguide structure of the to-be-bonded area; and the electro-optical thin film layer is bonded in the groove structure and forms a composite waveguide structure with the waveguide structure below the groove structure. According to the scheme, the process structure compatibility of the bonding area and the non-bonding area is improved, and the application range or scene of the D2W heterogeneous integration technology can be widened.

Description

Technical Field

[0001] The present invention relates to the technical field of electro-optic modulation devices, and in particular to a composite waveguide structure and a preparation method thereof. Background Art

[0002] Optical communications, radio frequency photonic systems, millimeter wave measuring instruments and other equipment using optical devices have increasingly higher requirements for bandwidth. In semiconductor photonic modulators, the limitation of electron carrier transmission time fundamentally affects the high-frequency working characteristics of diode-based electro-optic modulators (EOM), which has aroused great interest in the research of materials with high-frequency electro-optic modulation characteristics. Lithium niobate (LN) has attracted extensive attention in integrated optics due to its superior electro-optical and nonlinear optical properties. Its Mach-Zehnder modulators (MZM) heterogeneously integrated with silicon or silicon nitride waveguides have been proven to achieve very high modulation bandwidths and can support high-frequency modulation far exceeding 100 GHz.

[0003] The processing method of this electro-optic modulator is preferably compatible with the traditional CMOS process used in silicon photonic devices, so as to obtain higher performance, lower cost and better manufacturing scalability. For the electro-optic modulation (composite waveguide) structure composed of thin-film lithium niobate and silicon nitride, it can usually be realized by die-to-wafer (D2W) or wafer-to-wafer (W2W) bonding.

[0004] In the prior art, the processing flow of the LN-SiNx composite waveguide structure compatible with the CMOS process is as follows:

[0005] (1) Preparing a silicon dioxide (SiO2) thin film with a thickness of 1 to 8 μm on a silicon substrate by thermal oxidation or chemical vapor deposition (CVD);

[0006] (2) Deposition of metal electrode thin film materials, such as aluminum (Al), with a thickness of 0.5 to 1.5 μm;

[0007] (3) Metal electrode patterning (dry etching of Al);

[0008] (4) SiO2 thin film deposition and chemical mechanical polishing (CMP) to make the SiO2 surface flat and the thickness above the Al electrode 200 to 500 nm;

[0009] (5) Silicon nitride (SiNx) waveguide film deposition, thickness 100-500 nm, refractive index 1.9-2.2;

[0010] (6) SiNx waveguide patterning (dry etching SiNx);

[0011] (7) SiO2 thin film deposition and CMP flattening, so that the SiO2 surface roughness is less than 0.3nm and the thickness above the SiNx waveguide is less than 150nm;

[0012] (8) Opening the electrode pad (dry etching SiO2) to expose the metal Al pad;

[0013] (9) Cutting and dicing a thin film LN substrate (LNOI) with a LN thickness of 100 to 500 nm into single chips (die) with a size greater than 1 mm × 1 mm;

[0014] (10) combining the single LN chip obtained by slicing in the above step (9) and the SiNx waveguide wafer processed in step (8) through plasma surface activation, pre-bonding, annealing and other steps to form an LN-SiNx composite waveguide;

[0015] (11) Remove the Si substrate of the LN chip by grinding, dry etching or wet etching.

[0016] It can be seen from the prior art step (7) that CMP flattening acts on the entire surface of the wafer, resulting in poor process structure compatibility between the bonding area (the area that needs to form a composite waveguide with LN) and the non-bonding area (e.g., the bonding area SiO2 as the interlayer spacing of the LN-SiNx composite waveguide needs to be thin enough <150nm, and the non-bonding area SiO2 as the cladding layer of the independent SiNx waveguide needs to be thick enough >1μm), which limits the diversity of device structures and functions that can be processed on the same wafer. In fact, for heterogeneous integration technology using traditional bonding methods, whether W2W, D2W or D2D, they are all implemented on a uniform flat bonding surface of the bonded sample, which limits its application on chip samples with special structures (e.g., grooves) or different structural heights. Summary of the invention

[0017] In view of this, an embodiment of the present invention provides a composite waveguide structure to solve the technical problems of poor process structure compatibility and limited application of the bonding area and non-bonding area of ​​the composite waveguide structure in the prior art. The composite waveguide structure includes:

[0018] A waveguide wafer, the waveguide wafer comprising a silicon substrate 1, a SiO2 layer 2 arranged on the top surface of the silicon substrate 1, a waveguide structure 4 and a metal electrode 3, wherein the waveguide structure 4 and the metal electrode 3 are arranged in the SiO2 layer 2 and the layer position of the waveguide structure 4 is higher than the layer position of the metal electrode 3, and two adjacent waveguide structures 4 are on both sides of the metal electrode 3 in horizontal projection;

[0019] A groove structure 8 is arranged in the SiO2 layer 2, and the groove structure 8 is located above the waveguide structure 4 in the area to be bonded;

[0020] The electro-optical thin film layer 10 is bonded in the groove structure 8 , and forms a composite waveguide structure with the waveguide structure 4 below the groove structure 8 .

[0021] The embodiment of the present invention also provides a method for preparing a composite waveguide structure to solve the technical problems of poor process structure compatibility and limited application of the bonding area and non-bonding area of ​​the composite waveguide structure in the prior art. The preparation method includes:

[0022] The SiO2 layer 2 is prepared on the top surface of the silicon substrate 1, and the waveguide structure 4 and the metal electrode 3 are prepared in the SiO2 layer 2;

[0023] forming the groove structure 8 above the waveguide structure 4 in the to-be-bonded region of the SiO2 layer 2;

[0024] The electro-optical thin film layer 10 is bonded in the groove structure 8 , and the electro-optical thin film layer 10 and the waveguide structure 4 below the groove structure 8 form a composite waveguide structure.

[0025] Compared with the prior art, at least one of the above-mentioned technical solutions adopted in the embodiments of this specification can achieve at least the following beneficial effects: it is proposed to set a groove structure in the SiO2 layer of the waveguide wafer, and the groove structure is located above the waveguide structure in the area to be bonded, so that the thickness of the cladding layer of the waveguide structure in the bonding area and the non-bonding area can be different, thereby improving the process structure compatibility of the bonding area and the non-bonding area, which is beneficial to improving the diversity of processable device structures and functions on the same wafer; in addition, the electro-optical thin film layer is bonded in the groove structure to realize the electro-optical thin film layer and the waveguide structure under the groove structure to form a composite waveguide structure, which limits the requirement for flattening the surface of the entire waveguide wafer to the requirement for flattening the bottom of the groove in the bonding area, thereby improving the process processing flexibility and expanding the application scope and scenarios of the D2W heterogeneous integration technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 is a schematic cross-sectional structure diagram of a composite waveguide structure provided by an embodiment of the present invention;

[0028] Figure 2 is a schematic plan view of the shape of a groove structure 8 provided by an embodiment of the present invention;

[0029] Figure 3 is a flow chart of a method for preparing a composite waveguide structure provided by an embodiment of the present invention;

[0030] Figure 4 It is a schematic cross-sectional structure diagram of a SiO2 thin film (i.e., the first SiO2 layer) prepared on a Si substrate provided by an embodiment of the present invention;

[0031] Figure 5 It is a schematic diagram of a cross-sectional structure of a metal electrode prepared on a SiO2 film provided by an embodiment of the present invention;

[0032] Figure 6 It is a schematic cross-sectional structure diagram of a method for preparing a first SiO2 passivation layer provided in an embodiment of the present invention;

[0033] Figure 7 It is a schematic cross-sectional structure diagram of a waveguide structure prepared on a first SiO2 passivation layer provided by an embodiment of the present invention;

[0034] Figure 8 It is a schematic diagram of a cross-sectional structure of a SiO2 waveguide cladding provided by an embodiment of the present invention;

[0035] Fig. 9 It is a schematic diagram of a cross-sectional structure of etching and filling a metal interconnection through hole provided by an embodiment of the present invention;

[0036] Fig.10 It is a schematic cross-sectional structure diagram of preparing a metal electrode and a thermal adjustment structure on a SiO2 waveguide cladding provided by an embodiment of the present invention;

[0037] Fig.11 It is a schematic cross-sectional structure diagram of a method for preparing a second SiO2 passivation layer provided in an embodiment of the present invention;

[0038] Fig.12 It is a schematic cross-sectional structure diagram of a groove structure etched in a bonding area provided by an embodiment of the present invention;

[0039] Fig.13 is a schematic cross-sectional structure diagram of a pad window provided by an embodiment of the present invention;

[0040] Fig.14 It is a schematic cross-sectional structure diagram of bonding an LN chip in a groove structure provided by an embodiment of the present invention.

[0041] Reference numerals in the figures:

[0042] 1. Silicon substrate; 2. SiO2 layer; 3. Metal electrode; 4. Waveguide structure; 6. Through hole; 7. Thermal adjustment structure; 8. Groove structure; 9. Window; 10. Electro-optical thin film layer; 1', Si substrate of LN chip; 2', buried oxide layer BOX; 201, first SiO2 layer; 202, first SiO2 passivation layer; 203, SiO2 waveguide cladding; 204, second SiO2 passivation layer. DETAILED DESCRIPTION

[0043] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0044] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0045] In an embodiment of the present invention, a composite waveguide structure is provided, such as Figure 1 As shown, the composite waveguide structure includes:

[0046] A waveguide wafer, the waveguide wafer comprising a silicon substrate 1, a SiO2 layer 2 arranged on the top surface of the silicon substrate 1, a waveguide structure 4 and a metal electrode 3, wherein the waveguide structure 4 and the metal electrode 3 are arranged in the SiO2 layer 2 and the layer position of the waveguide structure 4 is higher than the layer position of the metal electrode 3, and two adjacent waveguide structures 4 are on both sides of the metal electrode 3 in horizontal projection;

[0047] A groove structure 8 is arranged in the SiO2 layer 2, and the groove structure 8 is located above the waveguide structure 4 in the area to be bonded;

[0048] The electro-optical thin film layer 10 is bonded in the groove structure 8 , and forms a composite waveguide structure with the waveguide structure 4 below the groove structure 8 .

[0049] Depend on Figure 1As shown, in an embodiment of the present invention, it is proposed to set a groove structure in the SiO2 layer of the waveguide wafer, and the groove structure is located above the waveguide structure in the area to be bonded, so that the thickness of the cladding layer of the waveguide structure at the bonding area and the non-bonding area can be different, thereby improving the process structure compatibility of the bonding area and the non-bonding area, which is beneficial to improving the diversity of processable device structures and functions on the same wafer; in addition, the electro-optical thin film layer is bonded in the groove structure to realize the electro-optical thin film layer and the waveguide structure under the groove structure to form a composite waveguide structure, which limits the requirement for flattening the surface of the entire waveguide wafer to the requirement for flattening the bottom of the groove in the bonding area, thereby improving the process processing flexibility and expanding the application scope and scenarios of the D2W heterogeneous integration technology.

[0050] In specific implementation, the electro-optical film layer is bonded in the groove structure to realize that the electro-optical film layer and the waveguide structure below the groove structure form a composite waveguide structure, so that the cladding thickness of the waveguide structure at the bonding area and the non-bonding area can be different, thereby resolving the processing contradiction caused by the inconsistent structural thickness due to different structural characteristics and requirements in the bonding area and the non-bonding area. Specifically, in the process of preparing a waveguide wafer, after the waveguide structure is completed, it is usually necessary to continue to make other structures upward, such as a thermal adjustment structure or even more layers of metal interconnection. At this time, the structural thickness above the waveguide structure in the bonding area and the non-bonding area increases with the subsequent process. The more processing processes are required later, the thicker the structural thickness above the waveguide structure will become, but the thickness above the waveguide in the bonding area needs to be thin enough to be fixed below 150nm. This in-groove bonding method can well solve the above processing contradiction. Although it is possible to solve the above-mentioned processing contradiction by moving the waveguide structure to the last few steps of the entire chip process for processing (that is, the SiNx waveguide structure is at the top layer of the chip structure), since the SiNx waveguide structure is a front-end process, no back-end processes such as metal can appear before the SiNx waveguide structure. Ultimately, it can only be placed after the SiNx waveguide structure to do thermal adjustment structure or other multi-layer interconnected metal processes. Therefore, this solution is very limited and the actual feasibility is not high.

[0051] In a specific implementation, the material of the waveguide structure 4 can be SiNx, Si, etc.

[0052] In specific implementation, in order to ensure that the electro-optical thin film layer 10 bonded in the groove structure 8 can form a composite waveguide structure with the waveguide structure 4, it is proposed that the SiO2 thickness between the bottom surface of the groove structure 8 and the top surface of the waveguide structure 4 in the bonding area is less than 150nm.

[0053] In the specific implementation, it is mainly necessary to consider the dicing size deviation of the electro-optical thin film layer 10 (such as LN lithium niobate chip) ±15μm / side, and the size processing (photolithography etching) deviation of the groove structure 8 ±3μm / side. In order to ensure that the LN chip (or electro-optical thin film layer 10) can be embedded in the groove structure 8, it is proposed that when the electro-optical thin film layer 10 is bonded in the groove structure 8, the spacing M between the electro-optical thin film layer 10 and each side of the groove structure 8 is greater than or equal to 10μm (if the LN dicing and groove patterning processing accuracy is high, the spacing size can be set smaller), such as Figure 2 shown.

[0054] In specific implementation, in order to meet the bonding requirements of electro-optical thin film layers 10 of different shapes, it is proposed that the geometric shape formed by the outer boundary of the electro-optical thin film layer 10 is allowed to be embedded in the groove structure 8, that is, the shape of the groove structure 8 has no mandatory association with the shape of the electro-optical thin film layer 10, as long as the geometric shape formed by the outer boundary of the electro-optical thin film layer 10 can be embedded in the groove structure 8 and the distance from each point to the groove boundary is greater than 10μm everywhere.

[0055] In a specific implementation, the electro-optical thin film layer 10 can be an electro-optical thin film layer in a single electro-optical thin film chip formed by cutting and slicing an LNOI substrate (or an electro-optical thin film wafer), and the electro-optical thin film layer 10 can be any one of electro-optical materials such as lithium niobate, lithium tantalate, and barium titanate.

[0056] In specific implementation, the shape of the electro-optical thin film layer 10 can be various shapes, for example, in addition to being rectangular, it can also be a triangle, a circle, a regular polygon, etc. Figure 2 In fact, taking the processing of LN chips as an example, the dicing direction of the electro-optical thin film layer 10 is usually horizontal and vertical through the entire LNOI wafer, so the processed LN chips are basically rectangular blocks; LN chips of other shapes need to be more easily obtained by photolithography and etching using micro-transfer technology.

[0057] In the specific implementation, in order to realize the bonding of multiple chips on the same waveguide wafer through the groove structure 8 and improve the application scope or scenario, it is proposed that the groove structure 8 can be multiple, that is, the groove structures 8 are respectively set in multiple areas to be bonded on the same waveguide wafer, so that the same waveguide wafer has multiple groove structures 8 at the same time, and the depths and shapes of the multiple groove structures 8 can be the same; in addition, in order to avoid the influence of the setting of the grooves between adjacent groove structures 8 on the performance of the composite waveguide structure, it is proposed that the distance between two adjacent groove structures 8 can be greater than 10μm.

[0058] In specific implementation, in order to further improve the bonding of multiple chips on the same waveguide wafer and improve the scope or scenario of application, the groove structure 8 may be provided at some of the areas to be bonded in the multiple areas to be bonded of the SiO2 layer 2. That is, the groove structure 8 may be provided at all of the areas to be bonded, or the groove structure 8 may not be provided at all of the areas to be bonded, that is, the groove structure 8 may be provided at several individual areas to be bonded or some of the areas to be bonded in the multiple areas to be bonded, and in this case, the number of the groove structures 8 provided is less than the number of the areas to be bonded.

[0059] In specific implementation, in order to realize that the processing mode and preparation method of the composite waveguide structure can be compatible with the traditional CMOS process used in silicon photonic devices, such as Figure 3 As shown, a method for preparing the composite waveguide structure includes the following steps:

[0060] Step S301: preparing the SiO2 layer 2 on the top surface of the silicon substrate 1, and preparing the waveguide structure 4 and the metal electrode 3 in the SiO2 layer 2;

[0061] Step S302: forming the groove structure 8 above the waveguide structure 4 in the to-be-bonded region of the SiO2 layer 2;

[0062] Step S303: bonding the electro-optic thin film layer 10 in the groove structure 8, the electro-optic thin film layer 10 and the waveguide structure 4 below the groove structure 8 forming a composite waveguide structure. Specifically, the process of bonding the electro-optic thin film layer 10 in the groove structure 8 can be performed by bonding one side of the electro-optic thin film layer in the electro-optic material wafer (or electro-optic thin film wafer) to the bottom surface in the groove structure 8, and then removing the substrate in the electro-optic material wafer to complete the bonding of the electro-optic thin film layer 10.

[0063] In a specific implementation, the process of preparing the waveguide structure 4 and the metal electrode 3 in the SiO2 layer 2 may include the following steps:

[0064] Preparing a first SiO2 layer 201 on the top surface of the silicon substrate 1, and forming the metal electrode 3 on the top surface of the first SiO2 layer 201;

[0065] Prepare a first SiO2 passivation layer 202 and planarize it, wherein the first SiO2 passivation layer 202 covers the metal electrode 3 and the first SiO2 layer 201;

[0066] forming the waveguide structure 4 on the top surface of the first SiO2 passivation layer 202;

[0067] Prepare and planarize a SiO2 waveguide cladding 203, wherein the SiO2 waveguide cladding 203 covers the waveguide structure 4 and the first SiO2 passivation layer 202;

[0068] A through hole 6 is formed in the SiO2 layer above the metal electrode 3, and a metal is filled in the through hole 6 and a planarization process is performed;

[0069] The metal electrode 3 and the heat adjustment structure 7 are formed at the through hole 6 on the top surface of the SiO2 waveguide cladding 203;

[0070] A second SiO2 passivation layer 204 is prepared and planarized, wherein the second SiO2 passivation layer 204 covers the SiO2 waveguide cladding 203, the metal electrode 3 and the thermal adjustment structure 7, wherein the first SiO2 layer 201, the first SiO2 passivation layer 202, the SiO2 waveguide cladding 203 and the second SiO2 passivation layer 204 constitute the SiO2 layer 2.

[0071] In a specific implementation, in order to realize the provision of the groove structure 8 in the SiO2 layer 2, the process of forming the groove structure 8 above the waveguide structure 4 in the to-be-bonded region of the SiO2 layer 2 can be realized in the following two ways, for example,

[0072] The first method is to prepare the waveguide structure 4 and the metal electrode 3 in the SiO2 layer 2, and after the preparation of the SiO2 layer 2 is completed, a groove is formed above the waveguide structure 4 in the bonding area of ​​the SiO2 layer 2 to form the groove structure 8;

[0073] The first method is: after preparing the SiO2 waveguide cladding 203 and flattening it, a sacrificial layer is prepared on the top surface of the SiO2 waveguide cladding 203 above the waveguide structure 4 (the thickness of SiO2 between the waveguide structure 4 and the sacrificial layer is controlled within 150nm, and the thickness of the sacrificial layer can be less than 1μm), and the size of the sacrificial layer is consistent with the size of the groove structure 8; after preparing the metal electrode 3, the thermal adjustment structure 7 and the second SiO2 passivation layer 204, the SiO2 layer (2) is grooved to the sacrificial layer, and after exposing the sacrificial layer, the sacrificial layer is removed (such as removing the sacrificial layer by wet etching) to form the groove structure 8.

[0074] In specific implementation, the structure (including shape, size, etc.) of the sacrificial layer can be consistent with or similar to the structure of the groove structure 8. The sacrificial layer can be one of Al, TiN or α-Si. The sacrificial layer can be removed by wet etching.

[0075] In a specific implementation, the electro-optical thin film layer 10 is taken as a lithium niobate (LN) thin film, and the groove structure 8 is set as an example by grooving. The process example of preparing the composite waveguide structure may include the following steps:

[0076] 1. Preparation of the first SiO2 film (i.e., the first SiO2 layer) 201: Figure 4 As shown, a SiO2 film with a thickness of 1 to 8 μm can be prepared on a Si substrate 1 by CVD or thermal oxidation growth;

[0077] 2. Preparation of metal electrode 3: PVD deposits metal film (such as Al, Cu, Au, etc.) with a thickness of 0.5 to 1.5 μm; then the metal film is patterned by photolithography and etching to form a lead electrode structure, such as Figure 5 As shown;

[0078] 3. Preparation and planarization of the first SiO2 passivation layer 202: Figure 6 As shown, SiO2 is deposited by CVD and then planarized by CMP until the thickness of SiO2 above the metal electrode 3 is 200 to 500 nm;

[0079] 4. Preparation of SiNx film and waveguide patterning: CVD deposits a SiNx film with a thickness of 100 to 500 nm and a refractive index of 1.9 to 2.2, and then patterns the SiNx film through processes such as photolithography and etching to form a waveguide structure 4, such as Figure 7 As shown;

[0080] 5. Preparation and flattening of SiO2 waveguide cladding 203: Figure 8 As shown, a SiO2 film is deposited by CVD and planarized by CMP until the thickness of the SiO2 above the waveguide structure 4 is 1 to 3 μm;

[0081] 6. Etching and filling of metal interconnection through-hole 6: SiO2 is dry-etched to form interconnection through-hole 6, and then through-hole filling is completed by tungsten (W) CVD or Cu electroplating and other processes, and CMP planarization is performed, such as Fig. 9 As shown;

[0082] 7. Preparation of metal electrode 3 and thermal adjustment structure 7: PVD deposits a metal film with a thickness of 0.5 to 1.5 μm and performs patterning to form metal electrode 3, and then PVD deposits a TiN film with a thickness of 50 to 150 nm and performs patterning to form thermal adjustment structure 7, such as Fig.10 As shown;

[0083] 8. Preparation and planarization of the second SiO2 passivation layer 204: Fig.11As shown, SiO2 with a thickness of 1 to 3 μm is deposited by CVD and planarized by CMP. At this time, the second SiO2 passivation layer 204 covers the SiO2 waveguide cladding 203, the metal electrode 3 and the thermal adjustment structure 7. The second SiO2 passivation layer 204, the SiO2 waveguide cladding 203, the first SiO2 passivation layer 202 and the first SiO2 film 201 constitute the SiO2 layer 2;

[0084] 9. Etching the groove structure 8 in the bonding area: Fig.12 As shown, SiO2 is dry-etched to form a groove structure 8, and the remaining thickness of SiO2 etched above the waveguide structure 4 is less than 150nm, and the plane size of the groove structure is greater than 1mm×1mm;

[0085] 10. Pad opening window 9: Fig.13 As shown, SiO2 is dry-etched to expose the metal pad of the metal electrode 3;

[0086] 11. LN-SiNx D2W bonding: Fig.14 As shown, the LNOI substrate (wherein the thickness of the LN film 10 is 100-500nm, and the thickness of the buried oxide layer BOX 2' is 0.1-2μm) is cut and diced into a single LN chip with a size smaller than the groove structure 8 (usually the size of each side is more than 20μm smaller than the corresponding side size of the bonding groove structure 8, that is, the spacing between each side of the LN groove is greater than 10μm, and the dicing size deviation, bonding alignment error, etc. need to be considered to ensure that the LN chip can be embedded in the groove structure 8), and then the surface thereof and the surface of the waveguide structure wafer obtained by the above-mentioned processing are cleaned and plasma activated, and then a pre-alignment bonding and annealing process (temperature is less than 250°C) are performed to combine the LN chip and the waveguide structure in the groove;

[0087] 12. Removal of Si substrate of LN chip: The Si substrate 1' of LN chip is removed by grinding, wet etching and other processes, such as Figure 1 As shown, the preparation of the composite waveguide structure is completed.

[0088] In specific implementation, the groove structure 8 can also be set by means of a sacrificial layer. For example, after step 5 of the above example, a sacrificial layer is set above the waveguide structure 4 in the bonding area, and the structure (including shape, size, etc.) of the sacrificial layer is consistent with the groove structure 8; then, step 6 is performed to etch and fill the metal interconnection through hole 6, and step 7 is performed to complete the preparation of the metal electrode 3 and the thermal adjustment structure 7, and step 9 is performed to realize the preparation and planarization of the second SiO2 passivation layer 204. At this time, the second SiO2 passivation layer 204 covers the SiO2 waveguide cladding 203, the sacrificial layer, the metal electrode 3 and the thermal adjustment structure 7; then, the sacrificial layer and the SiO2 above the sacrificial layer are removed to form the groove structure 8, and then steps 10-12 in the example are performed to complete the preparation of the composite waveguide structure.

[0089] The embodiments of the present invention achieve the following technical effects: 1. The characteristics of the D2W technology are fully utilized to realize the LN-SiNx heterogeneous integration in the groove structure of the wafer bonding area, thereby reducing the requirements for the flattening of the entire wafer surface; 2. While being compatible with the traditional CMOS process, the bonding area and the non-bonding area also have better process structure compatibility through the bonding in the groove.

[0090] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A composite waveguide structure, characterized in that: include: A waveguide wafer, the waveguide wafer comprising a silicon substrate (1), a SiO2 layer (2) arranged on the top surface of the silicon substrate (1), a waveguide structure (4) and a metal electrode (3), the waveguide structure (4) and the metal electrode (3) being arranged in the SiO2 layer (2) and the waveguide structure (4) being located at a higher level than the metal electrode (3), and two adjacent waveguide structures (4) being located on both sides of the metal electrode (3) in horizontal projection; A groove structure (8) is arranged in the SiO2 layer (2), and the groove structure (8) is located above the waveguide structure (4) in the area to be bonded; The electro-optical thin film layer (10) is bonded in the groove structure (8) and forms a composite waveguide structure with the waveguide structure (4) below the groove structure (8).

2. The composite waveguide structure according to claim 1, characterized in that: The thickness of SiO2 between the bottom surface of the groove structure (8) and the top surface of the waveguide structure (4) in the area to be bonded is less than 150 nm.

3. The composite waveguide structure according to claim 1, wherein: When the electro-optical thin film layer (10) is bonded in the groove structure (8), the spacing between the electro-optical thin film layer (10) and each side of the groove structure (8) is greater than or equal to 10 μm.

4. The composite waveguide structure according to any one of claims 1 to 3, characterized in that: The groove structure (8) allows the geometric shape formed by the peripheral boundary of the electro-optical thin film layer (10) to be embedded.

5. The composite waveguide structure according to any one of claims 1 to 3, characterized in that: There are a plurality of groove structures (8), and the distance between two adjacent groove structures (8) is greater than 10 μm.

6. The composite waveguide structure according to any one of claims 1 to 3, characterized in that: The groove structure (8) is provided at some of the areas to be bonded in the plurality of areas to be bonded of the SiO2 layer (2).

7. A method for preparing a composite waveguide structure according to any one of claims 1 to 6, characterized in that: include: The SiO2 layer (2) is prepared on the top surface of the silicon substrate (1), and the waveguide structure (4) and the metal electrode (3) are prepared in the SiO2 layer (2); forming the groove structure (8) above the waveguide structure (4) in the area to be bonded of the SiO2 layer (2); The electro-optical thin film layer (10) is bonded in the groove structure (8), and the electro-optical thin film layer (10) and the waveguide structure (4) below the groove structure (8) form a composite waveguide structure.

8. The preparation method according to claim 7, characterized in that: The waveguide structure (4) and the metal electrode (3) are prepared in the SiO2 layer (2), comprising: Preparing a first SiO2 layer (201) on the top surface of the silicon substrate (1), and forming the metal electrode (3) on the top surface of the first SiO2 layer (201); preparing a first SiO2 passivation layer (202) and planarizing it, wherein the first SiO2 passivation layer (202) covers the metal electrode (3) and the first SiO2 layer (201); forming the waveguide structure (4) on the top surface of the first SiO2 passivation layer (202); Preparing and planarizing a SiO2 waveguide cladding (203), wherein the SiO2 waveguide cladding (203) covers the waveguide structure (4) and the first SiO2 passivation layer (202); Forming a through hole (6) in the SiO2 layer above the metal electrode (3), filling the through hole (6) with metal and performing a planarization process; Forming the metal electrode (3) and the heat adjustment structure (7) at the through hole (6) on the top surface of the SiO2 waveguide cladding (203); A second SiO2 passivation layer (204) is prepared and planarized, wherein the second SiO2 passivation layer (204) covers the SiO2 waveguide cladding (203), the metal electrode (3) and the thermal adjustment structure (7), wherein the first SiO2 layer (201), the first SiO2 passivation layer (202), the SiO2 waveguide cladding (203) and the second SiO2 passivation layer (204) constitute the SiO2 layer (2).

9. The preparation method according to claim 7 or 8, characterized in that: The groove structure (8) is formed above the waveguide structure (4) in the area to be bonded of the SiO2 layer (2), comprising: The waveguide structure (4) and the metal electrode (3) are prepared in the SiO2 layer (2). After the preparation of the SiO2 layer (2) is completed, a groove is formed above the waveguide structure (4) in the area to be bonded of the SiO2 layer (2) to form the groove structure (8).

10. The preparation method according to claim 8, characterized in that: The groove structure (8) is formed above the waveguide structure (4) in the area to be bonded of the SiO2 layer (2), comprising: After the SiO2 waveguide cladding (203) is prepared and planarized, a sacrificial layer is prepared on the top surface of the SiO2 waveguide cladding (203) above the waveguide structure (4), wherein the size of the sacrificial layer is consistent with the size of the groove structure (8); After preparing the metal electrode (3), the heat adjustment structure (7) and the second SiO2 passivation layer (204), the SiO2 layer (2) is grooved to the sacrificial layer, and after exposing the sacrificial layer, the sacrificial layer is removed to form the groove structure (8).

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