Method for improving chip packaging reflow soldering yield

Abstract

The invention discloses a method for improving chip packaging reflow soldering yield, which comprises the following steps of: after a control rule 1 and a control rule 2 are established, carrying out step 5, judging whether a solder ball in a compression area of an initial packaging structure meets the control rule 1 and whether a solder ball in a pull-up area meets the control rule 2, if so, directly carrying out step 7, and if not, carrying out step 7; step 6, optimizing the initial design structure by adopting the optimization scheme 1 and the optimization scheme 2 respectively to enable the initial design structure to meet the control rule 1 and the control rule 2; step 7, performing actual production reflow soldering verification, and performing soldering quality yield inspection; and step 8, judging whether the welding quality yield meets the design requirement or not, if so, ending the process, and if not, repeating the steps 6-7 until the design requirement is met. The problem of poor soldering of chip packaging reflow soldering under different warping shapes is solved or the risk of poor soldering of chip packaging reflow soldering is reduced.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging, and in particular to a method for improving the reflow soldering yield of chip packaging. Background Art

[0002] In order to achieve better performance, maintain smaller size and lower power consumption, the existing packaging technology has developed from the early 2D packaging towards three-dimensional packaging (such as 2.5D packaging).

[0003] When performing 2.5D packaging, the interposer with the chip mounted on it and the packaging substrate are welded together through the reflow soldering process. For example, the initial solder balls on the interposer and the initial solder paste on the packaging substrate are welded together through the reflow soldering process.

[0004] As chips become larger, their sizes are getting bigger. The adapter boards with chips mounted on them are also warping more and more during the reflow soldering process. Excessive warping often leads to poor soldering problems (such as bridging, open soldering, etc.) or increases the risk of poor soldering.

[0005] Therefore, how to improve the problem of poor soldering or reduce the risk of poor soldering during chip packaging reflow soldering is an issue that the industry urgently needs to solve. Summary of the invention

[0006] The problem to be solved by this application is how to improve the problem of poor soldering or reduce the risk of poor soldering during chip packaging reflow soldering.

[0007] To solve the above problems, an embodiment of the present application provides a method for improving the chip package reflow soldering yield, including: Step 1, providing an initial design structure, wherein the initial design structure includes a packaging substrate and an adapter plate, wherein the upper surface of the packaging substrate has a plurality of discrete initial solder pastes, the upper surface of the adapter plate is mounted with a semiconductor chip, and the lower surface of the adapter plate has a plurality of discrete initial solder balls; Step 2, reflow soldering is performed on the initial design structure, and the initial solder balls on the lower surface of the adapter board in the initial design structure are soldered together with the initial solder paste corresponding to the upper surface of the packaging substrate in the initial design structure to form an initial packaging structure, and the initial solder balls and the corresponding initial solder paste are soldered together to form solder balls of the initial packaging structure, and the initial packaging structure is warped after reflow soldering, and the initial packaging structure includes at least one compression zone and at least one pull-up zone, the height of the solder balls in the compression zone is less than the ideal solder ball height, and the height of the solder balls in the pull-up zone is greater than the ideal solder ball height, and the ideal solder ball height is the ideal height of the solder balls obtained when the reflow soldering warping of the initial design structure is not considered; Step 3, obtaining the height values ​​of the corresponding solder balls in the compression zone and the tension zone of the initial packaging structure through chip warpage simulation or actual measurement, and further obtaining the diameters of the corresponding solder balls in the compression zone and the tension zone according to an empirical formula; Step 4, based on the height values ​​and diameters of the corresponding solder balls in the compression zone and the stretching zone of the initial packaging structure obtained, respectively establish control rule 1 for the diameters and spacings of adjacent solder balls in the compression zone and control rule 2 for the volume, height and diameter of solder balls in the stretching zone; Step 5, judging whether the solder balls in the compression area of ​​the initial packaging structure meet control rule 1, and whether the solder balls in the pull-up area meet control rule 2, if not, proceeding to step 6, if both meet, proceeding to step 7; Step 6, for the compression zone that does not satisfy control rule 1, optimize the parameters of the initial solder paste and / or initial solder ball in the area corresponding to the compression zone in the initial design structure by using optimization scheme 1, and make it satisfy control rule 1; for the stretching zone that does not satisfy control rule 2, optimize the parameters of the initial solder paste and / or initial solder ball in the area corresponding to the stretching zone in the initial design structure by using optimization scheme 2, and make it satisfy control rule 2; The optimization scheme 1 includes: reducing the volume of the initial solder paste in the corresponding area on the package substrate in the initial design structure, reducing the volume of the initial solder balls in the corresponding area on the transfer board in the initial design structure, or increasing the spacing between adjacent initial solder balls in the corresponding area on the transfer board, or a combination of these; The optimization scheme 2 includes: a method of increasing the volume of the initial solder paste in the corresponding area on the package substrate in the initial design structure, a method of increasing the volume of the initial solder balls in the corresponding area on the transfer board in the initial design structure, or a method of reducing the spacing between adjacent initial solder balls in the corresponding area on the transfer board, or a combination of the above; Step 7, performing actual production reflow soldering verification on the initial design structure that satisfies both control rule 1 and control rule 2 and the optimized initial design structure, and performing soldering quality yield inspection; Step 8, judging whether the welding quality yield rate meets the design requirements, if it meets the design requirements, then ending, if it does not meet the design requirements, then repeating steps 6-7 until the design requirements are met.

[0008] In an optional embodiment, the control rule 1 is: 1 / 2D ci +1 / 2 D ci+1 ≤K1×L i, i+1 , the selection range of K1 is 50%-80%, and the initial value of K1 can be 70%, where D ci is the diameter D of the i-th solder ball in the compression zone of the initial package structure i Or it is the diameter D of the i-th virtual solder ball obtained from the optimized initial design structure i’ , D ci+1 is the diameter D of the i+1th solder ball in the compression zone of the initial package structure i+1 Or it is the diameter D of the i+1th virtual solder ball obtained from the optimized initial design structure i’+1 , L i,i+1 is the distance between the i-th initial solder ball and the adjacent i+1-th initial solder ball in the area corresponding to the compression zone in the initial design structure, or is the distance between the i-th initial solder ball and the adjacent i+1-th initial solder ball in the area corresponding to the compression zone in the optimized initial design structure.

[0009] In an optional embodiment, the diameter D of the i-th solder ball in the compression zone of the initial packaging structure is i and the diameter D of the i+1th solder ball in the compression zone of the initial package structure i+1 The empirical formula 1 and the empirical formula 2 are used to obtain the formula D. i =((V i / πH i +1 / 12K3H i 2 )) 1 / 2 , the empirical formula 2 is: D i+1 =((V i+1 / πH i+1 +1 / 12K3H i+1 2 )) 1 / 2 ; Where K3 is the solder ball compression coefficient, V i is the volume of the i-th solder ball in the compression zone of the initial package structure, and V i= V = i = 1 / 2 ... i1 and the volume V of the i-th initial solder ball i2 The sum of H i is the height of the i-th solder ball in the compression zone of the initial package structure obtained through chip warpage simulation or actual measurement, V i+1 is the volume of the i+1th solder ball in the compression zone of the initial package structure, and V i+1 Equal to the volume V of the i+1th initial solder paste in the area corresponding to the compression zone in the initial design structure i1’ and the volume V of the i-th initial solder ball i2’ The sum of H i+1 is the height of the i+1th solder ball in the compression area of ​​the initial packaging structure obtained through chip warpage simulation or actual measurement.

[0010] In an optional embodiment, the diameter D of the i-th virtual solder ball corresponding to the optimized initial design structure is i’ The diameter D of the i+1th virtual solder ball corresponding to the optimized initial design structure i’+1 The empirical formula 3 and the empirical formula 4 are used to obtain the formula D. i’ =((V i’ / πH i +1 / 12K3H i 2 )) 1 / 2 , the empirical formula 4 is: D i’+1 =((V i’+1 / πH i+1 +1 / 12K3H i+1 2 )) 1 / 2 ; Where K3 is the solder ball compression coefficient, V i’ is the volume of the i-th virtual solder ball corresponding to the optimized initial design structure, and V i’ = is equal to the sum of the optimized or unoptimized volume of the i-th initial solder paste and the optimized or unoptimized volume of the i-th initial solder ball in the region corresponding to the compression zone in the initial design structure, H i is the height of the i-th solder ball in the compression zone of the initial package structure obtained through chip warpage simulation or actual measurement, V i’+1 is the volume of the i+1th virtual solder ball corresponding to the optimized initial design structure, and V i’+1 = is equal to the sum of the optimized or unoptimized volume of the i+1th initial solder paste in the region corresponding to the compression zone in the initial design structure and the optimized or unoptimized volume of the i+1th initial solder ball, H i+1 is the height of the i+1th solder ball in the compression area of ​​the initial packaging structure obtained through chip warpage simulation or actual measurement.

[0011] In an optional embodiment, when repeating step 6-step 7, the value of K1 in the control rule 1 is reduced; reducing the value of K1 in the control rule 1 includes: reducing K1 from the initial value to a value within the selected range of K1.

[0012] In an optional embodiment, the control rule 2 is: V ci ≥K2×1 / 6πD ci 2 H i , the selection range of K2 is 1.1-2, and the initial value of K2 can be 1.2, where V ci is the volume V of the i-th solder ball in the tensile zone of the initial package structure i Or it is the volume V of the i-th virtual solder ball obtained from the optimized initial design structure i’ , D ci is the diameter D of the i-th solder ball in the tensile zone of the initial package structure i Or it is the diameter D of the i-th virtual solder ball obtained from the optimized initial design structure i’ , H i is the height of the i-th solder ball in the compression zone of the initial package structure obtained through chip warpage simulation or actual measurement.

[0013] In an optional embodiment, the diameter D of the i-th solder ball in the stretching area of ​​the initial packaging structure is i and the diameter D of the i-th virtual solder ball corresponding to the optimized initial design structure i’ The empirical formula 5 and the empirical formula 6 are used to obtain the formula D. i =((V i / πH i -1 / 12K4H i 2 )) 1 / 2 , the empirical formula 6 is: D i’ =((V i’ / πH i -1 / 12K4H i 2 )) 1 / 2 ; Where K4 is the solder ball tensile coefficient, V i is the volume of the i-th solder ball in the tensile region of the initial package structure, and V i = V = i = 1 / 2 ... i1 and the volume V of the i-th initial solder ball i2 The sum of V i’is the volume of the i-th virtual solder ball corresponding to the optimized initial design structure, H i is the height of the i-th solder ball in the tensile zone of the initial packaging structure obtained through chip warpage simulation or actual measurement.

[0014] In an optional embodiment, when repeating step 6-step 7, the value of K2 in the control rule 2 is increased; increasing the value of K2 in the control rule 2 includes: increasing K2 from the initial value to a value within the selected range of K2.

[0015] In an optional embodiment, the optimization scheme 1 includes: reducing the volume of the initial solder paste in the corresponding area on the packaging substrate in the initial design structure, reducing the volume of the initial solder balls in the corresponding area on the adapter board in the initial design structure, or increasing the spacing between adjacent initial solder balls in the corresponding area on the adapter board. One, two or three combinations of the above.

[0016] In an optional embodiment, the optimization scheme 2 includes: a method of increasing the volume of the initial solder paste in the corresponding area on the packaging substrate in the initial design structure, a method of increasing the volume of the initial solder balls in the corresponding area on the adapter board in the initial design structure, or a method of reducing the spacing between adjacent initial solder balls in the corresponding area on the adapter board, a combination of one, two or three of the above.

[0017] In an optional embodiment, in the initial design structure, the upper surface of the packaging substrate has a plurality of discrete initial solder pastes with the same volume, the lower surface of the adapter plate has a plurality of discrete initial solder balls with the same volume, and the spacing between adjacent initial solder balls is the same.

[0018] In an optional embodiment, the warping of the initial packaging structure is in a "﹀" shape, and the initial packaging structure at least includes a first compression area located in the middle and a first stretching area located at the edge, the height of the solder ball in the first compression area is less than the ideal solder ball height, and the height of the solder ball in the first stretching area is greater than the ideal solder ball height; the packaging substrate and the adapter plate in the initial design structure both have a first area corresponding to the first compression area, and a second area corresponding to the first stretching area; the optimization scheme 1 includes: optimizing the initial design structure by reducing the volume of the initial solder paste in the first area on the packaging substrate in the initial design structure, reducing the volume of the initial solder balls in the first area on the adapter plate in the initial design structure, or increasing the spacing between adjacent initial solder balls in the first area on the adapter plate; the optimization scheme 2 includes: optimizing the initial design structure by increasing the volume of the initial solder paste in the second area on the packaging substrate in the initial design structure, increasing the volume of the initial solder balls in the second area on the adapter plate in the initial design structure, or reducing the spacing between adjacent initial solder balls in the second area on the adapter plate.

[0019] In an optional embodiment, the warping of the initial packaging structure is in a "︿" shape, and the initial packaging structure at least includes a first stretching area located in the middle and a first compression area located at the edge, the height of the solder ball in the first stretching area is greater than the ideal solder ball height, and the height of the solder ball in the first compression area is less than the ideal solder ball height; the packaging substrate and the adapter plate in the initial design structure both have a first area corresponding to the first stretching area, and a second area corresponding to the first compression area; the optimization scheme 1 includes: optimizing the initial design structure by reducing the volume of the initial solder paste in the second area on the packaging substrate in the initial design structure, reducing the volume of the initial solder balls in the second area on the adapter plate in the initial design structure, or increasing the spacing between adjacent initial solder balls in the second area on the adapter plate; the optimization scheme 2 includes: optimizing the initial design structure by increasing the volume of the initial solder paste in the first area on the packaging substrate in the initial design structure, increasing the volume of the initial solder balls in the first area on the adapter plate in the initial design structure, or reducing the spacing between adjacent initial solder balls in the first area on the adapter plate.

[0020] In an optional embodiment, the warping of the initial packaging structure is in a "W" shape, and the initial packaging structure at least includes a first stretching area in the middle, a first compression area on both sides of the first stretching area, and a second stretching area at the edge, the heights of the solder balls in the first stretching area and the second stretching area are greater than the ideal solder ball height, and the heights of the solder balls in the first compression area are less than the ideal solder ball height; the packaging substrate and the adapter plate in the initial design structure both have a first area corresponding to the first stretching area, a second area corresponding to the first compression area, and a third area corresponding to the second stretching area; the optimization scheme 1 includes: by reducing the initial area of ​​the second area on the packaging substrate in the initial design structure The initial design structure is optimized by one or a combination of increasing the volume of the initial solder paste in the first and third areas on the packaging substrate in the initial design structure, increasing the volume of the initial solder balls in the first and third areas on the adapter board in the initial design structure, or reducing the spacing between adjacent initial solder balls in the first and third areas on the adapter board; the optimization scheme 2 includes: optimizing the initial design structure by one or a combination of increasing the volume of the initial solder paste in the first and third areas on the packaging substrate in the initial design structure, increasing the volume of the initial solder balls in the first and third areas on the adapter board in the initial design structure, or reducing the spacing between adjacent initial solder balls in the first and third areas on the adapter board.

[0021] In an optional embodiment, the warping of the initial packaging structure is in an "M" shape, and the initial packaging structure at least includes a first compression area located in the middle, a first stretching area located on both sides of the first compression area, and a second compression area located at the edge, the height of the solder ball in the first stretching area is greater than the ideal solder ball height, and the height of the solder ball in the first compression area and the second compression area is less than the ideal solder ball height; the packaging substrate and the adapter plate in the initial design structure both have a first area corresponding to the first compression area, a second area corresponding to the first stretching area, and a second area corresponding to the second compression area; the optimization scheme 1 includes: by reducing the first area and the second area on the packaging substrate in the initial design structure The initial design structure is optimized by one or a combination of increasing the volume of the initial solder paste in the second area of ​​the packaging substrate in the initial design structure, increasing the volume of the initial solder balls in the second area of ​​the adapter board in the initial design structure, or reducing the spacing between adjacent initial solder balls in the second area of ​​the adapter board; the optimization scheme 2 includes: optimizing the initial design structure by one or a combination of increasing the volume of the initial solder paste in the second area of ​​the packaging substrate in the initial design structure, increasing the volume of the initial solder balls in the second area of ​​the adapter board in the initial design structure, or reducing the spacing between adjacent initial solder balls in the second area of ​​the adapter board.

[0022] In an optional embodiment, the plurality of discrete initial solder pastes on the upper surface of the packaging substrate are formed by brushing initial solder paste materials into a plurality of discrete mesh holes of a steel mesh; the method of reducing the volume of the initial solder paste in the corresponding area on the packaging substrate in the initial design structure is achieved by reducing the diameter and / or height of the mesh holes in the steel mesh; the method of increasing the volume of the initial solder paste in the corresponding area on the packaging substrate in the initial design structure is achieved by increasing the diameter and / or height of the mesh holes in the steel mesh.

[0023] In an optional embodiment, the packaging substrate is a PCB substrate or a resin substrate, and the adapter board is a silicon adapter board or an RDL adapter board.

[0024] The advantages of the technical solution of this application are: The method for improving the chip package reflow soldering yield rate in the present application, after establishing control rules 1 and control rules 2, first performs step 5 to determine whether the solder balls in the compression zone of the initial packaging structure meet control rule 1, and whether the solder balls in the pull-up zone meet control rule 2. If not, perform step 6, and respectively use optimization scheme 1 and optimization scheme 2 to optimize the situations that do not meet control rule 1 and control rule 2 to make them meet control rule 1 and control rule 2. After optimization, perform step 7 to verify the actual production reflow soldering and check the soldering quality yield rate. If both are met, perform step 7 directly. After performing step 7, perform step 8 to determine whether the soldering quality yield rate meets the design requirements. If so, perform the end. If not, repeat steps 6-7 until the design requirements are met, so as to improve the poor soldering (such as solder connection and / or open soldering) of chip package reflow soldering under different warping shapes or reduce the risk of poor soldering of chip package reflow soldering. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic flow chart of a method for improving chip package reflow soldering yield rate in one embodiment of the present application; Figure 2 This is a structural diagram of an initial design structure in an embodiment of the present application; Figure 3 A schematic diagram of the structure of the initial packaging structure obtained without considering the reflow soldering warpage in an embodiment of the present application Figure 4-5 This is a schematic structural diagram of an initial packaging structure obtained by considering reflow soldering warpage in an embodiment of the present application; Figure 6 It is a schematic diagram of a structure in which an initial packaging structure is warped and in a "﹀" shape in one embodiment of the present application; Figure 7 A schematic diagram of a structure for optimizing the volume of an initial solder paste on a packaging substrate in an initial design structure in an embodiment of the present application; Figure 8 A schematic diagram of a structure for optimizing the volume of an initial solder ball on an adapter plate in an initial design structure in an embodiment of the present application; Fig. 9 A schematic diagram of a structure for optimizing the spacing between adjacent initial solder balls on a transfer board in an initial design structure in one embodiment of the present application; Fig.10 It is a schematic diagram of a structure in which an initial packaging structure is warped and in a "︿" shape in one embodiment of the present application; Fig.11 A schematic diagram of a structure for optimizing the volume of an initial solder paste on a packaging substrate in an initial design structure in an embodiment of the present application; Fig.12 A schematic diagram of a structure for optimizing the volume of an initial solder ball on an adapter plate in an initial design structure in an embodiment of the present application; Fig.13 A schematic diagram of a structure for optimizing the spacing between adjacent initial solder balls on a transfer board in an initial design structure in one embodiment of the present application; Fig.14 This is a schematic diagram of a structure in which an initial packaging structure is warped and in a "W" shape in one embodiment of the present application; Fig.15 A schematic diagram of a structure for optimizing the volume of an initial solder paste on a packaging substrate in an initial design structure in an embodiment of the present application; Fig.16 A schematic diagram of a structure for optimizing the volume of an initial solder ball on an adapter plate in an initial design structure in an embodiment of the present application; Fig.17 A schematic diagram of a structure for optimizing the spacing between adjacent initial solder balls on a transfer board in an initial design structure in one embodiment of the present application; Fig.18 It is a schematic diagram of a structure in which an initial packaging structure is warped and in an "M" shape in one embodiment of the present application; Fig.19 A schematic diagram of a structure for optimizing the volume of an initial solder paste on a packaging substrate in an initial design structure in an embodiment of the present application; Fig. 20 A schematic diagram of a structure for optimizing the volume of an initial solder ball on an adapter plate in an initial design structure in an embodiment of the present application; Fig.21 It is a structural schematic diagram of optimizing the spacing between adjacent initial solder balls on the adapter board in the initial design structure in one embodiment of the present application. DETAILED DESCRIPTION

[0026] The specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present application in detail, for the sake of convenience, the schematic diagrams will not be partially enlarged according to the general proportion, and the schematic diagrams are only examples, which should not limit the scope of protection of the present application. In addition, in actual production, the three-dimensional dimensions of length, width and depth should be included.

[0027] An embodiment of the present application provides a method for improving the yield rate of chip packaging reflow soldering, referring to Figure 1 , the method for improving chip packaging reflow soldering yield comprises: Step 1, providing an initial design structure, wherein the initial design structure includes a packaging substrate and an adapter plate, wherein the upper surface of the packaging substrate has a plurality of discrete initial solder pastes, the upper surface of the adapter plate is mounted with a semiconductor chip, and the lower surface of the adapter plate has a plurality of discrete initial solder balls; Step 2, reflow soldering is performed on the initial design structure, and the initial solder balls on the lower surface of the adapter board in the initial design structure are soldered together with the initial solder paste corresponding to the upper surface of the packaging substrate in the initial design structure to form an initial packaging structure, and the initial solder balls and the corresponding initial solder paste are soldered together to form solder balls of the initial packaging structure, and the initial packaging structure is warped after reflow soldering, and the initial packaging structure includes at least one compression area and at least one pulling area; Step 3, obtaining the height values ​​of the corresponding solder balls in the compression zone and the tension zone of the initial packaging structure through chip warpage simulation or actual measurement, and further obtaining the diameters of the corresponding solder balls in the compression zone and the tension zone according to an empirical formula; Step 4, based on the height values ​​and diameters of the solder balls at different positions of the initial packaging structure obtained, respectively establish control rule 1 for the diameters and spacings of adjacent solder balls in the compression zone and control rule 2 for the volume, height and diameter of the solder balls in the stretching zone; Step 5, judging whether the solder balls in the compression area of ​​the initial packaging structure meet control rule 1, and whether the solder balls in the pull-up area meet control rule 2, if not, proceeding to step 6, if both meet, proceeding to step 7; Step 6, for the compression zone that does not satisfy control rule 1, optimize the parameters of the initial solder paste and / or initial solder ball in the area corresponding to the compression zone in the initial design structure by using optimization scheme 1, and make it satisfy control rule 1; for the stretching zone that does not satisfy control rule 2, optimize the parameters of the initial solder paste and / or initial solder ball in the area corresponding to the stretching zone in the initial design structure by using optimization scheme 2, and make it satisfy control rule 2; Step 7, performing actual production reflow soldering verification on the initial design structure that satisfies both control rule 1 and control rule 2 and the optimized initial design structure, and performing soldering quality yield inspection; Step 8, judging whether the welding quality yield rate meets the design requirements, if it meets the design requirements, then ending, if it does not meet the design requirements, then repeating steps 6-7 until the design requirements are met.

[0028] The method for improving the chip package reflow soldering yield rate is described in detail below with reference to the accompanying drawings.

[0029] First, refer to Figure 1 Combined with reference Figure 2 , perform step 1, provide an initial design structure 100, the initial design structure 100 includes a packaging substrate 101 and an adapter board 103, the upper surface of the packaging substrate 101 has a plurality of discrete initial solder pastes 102, the upper surface of the adapter board 103 is mounted with a semiconductor chip 105, and the lower surface of the adapter board 103 has a plurality of discrete initial solder balls 104.

[0030] The packaging substrate 101 plays the role of electrical connection, protection, support, heat dissipation and assembly in the chip packaging process. In one embodiment, the packaging substrate 101 includes a relative upper surface and a lower surface, the upper surface of the packaging substrate 101 has a plurality of discrete first pads (not shown in the figure), the lower surface of the packaging substrate 101 has a plurality of discrete second pads (not shown in the figure), and the packaging substrate 101 has a first connection circuit (not shown in the figure), part of the first connection circuit can be used for the electrical connection between the first pads on the upper surface of the packaging substrate 101 and the corresponding second pads on the lower surface of the packaging substrate 101, part of the first connection circuit can also be used for the electrical connection between part of the first pads on the upper surface of the packaging substrate 101, and part of the first connection circuit can also be used for the electrical connection between part of the second pads on the lower surface of the packaging substrate 101. In a specific embodiment, the packaging substrate 101 can be a PCB substrate, a resin substrate or a glass substrate.

[0031] The upper surface of the package substrate 101 has a plurality of discrete initial solder pastes 102, which are subsequently used to form solder balls by soldering initial solder balls 104 corresponding to the lower surface of the adapter plate 103 together through a reflow soldering process. In a specific embodiment, the initial solder paste 102 is formed on the surface of the first solder pad on the upper surface of the package substrate 101.

[0032] In one embodiment, in the initial design structure 100, the volumes of the several discrete initial solder pastes 102 formed on the upper surface of the package substrate 101 are equal. Specifically, the initial solder paste 102 is cylindrical, and the diameters and heights of the several initial solder pastes 102 are the same. The volume calculation formula of the initial solder paste 102 is: V i1 =1 / 4πd i 2 h di , V i1 represents the volume of the i-th initial solder paste 102 on the upper surface of the package substrate 101, d i represents the diameter of the i-th initial solder paste 102 on the upper surface of the package substrate 101, h di represents the height of the i-th initial solder paste 102 on the upper surface of the package substrate 101, i≥1, such as Figure 2As shown in Figure 2 The leftmost initial solder paste 102 is used as the first initial solder paste. The volume calculation formula of the first initial solder paste is: V 11 =1 / 4πd1 2 h d1 .

[0033] In one embodiment, the initial solder paste 102 is formed by a steel mesh printing process, and the specific process of forming the initial solder paste 102 is: providing a steel mesh with a plurality of discrete meshes; installing the steel mesh on the upper surface of the package substrate 101; brushing the initial solder paste material into the meshes; scraping off the excess initial solder paste material on the upper surface of the steel mesh by a scraper, and retaining the initial solder paste material in the meshes as the initial solder paste 102; and removing the steel mesh. Therefore, in one embodiment, the volume of the initial solder paste 102 can also be controlled by the volume of the meshes in the steel mesh, and specifically can be controlled by the diameter and / or height of the meshes.

[0034] In one embodiment, the material of the initial solder paste 102 is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-zinc, tin-lead, tin-indium, tin-gold, tin-copper, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-zinc-indium or tin-silver-antimony.

[0035] The interposer 103 is used for electrical connection between chips and between chips and packaging substrates during chip packaging to improve the efficiency and reliability of signal transmission, reduce transmission delay and power consumption, and improve the performance and bandwidth of the packaging structure.

[0036] In one embodiment, the interposer 103 includes a relative upper surface and a lower surface, the upper surface of the interposer 103 has a plurality of discrete third pads (not shown in the figure), the lower surface of the interposer 103 has a plurality of discrete fourth pads (not shown in the figure), the interposer 103 has a second connection circuit (not shown in the figure), the second connection circuit has a high wiring density, part of the second connection circuit can be used for electrical connection between the third pad on the upper surface of the interposer 103 and the corresponding fourth pad on the lower surface of the interposer 103, part of the second connection circuit can also be used for electrical connection between part of the third pad on the upper surface of the interposer 103, and part of the second connection circuit can also be used for electrical connection between part of the fourth pad on the lower surface of the interposer 103. In a specific embodiment, the interposer 103 can be a silicon interposer or an RDL (Re-distribution Layer, RDL) interposer.

[0037] The upper surface of the adapter board 103 is mounted with a semiconductor chip 105, and the lower surface of the adapter board 103 also has a plurality of discrete initial solder balls 104. In a specific embodiment, the semiconductor chip 105 can be electrically connected to the third solder pad on the upper surface of the adapter board 103, and the initial solder ball 104 can be electrically connected to the fourth solder pad on the lower surface of the adapter board 103.

[0038] In one embodiment, the semiconductor chip 105 can be mounted on the upper surface of the adapter board 103 by a flip-chip process or a face-up process. The number of the semiconductor chips 105 can be one or more (greater than or equal to 2). In one embodiment, when there are multiple semiconductor chips 105, the functions of the multiple semiconductor chips 105 can be the same or different. The shapes and volumes of the multiple semiconductor chips 105 can also be the same or different. The semiconductor chip 105 can be a logic chip or a memory chip.

[0039] In one embodiment, in the initial design structure 100, the volumes of the plurality of discrete initial solder balls 104 formed on the lower surface of the adapter plate 103 are equal. The volume calculation formula of the initial solder balls 104 is: V i2 =1 / 6πd i2 3 , V i1 represents the volume of the i-th initial solder ball 104 on the lower surface of the transfer plate 103, d i2 represents the diameter of the i-th initial solder ball 104 on the lower surface of the adapter plate 103, such as Figure 2 As shown in Figure 2 The leftmost initial solder ball 104 is taken as the first initial solder ball. The volume calculation formula of the first initial solder ball is: V 12 =1 / 6πd 12 3 .

[0040] In one embodiment, the material of the initial solder ball 104 is tin or a tin alloy, and the tin alloy is one or more of tin-silver, tin-zinc, tin-lead, tin-indium, tin-gold, tin-copper, tin-silver-copper, tin-silver-zinc, tin-bismuth-indium, tin-zinc-indium, or tin-silver-antimony.

[0041] Next, refer to Figure 1 Combined with reference Figure 2 and Figure 4 , perform step 2, reflow soldering the initial design structure 100, and solder the initial solder balls 104 (reference Figure 2 ) and the initial solder paste 102 corresponding to the upper surface of the package substrate 101 in the initial design structure 100 (reference Figure 2) are welded together to form an initial packaging structure 200 (reference Figure 4 ), and the initial solder ball 104 and the corresponding initial solder paste 102 are welded together to form the solder ball 106 of the initial packaging structure (refer to Figure 4 ), the initial packaging structure 200 has warpage, the initial packaging structure has warpage after reflow soldering, and the initial packaging structure 200 includes at least one compression zone and at least one pulling zone, the height Hi of the solder ball 106 in the compression zone is less than the ideal solder ball height H, the height Hi of the solder ball 106 in the pulling zone is less than the ideal solder ball height H, and the ideal solder ball height H is the ideal height of the solder ball obtained when the initial design structure 100 is subjected to reflow soldering warpage without considering the warpage.

[0042] The reflow soldering at least includes a heating process and a cooling process.

[0043] Without considering the reflow soldering warpage (in an ideal reflow soldering process) Figure 3 Since the mismatch between the coefficient of thermal expansion (CTE) of the adapter board 103 mounted with the semiconductor chip 105 and the coefficient of thermal expansion (CTE) of the packaging substrate 101 will not be considered, that is, the adapter board 103 mounted with the semiconductor chip 105 and the packaging substrate 101 will not warp or deform during the reflow soldering process, the formed initial packaging structure 200 is also in a rational state without warping or deformation, and the plurality of solder balls 106 in the initial packaging structure 200 are also in an ideal state without poor welding. The height H of the plurality of solder balls 106 can be kept consistent, the diameter D can be kept consistent, the spacing L can be kept consistent, and the volume V1 can be kept consistent. In this case, the height H of the solder balls 106 in the initial packaging structure 200 is the ideal solder ball height H mentioned above.

[0044] When actually performing reflow soldering, continue to refer to Figure 4Due to the mismatch or incompatibility between the coefficient of thermal expansion (CTE) of the adapter board 103 mounted with the semiconductor chip 105 and the coefficient of thermal expansion (CTE) of the packaging substrate 101, the adapter board 103 and the packaging substrate 101 will warp or deform during the actual reflow soldering process or after the reflow soldering. The warping or deformation of the adapter board 103 and the packaging substrate 101 will cause the solder balls 106 in the initial packaging structure 200 to have poor soldering problems (for example, there will be bridging between the solder balls 106, and there will be open soldering between the solder balls 106 and the packaging substrate 101, etc.) or increase the risk of poor soldering of the solder balls 106 (for example, there will be a risk of bridging between the solder balls 106, and there will be a risk of open soldering between the solder balls 106 and the packaging substrate 101). Specifically, when the warpage value of the adapter board 103 and the package substrate 101 is large, during or after the actual reflow soldering process, soldering 110 (the gap between the adapter board 103 and the package substrate 101 is reduced, and the solder balls 106 are squeezed to cause soldering 110 between adjacent solder balls 106) and / or soldering 111 (the gap between the adapter board 103 and the package substrate 101 is increased, and the initial solder ball of the solder ball 106 is pulled to cause soldering 111 between the solder ball 106 and the package substrate 101). It should be noted that in some embodiments, for the convenience of illustration, Figure 4 and Figure 5 In the figure and other subsequent figures, only the case where the adapter plate 103 is warped is shown. In other embodiments, the adapter plate 103 and the packaging substrate 101 may be warped at the same time.

[0045] The initial packaging structure 200 may be formed through actual production, or may be obtained through simulation using chip warpage simulation software. During the simulation, the reflow soldering warpage situation needs to be considered.

[0046] The warping of the adapter plate 103 and the package substrate 101 in the initial package structure 200 may cause the solder balls 106 in the initial package structure 200 to have both continuous soldering and open soldering problems (for example, Figure 4 There are both continuous welding 110 and open welding 111 in the process), or there may be only one of the continuous welding and open welding problems (for example Figure 5 There is only continuous welding 110 in the process), and there may be no actual continuous welding and open welding problems, but there is an issue of increasing the risk of poor welding due to continuous welding and open welding (for example Figure 5 There is a greater risk of open soldering between the two leftmost and rightmost solder balls 106 and the packaging substrate 101). The subsequent methods of this application are intended to solve the aforementioned problems.

[0047] When the adapter plate 103 and the package substrate 101 in the initial package structure 200 are warped, the initial package structure 200 will include at least one compression zone and at least one pull-up zone, and the heights of the solder balls 106 at different positions will be different. The compression zone is the area where the solder balls 106 are squeezed, and the height Hi of the solder balls 106 in the compression zone will be less than the ideal solder ball height H. The pull-up zone is the area where the solder balls 106 are stretched, and the height Hi of the solder balls 106 in the pull-up zone will be greater than the ideal solder ball height H. The ideal solder ball height H is the ideal height of the solder ball obtained by performing a reflow soldering operation without considering the warpage of the initial design structure (e.g. Figure 3 As shown), the specific value of the ideal solder ball height H can be obtained through simulation or calculated through an empirical formula.

[0048] When the initial package structure 200 is warped, it may have different shapes. In one embodiment, the initial package structure 200 is warped and has a “﹀” shape (refer to Figure 6 In another embodiment, the initial packaging structure 200 is warped and presents a “︿” shape (refer to Fig.10 In another embodiment, the initial package structure 200 is warped and presents a “W” shape (refer to Fig.14 In another embodiment, the initial packaging structure 200 is warped and presents an “M” shape (refer to Fig.18 ). Therefore, the subsequent method of the present application can improve the poor welding problem of chip package reflow soldering or reduce the risk of poor welding of chip package reflow soldering according to the different warping shapes of the initial packaging structure 200.

[0049] Next, refer to Figure 1 Combined with reference Figure 5 , proceed to step 3, obtain the height value Hi of the corresponding solder ball 106 in the compression zone and the tension zone of the initial packaging structure 200 through chip warpage simulation or actual measurement, and further obtain the diameter Di of the corresponding solder ball in the compression zone and the tension zone according to the empirical formula.

[0050] In one embodiment, the height Hi of the solder ball 106 is obtained by actual measurement, and is obtained by actual production. Figure 5 The initial package structure 200 is shown, and then the height of the solder ball 106 in the initial package structure 200 is actually measured. The actual measurement is a destructive measurement. Before the measurement, the solder ball 106 to be measured needs to be cut open, and then the height Hi of the solder ball 106 is measured after the cutting.

[0051] In another embodiment, when the height Hi of the solder ball 106 is obtained through warpage simulation, the warpage simulation process may be performed using professional warpage simulation software.

[0052] The diameter Di of the solder ball 106 is obtained by an empirical formula. The diameter Di of the solder ball 106 in the compression zone of the initial package structure 200 and the diameter Di of the solder ball 106 in the tension zone are obtained by using different empirical formulas.

[0053] In one embodiment, the diameter D of the i-th solder ball 106 in the compression region of the initial package structure 200 is i and the diameter D of the i+1th solder ball 106 in the compression region of the initial package structure 200 i+1 Obtained by empirical formula 1 and empirical formula 2 respectively, The empirical formula 1 is: D i =((V i / πH i +1 / 12K3H i 2 )) 1 / 2 , The empirical formula 2 is: D i+1 =((V i+1 / πH i+1 +1 / 12K3H i+1 2 )) 1 / 2 ; Among them, K3 is the solder ball compression coefficient, which is obtained based on experiments or experience, V i is the volume of the i-th solder ball 106 in the compression region of the initial package structure 200, and V i = equal to the volume V of the i-th initial solder paste in the region corresponding to the compression zone in the initial design structure 100 i1 and the volume V of the i-th initial solder ball i2 The sum of V i = V i1 + V i2 , V i1 and V i2 The calculation formula refers to the corresponding part above, V i1 and V i2 is known, so V i It is known that H i The height of the i-th solder ball 106 in the compression zone of the initial package structure obtained through chip warpage simulation or actual measurement is also known. Therefore, the diameter D of the i-th solder ball 106 in the compression zone of the initial package structure 200 can be obtained through empirical formula 1. i ; V i+1 is the volume of the i+1th solder ball 106 in the compression region of the initial package structure 200, and V i+1 = equal to the volume V of the i+1th initial solder paste in the region corresponding to the compression zone in the initial design structure 100 i1’and the volume V of the i-th initial solder ball i2’ The sum of V i+1 With V i The calculation process of H is similar and is also known. i+1 is the height of the i+1th solder ball in the compression zone of the initial package structure obtained through chip warpage simulation or actual measurement, which is also known. Therefore, the diameter D of the i+1th solder ball 106 in the compression zone of the initial package structure 200 can be obtained through empirical formula 2. i+1 It should be noted that the diameter D of the i-th solder ball 106 in the compression zone of the initial packaging structure 200 in this embodiment is i and the diameter D of the i+1th solder ball 106 in the compression region of the initial package structure 200 i+1 The above empirical formulas 1 and 2 are used as examples. In other embodiments, the diameter D of the i-th solder ball 106 in the compression zone of the initial packaging structure 200 is i and the diameter D of the i+1th solder ball 106 in the compression region of the initial package structure 200 i+1 It can be obtained through other existing empirical formulas.

[0054] In one embodiment, the diameter D of the i-th solder ball 106 in the tensile region of the initial package structure 200 is i According to the empirical formula 5, The empirical formula 5 is: D i =((V i / πH i -1 / 12K4H i 2 )) 1 / 2 , Among them, K4 is the solder ball tensile coefficient, which is obtained based on experiments or experience, V i is the volume of the i-th solder ball in the tensile region of the initial package structure, and V i = V = i = 1 / 2 ... i1 and the volume V of the i-th initial solder ball i2 The sum of V i = V i1 + V i2 , V i1 and V i2 The calculation formula refers to the corresponding part above, V i1 and V i2 is known, so V i It is known that H iThe height of the i-th solder ball in the stretching area of ​​the initial package structure obtained through chip warpage simulation or actual measurement is also known, so the diameter D of the i-th solder ball 106 in the stretching area of ​​the initial package structure 200 can be obtained through empirical formula 5. i It should be noted that the diameter D of the i-th solder ball 106 in the stretching area of ​​the initial packaging structure 200 in this embodiment is i The above empirical formula 5 is only used as an example. In other embodiments, the diameter D of the i-th solder ball 106 in the stretching area of ​​the initial packaging structure 200 is i It can be obtained through other existing empirical formulas.

[0055] Next, continue to refer to Figure 1 and Figure 5 , proceed to step 4, based on the obtained height values ​​Hi and diameter Di of the corresponding solder balls 106 in the compression zone and the tension zone of the initial packaging structure 200, establish control rule 1 for the diameters and spacings of adjacent solder balls in the compression zone and control rule 2 for the volume, height and diameter of solder balls in the tension zone.

[0056] In one embodiment, the control rule 1 is: 1 / 2D ci +1 / 2 D ci+1 ≤K1×L i, i+1 , The selection range of K1 is 50%-80%, specifically 50%, 60%, 70%, 80%. When performing the method of the present application, the initial value of K1 can be 70%, wherein D ci is the diameter D of the i-th solder ball 106 in the compression region of the initial package structure 200 i (The calculation process is described above) or the diameter D of the i-th virtual solder ball obtained from the optimized initial design structure i’ (The calculation process will be introduced later), D ci+1 is the diameter D of the i+1th solder ball in the compression region of the initial package structure 200 i+1 Or it is the diameter D of the i+1th virtual solder ball obtained from the initial design structure after subsequent optimization i’+1 , L i,i+1 For the initial design structure 100 (reference Figure 2 ) in the region corresponding to the compression zone and between the i-th initial solder ball 104 and the adjacent i+1-th initial solder ball 104 (L i,i+1 is a known parameter in the initial design structure 100) or is a distance between the i-th initial solder ball and the adjacent i+1-th initial solder ball in the region corresponding to the compression zone in the optimized initial design structure (L after optimization i,i+1It should be noted that, when the optimization is performed later, if the spacing between adjacent initial solder balls 104 corresponding to the optimized object (such as solder paste 102 or initial solder ball 104) remains unchanged, when determining whether the optimized object satisfies control rule 1, L in control rule 1 i,i+1 is the distance between the i-th initial solder ball and the adjacent i+1-th initial solder ball in the initial design structure 100; when the optimization is performed later, when the object to be optimized is the distance between the i-th initial solder ball and the adjacent i+1-th initial solder ball in the initial design structure 100, when determining whether the object to be optimized satisfies the control rule 1, L in the control rule 1 i,i+1 is the distance between the i-th initial solder ball and the adjacent i+1-th initial solder ball in the optimized initial design structure 100. It should be noted that when there are multiple compression zones in the initial packaging structure 200, the value of K1 may be different for different compression zones. For example, in a more severely compressed area, the value of K1 may be smaller, but it still needs to be within the selected range. Moreover, in the method of the present application, when steps 6 to 7 are subsequently repeated, the value of K1 may be changed based on the initial value, such as being reduced based on the initial value, but it still needs to be within the selected range.

[0057] In one embodiment, the control rule 2 is: V ci ≥K2×1 / 6πD ci 2 H i , The selection range of K2 is 1.1-2, specifically 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2. When performing the method of the present application, the initial value of K2 can be 1.2, where V ci is the volume V of the i-th solder ball in the tensile region of the initial package structure 200 i (is known, the calculation process is described above) or is the volume V of the i-th virtual solder ball obtained from the optimized initial design structure i’ (The calculation process will be introduced later), D ci is the diameter D of the i-th solder ball in the tensile zone of the initial package structure i (The calculation process is described above) or the diameter D of the i-th virtual solder ball obtained from the optimized initial design structure i’ (The calculation process will be introduced later), H iis the height of the i-th solder ball in the compression zone of the initial package structure obtained through chip warpage simulation or actual measurement (the calculation process is described above). It should be noted that when there are multiple stretching zones in the initial package structure 200, the value of K2 may be different for different stretching zones. For example, the value of K2 may be larger in the area that is more stretched, but it still needs to be within the selected range. In addition, in the method of the present application, when steps 6-7 are subsequently repeated, the value of K2 may be changed based on the initial value, such as increasing based on the initial value, but it still needs to be within the selected range.

[0058] Next, continue to refer to Figure 1 and Figure 5 , proceed to step 5, determine whether the solder balls 106 in the compression zone of the initial packaging structure 200 meet control rule 1, and whether the solder balls 106 in the pull-up zone meet control rule 2. If not, proceed to step 6; if both meet, proceed to step 7.

[0059] The non-satisfaction includes: the solder balls 106 in the compression area of ​​the initial packaging structure 200 do not satisfy control rule 1, and the solder balls 106 in the lifting area of ​​the initial packaging structure 200 do not satisfy one or both of control rule 2.

[0060] The simultaneous satisfaction includes: the solder balls 106 in the compression area of ​​the initial package structure 200 satisfy control rule 1, and the solder balls 106 in the lifting area of ​​the initial package structure 200 satisfy control rule 2.

[0061] When determining whether the solder ball 106 in the compression zone of the initial package structure 200 satisfies the control rule 1, the diameter D of the i-th solder ball 106 in the compression zone of the initial package structure 200 obtained in step 3 is i The diameter D of the i+1th solder ball 106 in the compression region of the initial package structure 200 is i+1 Substitute into the above control rule 1 and judge 1 / 2D i +1 / 2 D i+1 Is ≤K1×L i, i+1 , if 1 / 2D i +1 / 2 D i+1 The sum is less than or equal to K1×L i, i+1 , then the i-th solder ball 106 and the i+1-th solder ball 106 in the compression zone satisfy control rule 1. If 1 / 2D i +1 / 2 D i+1 The sum is not less than or equal to K1×L i, i+1 , then the i-th solder ball 106 and the i+1-th solder ball 106 in the compression zone do not satisfy control rule 1, and subsequent optimization is required.

[0062] When determining whether the solder ball 106 in the stretching area of ​​the initial package structure 200 satisfies control rule 2, the volume V of the i-th solder ball in the stretching area of ​​the initial package structure 200 is i (is known, the calculation process is described above), the diameter D of the i-th solder ball in the stretching area of ​​the initial package structure obtained in step 3 i (The calculation process is described above). In step 3, the height H of the i-th solder ball in the compression zone of the initial package structure obtained by chip warpage simulation or actual measurement is obtained. i , substitute it into the above control rule 2, and judge V i Is ≥K2×1 / 6πD i 2 H i , if V i is greater than or equal to K2×1 / 6πD i 2 H i , then the i-th solder ball 106 in the stretching zone satisfies control rule 2, if V i Not greater than or equal to K2×1 / 6πD i 2 H i , then the i-th solder ball 106 in the stretching zone needs to be optimized later.

[0063] Next, refer to Figure 1 Combined with reference Figure 6-Figure 9 , proceed to step 6, for the compression area that does not meet control rule 1 (such as Figure 6 The first compression zone 11 in the initial design structure 100 is optimized by using optimization scheme 1 for the region corresponding to the compression zone (e.g. Figure 7-Figure 9 The parameters of the initial solder paste 102 and / or the initial solder ball 104 in the first area 21 corresponding to the first compression area 11 are optimized to meet the control rule 1; for the tensile area (such as Figure 6 The first stretching zone 12 in the initial design structure 100 is optimized by using optimization scheme 2 for the region corresponding to the stretching zone (e.g. Figure 7-Figure 9 Optimizing the parameters of the initial solder paste 102 and / or the initial solder ball 104 in the second area 22 corresponding to the first stretching area 12, and making them satisfy the control rule 2; The optimization scheme 1 includes: reducing the corresponding area on the package substrate 101 in the initial design structure 200 (for example Figure 7 The volume of the initial solder paste 102 in the first area 21) is reduced, and the corresponding area on the adapter board 103 in the initial design structure 100 (for example Figure 8The volume of the initial solder ball 104 in the first area 21) is increased or the corresponding area on the adapter plate 103 (eg Fig. 9 One or a combination of the above methods for determining the spacing between adjacent initial solder balls 104 in the first region 21; The optimization scheme 2 includes: increasing the corresponding area on the packaging substrate 101 in the initial design structure 100 (for example Figure 7 The volume of the initial solder paste 102 in the second area 22) is increased by increasing the corresponding area on the transfer board 103 in the initial design structure 100 (for example Figure 8 The volume of the initial solder ball 104 in the second area 22) or the corresponding area on the adapter plate 103 (eg Fig. 9 The spacing between adjacent initial solder balls 104 in the second region 22 is controlled by one or a combination of the above methods.

[0064] In one embodiment, when optimizing scheme 1 is used to optimize the parameters of the initial solder paste and / or initial solder balls in the area corresponding to the compression zone in the initial design structure 100, the optimization scheme 1 includes: reducing the volume of the initial solder paste 102 in the corresponding area on the packaging substrate 101 in the initial design structure 100, reducing the volume of the initial solder balls 104 in the corresponding area on the adapter plate 103 in the initial design structure 100, or increasing the spacing between adjacent initial solder balls 104 in the corresponding area on the adapter plate 103. One, two or three combinations of these.

[0065] In one embodiment, optimization scheme 2 is used to optimize the parameters of the initial solder paste and / or initial solder balls in the area corresponding to the stretching zone in the initial design structure 100, and the optimization scheme 2 includes: a method of increasing the volume of the initial solder paste 102 in the corresponding area on the packaging substrate 101 in the initial design structure 100, a method of increasing the volume of the initial solder balls 104 in the corresponding area on the adapter plate 103 in the initial design structure 100, or a method of reducing the spacing between adjacent initial solder balls 104 in the corresponding area on the adapter plate 103, one, two or three of the combinations thereof.

[0066] For the compression area that does not meet the control rule 1, when the optimization scheme 1 is used for optimization, the optimized scheme also needs to meet the control rule 1. If the control rule 1 is not met, the volume of the initial solder paste 102 in the optimization scheme 1 that is being performed needs to be further reduced, or the volume of the solder ball 104 needs to be further reduced, or the spacing between adjacent solder balls 104 needs to be further increased until the control rule 1 is met. In a specific embodiment, for example, when the optimization scheme 1 that has been performed is: reducing the corresponding area on the package substrate 101 in the initial design structure 200 (for example Figure 7 The volume of the i-th initial solder paste 102 and the i+1-th initial solder paste 102 in the first area 21 in the initial design structure 200 is not calculated for the corresponding area on the package substrate 101 in the initial design structure 200 (for example Figure 8 and Fig. 9 When optimizing the volume of the solder balls 104 in the first region 21 and the spacing between adjacent solder balls 104, the corresponding region (eg Figure 7 After the volume of the i-th initial solder paste 102 and the i+1-th initial solder paste 102 in the first area 21 is reduced (after optimization), it is necessary to obtain the diameter D of the i-th virtual solder ball corresponding to the optimized initial design structure. i’ and the diameter D of the i+1th virtual solder ball i’+1 , D i’ and D i’+1 Substitute into the above control rule 1 to judge or verify 1 / 2D i’ +1 / 2 D i’+1 Is the sum of less than or equal to K1×L i, i+1 , if 1 / 2D i’ +1 / 2 D i’+1 The sum is less than or equal to K1×L i, i+1 , then the optimization scheme 1 that has been carried out satisfies the control rule 1, otherwise the optimization scheme 1 that has been carried out does not satisfy the control rule 1, and the optimization scheme 1 that has been carried out needs to be further adjusted, such as further reducing or increasing the adjusted parameters, or adding optimization combinations (such as changing from one of the aforementioned optimization schemes 1 to a combination of two or three). i’ and D i’+1 The specific calculation process will be described below.

[0067] In one embodiment, the diameter D of the i-th virtual solder ball corresponding to the optimized initial design structure is i’ The diameter D of the i+1th virtual solder ball corresponding to the optimized initial design structure i’+1 Obtained by empirical formula 3 and empirical formula 4 respectively, The empirical formula 3 is: D i’=((V i’ / πH i +1 / 12K3H i 2 )) 1 / 2 , The empirical formula 4 is: D i’+1 =((V i’+1 / πH i+1 +1 / 12K3H i+1 2 )) 1 / 2 ; Among them, K3 is the solder ball compression coefficient, V i’ is the volume of the i-th virtual solder ball corresponding to the optimized initial design structure, and V i’ is equal to the sum of the optimized or unoptimized volume of the ith initial solder paste and the optimized or unoptimized volume of the ith initial solder ball in the region corresponding to the compression zone in the initial design structure. Specifically, when the ith initial solder paste is optimized and the corresponding ith initial solder ball is not optimized, the volume V of the ith virtual solder ball is i’ = V = The optimized volume V of the i-th initial solder paste in the region corresponding to the compression zone in the initial design structure i1’ The volume V of the i-th initial solder ball that is not optimized in the initial design structure i2 The sum of V i’ = V i1’ +V i2 , V i1’ and V i2 The volume calculation formulas for solder paste and solder ball are used to calculate V. i1’ and V i2 It is known that V i’ It is known that H i is the height of the i-th solder ball in the compression zone of the initial package structure obtained through chip warpage simulation or actual measurement, H i is known, so D can be obtained through empirical formula 3 i’ , V i’+1 is the volume of the i+1th virtual solder ball corresponding to the optimized initial design structure, and V i’+1 = V is equal to the sum of the optimized or unoptimized volume of the i+1th initial solder paste in the region corresponding to the compression zone in the initial design structure and the optimized or unoptimized volume of the i+1th initial solder ball. i’+1 The calculation process of V i’ Similar to V i’+1 is known, H i+1 is the height of the i+1th solder ball in the compression zone of the initial package structure obtained through chip warpage simulation or actual measurement, H i+1is known, so D can be obtained by empirical formula 4 i’+1 It should be noted that the diameter D of the i-th virtual solder ball corresponding to the optimized initial design structure described in this embodiment is i’ The diameter D of the i+1th virtual solder ball corresponding to the optimized initial design structure i’+1 The above empirical formulas 3 and 4 are used as examples. In other embodiments, the diameter D of the i-th virtual solder ball corresponding to the optimized initial design structure is i’ The diameter D of the i+1th virtual solder ball corresponding to the optimized initial design structure i’+1 It can be obtained through other existing empirical formulas.

[0068] For the compression area that does not meet the control rule 1, by reducing the corresponding area on the adapter plate 103 in the initial design structure 100 (for example Figure 8 The volume of the initial solder ball 104 in the first area 21) is increased or the corresponding area on the adapter plate 103 (eg Fig. 9 When optimizing the spacing between adjacent initial solder balls 104 in the first area 21 in the initial design structure 200 or optimizing the spacing between adjacent initial solder balls 104 in the first area 21 in the initial design structure 200, ... initial design structure 200. Figure 7 The method for verifying whether the volume of the initial solder paste 102 in the first area 21 after optimization satisfies the control rule 1 is similar and will not be repeated here.

[0069] For the stretching area that does not meet the control rule 2, when the optimization scheme 2 is used for optimization, the optimized scheme also needs to meet the control rule 2. If the control rule 2 is not met, the volume of the initial solder paste 102 in the optimization scheme 2 that is being carried out needs to be further increased, or the volume of the solder ball 104 needs to be further increased, or the spacing between adjacent solder balls 104 needs to be further reduced until the control rule 2 is met. In a specific embodiment, for example, when the optimization scheme 2 that has been carried out is to increase the corresponding area on the packaging substrate 101 in the initial design structure 200 (for example Figure 7 The i-th initial solder paste 102 (in the second area 22) does not apply to the corresponding area (such as Figure 8 and Fig. 9 When optimizing the volume of the solder balls 104 in the second area 22 and the spacing between adjacent solder balls 104, the corresponding area (eg Figure 7After the volume of the i-th initial solder paste 102 in the second area 22 is increased (after optimization), it is necessary to obtain the diameter D of the i-th virtual solder ball corresponding to the optimized initial design structure. i’ and the volume V of the ith virtual solder ball i’ , D i’ and V i’ Substitute into the above control rule 2 to judge or verify V i’ ≥K2×1 / 6πD i’ 2 H i , if V i’ is greater than or equal to K2×1 / 6πD i’ 2 H i , then the optimization scheme 2 that has been carried out satisfies control rule 2, otherwise the optimization scheme 2 that has been carried out does not satisfy control rule 1, and it is necessary to further adjust the optimization scheme 2 that has been carried out, such as further reducing or increasing the adjusted parameters, or adding optimization combinations (such as changing from one of the optimization schemes 2 mentioned above to a combination of two or three). i’ and V i’ The specific calculation process will be described below.

[0070] The volume V of the i-th virtual solder ball i’ = V = i = 1 / 2 ... i1’ The volume V of the i-th initial solder ball that is not optimized in the initial design structure i2 The sum of V i’ = V i1’ +V i2 , V i1’ and V i2 The volume calculation formulas for solder paste and solder ball are used to calculate V. i1’ and V i2 It is known that V i’ It is known that H i is the height of the i-th solder ball in the compression zone of the initial package structure obtained through chip warpage simulation or actual measurement, H i Is known.

[0071] The diameter D of the i-th virtual solder ball obtained by the optimized initial design structure is i’ By empirical formula 6, The empirical formula 6 is: D i’ =((V i’ / πH i -1 / 12K4H i 2 )) 1 / 2; Where K4 is the solder ball tensile coefficient, V i’ is the volume of the i-th virtual solder ball corresponding to the optimized initial design structure, H i is the height of the i-th solder ball in the tensile zone of the initial package structure obtained through chip warpage simulation or actual measurement, V i’ and H i is known, D can be obtained by empirical formula 6 i’ It should be noted that the diameter D of the i-th virtual solder ball obtained by the optimized initial design structure in this embodiment is i’ The empirical formula 6 mentioned above is only used as an example. In other embodiments, the diameter D of the i-th virtual solder ball obtained by the optimized initial design structure is i’ It can be obtained by other existing empirical formulas.

[0072] The method of the present application, after establishing control rule 1 and control rule 2, first performs step 5 to determine whether the solder balls in the compression zone of the initial packaging structure meet control rule 1, and whether the solder balls in the pulling zone meet control rule 2. If not, perform step 6, and respectively use optimization scheme 1 and optimization scheme 2 to optimize the situations that do not meet control rule 1 and control rule 2 to make them meet control rule 1 and control rule 2. After optimization, perform subsequent step 7 to perform actual production reflow soldering verification and welding quality yield inspection. If both are met, perform step 7 directly. After step 7, perform subsequent step 8 to determine whether the welding quality yield meets the design requirements. If the design requirements are met, the process ends. If the design requirements are not met, repeat steps 6-7 until the design requirements are met, so as to improve the poor welding (such as continuous welding and / or open welding problems) of chip package reflow soldering under different warping shapes or reduce the risk of poor welding of chip package reflow soldering. In addition, the scheme of the present application first performs step 5 to determine whether the control rules are met, and only when the rules are not met will the optimization of step 6 be performed, thereby improving the efficiency of optimization. In addition, when optimizing in step 6, different optimization schemes (optimization scheme 1 and optimization scheme 1) can be used for different warping conditions (such as compression zone or tension zone), and there are multiple ways to combine the optimization schemes, which can prevent inaccurate and excessive optimization conditions from occurring, improve the accuracy of optimization, and further improve the efficiency of optimization.

[0073] In one embodiment, when the plurality of discrete initial solder pastes 102 on the upper surface of the packaging substrate 101 are formed by brushing initial solder paste materials into a plurality of discrete mesh holes of a steel mesh, the method of reducing the volume of the initial solder paste 102 in the corresponding area on the packaging substrate 101 in the initial design structure 100 is achieved by reducing the diameter and / or height of the mesh holes in the steel mesh; the method of increasing the volume of the initial solder paste 102 in the corresponding area on the packaging substrate 101 in the initial design structure 100 is achieved by increasing the diameter and / or height of the mesh holes in the steel mesh.

[0074] There are some differences in the specific optimization process for different warping shapes of the initial packaging structure 200 .

[0075] In a specific embodiment, reference Figure 6 , the initial packaging structure 200 is warped and presents a "﹀" shape, the initial packaging structure 200 at least includes a first compression region 11 located in the middle and a first stretching region 12 located at the edge, the height Hi of the solder ball 106 in the first compression region 11 is less than the ideal solder ball height H, and the height Hi of the solder ball 106 in the first stretching region 12 is greater than the ideal solder ball height H; reference Figure 7-Figure 9 The package substrate 101 and the transfer plate 103 in the initial design structure 100 both have a first area 21 corresponding to the first compression area 11, and a second area 22 corresponding to the first tension area 12; the optimization scheme 1 includes: reducing the volume of the initial solder paste 102 in the first area 21 on the package substrate 101 in the initial design structure 100, reducing the volume of the initial solder ball 104 in the first area 21 on the transfer plate 103 in the initial design structure 100, or increasing the volume of the adjacent initial solder ball 104 in the first area 21 on the transfer plate 103. The initial design structure 100 is optimized by one or a combination of methods of increasing the volume of the initial solder paste 102 in the second area 22 on the packaging substrate 101 in the initial design structure 100, increasing the volume of the initial solder balls 104 in the second area 22 on the adapter plate 103 in the initial design structure 100, or reducing the spacing between adjacent initial solder balls 104 in the second area 22 on the adapter plate 103. The optimization scheme 2 includes: optimizing the initial design structure 100 by one or a combination of methods of increasing the volume of the initial solder paste 102 in the second area 22 on the packaging substrate 101 in the initial design structure 100, increasing the volume of the initial solder balls 104 in the second area 22 on the adapter plate 103 in the initial design structure 100, or reducing the spacing between adjacent initial solder balls 104 in the second area 22 on the adapter plate 103.

[0076] In another specific embodiment, referring to Fig.10, the initial packaging structure 200 is warped and presents a "︿" shape, the initial packaging structure 200 at least includes a first tensile region 11 located in the middle and a first compression region 12 located at the edge, the height Hi of the solder ball 106 in the first tensile region 11 is greater than the ideal solder ball height H, and the height Hi of the solder ball 106 in the first compression region 12 is less than the ideal solder ball height H; reference Figure 11-13 The package substrate 101 and the adapter plate 103 in the initial design structure 100 both have a first area 21 corresponding to the first stretching area 11, and a second area 22 corresponding to the first compression area 12; the optimization scheme 1 includes: reducing the volume of the initial solder paste 102 in the second area 22 on the package substrate 101 in the initial design structure 100, reducing the volume of the initial solder ball 104 in the second area 22 on the adapter plate 103 in the initial design structure 100, or increasing the volume of the adjacent initial solder ball 104 in the second area 22 on the adapter plate 103. The initial design structure 100 is optimized by one or a combination of methods of increasing the volume of the initial solder paste 102 in the first area 21 on the packaging substrate 101 in the initial design structure 100, increasing the volume of the initial solder balls 104 in the first area 21 on the adapter plate 103 in the initial design structure 100, or reducing the spacing between adjacent initial solder balls 104 in the first area 21 on the adapter plate 103. The optimization scheme 2 includes: optimizing the initial design structure 100 by one or a combination of methods of increasing the volume of the initial solder paste 102 in the first area 21 on the packaging substrate 101 in the initial design structure 100, increasing the volume of the initial solder balls 104 in the first area 21 on the adapter plate 103 in the initial design structure 100, or reducing the spacing between adjacent initial solder balls 104 in the first area 21 on the adapter plate 103.

[0077] In another specific embodiment, referring to Fig.14 , the initial packaging structure 200 is warped and in a "W" shape, the initial packaging structure 200 at least includes a first stretching region 11 located in the middle, first compression regions 12 located on both sides of the first stretching region 11, and a second stretching region 13 located at the edge, the height Hi of the solder ball 106 in the first stretching region 11 and the second stretching region 13 is greater than the ideal solder ball height H, and the height Hi of the solder ball 106 in the first compression region 12 is less than the ideal solder ball height H; reference Figure 15-17The package substrate 101 and the transfer board 103 in the initial design structure 100 both have a first area 21 corresponding to the first stretching area 11, a second area 22 corresponding to the first compression area 12, and a third area 23 corresponding to the second stretching area 13; the optimization scheme 1 includes: reducing the volume of the initial solder paste 102 in the second area 22 on the package substrate 101 in the initial design structure 100, reducing the volume of the initial solder ball 104 in the second area 22 on the transfer board 103 in the initial design structure 100, or increasing the volume of the adjacent initial solder ball 104 in the second area 22 on the transfer board 103. The initial design structure 100 is optimized by one or a combination of methods of increasing the spacing between adjacent initial solder balls 104 in the first area 21 and the third area 23 on the packaging substrate 101 in the initial design structure 100; the optimization scheme 2 includes: optimizing the initial design structure 100 by one or a combination of methods of increasing the volume of the initial solder paste 102 in the first area 21 and the third area 23 on the transfer board 103 in the initial design structure 100, increasing the volume of the initial solder balls 104 in the first area 21 and the third area 23 on the transfer board 103 in the initial design structure 100, or reducing the spacing between adjacent initial solder balls 104 in the first area 21 and the third area 23 on the transfer board 103.

[0078] In another specific embodiment, referring to Fig.18, the initial packaging structure 200 is warped and presents an "M" shape, the initial packaging structure 200 at least includes a first compression area 11 located in the middle, first stretching areas 12 located on both sides of the first compression area 11, and a second compression area 13 located at the edge, the height Hi of the solder ball 106 in the first stretching area 12 is greater than the ideal solder ball height H, and the height Hi of the solder ball 106 in the first compression area 11 and the second compression area 13 is less than the ideal solder ball height H; the packaging substrate 101 and the adapter plate 103 in the initial design structure 100 both have a first area 21 corresponding to the first compression area 11, a second area 22 corresponding to the first stretching area 12, and a third area 23 corresponding to the second compression area 13; the optimization scheme 1 includes: by reducing the first area 21 and the third area 23 on the packaging substrate 101 in the initial design structure 100 The initial design structure 100 is optimized by increasing the volume of the initial solder paste 102 in the first area 22 on the packaging substrate 101 in the initial design structure 100, increasing the volume of the initial solder balls 104 in the second area 22 on the adapter board 103 in the initial design structure 100, or reducing the spacing between adjacent initial solder balls 104 in the first area 21 and the third area 23 on the adapter board 103, or by one or more of the combinations thereof; the optimization scheme 2 includes: optimizing the initial design structure 100 by increasing the volume of the initial solder paste 102 in the second area 22 on the packaging substrate 101 in the initial design structure 100, increasing the volume of the initial solder balls 104 in the second area 22 on the adapter board 103 in the initial design structure 100, or reducing the spacing between adjacent initial solder balls 104 in the second area 22 on the adapter board 103, or by one or more of the combinations thereof.

[0079] Continue to refer Figure 1 , proceed to step 7, perform actual production reflow soldering verification on the initial design structure that satisfies both control rule 1 and control rule 2 and the optimized initial design structure, and perform soldering quality yield inspection.

[0080] When performing step 7, the initial design structure 100 that satisfies both control rules 1 and control rules 2 in step 5 and the optimized initial design structure 100 in step 6 are subjected to reflow soldering in the actual production process, and the initial solder balls 104 on the lower surface of the adapter plate 103 that satisfies control rules 1 and control rules 2 or the optimized initial design structure 100 are welded together with the initial solder paste 102 that corresponds to the upper surface of the package substrate 101 in the initial design structure 100 that satisfies control rules 1 and control rules 2 or the optimized initial design structure to form a package structure to be inspected, and then the package structure to be inspected is subjected to a welding quality yield inspection to determine whether the package structure to be inspected meets the design requirements, and the welding quality yield inspection needs to detect the contents including whether there is continuous welding between the solder balls or whether the risk of continuous welding is high, and whether the solder balls are open-welded or whether the risk of open-welding is high. The process parameters of the reflow soldering when performing step 7 are exactly the same as the process parameters of the reflow soldering when performing step 2.

[0081] Continue to refer Figure 1 In step 8, it is determined whether the welding quality yield rate meets the design requirements. If it does, the process ends. If it does not, the process repeats steps 6 to 7 until the design requirements are met.

[0082] In one embodiment, by repeating steps 6 and 7, the value of K1 in the control rule 1 can be reduced, for example, K1 can be reduced from an initial value to a value within the selection range of K1, that is, the value of K1 after reduction must still be within the selection range of K1 (50%-80%); by repeating steps 6 and 7, the value of K2 in the control rule 2 can also be increased, for example, K2 can be increased from an initial value to a value within the selection range of K2, that is, the value of K2 after increase must still be within the selection range of K2 (1.1-2), so as to further improve the efficiency and accuracy of optimization.

[0083] In one embodiment, by repeating step 6-step 7, the optimization scheme 1 or the optimization scheme 2 may be changed to two or three, so as to further improve the efficiency and accuracy of the optimization.

[0084] Although the present application has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field can use the methods and technical contents disclosed above to make possible changes and modifications to the technical solution of the present application without departing from the spirit and scope of the present application. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are within the protection scope of the technical solution of the present application.

Claims

1. A method for improving chip packaging reflow soldering yield, characterized in that: include: Step 1, providing an initial design structure, wherein the initial design structure includes a packaging substrate and an adapter plate, wherein the upper surface of the packaging substrate has a plurality of discrete initial solder pastes, the upper surface of the adapter plate is mounted with a semiconductor chip, and the lower surface of the adapter plate has a plurality of discrete initial solder balls; Step 2, reflow soldering is performed on the initial design structure, and the initial solder balls on the lower surface of the adapter board in the initial design structure are soldered together with the initial solder paste corresponding to the upper surface of the packaging substrate in the initial design structure to form an initial packaging structure, and the initial solder balls and the corresponding initial solder paste are soldered together to form solder balls of the initial packaging structure, and the initial packaging structure is warped after reflow soldering, and the initial packaging structure includes at least one compression zone and at least one pull-up zone, the height of the solder balls in the compression zone is less than the ideal solder ball height, and the height of the solder balls in the pull-up zone is greater than the ideal solder ball height, and the ideal solder ball height is the ideal height of the solder balls obtained when the reflow soldering warping of the initial design structure is not considered; Step 3, obtaining the height values ​​of the corresponding solder balls in the compression zone and the tension zone of the initial packaging structure through chip warpage simulation or actual measurement, and further obtaining the diameters of the corresponding solder balls in the compression zone and the tension zone according to an empirical formula; Step 4, based on the height values ​​and diameters of the corresponding solder balls in the compression zone and the stretching zone of the initial packaging structure obtained, respectively establish control rule 1 for the diameters and spacings of adjacent solder balls in the compression zone and control rule 2 for the volume, height and diameter of solder balls in the stretching zone; Step 5, judging whether the solder balls in the compression area of ​​the initial packaging structure meet control rule 1, and whether the solder balls in the pull-up area meet control rule 2, if not, proceeding to step 6, if both meet, proceeding to step 7; Step 6, for the compression zone that does not satisfy control rule 1, optimize the parameters of the initial solder paste and / or initial solder ball in the area corresponding to the compression zone in the initial design structure by using optimization scheme 1, and make it satisfy control rule 1; for the stretching zone that does not satisfy control rule 2, optimize the parameters of the initial solder paste and / or initial solder ball in the area corresponding to the stretching zone in the initial design structure by using optimization scheme 2, and make it satisfy control rule 2; The optimization scheme 1 includes: reducing the volume of the initial solder paste in the corresponding area on the package substrate in the initial design structure, reducing the volume of the initial solder balls in the corresponding area on the transfer board in the initial design structure, or increasing the spacing between adjacent initial solder balls in the corresponding area on the transfer board, or a combination of these; The optimization scheme 2 includes: a method of increasing the volume of the initial solder paste in the corresponding area on the package substrate in the initial design structure, a method of increasing the volume of the initial solder balls in the corresponding area on the transfer board in the initial design structure, or a method of reducing the spacing between adjacent initial solder balls in the corresponding area on the transfer board, or a combination of the above; Step 7, performing actual production reflow soldering verification on the initial design structure that satisfies both control rule 1 and control rule 2 and the optimized initial design structure, and performing soldering quality yield inspection; Step 8, judging whether the welding quality yield rate meets the design requirements, if it meets the design requirements, then ending, if it does not meet the design requirements, then repeating steps 6-7 until the design requirements are met.

2. The method for improving chip package reflow soldering yield as claimed in claim 1, characterized in that: The control rule 1 is: 1 / 2D ci +1 / 2 D ci+1 ≤K1×L i, i+1 , the selection range of K1 is 50%-80%, and the initial value of K1 can be 70%, where D ci is the diameter D of the i-th solder ball in the compression zone of the initial package structure i Or it is the diameter D of the i-th virtual solder ball obtained from the optimized initial design structure i’ , D ci+1 is the diameter D of the i+1th solder ball in the compression zone of the initial package structure i+1 Or it is the diameter D of the i+1th virtual solder ball obtained from the optimized initial design structure i’+1 , L i,i+1 is the distance between the i-th initial solder ball and the adjacent i+1-th initial solder ball in the area corresponding to the compression zone in the initial design structure, or is the distance between the i-th initial solder ball and the adjacent i+1-th initial solder ball in the area corresponding to the compression zone in the optimized initial design structure.

3. The method for improving chip package reflow soldering yield as claimed in claim 2, characterized in that: The diameter D of the i-th solder ball in the compression zone of the initial package structure i and the diameter D of the i+1th solder ball in the compression zone of the initial package structure i+1 The empirical formula 1 and the empirical formula 2 are used to obtain the formula D. i =((V i / πH i +1 / 12K3H i 2 )) 1 / 2 , the empirical formula 2 is: D i+1 =((V i+1 / πH i+1 +1 / 12K3H i+1 2 )) 1 / 2 ; Where K3 is the solder ball compression coefficient, V i is the volume of the i-th solder ball in the compression zone of the initial package structure, and V i = V = i = 1 / 2 ... i1 and the volume V of the i-th initial solder ball i2 The sum of H i is the height of the i-th solder ball in the compression zone of the initial package structure obtained through chip warpage simulation or actual measurement, V i+1 is the volume of the i+1th solder ball in the compression zone of the initial package structure, and V i+1 Equal to the volume V of the i+1th initial solder paste in the area corresponding to the compression zone in the initial design structure i1’ and the volume V of the i-th initial solder ball i2’ The sum of H i+1 is the height of the i+1th solder ball in the compression area of ​​the initial packaging structure obtained through chip warpage simulation or actual measurement.

4. The method for improving chip package reflow soldering yield as claimed in claim 2, characterized in that: The diameter D of the i-th virtual solder ball corresponding to the optimized initial design structure is i’ The diameter D of the i+1th virtual solder ball corresponding to the optimized initial design structure i’+1 The empirical formula 3 and the empirical formula 4 are used to obtain the formula D. i’ =((V i’ / πH i +1 / 12K3H i 2 )) 1 / 2 , the empirical formula 4 is: D i’+1 =((V i’+1 / πH i+1 +1 / 12K3H i+1 2 )) 1 / 2 ; Where K3 is the solder ball compression coefficient, V i’ is the volume of the i-th virtual solder ball corresponding to the optimized initial design structure, and V i’ = is equal to the sum of the optimized or unoptimized volume of the i-th initial solder paste and the optimized or unoptimized volume of the i-th initial solder ball in the region corresponding to the compression zone in the initial design structure, H i is the height of the i-th solder ball in the compression zone of the initial package structure obtained through chip warpage simulation or actual measurement, V i’+1 is the volume of the i+1th virtual solder ball corresponding to the optimized initial design structure, and V i’+1 = is equal to the sum of the optimized or unoptimized volume of the i+1th initial solder paste in the region corresponding to the compression zone in the initial design structure and the optimized or unoptimized volume of the i+1th initial solder ball, H i+1 is the height of the i+1th solder ball in the compression area of ​​the initial packaging structure obtained through chip warpage simulation or actual measurement.

5. The method for improving chip package reflow soldering yield as claimed in claim 2, characterized in that: When repeating step 6-step 7, the value of K1 in the control rule 1 is reduced; reducing the value of K1 in the control rule 1 includes: reducing K1 from the initial value to a value within the selected range of K1.

6. The method for improving chip package reflow soldering yield as claimed in claim 1, characterized in that: The control rule 2 is: ci ≥K2×1 / 6πD ci 2 H i , the selection range of K2 is 1.1-2, and the initial value of K2 can be 1.2, where V ci is the volume V of the i-th solder ball in the tensile zone of the initial package structure i Or it is the volume V of the i-th virtual solder ball obtained from the optimized initial design structure i’ , D ci is the diameter D of the i-th solder ball in the tensile zone of the initial package structure i Or it is the diameter D of the i-th virtual solder ball obtained from the optimized initial design structure i’ , H i is the height of the i-th solder ball in the compression zone of the initial package structure obtained through chip warpage simulation or actual measurement.

7. The method for improving chip package reflow soldering yield as claimed in claim 6, characterized in that: The diameter D of the i-th solder ball in the stretching area of ​​the initial packaging structure i and the diameter D of the i-th virtual solder ball corresponding to the optimized initial design structure i’ The empirical formula 5 and the empirical formula 6 are used to obtain the formula D. i =((V i / πH i -1 / 12K4H i 2 )) 1 / 2 , the empirical formula 6 is: D i’ =((V i’ / πH i -1 / 12K4H i 2 )) 1 / 2 ; Where K4 is the solder ball tensile coefficient, V i is the volume of the i-th solder ball in the tensile region of the initial package structure, and V i = V = i = 1 / 2 ... i1 and the volume V of the i-th initial solder ball i2 The sum of V i’ is the volume of the i-th virtual solder ball corresponding to the optimized initial design structure, H i is the height of the i-th solder ball in the tensile zone of the initial packaging structure obtained through chip warpage simulation or actual measurement.

8. The method for improving chip package reflow soldering yield as claimed in claim 2, characterized in that: When repeating step 6-step 7, the value of K2 in the control rule 2 is increased; increasing the value of K2 in the control rule 2 includes: increasing K2 from the initial value to a value within the selected range of K2.

9. The method for improving chip package reflow soldering yield as claimed in claim 1, wherein the optimization scheme 1 comprises: One, two or three of the following methods: reducing the volume of the initial solder paste in the corresponding area on the packaging substrate in the initial design structure, reducing the volume of the initial solder balls in the corresponding area on the adapter board in the initial design structure, or increasing the spacing between adjacent initial solder balls in the corresponding area on the adapter board.

10. The method for improving chip package reflow soldering yield as claimed in claim 1, characterized in that: The optimization scheme 2 includes: a method of increasing the volume of the initial solder paste in the corresponding area on the packaging substrate in the initial design structure, a method of increasing the volume of the initial solder balls in the corresponding area on the adapter board in the initial design structure, or a method of reducing the spacing between adjacent initial solder balls in the corresponding area on the adapter board, or a combination of one, two or three of the above.

11. The method for improving chip package reflow soldering yield as claimed in claim 1, characterized in that: In the initial design structure, the upper surface of the packaging substrate has a plurality of discrete initial solder pastes with the same volume, the lower surface of the adapter plate has a plurality of discrete initial solder balls with the same volume, and the spacing between adjacent initial solder balls is the same.

12. The method for improving chip package reflow soldering yield as claimed in claim 1, characterized in that: The initial packaging structure is warped in a "﹀" shape, and the initial packaging structure at least includes a first compression area located in the middle and a first stretching area located at the edge, the height of the solder ball in the first compression area is less than the ideal solder ball height, and the height of the solder ball in the first stretching area is greater than the ideal solder ball height; The packaging substrate and the adapter plate in the initial design structure both have a first area corresponding to the first compression area, and a second area corresponding to the first stretching area; the optimization scheme 1 includes: optimizing the initial design structure by reducing the volume of the initial solder paste in the first area on the packaging substrate in the initial design structure, reducing the volume of the initial solder balls in the first area on the adapter plate in the initial design structure, or increasing the spacing between adjacent initial solder balls in the first area on the adapter plate; the optimization scheme 2 includes: optimizing the initial design structure by increasing the volume of the initial solder paste in the second area on the packaging substrate in the initial design structure, increasing the volume of the initial solder balls in the second area on the adapter plate in the initial design structure, or reducing the spacing between adjacent initial solder balls in the second area on the adapter plate.

13. The method for improving chip package reflow soldering yield as claimed in claim 1, characterized in that: The warping of the initial packaging structure is in a "︿" shape, and the initial packaging structure at least includes a first stretching area located in the middle and a first compression area located at the edge, the height of the solder ball in the first stretching area is greater than the ideal solder ball height, and the height of the solder ball in the first compression area is less than the ideal solder ball height; the packaging substrate and the adapter plate in the initial design structure both have a first area corresponding to the first stretching area, and a second area corresponding to the first compression area; the optimization scheme 1 includes: optimizing the initial design structure by reducing the volume of the initial solder paste in the second area on the packaging substrate in the initial design structure, reducing the volume of the initial solder balls in the second area on the adapter plate in the initial design structure, or increasing the spacing between adjacent initial solder balls in the second area on the adapter plate; the optimization scheme 2 includes: optimizing the initial design structure by increasing the volume of the initial solder paste in the first area on the packaging substrate in the initial design structure, increasing the volume of the initial solder balls in the first area on the adapter plate in the initial design structure, or reducing the spacing between adjacent initial solder balls in the first area on the adapter plate.

14. The method for improving chip package reflow soldering yield as claimed in claim 1, characterized in that: The warping of the initial packaging structure is in a "W" shape, and the initial packaging structure at least includes a first stretching area located in the middle, first compression areas located on both sides of the first stretching area, and a second stretching area located at the edge, the heights of the solder balls in the first stretching area and the second stretching area are greater than the ideal solder ball height, and the height of the solder balls in the first compression area is less than the ideal solder ball height; the packaging substrate and the adapter board in the initial design structure both have a first area corresponding to the first stretching area, a second area corresponding to the first compression area, and a third area corresponding to the second stretching area; The optimization scheme 1 includes: optimizing the initial design structure by reducing the volume of the initial solder paste in the second area on the packaging substrate in the initial design structure, reducing the volume of the initial solder balls in the second area on the adapter board in the initial design structure, or increasing the spacing between adjacent initial solder balls in the second area on the adapter board; the optimization scheme 2 includes: optimizing the initial design structure by increasing the volume of the initial solder paste in the first area and the third area on the packaging substrate in the initial design structure, increasing the volume of the initial solder balls in the first area and the third area on the adapter board in the initial design structure, or reducing the spacing between adjacent initial solder balls in the first area and the third area on the adapter board.

15. The method for improving chip package reflow soldering yield as claimed in claim 1, characterized in that: The initial packaging structure is warped in an "M" shape, and the initial packaging structure at least includes a first compression area located in the middle, first stretching areas located on both sides of the first compression area, and a second compression area located at the edge, the height of the solder balls in the first stretching area is greater than the ideal solder ball height, and the heights of the solder balls in the first compression area and the second compression area are less than the ideal solder ball height; The packaging substrate and the adapter plate in the initial design structure both have a first area corresponding to the first compression area, a second area corresponding to the first stretching area, and a second area corresponding to the second compression area; the optimization scheme 1 includes: optimizing the initial design structure by reducing the volume of the initial solder paste in the first area and the second area on the packaging substrate in the initial design structure, reducing the volume of the initial solder balls in the first area and the second area on the adapter plate in the initial design structure, or increasing the spacing between adjacent initial solder balls in the first area and the second area on the adapter plate; the optimization scheme 2 includes: optimizing the initial design structure by increasing the volume of the initial solder paste in the second area on the packaging substrate in the initial design structure, increasing the volume of the initial solder balls in the second area on the adapter plate in the initial design structure, or reducing the spacing between adjacent initial solder balls in the second area on the adapter plate.

16. The method for improving chip package reflow soldering yield as claimed in claim 1, characterized in that: The several discrete initial solder pastes on the upper surface of the packaging substrate are formed by brushing the initial solder paste material into several discrete mesh holes of the steel mesh; the method of reducing the volume of the initial solder paste in the corresponding area on the packaging substrate in the initial design structure is achieved by reducing the diameter and / or height of the mesh holes in the steel mesh; the method of increasing the volume of the initial solder paste in the corresponding area on the packaging substrate in the initial design structure is achieved by increasing the diameter and / or height of the mesh holes in the steel mesh.

17. The method for improving chip package reflow soldering yield as claimed in claim 1, characterized in that: The packaging substrate is a PCB substrate or a resin substrate, and the adapter board is a silicon adapter board or an RDL adapter board.

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