Method, system and substrate for improving asymmetric deformation resistance of wafer

Abstract

The invention provides a method, a system and a substrate for improving the asymmetric deformation resistance of a wafer, and the method comprises the steps: delimiting a to-be-strengthened region in the wafer according to the asymmetric stress which the wafer will suffer from, enabling the to-be-strengthened region to be strengthened after the to-be-strengthened region is strengthened, and enabling the to-be-strengthened region to be subjected to asymmetric deformation; when the wafer is subjected to the asymmetric stress, asymmetric deformation can be resisted; doping is carried out on the wafer in the to-be-strengthened area; and carrying out annealing treatment on the doped wafer so as to repair lattice damage caused by doping. According to the method, the asymmetric deformation resistance of the wafer can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor wafer production, and in particular to a method, system and substrate for improving the ability of a wafer to resist asymmetric deformation. Background Art

[0002] In modern semiconductor manufacturing processes, with the advancement of technology, the number of film layers on the wafer continues to increase. Although this multi-layer structure design can improve the performance and integration of devices, it also brings new challenges. In particular, the increase in the number of film layers easily leads to the asymmetry of the stress distribution of the film layer. This asymmetry may be caused by a variety of factors, including differences in the thermal expansion coefficient of the material when filling metal in different areas, or due to the uneven stress release during the etching process.

[0003] The asymmetric distribution of film stress will cause asymmetric deformation of the wafer, that is, when the wafer is subjected to asymmetric film stress, its deformation is non-uniform in different directions. Specifically, the wafer may bend or twist to different degrees in different areas, and this deformation affects the overall geometric symmetry of the wafer.

[0004] Asymmetric deformation of wafers will cause a series of adverse effects on subsequent processes. These effects include difficulties in process control, degradation of device performance, reduction in yield, thermal management issues, packaging difficulties, and increased costs. Therefore, solving the problem of asymmetric deformation of wafers is of great significance for improving the efficiency of semiconductor manufacturing processes and product quality. Summary of the invention

[0005] The present disclosure provides a method, system and substrate for improving the ability of a wafer to resist asymmetric deformation, which can improve the ability of a wafer to resist asymmetric deformation.

[0006] The technical solution of the present disclosure is achieved as follows: In a first aspect, the present disclosure provides a method for improving the ability of a wafer to resist asymmetric deformation, the method comprising: According to the asymmetric stress to be applied to the wafer, a region to be strengthened is defined in the wafer, so that after the region to be strengthened is strengthened, the wafer can resist the occurrence of asymmetric deformation when subjected to the asymmetric stress; doping the wafer in the region to be strengthened; The doped wafer is annealed to repair the lattice damage caused by doping.

[0007] In some optional examples, the region to be strengthened is away from the edge of the wafer to avoid causing lattice damage at the edge of the wafer.

[0008] In some optional examples, the area to be strengthened includes a plurality of continuous linear segments parallel to each other.

[0009] In some optional examples, the area to be strengthened is rectangular.

[0010] In some optional examples, doping the wafer includes: ionizing and accelerating the doping element to form a high-energy ion beam; Adjusting the energy of the high energy ion beam and the angle relative to the wafer; The adjusted high-energy ion beam is scanned on the area to be strengthened on the wafer.

[0011] In some optional examples, doping the wafer includes: bringing a dopant into contact with the region of the wafer to be strengthened; Performing a pre-diffusion process to allow the doping element to undergo a surface adsorption reaction in the area to be strengthened; A driven diffusion process is performed to diffuse the doping elements into the wafer to achieve a desired doping depth and doping concentration.

[0012] In some optional examples, the step of bringing the dopant into contact with the region to be strengthened of the wafer comprises: forming a mask pattern in an area of ​​the wafer except the area to be strengthened; The dopant is introduced to the wafer.

[0013] In some optional examples, the wafer is doped with antimony.

[0014] In a second aspect, the present disclosure provides a system for improving the ability of a wafer to resist asymmetric deformation, the system comprising: A demarcation unit, the demarcation unit being used to demarcate a region to be strengthened in the wafer according to the asymmetric stress to be applied to the wafer, so that after the region to be strengthened is strengthened, the wafer can resist the occurrence of asymmetric deformation when subjected to the asymmetric stress; A doping unit, the doping unit is used to dope the wafer in the area to be strengthened; An annealing unit is used to perform annealing on the doped wafer to repair lattice damage caused by doping.

[0015] In a third aspect, the present disclosure provides a substrate obtained by processing a wafer using the method for improving the ability of a wafer to resist asymmetric deformation according to the first aspect or the system for improving the ability of a wafer to resist asymmetric deformation according to the second aspect.

[0016] The present disclosure provides a method, system and substrate for improving the ability of wafers to resist asymmetric deformation. By combining doping and annealing treatment, the wafer's ability to resist asymmetric deformation is significantly improved, effectively avoiding the impact of asymmetric deformation on subsequent processes, including process control difficulties, device performance degradation, yield reduction, thermal management issues, packaging difficulties and cost increase. This provides a more reliable and economical solution for the manufacture of semiconductor devices such as three-dimensional non-volatile memory, also known as "3D NAND". BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A flow chart of a method for improving the ability of a wafer to resist asymmetric deformation provided by an embodiment of the present disclosure.

[0018] Figure 2 A schematic top view of a wafer with a region to be strengthened defined according to an embodiment of the present disclosure.

[0019] Figure 3 A schematic top view of a doped wafer according to an embodiment of the present disclosure.

[0020] Figure 4 A schematic top view of a wafer that has undergone annealing according to an embodiment of the present disclosure is provided.

[0021] Figure 5 A schematic top view of a wafer with a region to be strengthened defined is provided in accordance with another embodiment of the present disclosure.

[0022] Figure 6 A schematic top view of a wafer with a region to be strengthened defined is provided in accordance with another embodiment of the present disclosure.

[0023] Figure 7 A schematic diagram of a system for improving the ability of a wafer to resist asymmetric deformation provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] The technical solutions in the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings in the present disclosure.

[0025] In the three-dimensional non-volatile memory manufacturing process, namely the 3D NAND manufacturing process, in order to achieve higher storage density and capacity, a three-dimensional structure is formed by stacking storage cells on multiple film layers. However, in the final stage of the manufacturing process, especially after the slit etching process and metal filling, the wafer undergoes asymmetric deformation due to the asymmetric distribution of film layer stress, which seriously affects subsequent processes, including process control, device performance, yield, thermal management, packaging and cost. Currently, patterned annealing processes are used to mitigate this asymmetric deformation, but this method adds additional thermal budget, which may lead to unstable device performance, reduced yield and increased production costs.

[0026] In response to these problems in the prior art, the present disclosure proposes a new technical solution, which aims to effectively resist asymmetric deformation of the wafer without increasing the additional thermal budget.

[0027] Specifically, see Figure 1 Combined with Figures 2 to 4 , the embodiment of the present disclosure provides a method for improving the ability of wafer W to resist asymmetric deformation, which can be performed before double-sided polishing and final polishing of wafer W. The asymmetric deformation here is a professional term in the field of materials science and engineering, which describes the deformation of an object when it is subjected to external forces, and the non-uniformity of this deformation in different directions. In the context of wafer W, asymmetric deformation may refer to different degrees of bending or twisting of wafer W in different areas due to external stress, thereby affecting its overall geometric symmetry. The method may include the following steps.

[0028] S101: According to the asymmetric stress to be applied to the wafer W, a region WA to be strengthened is defined in the wafer W, so that after the region WA to be strengthened is strengthened, the wafer W can resist the occurrence of asymmetric deformation when subjected to the asymmetric stress, such as Figure 2 As shown in the figure, the asymmetric stress to which the wafer W will be subjected is along the X-axis direction rather than along the Y-direction. Such asymmetric stress will cause a local area of ​​the wafer W to bend, for example, in the X-axis direction, thereby causing asymmetric deformation of the wafer W. Accordingly, the area to be strengthened WA defined in the wafer W can be a plurality of mutually parallel continuous linear segments WL parallel to the X-axis direction. In this way, after these linear segments WL are strengthened, the wafer W can resist the occurrence of the above-mentioned asymmetric deformation.

[0029] S102: doping the wafer W in the area to be strengthened WA, such as Figure 3 The doped wafer W is shown in . Doping involves the introduction of specific impurity atoms into the crystal lattice of wafer W. These doping atoms have atomic radii that are different from those of the atoms of wafer W, resulting in local distortions in the lattice. Lattice distortion increases the resistance to the movement of dislocations in the lattice, because the dislocation lines must pass through these distorted areas when moving, thereby reducing the possibility of dislocation slip. The obstruction of dislocation movement directly increases the yield strength of wafer W, that is, the stress level that wafer W can withstand before plastic deformation. Therefore, the doped wafer W is more resistant to plastic deformation when subjected to asymmetric stress, thereby improving its ability to resist asymmetric deformation. In addition, doping can also promote grain refinement, which is a microstructural change that can further improve the strength of wafer W. Grain refinement means more grain boundaries, which restrict the movement of dislocations and make it difficult for dislocations to cross grain boundaries, thereby enhancing the overall strength of wafer W.

[0030] S103: Annealing the doped wafer W to repair the lattice damage caused by doping, such as Figure 4 The annealed wafer W is shown in FIG. Doping introduces lattice damage, such as defects such as vacancies and interstitial atoms, which may cause the mechanical properties of the wafer W, including mechanical strength, to be reduced. The purpose of the annealing treatment is to repair these lattice damages, rearrange the defects in the lattice through heat treatment, reduce vacancies and interstitial atoms, and thus restore the integrity of the lattice. Annealing can also promote the diffusion and redistribution of doping elements, so that they are more evenly distributed in the wafer W, further enhancing the mechanical properties of the wafer W. The annealing treatment not only repairs the lattice damage introduced during the ion implantation process, but also helps to activate the doping elements, so that it can more effectively improve the deformation resistance of the wafer W. In addition, the patterned annealing of the prior art is mainly to remove film stress, which usually requires higher temperatures and longer times, thereby increasing the thermal budget. The annealing treatment in the present disclosure is mainly to repair the lattice damage introduced during the doping process and activate the doping elements. The purpose of this annealing is more focused on the recovery of the lattice and the electrical activity of the doping elements, rather than the removal of stress. The present disclosure may use a lower annealing temperature and a shorter time to reduce the increase in the thermal budget. This optimization is based on the specific requirements for lattice damage repair and doping element activation during doping and annealing. By precisely controlling the temperature and time of annealing, the present disclosure can achieve effective repair of lattice damage and proper activation of doping elements without introducing additional thermal budget.

[0031] This technical solution achieves a significant improvement in the ability of the wafer W to resist asymmetric deformation through the combination of doping and annealing treatment, effectively avoiding the impact of asymmetric deformation on subsequent processes, including process control difficulties, device performance degradation, yield reduction, thermal management issues, packaging difficulties and cost increase. This provides a more reliable and economical solution for the manufacture of semiconductor devices such as 3D NAND.

[0032] In some embodiments of the present disclosure, see Figure 5 The area WA to be strengthened may be far away from the edge WE of the wafer W to avoid causing lattice damage at the edge WE of the wafer W.

[0033] In the above-mentioned embodiment of the present disclosure, the area WA to be strengthened is deliberately designed to be away from the edge WE of the wafer W. This design avoids doping at the edge of the wafer W, thereby reducing the risk of large lattice damage. Specifically, by precisely controlling the position of the doping area, the present disclosure effectively protects the edge WE of the wafer W and avoids lattice damage caused by particle injection, which is often difficult to repair and may become the source of wafer W fragments. In addition, by defining the area WA to be strengthened away from the edge of the wafer W and doping in these areas, the present disclosure enhances the overall mechanical strength of the wafer W. This enhancement not only improves the ability of the wafer W to resist asymmetric deformation, but also improves the reliability of the wafer W in subsequent processes.

[0034] In some embodiments of the present disclosure, see Figure 2 The area to be strengthened WA may include a plurality of mutually parallel continuous linear segments WL.

[0035] In the above embodiments of the present disclosure, the area to be strengthened WA is designed to include a plurality of mutually parallel continuous linear segments WL. This design makes the doping process more precise and controllable. Figure 2 As shown, by limiting the doping to a specific linear segment, the local area of ​​the wafer W can be targeted to enhance the ability to resist asymmetric deformation. This precise control helps to improve the efficiency and effect of doping. Since the area WA to be strengthened is divided into a plurality of parallel linear segments WL, the doping process can achieve higher uniformity in these segments. This uniformity is crucial to ensuring the mechanical properties of the wafer W, because it helps to avoid local stress concentration or weaknesses caused by uneven doping. The doping area design in the embodiment of the present disclosure simplifies the doping process. By doping in a specific linear segment WL, the required mask and lithography steps can be reduced in the case of diffusion doping, thereby reducing the complexity and cost of the process. In the case of ion implantation doping, this simplification makes the doping process easier to implement, because during the ion implantation process, multiple parallel linear segments WL can be quickly scanned and doped, reducing the equipment's occupancy time and production cycle.

[0036] In some embodiments of the present disclosure, see Figure 6 The area to be strengthened WA may be rectangular.

[0037] When the area to be strengthened WA is a rectangle, one side of the rectangle can be made perpendicular to the force direction, such as Figure 6As shown in , when the force direction is along the direction of the X-axis, the rectangle can be designed such that its vertical side is perpendicular to the X-axis, so that the size of the rectangle in the force direction can be adjusted according to the magnitude of the asymmetric stress, that is, the length of the side of the rectangle parallel to the X-axis is adjusted, thereby achieving precise stress direction strengthening. In this way, the key area of ​​the wafer W can obtain sufficient mechanical strength to resist asymmetric deformation. By adjusting the aspect ratio of the area to be strengthened WA, the strengthening effect of the wafer W in the lateral and vertical directions can be flexibly adjusted. This control capability enables the wafer W to achieve optimized mechanical properties according to specific stress distribution and process requirements.

[0038] In some examples, the aspect ratio of the rectangle may be no less than 4:1, and for a 300 mm wafer, the width of the rectangle may be greater than 50 mm.

[0039] In some embodiments of the present disclosure, doping the wafer W may be performed by ion implantation, which may specifically include: ionizing and accelerating the doping element to form a high-energy ion beam; Adjusting the energy of the high energy ion beam and the angle relative to the wafer W; The adjusted high-energy ion beam is scanned on the area WA of the wafer W to be strengthened.

[0040] Doping is achieved through ion implantation, and the implantation depth and concentration of the doping elements can be controlled with high precision. The doping elements are ionized and accelerated to form a high-energy ion beam. By adjusting the energy and angle of the ion beam, the doping elements can be accurately implanted into the area to be strengthened WA of the wafer W, achieving precise control of the doping depth and concentration. Ion implantation technology can achieve uniform distribution of doping elements on the wafer W. By scanning the adjusted high-energy ion beam on the area to be strengthened WA, it can be ensured that the doping elements are evenly distributed throughout the area to be strengthened WA, which is crucial to improving the performance and reliability of the device. Compared with other doping methods, ion implantation technology can be performed at a lower temperature, thereby reducing the impact on the thermal budget of the wafer W. This helps to maintain the original characteristics of the wafer and avoid changes in material properties caused by high-temperature processing.

[0041] In one example, before ion implantation, the wafer W is first thoroughly cleaned to remove impurities and oxide layers on the surface. This step ensures the cleanliness of the wafer surface and provides a good foundation for the subsequent ion implantation process. The cleaned wafer W is loaded onto the sample stage in the vacuum chamber of the ion implanter. In a high vacuum environment, the ion implanter is set up to ionize and accelerate the doping elements to form a high-energy ion beam. In the ion implanter, the doping elements are ionized by an ionization source and then accelerated by an electric field to form a high-energy ion beam with an energy of about 200 keV. The energy of the high-energy ion beam and the angle relative to the wafer W are adjusted, and the inclination angle of the ion implantation is set to 3° to control the implantation depth and distribution of the ion beam. The adjusted high-energy ion beam is scanned on the area WA to be strengthened on the wafer W to achieve ion implantation, and the implantation depth is controlled at about 150nm to achieve the improvement of local mechanical properties. The doping concentration is selected as 5E15cm -2 . By precisely controlling the flow rate and injection time of the ion beam, the doping concentration is ensured to reach a predetermined value. After the ion implantation is completed, the wafer W needs to be gradually cooled to room temperature to avoid lattice damage caused by too rapid temperature changes. In order to repair the lattice damage introduced during the ion implantation process and activate the doping elements, annealing is performed. The annealing is carried out in an argon atmosphere, and the annealing temperature is set to 1000°C for 30 seconds. After the annealing is completed, the wafer W is cooled to room temperature again. Afterwards, the electrical properties and mechanical properties of the wafer W are tested to verify the doping effect and lattice repair. Finally, the doped wafer W is quality controlled, including appearance inspection and performance testing, to ensure that the doping process meets the design requirements and performance standards. Through the above steps, the embodiment of the present disclosure provides a method for precisely controlling the doping process, which not only improves the local mechanical properties of the wafer W, but also repairs the lattice damage through optimized annealing treatment, thereby achieving an improvement in the ability of the wafer W to resist asymmetric deformation.

[0042] In one example, after the doping is achieved by the above-mentioned ion implantation and the area to be strengthened WA is as follows: Figure 2 In the case shown in , for a 300 mm wafer, the width of the line segment WL may be 4 mm, and the interval between two adjacent line segments WL may be 28 mm.

[0043] In some embodiments of the present disclosure, doping the wafer W may be accomplished by diffusion, which may specifically include: Bringing the dopant into contact with the area WA of the wafer W to be strengthened; Performing a pre-diffusion process to allow the doping element to undergo a surface adsorption reaction in the area to be strengthened WA; The driven diffusion process is performed to diffuse the doping elements into the wafer W to achieve a desired doping depth and doping concentration.

[0044] Through pre-diffusion treatment and driven diffusion treatment, the diffusion process of the doping elements in the area to be strengthened WA of the wafer W can be precisely controlled to ensure that the required doping depth and concentration are achieved. Diffusion doping can achieve uniform distribution of doping elements throughout the area to be strengthened WA. This uniformity is critical to improving the performance and reliability of the device because it helps avoid local stress concentration or performance differences caused by uneven doping. Compared with other doping methods, diffusion doping can be performed at a relatively low temperature, thereby reducing the impact on the thermal budget of the wafer W. This helps to maintain the original characteristics of the wafer and avoid changes in material properties caused by high temperature processing.

[0045] In one example, before starting the diffusion doping process, the wafer W is first thoroughly cleaned to remove impurities and oxide layers on the surface to ensure that the surface state of the area to be strengthened WA is suitable for subsequent diffusion processing. SiO2 is used as a diffusion mask material, and a mask is formed on the area to be strengthened WA of the wafer W through photolithography and etching processes to control the diffusion area and ensure that only the area to be strengthened WA is exposed to the dopant. The dopant is evenly placed on the area to be strengthened WA of the wafer W, ready for the diffusion process. In a diffusion furnace, N2 is used as a carrier gas, and the temperature is controlled between 900°C and 1000°C for pre-diffusion treatment. At this temperature, the dopant decomposes and releases doping elements, which react with the surface of the wafer W by adsorption. The temperature is raised to 1000°C to 1200°C, and a driven diffusion process is performed to diffuse the doping elements into the interior of the wafer W to achieve the desired doping depth and doping concentration. During the diffusion process, the distance between the diffuser and the wafer W is controlled between 6 mm and 15 mm to ensure effective contact and uniform diffusion of the dopant with the area WA to be strengthened of the wafer W. After the diffusion is completed, a wet chemical cleaning technique, such as a dilute acid solution, is used to clean the surface of the wafer W to remove residual dopants and reaction byproducts. Annealing heat treatment is performed at a temperature of 900°C to 1000°C to repair the lattice defects caused by the diffusion process, restore the lattice integrity of the wafer W, and activate the electrical activity of the doping elements. After the annealing is completed, the wafer W is gradually cooled to room temperature. After that, the electrical properties and mechanical properties of the wafer W are tested to verify the doping effect and lattice repair. Finally, the doped wafer W is quality controlled, including appearance inspection and performance testing, to ensure that the doping process meets the design requirements and performance standards. Through the above steps, the embodiment of the present disclosure provides a detailed process flow for achieving doping by diffusion. This process not only improves the local mechanical properties of the wafer W, but also repairs the lattice damage through optimized annealing treatment, thereby achieving the improvement of the ability of the wafer W to resist asymmetric deformation. At the same time, compared with other doping methods, this process has the advantages of better uniformity, precise control and environmental friendliness.

[0046] In some embodiments of the present disclosure, contacting the dopant with the to-be-strengthened area WA of the wafer W may include: forming a mask pattern in a region of the wafer W except for the region WA to be strengthened; Dopants are introduced to the wafer W.

[0047] By forming a mask pattern in areas other than the area WA to be strengthened in the wafer W, the disclosed embodiment ensures that the dopant only contacts the area WA to be strengthened. This ability to precisely control the doping area is critical to achieving predetermined electrical and mechanical properties because it prevents unwanted areas from being doped, thereby avoiding possible performance variations and device failures. Accurate mask patterning allows the dopant to be evenly distributed over the area WA to be strengthened, and this uniformity ensures that the entire area WA to be strengthened has consistent electrical properties, which is critical to improving device performance and reliability. By limiting the dopant to contact only the area WA to be strengthened, the disclosed embodiment reduces the risk of unnecessary side reactions in other areas of the wafer W, which helps to protect the overall integrity of the wafer W and avoid performance degradation or device damage due to side reactions.

[0048] In some embodiments of the present disclosure, the wafer W may be doped with antimony element having the chemical symbol Sb.

[0049] Antimony has a large atomic radius, and when doped into the crystal lattice, it causes a large lattice distortion, which increases the resistance to dislocation movement, thereby improving the mechanical strength of the wafer W. The doping activation energy of antimony in the wafer W is relatively low, which means that the dopant can be activated at a lower temperature, reducing the impact of heat treatment on the thermal budget of the wafer W.

[0050] In the case of the above-mentioned diffusion doping, Sb2O3 can be used as a dopant.

[0051] See also Figure 7 The embodiment of the present disclosure further provides a system 1 for improving the ability of a wafer W to resist asymmetric deformation. The system 1 may include: A demarcation unit 10, which is used to demarcate a to-be-strengthened area WA in the wafer W according to the asymmetric stress to be applied to the wafer W, so that after the to-be-strengthened area WA is strengthened, the wafer W can resist the occurrence of asymmetric deformation when subjected to the asymmetric stress; A doping unit 20, the doping unit 20 is used to dope the wafer W in the area to be strengthened WA; The annealing unit 30 is used to perform annealing on the doped wafer W to repair the lattice damage caused by doping.

[0052] The embodiments of the present disclosure also provide a substrate, which can be obtained by processing a wafer W using the method for improving the ability of wafer W to resist asymmetric deformation according to the aforementioned embodiments of the present disclosure or by using the system 1 for improving the ability of wafer W to resist asymmetric deformation according to the aforementioned embodiments of the present disclosure.

[0053] When conducting an asymmetric load test, the wafer produced by the disclosed method was compared with a polished wafer without crystal native defects (COP). The test results show that the deformation symmetry parameter of the polished wafer without COP is 0.53, while the deformation symmetry parameter of the wafer produced by the disclosed method is increased to 0.81, indicating that the symmetry has been significantly improved. Through this test, it is proved that the technical solution of the disclosed embodiment can effectively improve the ability of wafer W to resist asymmetric deformation. This improved symmetry parameter means that the substrate produced by the disclosed method is more stable in structure and can better withstand asymmetric stress, thereby showing better performance and reliability in subsequent processes and applications.

[0054] It should be noted that the technical solutions described in the present disclosure can be combined arbitrarily without conflict.

[0055] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A method for improving the ability of a wafer to resist asymmetric deformation, characterized in that: The method comprises: According to the asymmetric stress to be applied to the wafer, a region to be strengthened is defined in the wafer, so that after the region to be strengthened is strengthened, the wafer can resist the occurrence of asymmetric deformation when subjected to the asymmetric stress; doping the wafer in the region to be strengthened; The doped wafer is annealed to repair the lattice damage caused by doping.

2. The method for improving the ability of a wafer to resist asymmetric deformation according to claim 1, characterized in that: The area to be strengthened is away from the edge of the wafer to avoid causing lattice damage at the edge of the wafer.

3. The method for improving the ability of a wafer to resist asymmetric deformation according to claim 2, characterized in that: The area to be strengthened includes a plurality of continuous linear sections parallel to each other.

4. The method for improving the ability of a wafer to resist asymmetric deformation according to claim 2, characterized in that: The area to be strengthened is rectangular.

5. The method for improving the ability of a wafer to resist asymmetric deformation according to any one of claims 1 to 4, characterized in that: The step of doping the wafer comprises: ionizing and accelerating the doping element to form a high-energy ion beam; Adjusting the energy of the high energy ion beam and the angle relative to the wafer; The adjusted high-energy ion beam is scanned on the area to be strengthened on the wafer.

6. The method for improving the ability of a wafer to resist asymmetric deformation according to any one of claims 1 to 4, characterized in that: The step of doping the wafer comprises: bringing a dopant into contact with the region of the wafer to be strengthened; Performing a pre-diffusion process to allow the doping element to undergo a surface adsorption reaction in the area to be strengthened; A driven diffusion process is performed to diffuse the doping elements into the wafer to achieve a desired doping depth and doping concentration.

7. The method for improving the ability of a wafer to resist asymmetric deformation according to claim 6, characterized in that: The step of bringing the dopant into contact with the region to be strengthened of the wafer comprises: forming a mask pattern in an area of ​​the wafer except the area to be strengthened; The dopant is introduced to the wafer.

8. The method for improving the ability of a wafer to resist asymmetric deformation according to any one of claims 1 to 4, characterized in that: The wafer is doped with antimony element.

9. A system for improving the ability of a wafer to resist asymmetric deformation, characterized in that: The system comprises: A demarcation unit, the demarcation unit being used to demarcate a region to be strengthened in the wafer according to the asymmetric stress to be applied to the wafer, so that after the region to be strengthened is strengthened, the wafer can resist the occurrence of asymmetric deformation when subjected to the asymmetric stress; A doping unit, the doping unit is used to dope the wafer in the area to be strengthened; An annealing unit is used to perform annealing on the doped wafer to repair lattice damage caused by doping.

10. A substrate, characterized in that The substrate is obtained by processing a wafer using the method for improving the ability of a wafer to resist asymmetric deformation according to any one of claims 1 to 8 or the system for improving the ability of a wafer to resist asymmetric deformation according to claim 9.

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