Providing lower inductance paths in wiring substrates for capacitors, and related electronic devices and methods of manufacture

Abstract

An electronic device including a wiring substrate with a lower inductance path for a capacitor and a related manufacturing method. In an exemplary aspect, to provide a lower interconnect inductance for a capacitor coupled to a power distribution network in the wiring substrate, an additional metal layer providing an additional second power plane is provided in the dielectric layer between adjacent ones of the adjacent metallization layers. The additional second power plane is adjacent to a first power plane disposed in a first metal layer of one of the adjacent metallization layers. The arrangement of the additional metal layer in the dielectric layer of the metallization layer reduces the thickness of the dielectric material between the first power plane and the second power plane coupled to the capacitor as part of the power distribution network. The reduced dielectric thickness between the first power plane and the second power plane coupled to the capacitor reduces the interconnect inductance for the capacitor.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application serial number 17 / 934,651, filed on September 23, 2022, entitled “PROVIDING A LOWER INDUCTANCE PATH IN A ROUTING SUBSTRATE FOR A CAPACITOR, AND RELATED ELECTRONIC DEVICESAND FABRICATION METHODS,” which is incorporated herein by reference in its entirety. background I. Technical field

[0004] The field of the present disclosure relates to integrated circuit (IC) packages including one or more semiconductor dies supported by a packaging substrate, and more particularly to coupling capacitors to the dies in the IC package to support signal processing and / or power integrity. II. Background Technology

[0005] Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in IC packages (also referred to as "semiconductor packages" or "chip packages"). The IC package includes one or more semiconductor dies that are mounted on a package substrate and electrically coupled to the package substrate to provide physical support and electrical interfaces for the die(s). The IC package may be coupled to a printed circuit board (PCB) to dock the circuits in the IC package to other electrical components coupled to the PCB. The IC package may also be coupled to power rails and ground rails within a power distribution network in the PCB to receive power for operation. For example, the PCB may include an external interconnector that is configured to couple to a power source to receive a power signal that is distributed in its power distribution network to provide to the IC package.

[0006] Capacitors are usually coupled to circuits in IC packages. Capacitors may be coupled to circuits in IC packages as part of a filter circuit for a die in an IC package. Capacitors may also be coupled to circuits in IC packages to provide decoupling capacitance for circuits in a die in an IC package to shunt noise from one circuit (e.g., a power supply circuit) to another circuit (e.g., a powered circuit). For example, in order to provide decoupling capacitance for an IC package, a decoupling capacitor may be coupled to a package substrate of an IC package or the same PCB to which the IC package is coupled. Decoupling capacitors may be coupled to the outer surface of a package substrate or PCB so that the decoupling capacitors are electrically coupled to the power rails and ground rails of a power distribution network in the package substrate or PCB. For example, decoupling capacitors may be coupled to the same side of a PCB to which an IC package is coupled (i.e., the package side). Decoupling capacitors may also be coupled to the opposite side of a PCB to which an IC package is coupled (i.e., the pad side). In the case of a package side capacitor or a pad side capacitor, it is desirable to minimize the length of the signal routing path between the die in the IC package and the capacitor. This is because the inductance in the connection path increases according to the increased signal routing path length. The increased inductance may result in a loss of performance of the capacitor. If the capacitor cannot be mounted to a packaging substrate or PCB that is vertically oriented below the IC package (i.e., mounted to a packaging substrate or PCB that is laterally offset from the die), the signal routing path length between the capacitor and the die in the IC package may be further increased. Mounting the capacitor to a packaging substrate or PCB that is laterally offset from the die means that the signal routing path between the capacitor and the die will also include a horizontal routing path within the packaging substrate or PCB, thus helping to increase the signal routing path length. Summary of the invention

[0007] Various aspects disclosed herein include providing a lower inductance path in a wiring substrate for a capacitor. Related electronic devices and manufacturing methods are also disclosed. As an example, the wiring substrate can be a packaging substrate of an integrated circuit (IC) package. As another example, the wiring substrate can be a circuit board (e.g., a printed circuit board (PCB)), wherein an IC chip or other IC package is coupled to provide electrical signal wiring between the PCB and the IC chip / IC package. The wiring substrate includes one or more metallization layers, each of which includes a metal layer insulated by a dielectric layer. The capacitor is coupled to the wiring substrate and can be electrically coupled to a plane ("power plane") in a metal layer in the metallization layer of the wiring substrate to provide decoupling capacitance. The thickness of the dielectric layer between the metal layers in adjacent metallization layers affects the interconnection inductance of a device (e.g., a capacitor) coupled to a power plane in such adjacent metal layers, because when a power signal is carried in a power plane in an adjacent metal layer, a magnetic flux loop is generated between the adjacent metal layers. The greater the thickness of the dielectric layer between the adjacent metal layers, the greater the interconnection inductance between these adjacent metal layers. For example, the increased interconnection inductance can result in a performance loss of a capacitor coupled to such a power plane. Therefore, in an exemplary aspect, to provide lower interconnect inductance in a power distribution network in a wiring substrate, an additional metal plane for providing a second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The first power plane is disposed in a metal layer in one of the adjacent metallization layers. Providing the second power plane in a dielectric layer between adjacent metal layers in the adjacent metallization layers reduces the thickness of the dielectric material of the dielectric layer between the first power plane and the second power plane. This reduced dielectric thickness between the first power plane and the second power plane can reduce the interconnect inductance for capacitors coupled to the first power plane and the second power plane.

[0008] As an example, the additional metal plane as the additional second power plane can be a separate additional metal plane in a dielectric layer between adjacent metal layers in adjacent metallization layers. This reduces the thickness between the first power plane and the second power plane to reduce the interconnection inductance between the first power plane and the second power plane. As another example, the additional metal plane as the additional second power plane can be disposed in one of the metal layers of the adjacent metallization layers, and the thickness is increased to be at least partially disposed in a dielectric layer between adjacent metal layers in the adjacent metallization layers. In this example, this also reduces the thickness between the first power plane and the second power plane to reduce the interconnection inductance between the first power plane and the second power plane.

[0009] When the signal routing path to the coupled capacitor requires a horizontal routing path in the wiring substrate, it may be particularly advantageous to provide an additional metal plane as an additional second power plane in the metallization layer of the wiring substrate to reduce the thickness of the dielectric material between the first power plane and the second power plane. This is because circuit board or package substrate manufacturing limitations may impose or require a minimum distance between metallization layers in the wiring substrate, which controls the minimum dielectric layer thickness between adjacent metallization layers. Providing an additional metal plane as an additional second power plane for the coupled capacitor to reduce the interconnection inductance to the capacitor may allow more flexibility in placing the capacitor on the circuit board or package substrate. For example, the capacitor may be able to be placed in a circuit board or package substrate in an area where horizontal routing between the capacitor and an IC package or circuit will be required, which IC package or circuit would otherwise have an increased interconnection inductance to the capacitor due to the longer signal routing path caused by the horizontal routing. For example, it may be easier to place a capacitor on a circuit board or package substrate that requires horizontal signal routing than to place a capacitor on a circuit board or package substrate that will allow vertical signal routing.

[0010] In one exemplary aspect, the wiring substrate is a circuit board (e.g., a printed circuit board (PCB)). In one example, the IC package includes one or more dies coupled to the circuit board, wherein the dies are indirectly electrically coupled to the circuit board. In another example, the dies are directly coupled to the circuit board. The capacitor is also coupled to the circuit board and is coupled to a first power plane in a first metal layer of a first metallization layer and an additional metal plane as an additional second power plane, with a reduced dielectric material thickness between the two to provide decoupling capacitance to the IC package or die coupled to the circuit board. The capacitor can be a package side capacitor coupled to the outer surface of the circuit board on the same side of the circuit board when the IC package or die is coupled. The capacitor can also be a pad side capacitor (LSC) coupled to the outer surface of the circuit board on the opposite side of the circuit board when the IC package or die is coupled. The reduced interconnect inductance to the capacitor facilitated by the additional metal plane can mitigate or offset any increased inductance caused by the longer signal routing path provided to the capacitor. This provides additional flexibility when coupling the capacitor to the circuit board, which utilizes available space and / or avoids the need to increase the overall height of the IC package / die and the circuit board. Additional capacitors may also be coupled to the circuit board in vertical alignment with the IC package or die, requiring only vertical signal routing paths between the additional capacitors and the IC package or die.

[0011] In another exemplary aspect, the wiring substrate is a packaging substrate of an IC package. The capacitor is also coupled to the packaging substrate and coupled to a first power plane in a first metal layer of a first metallization layer and an additional metal plane as an additional second power plane, with a reduced dielectric material thickness between the two to provide decoupling capacitance to the tube core coupled to the packaging substrate. The capacitor can be a package side capacitor coupled to the outer surface of the packaging substrate on the same side of the packaging substrate to which the tube core is coupled. The capacitor can also be an LSC coupled to the outer surface of the packaging substrate on the opposite side of the packaging substrate to which the tube core is coupled. The reduced interconnect inductance to the capacitor promoted by the additional metal plane can alleviate or offset any increased inductance caused by the longer signal wiring path provided to the capacitor. This provides additional flexibility when coupling the capacitor to the packaging substrate, which utilizes available space and / or avoids the need to increase the overall height of the IC package. The additional capacitor can also be coupled to a package that is vertically aligned with the tube core, which only requires a vertical signal wiring path between the additional capacitor and the tube core.

[0012] In this regard, in an exemplary aspect, an electronic device is provided. The electronic device includes a wiring substrate, the wiring substrate including a plurality of metallization layers parallel to each other along a first direction. The plurality of metallization layers include a first metallization layer and a first dielectric layer adjacent to the first metal layer, the first metallization layer including a first metal layer having a first metal plane. The plurality of metallization layers also include a second metallization layer adjacent to the first metallization layer. The second metallization layer includes a second metal layer and a second dielectric layer adjacent to the second metal layer. The wiring substrate also includes a second metal plane disposed in the first dielectric layer along the first direction between the first metal layer and the second metal layer. The electronic device also includes a capacitor coupled to the first metal plane and the second metal plane.

[0013] In another exemplary aspect, a method for manufacturing an electronic device is provided. The method includes forming a wiring substrate, the wiring substrate including a plurality of metallization layers parallel to each other along a first direction, including forming a first metallization layer and forming a second metallization layer. Forming the first metallization layer includes forming a first metal layer including a first metal plane, and forming a first dielectric layer adjacent to the first metal layer. For the second metallization layer, it includes forming a second metal layer and forming a second dielectric layer adjacent to the second metal layer. Forming the wiring substrate including a plurality of metallization layers also includes forming a second metal plane in the first dielectric layer of the first metallization layer. Forming the wiring substrate also includes coupling the second metallization layer to the first metallization layer so that the second metal plane is located between the first metal layer and the second metal layer along a second direction orthogonal to the first direction. The method also includes coupling a capacitor to the wiring substrate, including coupling the capacitor to the first metal plane and the second metal plane. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a side view of an electronic device including an integrated circuit (IC) package coupled to a circuit board as a wiring substrate and a capacitor coupled to the circuit board and electrically coupled to a power plane in an adjacent metallization layer within the circuit board to provide decoupling capacitance;

[0015] Figure 2A and Figure 2B is a side view of an exemplary electronic device including an IC package coupled to a circuit board as a wiring substrate and a capacitor coupled to a first power plane disposed in a metal layer of a first metallization layer of the circuit board and coupled to an additional metal plane disposed in a dielectric layer of an adjacent second metallization layer as an additional power plane to reduce a thickness of a dielectric material between the first power plane coupled to the capacitor and the additional power plane, thereby reducing an interconnect inductance for the capacitor;

[0016] FIG. 3A to FIG. 3C is a top view of an exemplary layout of the electronic device of FIG. 2 , illustrating an additional power plane provided by an additional metal plane disposed in a dielectric layer of a metallization layer of a circuit board, and possible locations of capacitors coupled to the PCB and the power plane;

[0017] Figure 4 is a side view of another exemplary electronic device, the exemplary electronic device including an IC package coupled to a circuit board as a wiring substrate and a capacitor coupled to a first power plane disposed in a first metal layer of a first metallization layer of the circuit board and coupled to an additional metal plane disposed in a second metal layer of an adjacent second metallization layer and partially located between the adjacent first metal layer and the second metal layer as an additional power plane, to reduce a thickness of a dielectric material between the first power plane coupled to the capacitor and the additional power plane, thereby reducing an interconnect inductance for the capacitor;

[0018] Figure 5 is a side view of another exemplary electronic device including an IC package as a wiring substrate and a capacitor coupled to a first power plane disposed in a metal layer of a first metallization layer of a circuit board and coupled to an additional metal plane disposed in a dielectric layer of an adjacent second metallization layer as an additional power plane to reduce a thickness of a dielectric material between the first power plane coupled to the capacitor and the additional power plane, thereby reducing an interconnect inductance for the capacitor;

[0019] Figure 6is a flow chart illustrating an exemplary manufacturing process for manufacturing a wiring substrate for an electronic device, wherein the wiring substrate includes a metal layer as a first power plane in a first metallization layer of a circuit board, and an additional metal plane as a second additional power plane disposed in a dielectric layer adjacent to a second metallization layer, to reduce the thickness of a dielectric material between the first power plane and the additional power plane, thereby reducing interconnection inductance, including but not limited to Figures 2A to 5 A wiring substrate in;

[0020] 7A to 7C is a flow chart illustrating another exemplary process of manufacturing a wiring substrate for an electronic device, wherein the wiring substrate includes a metal layer as a first power plane in a first metallization layer of a circuit board, and an additional metal plane as a second additional power plane disposed in a dielectric layer adjacent to a second metallization layer, to reduce the thickness of a dielectric material between the first power plane and the additional power plane, thereby reducing interconnection inductance, including but not limited to Figures 2A to 5 A wiring substrate in;

[0021] FIG. 8A to FIG. 8F is based on 7A to 7C an exemplary manufacturing stage during the manufacture of a wiring substrate of an exemplary manufacturing process in;

[0022] 9A to 9C is a flow chart illustrating another exemplary process of manufacturing a wiring substrate for an electronic device, wherein the wiring substrate includes a metal layer as a first power plane in a first metallization layer of a circuit board, and an additional metal plane as a second additional power plane disposed in a dielectric layer adjacent to a second metallization layer, to reduce the thickness of a dielectric material between the first power plane and the additional power plane, thereby reducing interconnection inductance, including but not limited to Figures 2A to 5 A wiring substrate in;

[0023] FIG. 10A to FIG. 10F is based on 9A to 9C an exemplary manufacturing stage during the manufacture of a wiring substrate of an exemplary manufacturing process in;

[0024] Fig.11 is a block diagram of an exemplary wireless communication device including a radio frequency (RF) component, the radio frequency (RF) component may include an electronic device and a capacitor, the electronic device including a wiring substrate, the capacitor is coupled to a first power plane disposed in a metal layer of a first metallization layer of a circuit board, and is coupled to an additional metal plane disposed in a dielectric layer of an adjacent second metallization layer as a second additional power plane, to reduce the thickness of a dielectric material between the first power plane coupled to the capacitor and the second power plane, thereby reducing interconnection inductance for the capacitor, including but not limited to Figures 2A to 5 , FIG. 8A to FIG. 8F and FIG. 10A to FIG. 10FElectronic devices and wiring substrates in accordance with but not limited to Figures 6 to 8C and 9A to 9C Any of the exemplary manufacturing processes in the exemplary manufacturing process, and according to but not limited to Figures 6 to 8C any of the exemplary manufacturing processes in the exemplary manufacturing process; and

[0025] Fig.12 is a block diagram of an exemplary processor-based system including components, which may include an electronic device and a capacitor, the electronic device including a wiring substrate, the capacitor coupled to a first power plane disposed in a metal layer of a first metallization layer of a circuit board, and coupled to an additional metal plane disposed in a dielectric layer of an adjacent second metallization layer as a second additional power plane, to reduce the thickness of a dielectric material between the first power plane coupled to the capacitor and the second power plane, thereby reducing interconnect inductance for the capacitor, including but not limited to Figures 2A to 5 , FIG. 8A to FIG. 8F and FIG. 10A to FIG. 10F Electronic devices and wiring substrates in accordance with but not limited to Figures 6 to 8C and 9A to 9C Any exemplary manufacturing process in the exemplary manufacturing process. DETAILED DESCRIPTION

[0026] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0027] Various aspects disclosed herein include providing a lower inductance path in a wiring substrate for a capacitor. Related electronic devices and manufacturing methods are also disclosed. As an example, the wiring substrate can be a packaging substrate of an integrated circuit (IC) package. As another example, the wiring substrate can be a circuit board (e.g., a printed circuit board (PCB)), wherein an IC chip or other IC package is coupled to provide electrical signal wiring between the PCB and the IC chip / IC package. The wiring substrate includes one or more metallization layers, each of which includes a metal layer insulated by a dielectric layer. The capacitor is coupled to the wiring substrate and can be electrically coupled to a plane ("power plane") in a metal layer in the metallization layer of the wiring substrate to provide decoupling capacitance. The thickness of the dielectric layer between the metal layers in adjacent metallization layers affects the interconnection inductance of a device (e.g., a capacitor) coupled to a power plane in such adjacent metal layers, because when a power signal is carried in a power plane in an adjacent metal layer, a magnetic flux loop is generated between the adjacent metal layers. The greater the thickness of the dielectric layer between the adjacent metal layers, the greater the interconnection inductance between these adjacent metal layers. For example, the increased interconnection inductance can result in a performance loss of a capacitor coupled to such a power plane. Therefore, in an exemplary aspect, to provide lower interconnect inductance in a power distribution network in a wiring substrate, an additional metal plane for providing a second power plane is disposed in a dielectric layer between adjacent metal layers in adjacent metallization layers. The first power plane is disposed in a metal layer in one of the adjacent metallization layers. Providing the second power plane in a dielectric layer between adjacent metal layers in the adjacent metallization layers reduces the thickness of the dielectric material of the dielectric layer between the first power plane and the second power plane. This reduced dielectric thickness between the first power plane and the second power plane can reduce the interconnect inductance for capacitors coupled to the first power plane and the second power plane.

[0028] When the signal routing path to the coupled capacitor requires a horizontal routing path in the wiring substrate, it may be particularly advantageous to provide an additional metal plane as an additional second power plane in the metallization layer of the wiring substrate to reduce the thickness of the dielectric material between the first power plane and the second power plane. This is because circuit board or package substrate manufacturing limitations may impose or require a minimum distance between metallization layers in the wiring substrate, which controls the minimum dielectric layer thickness between adjacent metallization layers. Providing an additional metal plane as an additional second power plane for the coupled capacitor to reduce the interconnection inductance to the capacitor may allow more flexibility in placing the capacitor on the circuit board or package substrate. For example, the capacitor may be able to be placed in a circuit board or package substrate in an area where horizontal routing between the capacitor and an IC package or circuit will be required, which IC package or circuit would otherwise have an increased interconnection inductance to the capacitor due to the longer signal routing path caused by the horizontal routing. For example, it may be easier to place a capacitor on a circuit board or package substrate that requires horizontal signal routing than to place a capacitor on a circuit board or package substrate that will allow vertical signal routing.

[0029] Before discussing an example of an electronic device including a capacitor starting at FIG. 2 , a description is first given of Figure 1 The electronic device 100 in which the capacitor is coupled to a first power plane in a first metallization layer in a wiring substrate and is coupled to an additional metal plane as an additional second power plane disposed in a dielectric layer of an adjacent second metallization layer to reduce the thickness of the dielectric material between the first power plane and the second power plane, thereby reducing the interconnection inductance for the capacitor. As described below, the electronic device 100 does not include an additional power plane in the dielectric layer of the adjacent metallization layer to reduce the thickness of the dielectric material between the first power plane and the additional power plane, thereby reducing the interconnection inductance for the capacitor.

[0030] In this regard, Figure 11 is a side view of an electronic device 100. The electronic device 100 includes an integrated circuit (IC) package 102 coupled to a circuit board 104 as a wiring substrate 106. The IC package 102 in this example includes a first die 108(1) coupled to a package substrate 109. For example, the first die 108(1) may include a graphics processor chip 110. The IC package 102 also includes a second die 108(2) stacked above the first die 108(1) along a first vertical direction (Z-axis direction) and coupled to the first die 108(1). For example, the second die 108(2) may include a central processing unit (CPU) chip 112. The first die 108(1) and the second die 108(2) are electrically coupled to the package substrate 109 through corresponding external interconnectors 114(1), 114(2) (e.g., solder balls, ball grid array (BGA) interconnectors). The package substrate 109 includes one or more metallization layers including metal lines interconnected to provide signal routing paths between the first die 108(1) and the second die 108(2) and external interconnectors 115 (e.g., solder balls, BGA interconnectors) of the package substrate 109. The IC package 102 is coupled to the circuit board 104 through the external interconnectors 115.

[0031] Continue to refer Figure 1 , the circuit board 104 includes a plurality of metallization layers 116(1)-116(6), each of which includes metal lines that can provide signal routing paths within the circuit board 104. For example, an external interconnect 115 of the IC package 102 is coupled to the first metallization layer 116(1) of the circuit board 104 to electrically couple the IC package 102 and its first die 108(1) and second die 108(2) to the circuit board 104. The circuit board 104 in this example includes power planes that are configured to be coupled to a power source that is part of a power distribution network so that power can be tapped from these power planes to supply power to the IC package 102 and its first die 108(1) and second die 108(2) for operation. For example, as Figure 1 As shown, the second metallization layer 116(2) in the circuit board 104 includes a second metal layer 118(2) including a first power plane 120(1) configured to be coupled to a ground connection for a power source. The third metallization layer 116(3) in the circuit board 104 includes a third metal layer 118(3) including a second power plane 120(2) configured to be coupled to a power signal connection for a power source. Also, in this example, the fourth metallization layer 116(4) in the circuit board 104 includes a fourth metal layer 118(4) including a third power plane 120(3) also configured to be coupled to a ground connection for a power source.

[0032] The first capacitor 122(1) and the second capacitor 122(2) are also coupled to Figure 1 1 . The power planes 120(1)-120(3) of the circuit board 104 in the electronic device 100 in FIG. 1 . For example, the first capacitor 122(1) may provide a decoupling capacitor or filter for the circuit in the first die 108(1), and the second capacitor 122(2) may provide a decoupling capacitor or filter for the circuit in the second die 108(2). The first capacitor 122(1) and the second capacitor 122(2) may provide capacitors as part of a filtering circuit for the respective first die 108(1) and the second die 108(2). In this example, the first capacitor 122(1) and the second capacitor 122(2) provide decoupling capacitance to shunt noise from power and other circuits in the first die 108(1) and the second die 108(2). The first capacitor 122(1) has a first terminal 124(1) coupled to the first power plane 120(1) and a second terminal 124(2) coupled to the second power plane 120(2). In this example, the first capacitor 122(1) and its first terminal 124(1) and second terminal 124(2) are electrically coupled to the circuit board 104 and the sixth metallization layer 116(6). Metal lines 126 in the sixth metal layer 118(6) of the sixth metallization layer 116(6) can route signals between the first capacitor 122(1) and the first power plane 120(1) and the second power plane 120(2). The second capacitor 122(2) has a first terminal 128(1) coupled to the third power plane 120(3) and a second terminal 128(2) coupled to the second power plane 120(2). In this example, the second capacitor 122(2) and its first terminal 128(1) and second terminal 128(2) are electrically coupled to the circuit board 104 and the sixth metallization layer 116(6). Metal lines 126 in sixth metal layer 118 ( 6 ) of sixth metallization layer 116 ( 6 ) may route signals between second capacitor 122 ( 2 ) and second power plane 120 ( 2 ) and third power plane 120 ( 3 ).

[0033] like Figure 1As shown, the first power plane 120(1) and the second power plane 120(2) are separated from each other by a first height H1 along the first vertical direction (Z-axis direction) through the thickness of the third dielectric layer 130(3) of the third metallization layer 116(3) in the circuit board 104. The second power plane 120(2) and the third power plane 120(3) are separated from each other by a second height H2 along the first vertical direction (Z-axis direction) through the thickness of the fourth dielectric layer 130(4) of the fourth metallization layer 116(4) in the circuit board 104. The thickness of the third dielectric layer 130(3) of the third metallization layer 116(3) in the circuit board 104, as indicated by the first height H1 between the first power plane 120(1) and the second power plane 120(2) in the adjacent second metallization layer 116(2) and the third metallization layer 116(3), affects the interconnection inductance of the first capacitor 122(1) coupled to the first power plane 120(1) and the second power plane 120(2). This is because a magnetic flux loop is generated between the first power plane 120(1) and the second power plane 120(2) when power signals are carried in the first power plane 120(1) and the second power plane 120(2). Likewise, the thickness of the third dielectric layer 130(3) of the third metallization layer 116(3) in the circuit board 104, as indicated by the second height H2 between the second power plane 120(2) and the third power plane 120(3) in the adjacent third metallization layer 116(3) and the fourth metallization layer 116(4), affects the interconnection inductance of the second capacitor 122(2) coupled to the second power plane 120(2) and the third power plane 120(3). Again, this is because a magnetic flux loop is generated between the second power plane 120(2) and the third power plane 120(3) when power signals are carried in the second power plane 120(2) and the third power plane 120(3).

[0034] The greater the thickness of the dielectric layer between the power planes, the greater the interconnection inductance between these power planes. The increased interconnection inductance can cause performance loss of the first capacitor 122(1) and the second capacitor 122(2) coupled to the corresponding first power plane 120(1) and the second power plane 120(2) and the second power plane 120(2) and the third power plane 120(3). This is not a problem for the first capacitor 122(1) because the first capacitor 122(1) is the signal routing path to the IC package 102, not the second capacitor 122(2). The first capacitor 122(1) is coupled to the circuit board 104 below the IC package 102 along the first vertical direction (Z-axis direction), while the second capacitor 122(2) is coupled to the circuit board 104 that is laterally offset from the IC package 102 along the first vertical direction (Z-axis direction). Therefore, the signal routing path to the second capacitor 122(2) involves routing in the second power plane 120(2) and the third power plane 120(3), which extends horizontally in the third metal layer 118(3) and the fourth metal layer 118(4) thereof along a second horizontal direction (X-axis direction and / or Y-axis direction) orthogonal to the first vertical direction (Z-axis direction), thereby increasing the signal routing path length between the IC package 102 and the second capacitor 122(2). This increased signal routing path length to the second capacitor 122(2) means that the second capacitor 122(2) may have a greater interconnection inductance than the first capacitor 122(1) because the increased signal routing distance may also result in increased interconnection inductance.

[0035] Due to the reduced signal routing path length between the IC package 102 and the first capacitor 122(1), the interconnect inductance for the first capacitor 122(1) may be within acceptable limits. However, due to the increased signal routing path length between the IC package 102 and the second capacitor 122(2), the interconnect inductance for the second capacitor 122(2) may be outside of acceptable limits. The second capacitor 122(2) may be coupled to a different location on the circuit board 104 to reduce the signal routing path length between the IC package 102 and the second capacitor 122(2). However, this may not be possible or feasible due to package area limitations and / or other limitations. For example, in Figure 1 In the electronic device 100 of FIG. 1 , the first capacitor 122(1) occupies space below the IC package 102. It is desirable to be able to couple a capacitor to a die in an electronic device that allows for lateral displacement of signal routing paths between the capacitor and the die in a horizontal direction, but with reduced interconnect inductance.

[0036] In this regard, Figure 2A and Figure 2B2 is a side view of an exemplary electronic device 200 including an IC package 202 coupled to a circuit board 204 as a wiring substrate 206, wherein the interconnection inductance between the second capacitor 222(2) and the IC package 202 is reduced. In this regard, as described in more detail below and as shown in Figure 2A As shown, the second capacitor 222(2) is coupled to a first power plane 220(1) disposed in a third metal layer 218(3) of a third metallization layer 216(3) of the circuit board 204 for a first power connection. A power plane is a metal line or plane disposed in a metallization layer. The first power plane 220(1) is configured to carry a first power signal of a power source. The second capacitor 222(2) is also coupled to an additional metal plane 232 (also referred to as "second power plane 220(2)") as an additional second metal plane 220(2), which is disposed in a fourth dielectric layer 230(4) of an adjacent fourth metallization layer 216(4) to reduce the thickness of a dielectric material 234(4) between the first power plane 220(1) and the additional second power plane 220(2) coupled to the second capacitor 222(2). The second power plane 220(2) is disposed in a fourth dielectric layer 230(4) of a fourth metallization layer 216(4) adjacent to the third metallization layer 216(3) and between the third metal layer 218(3) and the fourth metal layer 218(4) along a first vertical direction (Z-axis direction) orthogonal to a second horizontal direction (X-axis direction and / or Y-axis direction) of the metallization layers 216(1)-216(6), the second horizontal direction being orthogonal to the first vertical direction. The second power plane 220(2) is configured to carry a second power signal (or return signal) of a power source. This has the effect of reducing the interconnection inductance to the second capacitor 222(2) because a first distance D1 between the first power plane 220(1) and the additional second power plane 220(2) is reduced compared to, for example, a third height H3 along the first vertical direction (Z-axis direction) between the first power plane 220(1) and the third power plane 220(3). In this way, when a power signal is carried in the first power plane 220(1) and the additional second power plane 220(2), the magnetic flux loop generated between the first power plane 220(1) and the additional second power plane 220(2) is smaller than the magnetic flux loop between the first power plane 220(1) and the third power plane 220(3).

[0037] In this example, providing the additional metal plane 232 in the fourth metallization layer 216(4) as the additional second power plane 220(2) reduces the thickness of the dielectric material 234(4) between the additional second power plane 220(2) and the first power plane 220(1), as indicated by the first distance D1. This may be particularly advantageous for the second capacitor 222(2) having a horizontal routing path in the circuit board 204. Providing the additional metal plane 232 in the fourth metallization layer 216(4) also causes the additional metal plane 232 to be located at a second distance D2 (which is less than the height H3 of the fourth dielectric layer 230(4)) from the fourth metal layer 218(4) in the fourth metallization layer 216(4). Figure 2B ). This is because the manufacturing of the circuit board 204 may impose or require a minimum distance (e.g., six (60) micrometers (μm)) between adjacent metallization layers 216(1)-216(6), which controls the minimum dielectric layer thickness between adjacent metallization layers 216(1)-216(6). Providing an additional second power plane 220(2) coupled to the second capacitor 222(2) to reduce the interconnect inductance to the second capacitor 222(2) may allow for greater flexibility in placing the second capacitor 222(2) on the circuit board 204. For example, Figure 2A As shown, it may be easier to place and couple the second capacitor 222(2) on the first top surface 236(1) of the circuit board 204 than to couple the second capacitor 222(2) to the second bottom surface 236(2) of the circuit board 204, which then requires horizontal signal routing in the circuit board 204 to the second capacitor 222(2).

[0038] refer to Figure 2B, the circuit board 204 includes a plurality of metallization layers 216(1)-216(6), each of which includes metal layers 218(1)-218(6), which may include metal lines to provide signal routing paths within the circuit board 204. Each metallization layer 216(1)-216(6) also has a corresponding dielectric layer 230(1)-230(6) of dielectric material adjacent to its corresponding metal layer 218(1)-218(6) to insulate the metal layers 218(1)-218(6) from each other. The metallization layers 216(1)-216(6) are parallel to each other along a second horizontal direction (X-axis direction and / or Y-axis direction) orthogonal to the first vertical direction (Z-axis direction). For example, the external interconnector 217 of the IC package 202 is coupled to the first metallization layer 216(1) of the circuit board 204 to electrically couple the IC package 202 and its first die 208(1) and second die 208(2) to the circuit board 204. The circuit board 204 in this example includes power planes that are configured to be coupled to a power source as part of a power distribution network so that power can be tapped from these power planes to supply power to the IC package 202 and its first die 208(1) and second die 208(2) for operation. For example, as Figure 2B As shown, the second metallization layer 216(2) in the circuit board 204 includes a second metal layer 218(2), which includes a fourth metal plane 220(4) configured to be coupled to a ground connection for a power source (also referred to as the "fourth power plane 220(4)"). The third metallization layer 216(3) in the circuit board 204 includes a third metal layer 218(3), which includes a first metal plane 220(1) configured to be coupled to a power signal connection for a power source (also referred to as the "first power plane 220(1)"). The first power plane 220(1) is configured to carry a power signal for the power source. Moreover, in this example, the fourth metallization layer 216(4) in the circuit board 204 includes a fourth metal layer 218(4), which includes a third metal plane 220(3) also configured to be coupled to a ground connection for a power source (also referred to as the "third power plane 220(3)").

[0039] Moreover, if Figure 2BAs shown, the first capacitor 222(1) and the second capacitor 222(2) are also coupled to the first power plane 220(1) and the second power plane 220(2) of the circuit board 204. For example, the first capacitor 222(1) may provide decoupling capacitance or a filter for the circuitry in the first die 208(1), and the second capacitor 222(2) may provide decoupling capacitance or a filter for the circuitry in the second die 208(2). The first capacitor 222(1) and the second capacitor 222(2) may each provide a capacitor as part of a filtering circuit for the respective first die 208(1) and the second die 208(2). In this example, the first capacitor 222(1) and the second capacitor 222(2) provide decoupling capacitance to shunt noise from the power and other circuitry in the first die 208(1) and the second die 208(2). The first capacitor 222(1) has a first terminal 224(1) coupled to the fourth power plane 220(4) and a second terminal 224(2) coupled to the first power plane 220(1). In this example, the second capacitor 222(2) is coupled to the same first power plane 220(1) as the first capacitor 222(1), but this is not required. For example, the second capacitor 222(2) may be coupled to a separate power plane in the same third metal layer 218(3) of the third metallization layer 216(3) that is coupled to the first power plane 220(1).

[0040] In this example, the first capacitor 222(1) and its first terminal 224(1) and second terminal 224(2) are electrically coupled to the circuit board 204 and the sixth metallization layer 216(6) via a first external interconnector 238(1) (e.g., a solder ball, a BGA interconnector). Metal lines 226(3)-226(6) in the third, fourth, fifth, and sixth metal layers 218(3)-218(6) of the third, fourth, fifth, and sixth metallization layers 216(3)-216(6) can route signals between the first capacitor 222(1) and the first power plane 220(1) and the fourth power plane 220(4). The second capacitor 222(2) has a first terminal 228(1) coupled to the third power plane 220(3) and a second terminal 228(2) coupled to the first power plane 220(1). In this example, the second capacitor 222(2) and its first terminal 228(1) and second terminal 228(2) are electrically coupled to the circuit board 204 and the first metallization layer 216(1) via a second external interconnector 238(2) (e.g., a solder ball, a BGA interconnector). Metal lines 226(1)-226(3) in the first, second, and third metal layers 218(1)-218(3) of the first, second, and third metallization layers 216(1)-216(3) can route signals between the second capacitor 222(2) and the first power plane 220(1) and the second power plane 220(2).

[0041] Due to the reduced signal routing path length between the IC package 202 and the first capacitor 222(1), the first interconnect inductance for the first capacitor 222(1) can be within acceptable limits. The first capacitor 222(1) is coupled to the circuit board 204 below the IC package 202 along a first vertical direction (Z-axis direction) such that the IC package 202 and the first capacitor 222(1) share a common vertical plane (e.g., plane P1) along the vertical directions (Y-axis direction and Z-axis direction). Therefore, in this example, no horizontal signal routing path is required between the first capacitor 222(1) and the IC package 202 in the circuit board 204. However, the second capacitor 222(2) is coupled to the circuit board 204 that is laterally offset from the IC package 202 along the first vertical direction (Z-axis direction) such that the second capacitor 222(2) and the IC package 202 do not share a common vertical plane along the first vertical direction (Y-axis direction and Z-axis direction). Therefore, the signal routing path to the second capacitor 222(2) involves horizontal routing in the first power plane 220(1) and the second power plane 220(2), which horizontally extends in the second horizontal direction (X-axis direction and / or Y-axis direction) in its corresponding metal layer 218(3), 218(4), thereby increasing the signal routing path length between the IC package 202 and the second capacitor 222(2). This increased signal routing path length to the second capacitor 222(2) means that the second capacitor 222(2) can have a larger interconnect inductance than the first capacitor 222(1) because the increased signal routing distance can also result in increased interconnect inductance.

[0042] By providing an additional metal plane 232 to provide the second power plane 220(2) with a reduced distance D1 to the adjacent third metal layer 218(3) and its first power plane 220(1), the second interconnect inductance for the second capacitor 222(2) is also reduced. For example, the second interconnect inductance for the second capacitor 222(2) can be reduced to sixteen (16.0) picohenries (pH) or less (e.g., 15.1 pH or 2.5 pH). This reduced interconnect inductance can mitigate or offset the increased inductance due to the increased signal routing path length between the IC package 202 and the second capacitor 222(2). The second interconnect inductance for the second capacitor 222(2) is less than the third interconnect inductance between the first power plane 220(1) and the third power plane 220(3). The third interconnect inductance between the first power plane 220(1) and the third power plane 220(3) can exceed 170 pH (e.g., 176 pH). This is due to the increased height H3 of the fourth dielectric layer 230(4) and its dielectric material 234(4) between the first power plane 220(1) and the third power plane 220(3) compared to the reduced first distance D1 between the first power plane 220(1) and the second power plane 220(2) coupled to the second capacitor 222(2). This may, for example, allow the second capacitor 222(2) to be coupled to the circuit board 204 that is laterally offset from the IC package 202 along the first vertical direction (Z-axis direction) and the second interconnect inductance of the second capacitor 222(2) to remain within acceptable limits or desired limits.

[0043] For another example, the third height H3 of the fourth dielectric layer 230(4) can be between fifty (50) μm and seventy (70) μm. The first distance D1 between the additional plane 232 in the fourth dielectric layer 230(4) providing the second power plane 220(2) and the third plane 218(3) in the adjacent third metallization layer 216(3) can be between 1.0 μm and 5.0 μm. The ratio of the third height H3 of the fourth dielectric layer 230(4) to the first distance D1 between the additional metal plane 232 in the fourth dielectric layer 230(4) and the third metal layer 218(3) in the third metallization layer 216(3) can be at least 10.0. For another example, the ratio of the third interconnect inductance between the first power plane 220(1) and the third power plane 220(3) to the second interconnect inductance between the first power plane 220(1) and the second power plane 220(2) can be at least 10.0. Note that the first capacitor 222 ( 1 ) or any other capacitors need not be provided in the electronic device 200 .

[0044] FIG. 3A to FIG. 3C yes Figure 2A and Figure 2B2 is a top view of an exemplary layout of an electronic device 200 in FIG. 1 , illustrating an additional metal plane 232 provided by being disposed in a dielectric layer of a metallization layer of a circuit board 204 to provide an additional power plane for a second capacitor 222 (2) to reduce interconnect inductance. Figure 3A As shown, it provides a similar Figure 2A and Figure 2B The electronic device 200 (1) of the electronic device 200 in FIG. Figure 3A In the electronic device 200(1) of FIG. 1 , a plurality of second capacitors 222(2) are placed on the first top surface 204(1) of the circuit board 236. The second capacitors 222(2) are placed on the circuit board 204 laterally displaced from the IC package 202 along a second horizontal direction (X-axis direction and / or Y-axis direction). Figure 3A In this example, because a plurality of second capacitors 222 (2) are arranged around the IC package 202, an additional metal plane 232 is provided in a larger horizontal area along the second horizontal direction (X-axis direction and / or Y-axis direction), so that the second capacitors 222 (2) can be coupled to the additional metal plane through a signal wiring path along the first vertical direction (Z-axis direction).

[0045] like Figure 3B As shown, it provides a similar Figure 2A and Figure 2B Another electronic device 200(2) of the electronic device 200. Figure 3B In the electronic device 200(2) of FIG. 1 , a plurality of second capacitors 222(2) are placed on the first top surface 204(1) of the circuit board 236. The second capacitors 222(2) are placed on the circuit board 204 laterally displaced from the IC package 202 along a second horizontal direction (X-axis direction and / or Y-axis direction). Figure 3B In this example, because the second capacitor 222 (2) disposed around the IC package 202 is larger than Figure 3A Since there are fewer electronic devices 200(1), an additional metal plane 232 can be provided in a reduced horizontal area (along the X-axis direction and the Y-axis direction) so that the second capacitor 222(2) can be coupled to the additional metal plane through a signal wiring path along the first vertical direction (Z-axis direction).

[0046] like Figure 3C As shown, it provides a similar Figure 2A and Figure 2B Another electronic device 200 (3) of the electronic device 200 in the embodiment. Figure 3CIn the electronic device 200(3) of FIG. 1 , two (2) second capacitors 222(2) are placed on the first top surface 204(1) of the circuit board 236. The second capacitors 222(2) are placed on the circuit board 204 laterally displaced from the IC package 202 along a second horizontal direction (X-axis direction and / or Y-axis direction). Figure 3C In this example, two (2) separate additional metal planes 232 (1), 232 (2) coupled to the corresponding second capacitors 222 (2) are provided in the circuit board 204. The additional metal planes 232 (1), 232 (2) can be arranged in a reduced horizontal area along the second horizontal direction (X-axis direction and Y-axis direction) so that the second capacitor 222 (2) can be coupled to the additional metal planes through the signal wiring path along the first vertical direction (Z-axis direction). In this example, the two (2) capacitors 222 (2) can be coupled to their different corresponding power planes in different power domains. Therefore, using this example, the two (2) separate additional metal planes 232 (1), 232 (2) are arranged between different corresponding power planes in each power domain coupled to the corresponding capacitor 222 (2).

[0047] Figure 4 4 is a side view of another exemplary electronic device 400 including an IC package 402 coupled to a circuit board 404 as a wiring substrate 406, wherein the interconnection inductance between a capacitor 422 and the IC package 402 is reduced. The electronic device 400 is similar to FIG. 2A to FIG. 2B The electronic device 200 in. Figure 2A and Figure 2B The electronic device 200 and Figure 4 Common components between the electronic devices 400 in FIG. 4 are shown with common component numbers.

[0048] However, as discussed in more detail below, in the Figure 4 The fourth dielectric layer 230(4) of the fourth metallization layer 216(4) in the electronic device 400 is provided with a thicker additional metal plane 432, and the thicker additional metal plane has a thickness greater than 100 mm in the first vertical direction (Z-axis direction). FIG. 2A to FIG. 2BThe additional metal plane 432 provides an additional second metal plane 420(2) (also referred to as "second power plane 420(2)") in the circuit board 404. The second power plane 420(2) in this example is disposed in the third metal layer 218(3) of the third dielectric layer 216(3) and is also partially disposed in the fourth dielectric layer 230(4) of the fourth metallization layer 216(4), as opposed to being disposed as a separate metal plane that is not at least partially disposed in the third metal layer 218(3). The second power plane 420(2) is configured to carry a second power signal (or return signal) of a power source. The capacitor 422 is coupled to the first metal plane 420(1) (also referred to as "first power plane 420(1)") disposed in the fourth metal layer 218(4) of the fourth metallization layer 216(4) of the circuit board 204 for a first power supply connection. The capacitor 422 is also coupled to an additional metal plane 432 as a second power plane 420(2) disposed in a fourth dielectric layer 230(4) of an adjacent fourth metallization layer 216(4) to reduce the thickness of the dielectric material 234(4) between the first power plane 420(1) and the additional second power plane 420(2) coupled to the capacitor 422. The second power plane 420(2) is disposed in a fourth dielectric layer 230(4) of a fourth metallization layer 216(4) adjacent to the third metallization layer 216(3) and between the third metal layer 218(3) and the fourth metal layer 218(4) along a first vertical direction (Z-axis direction) orthogonal to a second horizontal direction (X-axis direction and / or Y-axis direction) of the metallization layers 216(1)-216(6), the second horizontal direction being orthogonal to the first vertical direction (Z-axis direction).

[0049] The additional metal plane 432 as the second power plane 420(2) has the effect of reducing the interconnection inductance to the capacitor 422. This is because, for example, the third distance D3 between the first power plane 420(1) and the additional second power plane 420(2) is reduced compared to the third height H3 along the first vertical direction (Z-axis direction) between the third metal layer 218(3) in the third metallization layer 216(3) and the first power plane 420(1) in the fourth metal layer 218(4) in the adjacent fourth metallization layer 216(4). Thus, when power signals are carried in the first power plane 420(1) and the additional second power plane 420(2), the magnetic flux loop generated between the first power plane 420(1) and the additional second power plane 420(2) is smaller than the magnetic flux loop between the third metal layer 218(3) and the first power plane 420(1).

[0050] Providing an additional metal plane 432 in the fourth metallization layer 216(4) as an additional second power plane 420(2) reduces the thickness (third distance D3) of the dielectric material 234(4) between the additional second power plane 420(2) and the first power plane 420(1). This may be particularly advantageous for capacitors 422 having horizontal wiring paths in the circuit board 404. This is because the manufacture of the circuit board 404 may impose or require a minimum distance (e.g., sixty (60) microns (μm)) between adjacent metallization layers 216(1)-216(6), which controls the minimum dielectric layer thickness between adjacent metallization layers 216(1)-216(6). Providing an additional metal plane 432 coupled to the capacitor 422 to reduce the interconnect inductance to the capacitor 422 may allow greater flexibility in placing the capacitor 422 on the circuit board 404. For example, as Figure 4 As shown, it may be easier to place and couple the capacitor 422 on the first top surface 436 ( 1 ) of the circuit board 404 than to couple the capacitor 422 on the second bottom surface 436 ( 1 ) of the circuit board 404 , which then requires horizontal signal routing to the capacitor 422 in the circuit board 404 .

[0051] Continue to refer Figure 4 In this example, the external interconnector 217 of the IC package 402 is coupled to the first metallization layer 216 (1) of the circuit board 404 to electrically couple the IC package 402 and its die 408 to the circuit board 404. The circuit board 404 in this example includes power planes that are configured to be coupled to a power source as part of a power distribution network so that power can be tapped from these power planes to supply power to the IC package 402 and its die 408 for operation. For example, Figure 4 As shown, the fourth metallization layer 216(4) in the circuit board 404 includes a fourth metal layer 218(4) including a first power plane 420(1) configured to be coupled to a ground signal connection for a power source. The first power plane 420(1) is configured to carry a power signal for the power source. Moreover, in this example, the fourth metallization layer 216(4) in the circuit board 404 includes an additional second power plane 420(2) that is also configured to be coupled to a power signal connection for the power source.

[0052] Moreover, if Figure 4As shown, capacitor 422 may provide capacitive decoupling or a filter for circuits in die 408. Capacitor 422 may provide a capacitor as part of a filter circuit for die 408. In this example, capacitor 422 provides decoupling capacitance to shunt noise from power and other circuits in die 408. Capacitor 422 has a first terminal 424(1) coupled to first power plane 420(1) and a second terminal 424(2) coupled to second power plane 420(2). First terminal 424(1) and second terminal 424(2) are electrically coupled to circuit board 404 and first metallization layer 216(1) via external interconnects 438 (e.g., solder balls, BGA interconnects). Metal lines in the third, fourth, fifth, and sixth metal layers 218(3)-218(6) of the third, fourth, fifth, and sixth metallization layers 216(3)-216(6) may route signals between the capacitor 422 and the first power plane 420(1) and the second power plane 420(2).

[0053] Capacitor 422 is coupled to circuit board 404 that is laterally offset from IC package 402 along a first vertical direction (Z-axis direction) such that capacitor 422 and IC package 402 do not share a common vertical plane along the first vertical direction (Y-axis direction and Z-axis direction). Therefore, the signal routing path to capacitor 422 involves horizontal routing in first power plane 420(1) and second power plane 420(2) that extends horizontally in their respective third metallization layer 216(3) and fourth metallization layer 216(4) along a second horizontal direction (X-axis direction and / or Y-axis direction) orthogonal to the first vertical direction (Z-axis direction), thereby increasing the signal routing path length between IC package 402 and capacitor 422. This increased signal routing path length to capacitor 422 means that capacitor 422 may have a greater interconnect inductance than first capacitor 122(1) because the increased signal routing distance may also result in increased interconnect inductance. However, by providing an additional metal plane 432 to provide the second power plane 420(2) with a reduced third distance D3 to the adjacent fourth metal layer 218(4) and its first power plane 420(1), the interconnect inductance for the capacitor 422 is reduced. For example, the interconnect inductance for the capacitor 422 may be reduced to sixteen (16.0) picohenries (pH) or less (e.g., 15.1 pH or 2.5 pH). This reduced interconnect inductance may mitigate or offset the increased inductance due to the increased signal routing path length between the IC package 402 and the capacitor 422. The interconnect inductance for the capacitor 422 is less than the interconnect inductance between the third metal layer 218(3) and the first power plane 420(1). The interconnect inductance between the third metal layer 218(3) and the first power plane 420(1) may exceed 170 pH (e.g., 176 pH). This is due to the increased height H3 of the fourth dielectric layer 230(4) and its dielectric material 234(4) between the third metal layer 218(3) and the first power plane 420(1) compared to the reduced third distance D3 between the first power plane 420(1) and the second power plane 420(2) coupled to the capacitor 422. This may, for example, allow the capacitor 422 to be coupled to the circuit board 204 that is laterally offset from the IC package 402 in the first vertical direction (Z-axis direction) and the second interconnect inductance of the second capacitor 222(2) to remain within acceptable or desired limits.

[0054] As another example, the third height H3 of the fourth dielectric layer 230(4) can be between fifty (50) μm and seventy (70) μm. The third distance D3 between the additional plane 432 in the fourth dielectric layer 230(4) providing the second power plane 420(2) and the adjacent fourth metal layer 418(4) can be between 1.0 μm and 5.0 μm. The ratio of the third height H3 of the fourth dielectric layer 230(4) to the third distance D3 between the additional metal plane 432 in the fourth dielectric layer 230(4) and the fourth metal layer 218(4) in the fourth metallization layer 216(4) can be at least 10.0. As another example, the ratio of the interconnection inductance between the third metal layer 218(3) and the first power plane 420(1) to the interconnection inductance between the first power plane 420(1) and the second power plane 420(2) can be at least ten (10.0). Note that the additional capacitor can be coupled to Figure 4 The circuit board 404 and its power planes 420(1)-420(3) in FIG.

[0055] Note that although Figure 4 The wiring substrate 406 in the electronic device 400 in FIG. 4 has an additional second metal plane 420(2) of increased thickness, which is also part of the third metal layer 218(3) in the third metallization layer 216(3), but this is not required. For example, the additional second metal plane 420(2) of increased thickness can be completely disposed outside the third metal layer 218(3) and completely disposed within the fourth dielectric layer 230(4) of the fourth metallization layer 216(4), similar to Figure 2A and Figure 2B 2. The second metal plane 220(2) in the electronic device 200 in FIG. 2 is preferably configured to provide a power plane connection between the capacitor 422 and the second metal plane 420(2) and the metal planes in either the adjacent third metal layer 218(3) or the fourth metal layer 218(4). However, in the case where the additional second metal plane 420(2) of increased thickness is disposed within the fourth dielectric layer 230(4) of the fourth metallization layer 216(4), the second metal plane 420(2) may be disposed to reduce the distance between the second metal plane 420(2) and both the adjacent third metal layer 218(3) and the fourth metal layer 218(4). Therefore, the power plane connection between the capacitor 422 and the second metal plane 420(2) and the metal planes in either the adjacent third metal layer 218(3) or the fourth metal layer 218(4) may still provide a reduced interconnect inductance.

[0056] Figure 5 5 is a side view of another exemplary electronic device 500 including an IC package 502 having a packaging substrate 504 as a wiring substrate 506, wherein the interconnect inductance between a capacitor 522 and a die 508 is reduced. As described in more detail below and as Figure 5As shown, capacitor 522 is coupled to a first metal plane 520(1) (also referred to as "first power plane 520(1)") disposed in a third metal layer 518(3) of a third metallization layer 516(3) of a packaging substrate 504 for a first power connection. The first power plane 520(1) is configured to carry a first power signal of a power source. Capacitor 522 is also coupled to an additional metal plane 532 (also referred to as "second power plane 520(2)") as an additional second metal plane 520(2), which is disposed in a fourth dielectric layer 530(4) of an adjacent fourth metallization layer 516(4) to reduce the thickness of a dielectric material 534(4) between the first power plane 520(1) and the additional second power plane 520(2) coupled to capacitor 522. The second power plane 520(2) is disposed in a fourth dielectric layer 530(4) of a fourth metallization layer 516(4) adjacent to the third metallization layer 516(3) and between the third metal layer 518(3) and the fourth metal layer 518(4) along a first vertical direction (Z-axis direction) orthogonal to the second horizontal direction (X-axis direction and / or Y-axis direction) of the metallization layers 516(1)-516(6), the second horizontal direction being orthogonal to the first vertical direction (Z-axis direction). The second power plane 520(2) is configured to carry a second power signal (or return signal) of the power source. This has the effect of reducing the interconnection inductance to the capacitor 522 because a fourth distance D4 between the first power plane 520(1) and the additional second power plane 520(2) is reduced compared to, for example, a fifth height H5 along the first vertical direction (Z-axis direction) between the first power plane 520(1) and the second power plane 520(2). In this way, when power signals are carried in the first power plane 520(1) and the additional second power plane 520(2), the magnetic flux loop generated between the first power plane 520(1) and the additional second power plane 520(2) is smaller than the magnetic flux loop between the first power plane 520(1) and the third metal plane 520(3) (also referred to as "third power plane 520(3)") in the adjacent fourth metal layer 518(4) of the fourth metallization layer 516(4).

[0057] In this example, providing an additional metal plane 532 as an additional second power plane 520(2) in the fourth metallization layer 516(4) reduces the thickness of the dielectric material 534(4) between the second power plane 520(2) and the first power plane 520(1), as indicated by the fourth distance D4. This may be particularly advantageous for capacitors 522 having horizontal wiring paths in the packaging substrate 504. Providing the additional metal plane 532 in the fourth metallization layer 516(4) also causes the additional metal plane 532 to be located at a fifth distance D5 from the fourth metal layer 518(4) in the fourth metallization layer 516(4) that is less than the fifth height H5 of the fourth dielectric layer 530(4). This is because the manufacturing of the packaging substrate 504 may impose or require a minimum distance between adjacent metallization layers 516(1)-516(6), which controls the minimum dielectric layer thickness between adjacent metallization layers 516(1)-516(6). Providing an additional second power plane 520(2) coupled to capacitor 522 to reduce the interconnect inductance to capacitor 522 may allow for greater flexibility in placing capacitor 522 on package substrate 504. For example, Figure 5 As shown, it may be easier to place and couple the capacitor 522 on the first top surface 536 ( 1 ) of the packaging substrate 504 than to couple the capacitor 522 on the second bottom surface 536 ( 1 ) of the packaging substrate 504 , which then requires horizontal signal routing to the capacitor 522 in the packaging substrate 504 .

[0058] refer to Figure 5 , the package substrate 504 includes a plurality of metallization layers 516(1)-516(6), each of which includes metal layers 518(1)-518(6), which may include metal lines to provide signal routing paths within the package substrate 504. Each metallization layer 516(1)-516(6) also has a corresponding dielectric layer 530(1)-530(6) of dielectric material adjacent to its corresponding metal layer 518(1)-518(6) to insulate the metal layers 518(1)-518(6) from each other. The metallization layers 516(1)-516(6) are parallel to each other along a first horizontal direction (X-axis direction and / or Y-axis direction). For example, an external interconnector 517 is coupled between the die 508 and the first metallization layer 516(1) of the package substrate 504 to electrically couple the die 508 to the package substrate 504. The packaging substrate 504 in this example includes power planes that are configured to be coupled to a power source as part of a power distribution network so that power can be tapped from these power planes to supply power to the packaging substrate 504 and the die 508(1) for operation. Figure 5As shown, the third metallization layer 516(3) in the package substrate 504 includes a third metal layer 518(3) including a first power plane 520(1) configured to be coupled to a ground connection for a power source. The fourth metallization layer 516(4) in the package substrate 504 includes a second power plane 520(2) provided by an additional metal plane 532 and configured to be coupled to a power signal connection for a power source. Also, in this example, the fourth metallization layer 516(4) in the circuit board 204 includes a fourth metal layer 518(4) including a third power plane 520(3) also configured to be coupled to a ground connection for a power source.

[0059] Moreover, if Figure 5 As shown, the die 508 is also coupled to a first power plane 520(1) and a second power plane 520(2) in the package substrate 504. Capacitor 522 can provide decoupling capacitance or a filter for the circuit in the die 508. Capacitor 522 can provide a capacitor as part of a filtering circuit for the die 508. In this example, capacitor 522 provides decoupling capacitance to shunt noise from power and other circuits in the die 508. Capacitor 522 has a first terminal 524(1) coupled to the first power plane 520(1) and a second terminal 524(2) coupled to an additional second power plane 520(2). In this example, for example, capacitor 522 can be a deep trench capacitor (DTC). Capacitor 522 and its first terminal 524(1) and second terminal 524(2) are electrically coupled to the package substrate 504 and the first metallization layer 516(1) through an external interconnect 538 (e.g., a solder ball, a BGA interconnect). Metal lines in the first, second, third, and fourth metal layers 518(1)-518(4) of the first, second, third, and fourth metallization layers 516(1)-516(4) may route signals between the capacitor 522 and the first power plane 520(1) and the second power plane 520(2).

[0060] Continue to refer Figure 5, capacitor 522 is coupled to the package substrate 504 that is laterally offset from the die 508 along a first vertical direction (Z-axis direction), so that the capacitor 522 and the die 508 do not share a common vertical plane along the first vertical direction (Y-axis direction and Z-axis direction). Therefore, the signal routing path to the capacitor 522 involves horizontal routing in the first power plane 520 (1) and the second power plane 520 (2), which horizontally extends along the second horizontal direction (X-axis direction and / or Y-axis direction) in their respective third metal layers 518 (3) and fourth metal layers 518 (4), thereby increasing the signal routing path length between the die 508 and the capacitor 522. This increased signal routing path length to the capacitor 522 means that the capacitor 522 can have a larger interconnect inductance, because the increased signal routing distance can also result in increased interconnect inductance.

[0061] By providing an additional metal plane 532 to provide the second power plane 520(2) with a reduced fourth distance D4 to the adjacent third metal layer 518(3) and its first power plane 520(1), the interconnect inductance for the capacitor 522 is also reduced. For example, the interconnect inductance for the capacitor 522 can be reduced to sixteen (16.0) picohenries (pH) or less (e.g., 15.1 pH or 2.5 pH). This reduced interconnect inductance can mitigate or offset the increased inductance due to the increased signal routing path length between the die 508 and the capacitor 522. The interconnect inductance for the capacitor 522 is less than the interconnect inductance between the second power plane 520(2) and the third power plane 520(3). The interconnect inductance between the second power plane 520(2) and the third power plane 520(3) can exceed 170 pH (e.g., 176 pH). This is due to the increased fifth height H5 of the fourth dielectric layer 530(4) and its dielectric material 534(4) between the second power plane 520(2) and the third power plane 520(3) compared to the reduced fourth distance D4 between the first power plane 520(1) and the second power plane 520(2) coupled to the capacitor 522. This may, for example, allow the capacitor 522 to be coupled to the packaging substrate 504 that is laterally offset from the die 508 along the first vertical direction (Z-axis direction) and the interconnect inductance of the capacitor 522 is still within acceptable limits or desired limits.

[0062] As another example, the fifth height H5 of the fourth dielectric layer 530(4) can be between fifty (50) μm and seventy (70) μm. A fourth distance D4 between the additional plane 532 in the fourth dielectric layer 530(4) providing the second power plane 520(2) and the third plane 518(3) in the adjacent third metallization layer 516(3) can be between 1.0 μm and 5.0 μm. A ratio of the fifth height H5 of the fourth dielectric layer 530(4) to the fourth distance D4 between the additional metal plane 532 in the fourth dielectric layer 530(4) and the third metal layer 518(3) in the third metallization layer 516(3) can be at least 10.0. As another example, a ratio of the interconnection inductance between the second power plane 520(2) and the third power plane 520(3) to the interconnection inductance between the first power plane 520(2) and the second power plane 520(4) can be at least ten (10.0).

[0063] A manufacturing process may be used to manufacture an electronic device and a wiring substrate thereof, wherein the wiring substrate includes a metal layer as a first power plane in a first metallization layer of a circuit board, and an additional metal plane as an additional power plane disposed in a dielectric layer of an adjacent second metallization layer, to reduce the thickness of a dielectric material between the first power plane and the additional power plane, thereby reducing interconnection inductance, including but not limited to Figures 2A to 5 In this regard, the electronic devices 200, 200(1)-200(3), 400, 500 and the wiring substrates 206, 406, 506. Figure 6 is a flow chart illustrating an exemplary manufacturing process 600 for manufacturing an electronic device including a wiring substrate, wherein the wiring substrate includes a metal layer as a first power plane in a first metallization layer of a circuit board, and an additional metal plane as an additional power plane disposed in a dielectric layer of an adjacent second metallization layer to reduce a thickness of a dielectric material between the first power plane and the additional power plane, thereby reducing interconnect inductance, including but not limited to Figures 2A to 5 The electronic devices 200, 200(1)-200(3), 400, 500 and the wiring substrates 206, 406, 506 are described. Figure 6 The manufacturing process in 600 Figure 2A and Figure 2B The electronic device 200 and the wiring substrate 206 in FIG. 7 are discussed, but it should be noted that the manufacturing process 700 is not limited to manufacturing Figure 2A and Figure 2B The electronic device 200 and the wiring substrate 206 are shown in FIG.

[0064] In this regard, if Figure 6As shown, in this example, the first step in the manufacturing process 600 of manufacturing the electronic device 200 may include forming a wiring substrate 206, which includes a plurality of metallization layers 216 (1)-216 (6) ( Figure 6 6. The next step in forming the wiring substrate 206 in the manufacturing process 600 may include forming the first metallization layer as the fourth metallization layer 216(4) ( Figure 6 6. Forming fourth metallization layer 216(4) may include forming a first metal layer as fourth metal layer 220(4) including third metal plane 218(3) and forming a first dielectric layer as fourth dielectric layer 218(4) adjacent to fourth metal layer 230(4). The next step in forming wiring substrate 206 in manufacturing process 600 may include forming a second metallization layer as third metallization layer 216(3) ( Figure 6 Forming third metallization layer 216(3) may include forming the second metal layer as third metal layer 218(3) and forming the second dielectric layer as third dielectric layer 230(3) adjacent to third metal layer 218(3). First metal plane 220(1) may be formed in third metallization layer 216(3). The next step in forming wiring substrate 206 in manufacturing process 600 may include forming second metal plane 220(2) in fourth dielectric layer 230(4) of fourth metallization layer 216(4) ( Figure 6 The next step in forming wiring substrate 206 in manufacturing process 600 may include coupling third metallization layer 216(3) to fourth metallization layer 216(4) such that second metal plane 220(2) is located between fourth metal layer 218(4) in fourth metallization layer 216(4) and third metal layer 218(3) in third metallization layer 216(3) ( Figure 6 The next step in the manufacturing process 600 for manufacturing the electronic device 200 may include coupling the second capacitor 222(2) to the wiring substrate 206( Figure 6 6. Coupling second capacitor 222(2) may include coupling second capacitor 222(2) to one of first metal plane 220(3) and first metal plane 220(1) and coupling second capacitor 222(2) to second metal plane 220(2). A next step in manufacturing process 600 of manufacturing electronic device 200 may include coupling first die 208(1) and second die 208(2) to first metal plane 220(3) and second metal plane 220(4) ( Figure 6 614 in FIG.

[0065] Other manufacturing processes may be used to manufacture electronic devices and wiring substrates thereof, wherein the wiring substrate includes a metal layer as a first power plane in a first metallization layer of a circuit board, and an additional metal plane as an additional second power plane disposed in a dielectric layer of an adjacent second metallization layer, to reduce the thickness of the dielectric material between the first power plane and the additional power plane, thereby reducing the interconnection inductance, including but not limited to Figures 2A to 5 The electronic devices 200, 200(1)-200(3), 400, 500 and the wiring substrates 206, 406, 506 are described.

[0066] In this regard, 7A to 7C is a flow chart illustrating another exemplary manufacturing process 700 of a wiring substrate for an electronic device, wherein the wiring substrate includes a metal layer as a first power plane in a first metallization layer of a circuit board, and an additional metal plane as an additional second power plane disposed in a dielectric layer adjacent to a second metallization layer, to reduce the thickness of a dielectric material between the first power plane and the additional second power plane, thereby reducing interconnection inductance, including but not limited to Figures 2A to 5 The electronic devices 200, 200(1)-200(3), 400, 500 and the wiring substrates 206, 406, 506 are described. FIG. 8A to FIG. 8F is based on 7A to 7C Exemplary manufacturing stages 800A-800F during manufacturing of a wiring substrate in the manufacturing process 700 of FIG. 7A to 7C In the manufacturing process 700, an additional metal plane with a reduced distance to an adjacent metallization layer is formed in an upper portion of the dielectric layer so as to be closer to the adjacent metal layer above the additional metal plane in the vertical direction (Z-axis direction).

[0067] In this regard, if Fig. 8A As shown in manufacturing stage 800A in FIG. 7 , the first step in manufacturing process 700 is to form a core substrate 802 and a first metal layer 804(1) and a second metal layer 804(2) (e.g., a copper layer) located on respective outer surfaces 806(1) and 806(2) of the core substrate 802. Fig. 7A In this example, the wiring substrate to be formed includes a core substrate 802 as an inner layer. Fig. 8A800A, openings 808(1), 808(2) are formed in respective metal layers 804(1), 804(2) to form separate metal layers 810(1)-810(6). The first metal layer 804(1) and the second metal layer 804(2) will serve as metal layers for additional metallization layers to be formed. The metal planes 810(1), 810(4) are coupled to each other through first metal vias 812(1) formed in the core substrate 802. The metal planes 810(3), 810(6) are coupled to each other through second metal vias 812(2) formed in the core substrate 802.

[0068] Then, if Figure 8B As shown in manufacturing stage 800B in FIG. 7 , the next step in manufacturing process 700 is to form a first dielectric layer 814(1) and a second dielectric layer 814(2) of dielectric material on the corresponding first metal layer 804(1) and the second metal layer 804(2) to insulate the corresponding metal planes 810(1)-810(6) formed on the outer surfaces 806(1), 806(2) of the core substrate 802. Fig. 7A For example, the first dielectric layer 814(1) and the second dielectric layer 814(2) may be laminated onto the metal layers 804(1), 804(2). Then, as shown in FIG. Figure 8B As shown in the manufacturing stage 800B in FIG. 1 , a third metal layer 804(3) and a fourth metal layer 804(4) (e.g., a copper layer) are then formed on the outer surfaces 816(1) and 816(2) of the first dielectric layer 814(1) and the second dielectric layer 814(2). Fig. 7A 704 in FIG.

[0069] Then, if Figure 8C As shown in manufacturing stage 800C in FIG. 7 , the next step in manufacturing process 700 is to pattern and remove portions of fourth metal layer 804 ( 4 ) to form an additional metal plate 810 ( 7 ) as a ground plane in this example ( Fig. 7A 7). In this example, metal plane 810(7) is an additional metal plane that will be disposed in a subsequently formed dielectric layer to provide a power plane having a reduced distance to an adjacent metal plane to be formed on the dielectric layer to reduce interconnect inductance to additional metal plane 810(7). In this regard, Fig.8D As shown in manufacturing stage 800D in FIG. 1 , the next step is to form a third dielectric layer 814 ( 3 ) on the additional metal plane 814 ( 7 ) and the second dielectric layer 810 ( 2 ), and to form a fifth dielectric layer 804 ( 5 ) on the third dielectric layer 814 ( 3 ) ( Figure 7B 708 in FIG. Fig.8DAs shown, the distance D6 between the fifth metal layer 804(5) and the metal plane 810(5) is less than the height H6 of the second dielectric layer 814(2) and the third dielectric layer 814(3) between the second metal layer 804(2) and the fifth metal layer 804(5). Therefore, if a component such as a capacitor is coupled to the additional metal plane 810(7) and the metal plane formed in the fifth metal layer 804(5) as a power plane, the interconnect inductance resulting from such a connection will be less than if the component is coupled to the metal plane formed in the fifth metal layer 804(5) and the metal planes 804(4)-810(6) in the second metal layer 810(2) as a power plane.

[0070] Then, if Fig. 8E As shown in manufacturing stage 800E in FIG. 7 , the next step in manufacturing process 700 is to pattern the third metal layer 804(3) and the fifth metal layer 804(5) to form metal vias 812(3)-812(4) and metal vias 812(5)-812(6) ( Figure 7B 710 in FIG. 710). Also as shown in FIG. Fig. 8E As shown in manufacturing stage 800E in FIG. 1 , the respective third metal layer 804(3) and fourth metal layer 804(4) are patterned, and metal lines or metal layers 810(8)-810(13) are formed in the third metal layer 804(3) and fourth metal layer 804(4). Metal planes 810(8), 810(10) are formed to contact metal vias 812(3), 812(4). Metal planes 810(11), 810(13) are formed to contact metal vias 812(5), 812(6). Then, as shown in FIG. Figure 8F As shown in manufacturing stage 800F in FIG. 7 , the next step in manufacturing process 700 is to form additional dielectric layers 814(4), 814(5) on the respective third metal layer 810(3) and fourth metal layer 804(4) to insulate the metal layers 804(8)-810(13) ( Figure 7C 712 in FIG. 1 ). Also as shown in FIG. Figure 8F As shown in manufacturing stage 800F in FIG. 1 , additional dielectric layers 814(4), 814(5) are patterned and openings are formed therein to form metal vias 812(7), 812(8) ( coupled to corresponding metal planes 810(9), 810(11) Figure 7C 712 in the figure). Additional metal layers 804(6), 804(7) are then formed on the additional dielectric layers 804(4), 814(5) and patterned to form additional metal planes 810(14)-810(19) in the respective metal layers 814(6), 804(7) ( Figure 7C810(15), 810(18) are coupled to respective metal vias 812(7), 812(8) to couple the metal planes 810(15), 810(18) to respective metal planes 810(7), 810(12).

[0071] 9A to 9C is a flow chart illustrating another exemplary manufacturing process 900 of a wiring substrate for an electronic device, wherein the wiring substrate includes a metal layer as a first power plane in a first metallization layer of a circuit board, and an additional metal plane as an additional second power plane disposed in a dielectric layer adjacent to a second metallization layer to reduce the thickness of a dielectric material between the first power plane and the second power plane, thereby reducing interconnect inductance, including but not limited to Figures 2A to 5 The electronic devices 200, 200(1)-200(3), 400, 500 and the wiring substrates 206, 406, 506 are described. FIG. 10A to FIG. 10F is based on 9A to 9C Exemplary manufacturing stages 1000A-1000F during manufacturing of a wiring substrate in the manufacturing process 900 of FIG. 9A to 9C In the manufacturing process 900, an additional metal plane with a reduced distance to an adjacent metallization layer is formed in a lower portion of the dielectric layer so as to be closer to the adjacent metal layer below the additional metal plane in the vertical direction (Z-axis direction).

[0072] In this regard, if Fig. 10A As shown in manufacturing stage 1000A in FIG. 1 , the first step in manufacturing process 900 is to form a core substrate 1002 and a first metal layer 1004(1) and a second metal layer 1004(2) (e.g., a copper layer) located on respective outer surfaces 1006(1) and 1006(2) of the core substrate 1002. Fig.9A In this example, the wiring substrate to be formed includes a core substrate 1002 as an inner layer. Fig. 10A As shown in manufacturing stage 1000A in FIG. 1 , openings 1008(1), 1008(2) are formed in respective first metal layer 1004(1) and second metal layer 1004(2) to form separate metal layers 1010(1)-1010(6). First metal layer 1004(1) and second metal layer 1004(2) will serve as metal layers for additional metallization layers to be formed. Metal planes 1010(1), 1010(4) are coupled to each other through first metal vias 1012(1) formed in core substrate 1002. Metal planes 1010(3), 1010(6) are coupled to each other through second metal vias 1012(2) formed in core substrate 1002.

[0073] Then, if Fig. 10BAs shown in manufacturing stage 1000B in FIG. 1 , the next step in manufacturing process 900 is to form a thin resin as a first dielectric layer 1014(1) on the second metal layer 1004(2) and to form a third metal layer 1014(3) on the first dielectric layer 1004(1) ( Fig.9A 904 in block 904). First dielectric layer 1014(1) is used to provide an additional metal plane formed in third metal layer 1004(3) with a reduced distance to second metal layer 1004(2) such that components coupled to the additional metal plane formed in third metal layer 1004(3) have reduced interconnect inductance. In this regard, as Fig. 10C As shown in manufacturing stage 1000C in FIG. 1 , the next step in manufacturing process 900 is to pattern and remove portions of third metal layer 1004 ( 3 ) to form an additional metal plate 1010 ( 7 ) as a ground plane in this example ( Fig.9A 906 in ). In this example, metal plane 1010(7) is an additional metal plane that will be disposed in a subsequently formed dielectric layer to provide a power plane having a reduced distance to an adjacent metal plane to be formed on the dielectric layer to reduce interconnect inductance to additional metal plane 1010(7).

[0074] Then, if Fig. 10D As shown in manufacturing stage 1000D in the manufacturing process 900, the next step in the manufacturing process 900 is to form a second dielectric layer 1014(2) and a third dielectric layer 1014(3) on the corresponding first metal layer 1014(1) and the first dielectric layer 1014(1), and then form an additional fourth metal layer 1004(4) and a fifth metal layer 1004(5) on the corresponding second dielectric layer 1004(2) and the third dielectric layer 1014(3) ( Fig. 9B 908 in FIG. 1 ). Second dielectric layer 1014(2) and third dielectric layer 1014(3) insulate first metal layer 1004(1) and second metal layer 1004(2) from fourth metal layer 1004(4) and fifth metal layer 1004(5). Fig. 10D As shown, the distance D7 between the second metal layer 1004(2) and the additional metal plane 1010(7) is less than the height H7 of the third dielectric layer 1014(3) between the second metal layer 1004(2) and the fifth metal layer 1004(5). Therefore, if a component such as a capacitor is coupled to the additional metal plane 1010(7) and the metal plane formed in the second metal layer 1004(4) as a power plane, the interconnection inductance resulting from such a connection will be less than if the component is coupled to the metal plane formed in the second metal layer 1004(2) and the metal plane in the fifth metal layer 1004(5) as a power plane.

[0075] Then, if Fig.10E As shown in manufacturing stage 1000E in FIG. 9 , the next step in manufacturing process 900 is to pattern fourth metal layer 1004(4) and fifth metal layer 1004(5) to form metal vias 1012(3)-1012(4) coupled to respective metal planes 1010(1), 1010(3) and metal vias 1012(5)-1012(6) coupled to metal planes 1010(4), 1010(6) ( Fig. 9B 910 in FIG. 1 ). Also as shown in FIG. Fig.10E As shown in manufacturing stage 1000E in FIG. 1 , the respective fourth metal layer 1004(4) and fifth metal layer 1004(5) are patterned, and metal lines or metal layers 1010(8)-1010(13) are formed. Metal planes 1010(8), 1010(10) are formed to contact metal vias 1012(3), 1012(4). Metal planes 1010(11), 1010(13) are formed to contact metal vias 1012(5), 1012(6). Then, as shown in FIG. Fig.10F As shown in manufacturing stage 1000F in FIG. 1 , the next step in manufacturing process 900 is to form additional dielectric layers 1014(4), 1014(5) on the respective fourth metal layer 1004(4) and fifth metal layer 1004(5) to insulate metal layers 1010(8)-1010(13) ( Fig. 9C In this example, also as shown in box 912. Fig.10F As shown in manufacturing stage 1000F in FIG. 1 , additional dielectric layer 1014(4) is patterned and openings are formed therein to form metal vias 1012(7), 1012(8) ( Fig. 9C 912 in the process). Additional metal layers 1004(6), 1004(7) are then formed on the respective additional dielectric layers 1004(4), 1014(5) and patterned to form additional metal planes 810(14)-812(19) in the respective metal layers 1014(6), 1004(7) ( Fig. 9C 9). Metal planes 1010(14), 1010(15) are coupled to respective metal vias 1012(7), 1012(8) to couple metal planes 1010(14), 1010(15) to respective metal planes 1010(8), 1010(9).

[0076] It is noted that the term "metal plane" refers to a metal structure that can be arranged in a plane along two or more directional axes. The term "power plane" is a metal plane configured to be coupled to a power source to conduct power signals. The terms "top" and "bottom" are relative terms and are not necessarily limited to components described as "top" or "bottom" components being above or below another component relative to the ground / ground. It is also noted that components described herein as "disposed in..." (such as disposed in a layer, packaging substrate, or circuit board) are not limited to such components being completely disposed in such layer, packaging substrate, or circuit board. It is also noted that the term "external" used with reference to a particular component or structure (including but not limited to a packaging substrate, circuit board, die, and capacitor) is a component that is fully or partially exposed from the outer surface of such a component or structure.

[0077] An electronic device including a wiring substrate includes a metal layer as a first power plane in a first metallization layer of a circuit board and an additional metal plane as an additional second power plane disposed in a dielectric layer of an adjacent second metallization layer to reduce a thickness of a dielectric material between the first power plane and the second power plane, thereby reducing interconnection inductance, including but not limited to Figures 2A to 5 , FIG. 8A to FIG. 8F and FIG. 10A to FIG. 10F The electronic device 200, 200(1)-200(3), 400, 500 and the wiring substrate 206, 406, 506 in the embodiment of the present invention are based on but not limited to Figures 6 to 8C and 9A to 9C Any of the exemplary manufacturing processes in the exemplary manufacturing process of and according to any aspect disclosed herein can be set in or integrated into any processor-based device. Non-limiting examples include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, global positioning system (GPS) devices, mobile phones, cellular phones, smart phones, session initiation protocol (SIP) phones, tablets, tablet phones, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smart watches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, motor vehicles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0078] Fig.11An exemplary wireless communication device 1100 including a radio frequency (RF) component formed of one or more ICs 1102 is illustrated, wherein any of the ICs 1102 may be included in an electronic device 1103. The electronic device 1103 may include a wiring substrate including a metal layer as a first power plane in a first metallization layer of a circuit board and an additional metal plane as an additional second power plane disposed in a dielectric layer adjacent to the second metallization layer to reduce a thickness of a dielectric material between the first power plane and the second power plane, thereby reducing interconnect inductance, including but not limited to Figures 2A to 5 , FIG. 8A to FIG. 8F and FIG. 10A to FIG. 10F The electronic device 200, 200(1)-200(3), 400, 500 and the wiring substrate 206, 406, 506 in the embodiment of the present invention are based on but not limited to Figures 6 to 8C and 9A to 9C Any exemplary manufacturing process in the exemplary manufacturing process of, and according to any aspect disclosed herein. As an example, the wireless communication device 1100 may include or be arranged in any of the devices mentioned above. Fig.11 As shown, the wireless communication device 1100 includes a transceiver 1104 and a data processor 1106. The data processor 1106 may include a memory for storing data and program codes. The transceiver 1104 includes a transmitter 1108 and a receiver 1110 that support two-way communication. In general, the wireless communication device 1100 may include any number of transmitters 1108 and / or receivers 1110 for any number of communication systems and frequency bands. All or part of the transceiver 1104 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed signal ICs, etc.

[0079] The transmitter 1108 or the receiver 1110 may be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is converted between RF and baseband in multiple stages, such as from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage for the receiver 1110. In a direct conversion architecture, the signal is converted between RF and baseband in one stage. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements. Fig.11 In the wireless communication device 1100 in FIG. 1 , the transmitter 1108 and the receiver 1110 are implemented using a direct conversion architecture.

[0080] In the transmit path, the data processor 1106 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 1108. In the exemplary wireless communication device 1100, the data processor 1106 includes digital-to-analog converters (DACs) 1111(1), 1112(2) to convert the digital signals generated by the data processor 1106 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0081] Within transmitter 1108, low pass filters 1114(1), 1114(2), respectively, filter the I and Q analog output signals to remove undesired signals caused by the preceding digital-to-analog conversion. Amplifiers (AMPs) 1116(1), 1116(2) respectively amplify the signals from low pass filters 1114(1), 1114(2) and provide I and Q baseband signals. Up converter 1118 upconverts the I and Q baseband signals via mixers 1120(1), 1120(2) using I and Q TX LO signals from a transmit (TX) local oscillator (LO) signal generator 1122 to provide upconverted signals 1124. Filter 1126 filters the upconverted signals 1124 to remove undesired signals caused by the upconversion and noise in the receive band. A power amplifier (PA) 1128 amplifies the upconverted signal 1124 from the filter 1126 to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch 1130 and transmitted via an antenna 1132.

[0082] In the receive path, antenna 1132 receives the signal transmitted by the base station and provides a received RF signal, which is routed through a duplexer or switch 1130 and provided to a low noise amplifier (LNA) 1134. The duplexer or switch 1130 is designed to operate with a specific receive (RX) and TX duplexer frequency separation so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1134 and filtered by filter 1136 to obtain the desired RF input signal. Down-conversion mixers 1138 (1), 1138 (2) mix the output of filter 1136 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1140 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1142(1), 1142(2) and further filtered by low pass filters 1144(1), 1144(2) to obtain I and Q analog input signals, which are provided to the data processor 1106. In this example, the data processor 1106 includes analog-to-digital converters (ADCs) 1146(1), 1146(2) to convert the analog input signals into digital signals to be further processed by the data processor 1106.

[0083] exist Fig.11 In the wireless communication device 1100 of the embodiment of the present invention, the TX LO signal generator 1122 generates I and Q TX LO signals for up-conversion, and the RX LO signal generator 1140 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 1148 receives timing information from the data processor 1106 and generates a control signal for adjusting the frequency and / or phase of the TX LO signal from the TX LO signal generator 1122. Similarly, the RX PLL circuit 1150 receives timing information from the data processor 1106 and generates a control signal for adjusting the frequency and / or phase of the RX LO signal from the RX LO signal generator 1140.

[0084] In this regard, Fig.12 An example of a processor-based system 1200 is illustrated, the system including circuitry that may be provided in one or more electronic devices 1202(1)-1202(7). The electronic devices 1202(1)-1202(7) may include a wiring substrate including a metal layer as a first power plane in a first metallization layer of a circuit board and an additional metal plane as an additional second power plane disposed in a dielectric layer adjacent to a second metallization layer to reduce a thickness of a dielectric material between the first power plane and the second power plane, thereby reducing interconnect inductance, including but not limited to Figures 2A to 5 , FIG. 8A to FIG. 8Fand FIG. 10A to FIG. 10F The electronic device 200, 200(1)-200(3), 400, 500 and the wiring substrate 206, 406, 506 in the embodiment of the present invention are based on but not limited to Figures 6 to 8C and 9A to 9C , and according to any aspect disclosed herein. In this example, the processor-based system 1200 may be formed as an IC 1204 in an electronic device 1202 and as a system on a chip (SoC) 1206. The processor-based system 1200 includes a central processing unit (CPU) 1208, which includes one or more processors 1210, which may also be referred to as CPU cores or processor cores. The CPU 1208 may have a cache memory 1212 coupled to the CPU 1208 for fast access to temporarily stored data. The CPU 1208 is coupled to a system bus 1214, and may couple master devices and slave devices included in the processor-based system 1200 to each other. As is well known, the CPU 1208 communicates with these other devices by exchanging address, control, and data information on the system bus 1214. For example, the CPU 1208 may communicate a bus transaction request to a memory controller 1216, which is an example of a slave device. Although in Fig.12 Although not illustrated in the figure, multiple system buses 1214 may be provided, each of which constitutes a different structure.

[0085] Other master devices and slave devices may be connected to the system bus 1214. Fig.12As illustrated, these devices may include, by way of example, a memory system 1220 (which includes a memory controller 1216 and a memory array 1218), one or more input devices 1222, one or more output devices 1224, one or more network interface devices 1226, and one or more display controllers 1228. Each of the memory system 1220, one or more input devices 1222, one or more output devices 1224, one or more network interface devices 1226, and one or more display controllers 1228 may be provided in the same or different electronic devices 1202(2)-1202(7). The input devices 1222 may include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output devices 1224 may include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device 1226 may be any device configured to allow data exchange to and from the network 1230. The network 1230 can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a Bluetooth TM Networks and the Internet. The network interface device 1226 may be configured to support any type of communication protocol desired.

[0086] The CPU 1208 may also be configured to access a display controller 1228 via the system bus 1214 to control information transmitted to one or more displays 1232. The display controller 1228 transmits information to be displayed to the display 1232 via one or more video processors 1234, which processes the information to be displayed into a format suitable for the display 1232. As an example, the display controller 1228 and the video processor 1234 may be included as ICs in the same or different electronic devices 1202(2), 1202(3), and in the same or different electronic device 1202 that includes the CPU 1208. The display 1232 may include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

[0087] Those skilled in the art will further appreciate that the various exemplary logic blocks, modules, circuits and algorithms described in conjunction with the various aspects disclosed herein may be implemented as electronic hardware, stored in a memory or in another computer-readable medium and executed by a processor or other processing device, or a combination of the two. The memory disclosed herein may be a memory of any type and size, and may be configured to store any type of information desired. In order to clearly illustrate this interchangeability, the functionality of various exemplary components, blocks, modules, circuits and steps has been generally described above. How such functionality is implemented depends on specific applications, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as causing departure from the scope of the present disclosure.

[0088] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or executed with a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic components, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0089] The various aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from and write information to the storage medium. In an alternative, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0090] It is also noted that the operation steps described in any of the exemplary aspects of this paper are described in order to provide examples and discussions. The described operations can be performed in many different orders except for the illustrated order. In addition, the operations described in a single operation step can actually be performed in a plurality of different steps. In addition, one or more operation steps discussed in the exemplary aspects can be combined. It will be understood that, as will be apparent to those skilled in the art, many different modifications can be made to the operation steps illustrated in the flow chart. It will be equally understood by those skilled in the art that any of a variety of different technologies and techniques can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0091] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

[0092] Specific implementation examples are described in the following numbered clauses:

[0093] 1. An electronic device, comprising:

[0094] A wiring substrate, the wiring substrate comprising a plurality of metallization layers parallel to each other along a first direction, the plurality of metallization layers comprising:

[0095] A first metallization layer, the first metallization layer comprising:

[0096] a first metal layer, the first metal layer comprising a first metal plane;

[0097] and

[0098] a first dielectric layer, the first dielectric layer being adjacent to the first metal layer;

[0099] A second metallization layer, the second metallization layer is adjacent to the first metallization layer, and the second metallization layer comprises:

[0100] a second metal layer; and

[0101] a second dielectric layer, the second dielectric layer being adjacent to the second metal layer; and

[0102] a second metal plane disposed in the first dielectric layer along the first direction between the first metal layer and the second metal layer; and

[0103] A capacitor is coupled to the first metal plane and the second metal plane.

[0104] 2. An electronic device according to clause 1, wherein:

[0105] The first metal plane and the second metal layer are configured to generate a first interconnect inductance in response to a voltage difference between the first metal plane and the second metal layer; and

[0106] The first metal plane and the second metal plane are configured to generate a second interconnect inductance that is less than the first interconnect inductance in response to a voltage difference between the first metal plane and the second metal plane.

[0107] 3. The electronic device of clause 2, wherein a ratio of the first interconnect inductance to the second interconnect inductance is at least 10.0.

[0108] 4. The electronic device of any of clauses 1 to 3, wherein the second metal plane is coupled to a third metal plane in the second metal layer.

[0109] 5. An electronic device according to clause 4, wherein:

[0110] The first metal plane is configured to be coupled to a first power signal of a power source to carry the first power signal; and

[0111] The second metal plane is configured to be coupled to a second power signal of the power source to carry the second power signal.

[0112] 6. An electronic device according to any one of clauses 1 to 5, wherein:

[0113] The first dielectric layer between the first metal layer and the second metal layer has a first height along a second direction orthogonal to the first direction; and

[0114] The second metal plane is arranged at a first distance from the second metal layer along the second direction,

[0115] The first distance is smaller than the first height.

[0116] 7. The electronic device according to clause 6, wherein the second metal plane is disposed at a second distance from the first metal layer along the second direction,

[0117] The first distance is smaller than the second distance.

[0118] 8. An electronic device according to clause 6 or 7, wherein:

[0119] The first height is between fifty (50) micrometers (μm) and seventy (70) μm; and

[0120] The first distance is between 1.0 μm and 5.0 μm.

[0121] 9. An electronic device as described in any of clauses 6 to 8, wherein a ratio between the first height and the first distance is at least 10.0.

[0122] 10. An electronic device according to any one of clauses 1 to 5, wherein:

[0123] The first dielectric layer between the first metal layer and the second metal layer has a first height; and

[0124] The second metal plane is disposed at a first distance from the first metal layer, and the first distance is smaller than the first height.

[0125] 11. The electronic device according to clause 10, wherein the second metal plane is disposed at a second distance from the second metal layer along a second direction orthogonal to the first direction,

[0126] The first distance is smaller than the second distance.

[0127] 12. An electronic device according to clause 10 or 11, wherein:

[0128] The first height is between fifty (50) micrometers (μm) and seventy (70) μm; and

[0129] The first distance is between 1.0 μm and 5.0 μm.

[0130] 13. An electronic device as recited in any one of clauses 10 to 12, wherein a ratio between the first height and the first distance is at least 10.0.

[0131] 14. The electronic device according to any one of clauses 1 to 13, further comprising: an IC package;

[0132] in:

[0133] The wiring substrate includes a circuit board;

[0134] The IC package is coupled to the circuit board; and

[0135] The IC package includes a package substrate including a first metal line coupled to the first metal plane and a second metal line coupled to the second metal plane; and

[0136] The IC package also includes a die coupled to the first metal line and the second metal line.

[0137] 15. An electronic device according to clause 14, wherein:

[0138] The plurality of metallization layers are disposed in a first plane; and

[0139] The packaging substrate and the capacitor do not share a common second plane that is orthogonal to the first plane.

[0140] 16. An electronic device according to any one of clauses 1 to 13, comprising an IC package, the IC package comprising:

[0141] a packaging substrate, the packaging substrate including the wiring substrate; and

[0142] A die is electrically coupled to the first metal plane and the second metal plane of the packaging substrate.

[0143] 17. An electronic device according to clause 16, wherein:

[0144] The plurality of metallization layers are disposed in a first plane; and

[0145] The die and the capacitor do not share a common second plane orthogonal to the first plane.

[0146] 18. An electronic device as described in any of clauses 1 to 17, wherein the capacitor comprises a deep trench capacitor (DTC).

[0147] 19. An electronic device according to any one of clauses 1 to 18, wherein:

[0148] The plurality of metallization layers are disposed in a first plane; and

[0149] The electronic device further comprises:

[0150] a second capacitor coupled to the wiring substrate;

[0151] a die electrically coupled to the first metal plane and the second metal plane of the wiring substrate; and

[0152] The die and the second capacitor share a common second plane that is orthogonal to the first plane.

[0153] 20. An electronic device according to any of clauses 1 to 19, wherein the IC package is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet computer; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD)

[0154] players; portable digital video players; automobiles; vehicle components; avionics systems; drones; and multirotors.

[0155] 21. A method of manufacturing an electronic device, the method comprising:

[0156] A wiring substrate is formed, wherein the wiring substrate includes a plurality of

[0157] metallization layers, including:

[0158] Forming a first metallization layer, the forming of the first metallization layer comprising:

[0159] forming a first metal layer, the first metal layer comprising a first metal plane; and

[0160] forming a first dielectric layer, the first dielectric layer being adjacent to the first metal layer;

[0161] Forming a second metallization layer, the forming the second metallization layer comprising:

[0162] forming a second metal layer; and

[0163] forming a second dielectric layer, the second dielectric layer being adjacent to the second metal layer;

[0164] forming a second metal plane in the first dielectric layer of the first metallization layer; and

[0165] coupling the second metallization layer to the first metallization layer such that the second metal plane is located between the first metal layer and the second metal layer along a second direction orthogonal to the first direction; and

[0166] Coupling a capacitor to the wiring substrate includes:

[0167] The capacitor is coupled to the first metal plane and the second metal plane.

[0168] 22. The method of clause 21, further comprising coupling the second metal plane to a third metal plane in the second metal layer.

[0169] 23. A method according to clause 21 or 22, wherein:

[0170] The first dielectric layer between the first metal layer and the second metal layer has a first height along the second direction; and

[0171] Forming the second metal plane further comprises forming the second metal plane at a first distance from the second metal layer along the second direction, and

[0172] The first distance is smaller than the first height.

[0173] 24. The method of clause 23, wherein forming the second metal plane further comprises forming the second metal plane a second distance from the first metal layer along the second direction, and

[0174] The first distance is smaller than the second distance.

[0175] 25. A method according to clause 21 or 22, wherein:

[0176] The first dielectric layer between the first metal layer and the second metal layer has a first height; and

[0177] Forming the second metal plane also includes forming the second metal plane a first distance from the first metal layer, and

[0178] The first distance is smaller than the first height.

[0179] 26. The method of clause 25, wherein forming the second metal plane further comprises forming the second metal plane a second distance from the second metal layer along the second direction, and

[0180] The first distance is smaller than the second distance.

[0181] 27. The method of any of clauses 21 to 26, further comprising coupling a die to the first metal plane and the second metal plane.

[0182] 28. A method according to clause 27, wherein:

[0183] The plurality of metallization layers are disposed in a first plane; and

[0184] The die and the capacitor do not share a common second plane orthogonal to the first plane.

Claims

1. An electronic device, comprising: A wiring substrate, the wiring substrate comprising a plurality of metallization layers parallel to each other along a first direction, the plurality of metallization layers comprising: A first metallization layer, the first metallization layer comprising: a first metal layer, the first metal layer comprising a first metal plane; and a first dielectric layer, the first dielectric layer being adjacent to the first metal layer; A second metallization layer, the second metallization layer is adjacent to the first metallization layer, and the second metallization layer comprises: a second metal layer; and a second dielectric layer, the second dielectric layer being adjacent to the second metal layer; and a second metal plane disposed in the first dielectric layer along the first direction between the first metal layer and the second metal layer; and A capacitor is coupled to the first metal plane and the second metal plane.

2. The electronic device according to claim 1, wherein: The first metal plane and the second metal layer are configured to generate a first interconnect inductance in response to a voltage difference between the first metal plane and the second metal layer; and The first metal plane and the second metal plane are configured to generate a second interconnect inductance that is less than the first interconnect inductance in response to a voltage difference between the first metal plane and the second metal plane. 3 . The electronic device of claim 2 , wherein a ratio of the first interconnect inductance to the second interconnect inductance is at least 10.

0. 4 . The electronic device of claim 1 , wherein the second metal plane is coupled to a third metal plane in the second metal layer.

5. The electronic device according to claim 4, wherein: The first metal plane is configured to be coupled to a first power signal of a power source to carry the first power signal; and The second metal plane is configured to be coupled to a second power signal of the power source to carry the second power signal.

6. The electronic device according to claim 1, wherein: The first dielectric layer between the first metal layer and the second metal layer has a first height along a second direction orthogonal to the first direction; and The second metal plane is arranged at a first distance from the second metal layer along the second direction, The first distance is smaller than the first height.

7. The electronic device according to claim 6, wherein the second metal plane is arranged at a second distance from the first metal layer along the second direction, The first distance is smaller than the second distance.

8. The electronic device according to claim 6, wherein: The first height is between fifty (50) micrometers (μm) and seventy (70) μm; and The first distance is between 1.0 μm and 5.0 μm. 9 . The electronic device of claim 6 , wherein a ratio between the first height and the first distance is at least 10.

0.

10. The electronic device according to claim 1, wherein: The first dielectric layer between the first metal layer and the second metal layer has a first height; and The second metal plane is disposed at a first distance from the first metal layer, and the first distance is smaller than the first height.

11. The electronic device according to claim 10, wherein the second metal plane is arranged at a second distance from the second metal layer along a second direction orthogonal to the first direction, The first distance is smaller than the second distance.

12. The electronic device according to claim 10, wherein: The first height is between fifty (50) micrometers (μm) and seventy (70) μm; and The first distance is between 1.0 μm and 5.0 μm.

13. The electronic device of claim 10, wherein a ratio between the first height and the first distance is at least 10.

0.

14. The electronic device according to claim 1, further comprising: IC packages; in: The wiring substrate includes a circuit board; The IC package is coupled to the circuit board; and The IC package includes a package substrate including a first metal line coupled to the first metal plane and a second metal line coupled to the second metal plane; and The IC package also includes a die coupled to the first metal line and the second metal line.

15. The electronic device according to claim 14, wherein: The plurality of metallization layers are disposed in a first plane; and The packaging substrate and the capacitor do not share a common second plane that is orthogonal to the first plane.

16. The electronic device according to claim 1, comprising: An IC package, the IC package comprising: a packaging substrate, the packaging substrate including the wiring substrate; and A die is electrically coupled to the first metal plane and the second metal plane of the packaging substrate.

17. The electronic device according to claim 16, wherein: The plurality of metallization layers are disposed in a first plane; and The die and the capacitor do not share a common second plane orthogonal to the first plane.

18. The electronic device of claim 1, wherein the capacitor comprises a deep trench capacitor (DTC).

19. The electronic device according to claim 1, wherein: The plurality of metallization layers are arranged in a first plane; and The electronic device further comprises: a second capacitor coupled to the wiring substrate; a die electrically coupled to the first metal plane and the second metal plane of the wiring substrate; and The die and the second capacitor share a common second plane that is orthogonal to the first plane.

20. The electronic device of claim 1, wherein the electronic device is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; drones; and multirotors.

21. A method of manufacturing an electronic device, the method comprising: A wiring substrate is formed, the wiring substrate comprising a plurality of metallization layers parallel to each other along a first direction, comprising: Forming a first metallization layer, the forming of the first metallization layer comprising: forming a first metal layer, the first metal layer comprising a first metal plane; and forming a first dielectric layer, the first dielectric layer being adjacent to the first metal layer; Forming a second metallization layer, the forming the second metallization layer comprising: forming a second metal layer; and forming a second dielectric layer, the second dielectric layer being adjacent to the second metal layer; forming a second metal plane in the first dielectric layer of the first metallization layer; and coupling the second metallization layer to the first metallization layer such that the second metal plane is located between the first metal layer and the second metal layer along a second direction orthogonal to the first direction; and Coupling a capacitor to the wiring substrate includes: The capacitor is coupled to the first metal plane and the second metal plane.

22. The method of claim 21, further comprising coupling the second metal plane to a third metal plane in the second metal layer.

23. The method of claim 21, wherein: The first dielectric layer between the first metal layer and the second metal layer has a first height along the second direction; and Forming the second metal plane further comprises forming the second metal plane at a first distance from the second metal layer along the second direction, and The first distance is smaller than the first height.

24. The method of claim 23, wherein forming the second metal plane further comprises forming the second metal plane at a second distance from the first metal layer along the second direction, and The first distance is smaller than the second distance.

25. The method of claim 21, wherein: The first dielectric layer between the first metal layer and the second metal layer has a first height; and Forming the second metal plane also includes forming the second metal plane a first distance from the first metal layer, and The first distance is smaller than the first height.

26. The method of claim 25, wherein forming the second metal plane further comprises forming the second metal plane at a second distance from the second metal layer along the second direction, and The first distance is smaller than the second distance.

27. The method of claim 21, further comprising coupling a die to the first metal plane and the second metal plane.

28. The method of claim 27, wherein: The plurality of metallization layers are disposed in a first plane; and The die and the capacitor do not share a common second plane orthogonal to the first plane.

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