Wafer carrier assembly with improved temperature consistency

Abstract

The wafer carrier includes a susceptor including a substantially planar bottom surface and a top surface, the top surface including a plurality of platforms extending over the top surface. The wafer carrier includes a thermal cap defining a plurality of recesses. The thermal cover is configured to be coupled to the base by at least one fastener, and the plurality of grooves are arranged such that when the thermal cover is supported by a plurality of first bases extending from a top surface of the base, each of the plurality of grooves is aligned with a respective one of the plurality of platforms. A plurality of second pedestals are positioned along a plurality of platforms for supporting one or more wafers, where each platform includes at least one second pedestal extending from a top surface of a platform for supporting one wafer.

Description

[0001] Cross-references to related patent applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 409,557, filed on September 23, 2022, which is incorporated herein by reference as if its entirety were expressly set forth herein. Technical Field

[0003] The present disclosure relates generally to semiconductor manufacturing technology, and more particularly to a wafer carrier assembly for a chemical vapor deposition (CVD) reactor having a contoured pedestal and a susceptor base for supporting a wafer to improve thermal uniformity management during a CVD process. Background Art

[0004] Certain processes for manufacturing semiconductors may require complex processes for growing epitaxial layers to produce multi-layer semiconductor structures used to manufacture high-performance devices such as light emitting diodes (LEDs), laser diodes, optical detectors, power electronics, and field effect transistors. In this process, the epitaxial layers are grown through a general process called chemical vapor deposition (CVD). One type of CVD process is called Metal Organic Chemical Vapor Deposition (MOCVD). In MOCVD, reactant gases are introduced into a sealed reaction chamber in a controlled environment, which enables the reactant gases to be deposited on a substrate (commonly called a wafer) to grow thin epitaxial layers. Examples of current product lines of such manufacturing equipment include Series MOCVD systems and Power GaN MOCVD System( Power GaN MOCVD), which are manufactured by VeecoInstruments Inc. in Plainview, New York.

[0005] During the epitaxial layer growth process, many process parameters, such as temperature, pressure and gas flow rate, are controlled to obtain the desired quality in the epitaxial layer. Different layers are grown using different materials and process parameters. For example, devices formed from compound semiconductors (e.g., III-V semiconductors) are typically formed by growing a series of different layers. In this process, the wafer is exposed to a combination of reactant gases, typically including a metal organic compound formed using an alkyl source containing a Group III metal (e.g., gallium, indium, aluminum, and combinations thereof), and a hydride source containing a Group V element (e.g., NH3, AsH3, PH3) or a Sb metal organic (e.g., tetramethyl antimony). Typically, the alkyl and hydride sources are mixed with a carrier gas (e.g., N2 and / or H2) that does not significantly participate in the reaction. In these processes, the alkyl and hydride sources flow over the surface of the wafer and react with each other to form a metal organic compound of the general formula In X Ga y Al z N A A SB P C Sb D A III-V compound wherein x+y+z is approximately equal to 1, A+B+C+D is approximately equal to 1, and each of x, y, z, A, B, C, D can be between 0 and 1. In other processes, often referred to as "halide" or "chloride" processes, the source of the Group III metal is a volatile halide of one or more metals, most commonly a chloride, such as GaCl2. In other processes, bismuth is used to replace some or all of the other Group III metals.

[0006] Suitable substrates for the reaction may be in the form of wafers having metallic, semiconductor and / or insulating properties. In some processes, the wafer may be formed of sapphire, aluminum oxide, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), indium phosphide (InP), indium arsenide (InAs), gallium phosphide (GaP), aluminum nitride (AlN), silicon dioxide (SiO2), etc.

[0007] In a CVD reaction chamber, one or more wafers are positioned in a tray (commonly referred to as a wafer carrier) so that the top surface of each wafer is exposed, thereby providing a uniform exposure of the top surface of the wafer to the atmosphere in the reaction chamber for deposition of semiconductor materials. The wafer carrier typically rotates at a speed of about 50 to 1500 revolutions per minute or more. As the wafer carrier rotates, reactant gases are introduced into the chamber from a gas distribution device located upstream of the wafer carrier. The flowing gas flows downstream to the wafer carrier and the wafer, ideally flowing in a laminar flow. One such example of a CVD reaction chamber is disclosed in U.S. Patent No. 10,570,510, the entire contents of which are incorporated herein by reference. The wafer carrier includes a carrier element having a groove for a semiconductor wafer, commonly referred to as a susceptor or platen or base, which is typically formed of a single block material (such as graphite or silicon carbide). In various embodiments, the wafer carrier may include a cover limiter located above the susceptor or platen or base to help define the groove and keep the wafer in the groove. Various configurations and shapes of carriers / platens / bases and lid restraints have been developed for processing, such as disclosed in U.S. Pat. No. 8,888,919 (which is incorporated herein by reference in its entirety). The '919 patent also describes and illustrates a conventional chemical vapor deposition apparatus that can be used with the wafer carrier described herein.

[0008] During the CVD process, the wafer carrier is maintained at a desired elevated temperature by a heating element, which is typically located below the wafer carrier. Heat is thus transferred from the heating element to the bottom surface of the wafer carrier and flows upward through the wafer carrier to the one or more wafers. Depending on the process, the temperature of the wafer carrier is maintained on the order of 450-1200°C. However, the reactive gases are introduced into the chamber at a much lower temperature (typically 200°C or less) through a gas distribution device to inhibit premature reactions of the gases.

[0009] In such environments, it is often desirable to maintain a highly consistent deposition rate for the epitaxially grown material or materials. A more consistent thickness across the wafer or constituent layers within a wafer results in lower scrap or higher yield. In conventional chemical vapor deposition systems that include a thermal cover, heat is transferred directly from the carrier / platen / pedestal to the wafer substrate, with reduced heat transferred to the cover. Typical systems have a temperature differential of about 30°C between the wafer and the substrate itself, and the temperature within the wafer can vary over a range of about 3-4°C, but even these small variations can affect wafer uniformity.

[0010] Therefore, it is desirable to optimize the temperature uniformity of the wafer carrier and reduce or eliminate areas that are outside of the desired temperature distribution of the wafer carrier. Summary of the invention

[0011] One drawback of existing wafer carrier designs is the presence of a cold ring area of ​​lower temperature along the circumference of the wafer. Existing wafer carrier designs support the wafer on a thermal cover, such as by positioning the wafer on a ledge or protrusion that is part of the thermal cover. In these designs, the outer edge of the wafer is placed on the thermal cover and suspended above the (platform) base of the wafer carrier. The outer edge of the wafer placed on the thermal cover has a lower temperature than the inner portion of the wafer, resulting in inconsistent temperature distribution. As opposed to supporting the wafer on a thermal cover, the wafer carrier described herein overcomes this drawback by providing a base support feature that is directly associated with the base of the wafer carrier, so that there is no contact between the wafer and the thermal cover.

[0012] Another drawback of conventional wafer carriers is that hot spots may occur between the center of the thermal cover and the wafer. Generally speaking, the larger the gap between the center of the thermal cover and the wafer, the greater the possibility of hot spots and the greater the degree of the hot spots. The increased temperature (hot spot) between the center of the thermal cover and the inner edge of the wafer will adversely affect the inner surface (inner portion) of the wafer closest to the wafer carrier and the center of the thermal cover. Due to these hot spots, the wafer has an inconsistent temperature distribution. In certain embodiments, optionally, the wafer carrier described herein is configured to reduce and / or eliminate the hot spots between the center of the thermal cover and the wafer by modifying the top surface of the base of the wafer carrier. More specifically, as described herein, the inclined central recessed area can be incorporated into the top surface of the base.

[0013] Thus, in one embodiment, a wafer carrier for a system for growing epitaxial layers on one or more wafers by CVD is described and illustrated herein. The wafer carrier includes a base including a substantially flat bottom surface and a top surface substantially parallel to the bottom surface. The top surface also includes a plurality of first pedestals and a plurality of platforms extending above the top surface of the base. The wafer carrier includes a thermal cover defining a plurality of grooves. The thermal cover is configured to be coupled to the base by at least one fastener, and the plurality of grooves are arranged so that when the thermal cover is supported by the plurality of first pedestals, each of the plurality of grooves is aligned with a corresponding platform in the plurality of platforms. A plurality of second pedestals are positioned along a plurality of platforms for supporting one or more wafers, wherein each platform includes at least one second pedestal extending from the top surface of the platform for supporting one wafer. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The subject matter of the present invention may be more fully understood by considering the following detailed description of various embodiments in conjunction with the accompanying drawings, in which:

[0015] Figure 1 is a perspective view of a wafer carrier according to an embodiment;

[0016] Figure 2 yes Figure 1A perspective view of a wafer carrier with its thermal cover removed;

[0017] Figure 3 yes Figure 1 A detailed view of a central area of ​​a wafer carrier;

[0018] Figure 4 is a perspective view of a wafer carrier according to another embodiment;

[0019] Figure 5 yes Figure 4 An exploded perspective view of a wafer carrier;

[0020] Figure 6 yes Figure 4 A perspective view of a wafer carrier showing two segmented thermal covers removed;

[0021] Figure 7 is an enlarged partial view of overlapping edges of a segmented thermal cover;

[0022] Figure 8 is an enlarged partial cross-sectional view of a central portion of a wafer carrier illustrating an improvement for dissipating and / or eliminating hot spots in the center of the wafer carrier; and

[0023] Fig. 9 is an enlarged partial cross-sectional view of the base wafer support features of the wafer carrier.

[0024] Although various embodiments may have various modifications and alternative forms, details thereof have been illustrated by way of example in the accompanying drawings and will be described in detail. However, it should be understood that the purpose is not to limit the claimed invention to the specific embodiments described. On the contrary, the present invention is intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the subject matter defined by the claims. DETAILED DESCRIPTION

[0025] The embodiments described herein provide several improvements, some or all of which may be applicable to different embodiments, either alone or in combination, each of which will be described in more detail below.

[0026] Throughout this application, some terms known to those skilled in the art of chemical vapor deposition and similar systems are used. In some cases, these terms may differ from the ordinary meanings of these terms in common parlance. As used in this application, the following terms are defined as follows:

[0027] The susceptor is a structure arranged in the reactor to receive the precursor gas. The susceptor may have various grooves defined therein on which the wafer is grown. In an embodiment, a substrate is positioned within each groove and the wafer is grown on these substrates by epitaxial growth in the reaction chamber.

[0028] During the wafer growth process, the susceptor is typically heated and rotated along with the rest of the wafer carrier assembly. The heating provides energy to promote the reaction of the precursor gases incident on the substrate in the wafer carrier assembly, while the rotation of the wafer carrier assembly promotes uniform growth across the wafer.

[0029] A thermal cover is a structure that can be attached to a susceptor. The thermal cover typically covers those portions of the susceptor other than the recesses, so that precursor gases can still enter those recesses (and / or the wafer and susceptor that may be located therein).

[0030] Base and platform, while having similar meanings in everyday use, are defined herein as referring to different structures / areas of a wafer carrier assembly. The platform as used herein refers to a relatively large raised portion compared to the base. The platform is arranged below the wafer or substrate and defines a height relative to the base portion that is not below the wafer or substrate, and defines a height relative to the base portion that is not below the wafer or substrate. On the other hand, the base provides support for components (e.g., substrate, thermal cover, etc.), but is small enough to provide sufficient mechanical support without promoting any significant level of heat transfer. The base can extend upward from the platform.

[0031] Throughout this application, references may be made to directions. When one component is referred to as being "above" or "below" another component, this refers to the typical orientation when such a system is used. In a typical vapor deposition system, a showerhead or other sprayer for the precursor chemicals is arranged at the gravitational top of the reaction chamber. Therefore, the wafer carrier assembly has a thermal cover at its uppermost portion. The heater is typically located below the base, or in some embodiments, within the base of the wafer carrier assembly. It should be understood that this directional language is used to refer to a typical system, but alternative chemical vapor deposition or other epitaxial growth systems may be arranged differently. Therefore, these directions are used for discussion of the drawings and common embodiments and should not be construed as limitations on the embodiments described herein.

[0032] As previously mentioned, in a typical chemical vapor deposition process, a number of wafers are held on a component commonly referred to as a wafer carrier so that the top surface of each wafer is exposed on the top surface of the wafer carrier. The wafer carrier is then placed into a reaction chamber and maintained at a desired temperature while a gas mixture flows over the surface of the wafer carrier. In this process, it is very important to maintain consistent conditions at all points on the top surface of the various wafers on the carrier. Small changes in reactant gas composition and wafer surface temperature lead to undesirable changes in the performance of the resulting semiconductor device.

[0033] Wafer carriers are usually indicated by the number of wafers they can hold and the size of each wafer. For example, a 3×8 inch wafer carrier (such as Figure 1The exemplary wafer carrier shown is designed to accommodate three (3) wafers, each having a diameter of 8 inches. Figure 4-7 An exemplary 15×4 inch wafer carrier is shown, which accommodates fifteen (15) wafers, each having a diameter of 4 inches. It should be understood that with fewer wafers on the wafer carrier, there is less crowding, which results in increased spacing between individual wafers as discussed herein. It should be understood that the teachings of the present application can be implemented in wafer carriers having dimensions other than those described above.

[0034] Figure 1-3 1 is a perspective view of a wafer carrier 100 according to an exemplary embodiment. It should be understood that the wafer carrier 100 can also be considered a wafer carrier assembly because it is formed of several parts / components attached to each other. The wafer carrier 100 includes a body generally referred to as a base 110 and a thermal cover 200. The wafer carrier 100 includes a plurality of grooves 112, each groove corresponding to an opening defined by the thermal cover 200. Thus, the grooves 112 are open along the top surface of the wafer carrier 100 and are arranged circumferentially around the wafer carrier 100, each such groove being configured to removably receive a disc-shaped wafer 10 ( Fig. 9 ) and hold such wafers 10 during an MOCVD process (or other semiconductor manufacturing process) such as described below. Each wafer 10 is formed of a suitable wafer material, including but not limited to sapphire, silicon carbide, silicon or other crystalline substrate material. Typically, the thickness of each wafer 10 is small compared to the size of its major surface. Each wafer 10 can be disposed on or adjacent to a wafer carrier 100 with its top surface facing upward so that the top surface of the wafer 10 is exposed and accessible at the top surface of the wafer carrier 100. The wafer 10 may be coplanar or approximately coplanar with the top surface of the wafer carrier 100.

[0035] The thermal cover 200 may be Figure 1 As shown in the single piece, or with Figure 4-7 Multiple overlapping segments are shown. This segmented design is described in more detail below and is more common in larger size wafer carriers.

[0036] Although not shown in the drawings, each groove 112 may have a flat surface. As is well known, a flat surface may be used in a chemical vapor deposition system to lock a wafer (not shown) in a corresponding groove 112 to prevent it from rotating during epitaxial growth. Figure 6 and 7 As shown, in some embodiments, each recess may include a protrusion for supporting the wafer.

[0037] The thermal cover 200 is coupled to the base 110 using conventional techniques (e.g., using fasteners, etc.). For example, a surface of the thermal cover 200 includes a plurality of holes 202, and in the illustrated embodiment, the thermal cover 200 includes nine (9) holes 202. As described in more detail below, the holes 202 are openings through which fastening pins can be driven. Additionally, screws can be used to fasten the thermal cover 200 to the base 110.

[0038] In certain embodiments, pins may be used in conjunction with screws to achieve the desired level of constraint. Not all of the different embodiments of this fastening configuration are shown here, and it should be understood that the outer constraint is typically a screw, while the radially inner constraint may be an angled pin or screw to achieve the desired result. Some embodiments are "pinless" presentations that use back screws to keep the thermal cover fastened inside. In various embodiments, screws or pins may be used to minimize or eliminate thermal imprints on the top side by accessing from the back. Any combination of constraints using appropriately positioned pins and screws can effectively prevent deformation of the thermal cover 200 that results in inconsistent temperatures.

[0039] Figure 3 Pins 135 are shown connecting the thermal cover 200 to the base 110. The pins 135 may be angled to prevent the thermal cover 200 from being lifted off the base 110.

[0040] The 3-by-8-inch wafer carrier can use pins and screws, while the 15-by-4-inch carrier does not require pins.

[0041] Generally, during epitaxial growth of a substrate in a CVD system, the wafer carrier 100 is positioned in a reaction chamber and heated from below (i.e., from the side opposite the recess 112). The chamber is typically in a vacuum state, and some gas introduced from one or more sources is directed toward the wafer carrier 100 so that it flows over the top surface of the wafer carrier 100. The gas may include a purge gas and one or more precursor gases that react when heated to deposit the desired material in the recess 112.

[0042] In a typical CVD process, it is desirable to produce growth at the recesses 112 in a uniform, predictable, and consistent manner from run to run. It is also desirable to reduce the amount of system time required to manufacture each wafer 10, either by increasing the speed of the run or by reducing system downtime. For example, when unwanted material deposition occurs in an undesirable location, the system may need to be shut down for cleaning.

[0043] The thermal cover 200 can introduce other variables that negatively impact the ability to produce uniform, predictable, and consistent growth over the recesses 112. For example, if the surface of the wafer 10 located above the recesses 112 is significantly hotter or cooler than the surrounding thermal cover 200, as is the case with conventional monolithic wafer carriers, then the gas flowing over the surface of the wafer carrier 100 can exhibit a temperature gradient and result in inconsistent deposition. In contrast, as described herein, the thermal cover can prevent such temperature differences, or can be used to adjust the temperature differences as desired by adjusting the thermal gap between its components / portions.

[0044] Likewise, the thermal cover 200 can prevent physical obstructions to the flow of precursor gases that affect the quality of epitaxial growth at the grooves 112. During deposition, the rotation of the wafer carrier generally improves consistency and maintains consistency between the individual grooves 112 therein. However, deformation of the thermal cover 200 can affect the space between parts of the wafer carrier 100, which in turn affects the heat transfer characteristics of the entire device and can affect the fluid layer height. It should be understood that the fluid boundary layer can also affect the growth rate, and in particular, small changes that affect the fluid boundary layer will affect the consistency of the growth rate. Because these characteristics are affected by undesirable deformation, different areas may be hotter or colder, and the deposition rate and pattern may be affected. These patterns lead to inconsistent deposition and inconsistent thickness, and are therefore generally undesirable. Therefore, it is beneficial to control the deformation of the thermal cover 200 to maintain a generally flat, consistent surface that is not a significant dish / bowl or bow / mountaintop shape relative to a plane representing an ideal flat, consistent surface. The flatness of the cover may also become uneven due to film stress from the deposited material on its surface.

[0045] As described herein, non-uniform temperature distribution is a problem, and the wafer carrier disclosed herein is configured to provide a more uniform temperature distribution and overcome the local non-uniform temperature distribution associated with existing wafer carriers. More specifically, existing wafer carrier designs are susceptible to the following defects: 1) thermal "hot spots" between the center of the thermal cover and the wafer; and 2) low temperature "cold ring" areas along the circumference of the wafer. These problems combine to reduce overall wavelength uniformity and device yield, and therefore, the wafer carrier of the present application has improved overall wafer temperature and wavelength uniformity.

[0046] Internal hot spots

[0047] One drawback of conventional wafer carriers is that hot spots can exist between the center of the thermal cover and the wafer. Generally speaking, the greater the amount of air space between the center of the thermal cover and the wafer, the greater the likelihood and extent of hot spots. The elevated temperature (hot spot) between the center of the thermal cover and the inner edge of the wafer can adversely affect the inner surface (inner portion) of the wafer closest to the wafer carrier and the center of the thermal cover. Due to these hot spots, the wafer has an inconsistent temperature distribution.

[0048] The wafer carrier described herein is configured to mitigate and / or eliminate hot spots between the center of the thermal cover and the wafer by modifying the top surface of the base of the wafer carrier. Figure 2 , 3 and 8, the top surface of the pedestal 110 of the wafer carrier is modified in a manner to reduce and / or eliminate hot spots between the center of the thermal cover 200 and the wafer 100. In particular, the top surface of the pedestal 110 around the center of the wafer carrier 100 is modified to include local features that dissipate the hot spots between the center of the cover and the wafer 10. This modification is in the form of an area of ​​reduced thickness of the pedestal 110 around the center of the wafer carrier 100 and the thermal cover 200 and outside of the area where the platform is formed. This modification is introduced to reduce the cover temperature at the center of the wafer carrier 100.

[0049] The modification includes removing material from the top surface of the susceptor 110 to further adjust the lid temperature in the central region thereof. The removal of susceptor material results in the formation of an inclined central recessed region 115 of the susceptor 110. Figure 2 The susceptor 110 is shown without the thermal cover 200 and illustrates the location of the angled central recessed area 115. As shown, the angled central recessed area 115 is formed around the center of the susceptor 110 and is formed in the area between the wafer receiving areas of the susceptor 110. Figure 2 In the illustrated embodiment, there are three wafer receiving areas, and thus, the angled central recessed area 115 can be described as comprising three spokes extending radially outward from the center. Figure 3 As best shown in FIG. 1 , within the angled central recessed region 115, there may be mounting features, such as openings that allow for the passage of mounting hardware (e.g., pins and / or screws) to couple the thermal cover 200 to the base 110. Additionally, other support features may be provided within the angled central recessed region 115. For example, Figure 3 and Figure 8 As shown, a larger base 201 may be provided at the exact center of the wafer carrier.

[0050] The interface between the inclined central recessed area 115 and the surrounding flat portion of the base 110 is defined by an outer edge, shoulder or step 119. Figure 2In the illustrated embodiment, there are three steps 119 due to the three-spoke structure of the inclined central recessed area 115 .

[0051] like Figure 8 As shown, the inclined central recessed area 115 can be described by a dimension B and a dimension C. Dimension B is the distance between the top surface of the base 110 and the thermal cover 200. It should be understood that, given that the inclined central recessed area 115 is defined by an inclined (angled) surface, the dimension B is not constant along the length / width (dimension C) of the inclined central recessed area 115. The inclined central recessed area 115 slopes downward toward the center of the wafer carrier 100, and therefore, the dimension B is larger toward the center.

[0052] The slope of the inclined center recessed area 115 can be expressed as an angle. For example, in one embodiment of a first type of wafer carrier, the angle is 0.41826 arc seconds, and in another embodiment of another type of wafer, the angle is 0.55330 arc seconds. It should be understood that these values ​​are exemplary only and many different other slope angles can be used. In particular, the slope of the inclined center recessed area 115 is driven by the temperature distribution of the wafer carrier design. As described above, the larger the empty space in the wafer carrier, the larger the slope angle, and for certain more crowded wafer carrier designs (such as 15×4 inch wafer carriers), it may not be necessary to include this feature, nor is it necessary to provide and incorporate an inclined center recessed area 115 in the wafer carrier. Therefore, this heat dissipation feature is optional for certain wafer carrier designs, can be eliminated, and is not included in certain wafer carriers that do not benefit from this feature.

[0053] also, Figure 8 The dimension A shown in represents the gap distance between the thermal cover 200 and the base portion of the susceptor 110. The gap A increases the cover-to-base clearance at the center of the thermal cover to reduce the cover temperature.

[0054] In one example, dimension A = 0.2 mm to 2 mm; dimension B = 0.3 mm to 2 mm and dimension C = 0 to 65 mm. For wafer carriers that do not include this optional heat sink function, C = 0. It should be understood and appreciated that the above values ​​are exemplary only and do not limit the scope of the present invention.

[0055] Submount Wafer Support Features

[0056] As mentioned above, another drawback of existing wafer carrier designs is the presence of a cold ring area of ​​lower temperature along the circumference of the wafer. Existing wafer carrier designs support the wafer on a thermal cover, such as by positioning the wafer on a ledge or protrusion that is part of the thermal cover. In these designs, the outer edge of the wafer is placed on the thermal cover and suspended above the base of the wafer carrier. The outer edge of the wafer placed on the thermal cover has a lower temperature than the inner portion of the wafer, resulting in inconsistent temperature distribution.

[0057] The wafer carrier described herein overcomes this limitation by providing a base support feature associated with the wafer carrier base, as opposed to supporting the wafer on a thermal cover.

[0058] Now refer to Fig. 9 , which illustrates a base support feature for supporting a wafer 10 according to the present disclosure. The platform of the base 110 of the wafer carrier 100 includes one or more first bases 130 disposed along the top surface of the base 110, and one or more second bases 140 also disposed along the top surface of the platform of the base 110. The one or more second bases 140 are located within the recess of the wafer carrier 100, and the one or more first bases 130 are located radially outside the one or more second bases 140. Although the term "base" is used to describe each structure identified at 130, 140, it should be understood that these structures may also be described as support protrusions, etc.

[0059] Fig. 9 The base 110 in the embodiment can be considered to have a first region where one or more first seats 130 are recessed relative to a second region (defined by the platform) where one or more second seats 140 are located. A wall 150 is located between one first region and one second region. The wall 150 is formed at right angles to the top surface in the first region and the top surface in the second region (i.e., the wall 150 extends from the top surface of the base to the top surface of the platform).

[0060] One or more first mounts 130 are located radially outward from the wall 150 and are configured to support the thermal cover 200. In one embodiment, each of the one or more first mounts 130 includes a plurality of discrete mounts (pads) upon which the thermal cover 200 rests; however, other configurations are possible.

[0061] As described in more detail below, the one or more second pedestals 140 provide a surface on which the wafer 10 rests within the recess. In one embodiment, each of the one or more second pedestals 140 includes a single continuous annular pedestal on which the wafer 10 rests. In another embodiment, each of the one or more second pedestals 140 includes a plurality of discrete protrusions that are circumferentially spaced from one another and thus define a discontinuous surface on which the wafer 10 rests.

[0062] The thermal cover 200 includes a groove as described above, in which the wafer 10 is located. The thermal cover 200 is constructed according to the contour of the platform of the base 110. For example, the groove of the thermal cover 200 is defined by the inner edge of the thermal cover 200, which has a contour complementary to the shape of the platform. More specifically, the inner edge of the thermal cover 200 defining a groove includes a first inner edge 205 and a second inner edge (inner peripheral edge) 207 located above the first inner edge 205. The first inner edge 205 is located radially outside the second inner edge 207. The first inner edge 205 is parallel to the wall 150. In the illustrated embodiment, the first inner edge 205 and the second inner edge 207 are formed in a non-parallel manner. The first bottom edge 209 is located between the first inner edge 205 and the second inner edge 207. The first bottom edge 209 is formed perpendicular to the first inner edge 205 and intersects with the second inner edge 207, so that the angle between the second inner edge 207 and the first bottom edge 209 is not 90 degrees.

[0063] In addition, the top surface of the thermal cover 200 can include an angled portion 240 around each groove. As shown, the angled portion 240 has a downward slope in the direction toward the groove. The angled or inclined portion 240 intersects the second inner edge 207. The angled portion 240 has an annular shape and surrounds the groove opening. The width of the angled portion 240 can be selected based on many factors discussed herein. The angled portion 240 promotes smooth flow of gas into and out of the groove, particularly around the outer edge of the wafer.

[0064] like Fig. 9 As shown, the thermal cover 200 partially overhangs (overlaps) the elevated platform, and one or more second bases 140 protrude upward from the elevated platform. In particular, the inner portion of the first bottom edge 209 and the second inner edge 207 are located above the elevated platform, but radially outside the one or more second bases 140.

[0065] The second inner edge 207 provides lateral mechanical restraint for the wafer 10. In other words, the second inner edge 207 prevents the wafer 10 from undesirably moving within the recess and prevents the wafer 10 from flying out of the one or more second pedestals 140.

[0066] As described above, in contrast to conventional wafer carrier designs, one or more second pedestals 140 support the outer edges of wafer 10. This design prevents the outer edges of the wafer from dissipating heat to the cooler thermal cover 200 and eliminates undesirable low temperature "cold ring" regions along the perimeter of the wafer.

[0067] Fig. 9There are multiple labels with certain dimensions for defining the configuration and features of the wafer carrier 100. For example, dimension A is the distance (gap) between the thermal cover 200 and the top surface of the platform in the recessed area where one or more first bases 130 are located. This dimension A is selected to balance the average wafer and cover top surface temperature. Dimension B is the distance between the wafer 10 and the top surface of the platform below the wafer 10. This dimension B prevents a bent wafer from contacting the platform during the manufacturing process. Dimensions C and D are the distance (gap) between the thermal cover 200 and the platform of the base 110. Dimension C is the distance between the first inner edge 205 and the wall 150, while dimension D is the distance between the first bottom edge 209 and the top surface of the elevated platform of the base 110. These dimensions C and D are calibrated to optimize the edge temperature of the wafer. Dimension E is the width of the angled portion 240 at the inner edge of the thermal cover 200 defined on the groove. Dimension F is the height of the second inner edge 207. Dimensions E and F are designed to provide smooth airflow around the wafer edge.

[0068] In one example, dimension A = 0.2 mm to 2 mm; dimension B = 0.2 mm to 0.4 mm; dimension C = 0.5 mm to 1.5 mm; dimension D = 0.2 mm to 0.5 mm; dimension E = 1 mm to 3 mm; and dimension F = 0.5 mm to 2 mm. For those wafer carriers that do not include this optional heat sink feature, C = 0. It should be understood and appreciated that the above values ​​are exemplary only and do not limit the scope of the present invention.

[0069] It should be understood that Fig. 9 The base wafer support features shown in the Figure 1-3 The wafer carrier 100 and Figure 4-7 (which will be described below), as well as being incorporated into other wafer carrier designs. In addition, it should be understood that Fig. 9 The base wafer support feature can be used in conjunction with the inclined center recessed area 115, or can be used without such a feature. As previously mentioned, the inclusion of the inclined center recessed area 115 is optional and depends on the characteristics of the wafer carrier (such as size and number of wafers and spacing).

[0070] Figure 4-7 is a perspective view of a wafer carrier 300 according to another exemplary embodiment. Specifically, the wafer carrier 300 has a 15×4 inch design. For wafer carriers of this size, the thermal cover is usually a multi-piece (segmented) structure.

[0071] The wafer carrier 300 includes a base 110 and includes Fig. 9 The wafer support features of the base; however, it does not include Figure 7The inclined central recessed area 115, because it does not include the central spatial blank degree, is like Figure 1-3 The situation like the wafer carrier 100.

[0072] It should be understood that the wafer carrier 300 can also be considered a wafer carrier assembly because it is formed of several parts / components attached to each other. The wafer carrier 100 includes a body (e.g., a base 110) and a thermal cover 310. The wafer carrier 100 includes a plurality of grooves 312, each groove corresponding to an opening defined by the thermal cover 310. Thus, the grooves 312 are open along the top surface of the wafer carrier 100 and are arranged circumferentially around the wafer carrier 100, each such groove being configured to removably receive a disc-shaped wafer 10 ( Fig. 9 ) and maintain such a wafer 10 during an MOCVD process (or other semiconductor manufacturing process) such as described below.

[0073] The thermal cover 310 is defined by a plurality of thermal cover pieces (segments), generally indicated at 320, which are engaged with one another to define the assembled thermal cover 310. Figure 4-7 In FIG. 5 , five (5) thermal covers 320 are arranged around the center of the wafer carrier. Although the thermal covers 320 shown are generally of the same size, there are differences. For example, an interlocking mechanism can be provided to couple the thermal covers together. Figure 7 As shown, the first side edge of each thermal cover 320 includes a first locking feature, generally indicated at 325, and the opposite second side edge of the thermal cover 320 includes a second locking feature, generally indicated at 327. When adjacent thermal covers 320 are mated together, the first and second locking features complement each other and define an overlapping structure. For example, the first and second locking features can be male / female parts. Figure 7 In the embodiment of the present invention, the first locking feature 325 is a female component and the second locking feature 327 is a male component. When two adjacent thermal covers 320 are engaged with each other, the second locking male feature 327 is located within the stepped first locking feature 325 to provide a seal due to the overlapping structure.

[0074] Example - CVD Equipment and Process Conditions

[0075] Conventional chemical vapor deposition equipment includes a reaction chamber having a gas inlet manifold disposed at one end of the chamber. The end of the chamber having the gas inlet manifold is referred to herein as the "top" end of the chamber. This end of the chamber is typically (but not necessarily) disposed at the top of the chamber in a normal gravitational reference frame. Thus, the downward direction used herein refers to the direction away from the gas inlet manifold; and the upward direction refers to the direction within the chamber toward the gas inlet manifold, regardless of whether these directions coincide with the upward and downward directions of gravity.

[0076] The spindle is arranged in the chamber for rotating around a vertical central axis. The central axis of the spindle extends in the upward and downward directions of the reaction chamber. The spindle is installed to the chamber by a conventional rotary through-apparatus in combination with bearings and seals, so that the spindle can rotate around the central axis while maintaining the seal between the spindle and the chamber substrate. The spindle is connected to a rotary drive mechanism (e.g., a motor drive) arranged to rotate the spindle around the central axis. The spindle may also be provided with an internal coolant channel extending approximately in the axial direction of the spindle in the gas channel. The internal coolant channel may be connected to a coolant source so that a fluid coolant can be circulated by the coolant source through the coolant channel and returned to the coolant source. A wafer carrier (e.g., wafer carrier 100, 300) is mounted on the spindle so that the central axis of the wafer carrier is consistent with the axis of the spindle.

[0077] The wafer carrier is maintained at the desired elevated temperature by heating elements, which are typically resistive heating elements disposed beneath the bottom surface of the wafer carrier. These heating elements are maintained at a temperature above the desired temperature of the wafer surface, while the gas distribution elements are typically maintained at a temperature well below the desired reaction temperature to prevent the gases from reacting prematurely. Thus, heat is transferred from the heating elements to the bottom surface of the wafer carrier and flows upward through the wafer carrier to the individual wafers.

[0078] In operation, for some MOCVD processes, the spindle typically rotates at 400-800 revolutions per minute, with a typical speed (RPM) of 500 rpm. In some embodiments, the typical deposition range is 25 to 100 Torr, typically in an H2 environment. Small amounts of N2 can be added to the total flow, but these are typically <5%. Typically, the wafer is maintained at a temperature of 500-750°C during material deposition. It should be understood that the above values ​​relate to AsP deposition, and other materials can be deposited at higher or lower pressures and / or higher or lower temperature ranges. It should be understood that the above parameters are only exemplary parameters for certain embodiments and may vary depending on the precise process operations implemented.

[0079] In one embodiment, the thermal cover can be formed of graphite and the base can also be formed of graphite. However, other materials, such as those described herein, can also be used. For example, the thermal cover and / or the base can be formed of silicon carbide (SiC) or coated with a silicon carbide coating.

[0080] It should be understood that like numbers in the drawings represent like elements in some drawings, and not all embodiments or arrangements require all components and / or steps described and shown with reference to the drawings.

[0081] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprise" and / or "include" when used in this specification specify the presence of the features, components, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, components, steps, operations, elements, parts, and / or groups thereof.

[0082] In addition, the phraseology and terminology used herein are for descriptive purposes and should not be considered limiting. The use of "including," "comprising," or "having," "containing," "involving," and variations thereof herein is meant to encompass the items listed thereafter, their equivalents, and additional items.

[0083] The subject matter described above is provided by way of illustration only and should not be construed as limiting. Various modifications and changes may be made to the subject matter described herein without following the exemplary embodiments and applications shown and described without departing from the true spirit and scope of the invention as set forth in the appended claims.

Claims

1. A wafer carrier for use in a system for growing an epitaxial layer on one or more wafers by chemical vapor deposition (CVD), the wafer carrier comprising: a base comprising a generally planar bottom surface and a top surface generally parallel to the bottom surface, wherein the top surface of the base comprises a plurality of first pedestals and a plurality of platforms extending above the top surface; as well as a thermal cover defining a plurality of grooves, wherein the thermal cover is configured to be coupled to the base via at least one fastener, and the plurality of grooves are arranged such that each groove of the plurality of grooves is aligned with a corresponding platform of the plurality of platforms when the thermal cover is supported by the plurality of first bases; Wherein, a plurality of second pedestals are positioned along a plurality of platforms for supporting one or more wafers, wherein each platform includes at least one second pedestal extending from a top surface of a platform for supporting one wafer.

2. The wafer carrier according to claim 1, wherein: Each recess comprises a single continuous second base having an annular shape for supporting a wafer.

3. The wafer carrier according to claim 1, wherein: Each recess includes a second seat in the form of a plurality of discrete protrusions, which are circumferentially arranged for supporting a wafer.

4. The wafer carrier according to claim 1, wherein: The first plurality of mounts include a plurality of discrete pads, and the thermal cover is located on the discrete pads.

5. The wafer carrier according to claim 1, wherein: The plurality of first bases are located radially outward of the plurality of platforms including the plurality of second bases.

6. The wafer carrier according to claim 5, wherein: The plurality of second bases are elevated relative to the plurality of first bases.

7. The wafer carrier according to claim 1, wherein: The thermal cover partially overlaps with a plurality of the platforms.

8. The wafer carrier according to claim 1, wherein: Each platform is defined by an outer wall extending upward from a top surface of the base, wherein a height of the outer wall is greater than a height of each first seat.

9. Wafer carrier 1, wherein: Each platform includes an outer peripheral region positioned radially outward from at least one second base of the platform, the thermal cover overlapping the outer peripheral region in each recess.

10. The wafer carrier according to claim 9, wherein: Each recess of the thermal cover is defined by an inner circumferential edge located radially outward of at least one second pedestal for providing lateral mechanical restraint to a wafer within the recess.

11. The wafer carrier according to claim 10, wherein: The inner circumferential edge is at an angle other than 90 degrees relative to the flat top surface of the platform.

12. The wafer carrier according to claim 1, wherein: The top surface of the thermal cover immediately surrounding each groove is defined by a downwardly angled portion that defines and circumferentially surrounds a groove.

13. The wafer carrier according to claim 1, wherein: One or more of the wafers are not in direct contact with the thermal cover.

14. The wafer carrier according to claim 1, wherein: The distance between the top surface of the platform and the thermal cover is between 0.2 mm and 0.4 mm, wherein the distance between the underside of the thermal cover and the top surface of the base is between 0.2 mm and 2 mm, and wherein the distance between the thermal cover and the top surface of the platform is between 0.2 mm and 0.5 mm.

15. The wafer carrier of claim 1, wherein: The top surface of the base includes an inclined central recessed area at the center of the base in the area between the platforms.

16. The wafer carrier according to claim 15, wherein: A step is formed between the inclined central recessed area and the flat portion surrounding the top surface.

17. The wafer carrier of claim 15, wherein: The sloped central recessed area slopes downwardly toward a center point of the base.

18. The wafer carrier of claim 15, wherein: The angle of the inclined central recessed area is less than 1 degree.

19. The wafer carrier of claim 1, wherein: The thermal cover includes a segmented thermal cover including a plurality of thermal cover pieces that interlock with each other to form the thermal cover.

20. A wafer carrier for use in a system for growing an epitaxial layer on one or more wafers by chemical vapor deposition (CVD), the wafer carrier comprising: a base comprising a generally planar bottom surface and a top surface generally parallel to the bottom surface, wherein the top surface comprises a plurality of terraces extending above the top surface of the base; and a thermal cover defining a plurality of grooves, wherein the thermal cover is configured to be coupled to the base via at least one fastener, and the plurality of grooves are arranged such that each groove of the plurality of grooves is aligned with a corresponding platform of the plurality of platforms when the thermal cover is supported by the plurality of first seats of the base; The base includes a plurality of second pedestals extending from top surfaces of the plurality of platforms to support one or more wafers so that during operation, the one or more wafers are not in direct contact with the thermal cover.

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