A chip and substrate connection structure

Abstract

This invention relates to the field of chip packaging, and more particularly to a chip-substrate connection structure. It includes multiple first UBM pads and second UBM pads. The multiple first UBM pads are located in a region near the center of a first interconnect layer, and the multiple second UBM pads are located in a region away from the center of the first interconnect layer. The difference between the area of ​​the second UBM pad and the area of ​​the first UBM pad is less than or equal to a first preset threshold. In this invention, first UBM pads and second UBM pads of different sizes are provided in the chip-substrate connection structure. When larger second UBM pads are arranged in the corresponding high-stress areas, the bump density in that area can be increased to meet the differentiated bump density requirements of high-performance chips in corner areas, thereby reducing the risk of breakage of the ELK isolation dielectric layer in high-stress areas and improving the operational stability of the chip.

Description

Technical Field

[0001] This invention relates to the field of chip packaging, and more particularly to a connection structure between a chip and a substrate. Background Technology

[0002] With the development of advanced technologies such as AI computing inference, big data, and cloud services, the required computing power is increasing exponentially. To meet these computing demands, more transistors and metal layers can be placed on computing chips using more advanced manufacturing processes (such as 5nm and 7nm). These metal layers act as circuits, connecting different transistors in different ways to meet the corresponding power supply and logic operation requirements. To prevent conductivity between adjacent stacked metal layers, an insulating medium is placed between any two adjacent metal circuit layers. Furthermore, to reduce dielectric loss and improve signal transmission quality and speed when communicating between different metal circuit layers, ELK (extremely low-k) materials with low dielectric constants are typically used as the insulating medium between different circuit layers.

[0003] For chips used in high-computation applications such as AI computing inference, big data, and cloud services, their large size and the need for more complex and frequent communication between different metal layers necessitate a lower K-value isolation medium to reduce electrical losses. Since vacuum has the lowest dielectric constant, increasing the proportion of vacuum or air in the dielectric material lowers the overall dielectric constant. However, to reduce the K-value, the dielectric material contains more and more pores, resulting in lower mechanical strength. Furthermore, these high-computation chips typically generate extremely high amounts of heat. With temperature changes, the mismatch in thermal expansion coefficients between the chip and the substrate causes warping deformation (like a "crying face" or "smiling face") at the substrate edges and corners, leading to greater compressive stress on the isolation dielectric layer and further increasing the risk of ELK isolation dielectric layer fracture. Generally, a higher bump density between the chip and the substrate is more effective in mitigating compressive stress. Therefore, for the aforementioned high-computation chips, a higher bump density is needed in areas of high stress to improve chip operational stability.

[0004] Existing technologies all use bumps of the same size for connection, resulting in identical bump sizes across all areas of the chip. However, the corners of the chip typically require higher bump density, and existing bump configurations often fail to meet the minimum bump density requirements at these corners. This increases the risk of breakage in the ELK isolation dielectric layer and reduces the chip's operational stability. Summary of the Invention

[0005] In view of this, the present invention provides a connection structure between a chip and a substrate, which at least partially solves the problems existing in the prior art.

[0006] According to one aspect of the present invention, a connection structure between a chip and a substrate is provided, comprising:

[0007] The first interconnect layer is fixedly disposed on the side of the chip closest to the substrate.

[0008] Multiple first UBM pads and multiple second UBM pads are fixed to the first connecting layer at intervals. The multiple first UBM pads are located in the region near the center of the first connecting layer, and the multiple second UBM pads are located in the region away from the center of the first connecting layer. The first UBM pads are the UBM pads with the smallest area in the connecting structure, and the second UBM pads are the UBM pads with the largest area in the connecting structure.

[0009] The difference between the area of ​​the second UBM pad and the area of ​​the first UBM pad is less than or equal to the first preset threshold.

[0010] Furthermore, it also includes:

[0011] Multiple first connecting protrusions are respectively fixed on the first UBM pad, and the volume of the first connecting protrusion is positively correlated with the area of ​​the first UBM pad.

[0012] Multiple second connecting bumps are respectively fixed to the second UBM pad, and the volume of the second connecting bump is positively correlated with the area of ​​the second UBM pad. The difference between the height of the second connecting bump and the height of the first connecting bump is less than or equal to a second preset threshold.

[0013] The second connection layer is fixedly disposed on the side of the substrate closest to the chip. Each first connection bump and each second connection bump are fixedly connected to the second connection layer.

[0014] Furthermore, the first connection layer includes:

[0015] A passivation layer is fixedly applied to the metal layer on the side of the chip closest to the substrate.

[0016] An energy-absorbing layer is fixedly applied over the passivation layer.

[0017] Multiple first mounting through holes penetrate the energy-absorbing layer and the passivation layer. The positions of the multiple first mounting through holes correspond one-to-one with the positions of the first UBM pad and the second UBM pad. A connecting end of the first UBM pad and the second UBM pad is fixedly installed in the corresponding first mounting through hole.

[0018] Furthermore, the second connection layer includes:

[0019] A protective layer is fixedly applied to the metal layer on the side of the substrate closest to the chip.

[0020] Multiple second mounting through holes are disposed through the protective layer, and the positions of the multiple second mounting through holes correspond one-to-one with the positions of the first mounting through holes. The other connecting ends of the first connecting protrusion and the second connecting protrusion are respectively fixedly disposed in the corresponding second mounting through holes.

[0021] Furthermore, the first connection layer is rectangular, and its shape is the same as that of the chip.

[0022] Multiple second UBM pads are located in the four apex regions of the first connecting layer.

[0023] Furthermore, the apex region is a rectangle or a triangle.

[0024] Furthermore, both the first UBM pad and the second UBM pad are cylindrical pads.

[0025] The diameter of the second UBM pad is determined according to the following steps:

[0026] An initial diameter range is generated based on the diameter of the first UBM pad and the first preset threshold.

[0027] Multiple initial diameter values ​​are obtained from the initial diameter range.

[0028] Based on the first mapping table, obtain the cushioning interval value corresponding to each initial diameter value.

[0029] Based on each initial diameter value and the corresponding pad spacing value, determine the number of second UBM pads formed by each initial diameter value in the preset area: A1, A2, ..., A1. i A z Among them, A i The number of second UBM pads formed by the i-th initial diameter value in the preset area. z is the total number of initial diameter values, i = 1, 2, ..., z.

[0030] like Then determine Let be the target diameter, and generate multiple target diameters. Here, ρ is the lower limit of the convexity density of the preset region. S is the total area of ​​the preset region. Let be the i-th initial diameter value.

[0031] The diameter of the second UBM pad is obtained from multiple target diameters.

[0032] Furthermore, multiple initial diameter values ​​are obtained from the initial diameter range, including:

[0033] According to the preset numerical interval, multiple initial diameter values ​​are obtained from the initial diameter value range.

[0034] Furthermore, the second preset threshold is 10µm.

[0035] Furthermore, the second preset threshold is positively correlated with the first preset threshold.

[0036] The technical solution of the present invention has at least the following beneficial effects:

[0037] Typically, chips are connected to substrates using more advanced flip-chip bonding technology. Specifically, a bumping process (wafer-level bumping) is used to form solder bumps on the pads of the I / O ports on the wafer, and these bumps then connect the chip to the substrate. Correspondingly, a higher bump density in the connection structure provides greater stress relief for the ELK (Elastic Discrete) dielectric layer, thus reducing the risk of ELK dielectric layer fracture. Simultaneously, the size of the bumps is affected by the size of the corresponding UBM (underball metal) layer. Specifically, the size of the UBM layer is positively correlated with the size of the bumps. Therefore, controlling the size of the UBM layer during the design phase allows for control over the bump dimensions.

[0038] In this invention, a first UBM pad and a second UBM pad of different sizes are provided in the chip-substrate connection structure. The larger second UBM pad is placed in the edge and / or corner regions where the chip experiences greater stress when subjected to warping and compression. Therefore, when the larger second UBM pad is arranged in the corresponding high-stress region, the bump density in that region can be increased to meet the differentiated bump density requirements of high-performance chips in corner regions. This reduces the risk of breakage of the ELK isolation dielectric layer in high-stress regions and improves the operational stability of the chip. Attached Figure Description

[0039] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a cross-sectional view of a chip-substrate connection structure according to an embodiment of this application.

[0041] Figure 2 This is a schematic diagram of the connection structure between the chip, the first connection layer, the UBM pad layer, and the bumps in another embodiment of this application.

[0042] Figure 3This is a schematic diagram of the structure of the high-stress preset area with protrusions arranged in a certain arrangement according to another embodiment of this application.

[0043] Figure 4 This is a schematic diagram of the structure of the high-stress preset area with convex points arranged in arrangement method two in another embodiment of this application.

[0044] Figure 5 This is a schematic diagram of the stress at the protrusions in each region under the condition of high-temperature (240°C) warping deformation of the substrate in another embodiment of this application.

[0045] Figure Labels

[0046] 1. First connecting layer; 10. Passivation layer; 11. Energy absorbing layer; 12. First mounting through hole; 2. UBM pad; 3. Bump; 31. First connecting bump; 32. Second connecting bump; 4. Protective layer. Detailed Implementation

[0047] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0048] It should be noted that, unless otherwise specified, the following embodiments and features can be combined with each other. Furthermore, all other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0049] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0050] As one embodiment of the present invention, such as Figure 1 and Figure 2 As shown, a chip-substrate connection structure is provided, including: a first connection layer 1, a plurality of first UBM pads, and a plurality of second UBM pads.

[0051] The first interconnect layer 1 includes a passivation layer 10, an energy absorption layer 11, and a plurality of first mounting vias 12. The first interconnect layer 1 is rectangular, and its shape is the same as that of the chip.

[0052] Specifically, the passivation layer 10 is fixedly applied to the metal layer on the side of the chip closest to the substrate. The passivation layer 10 is mainly used to prevent oxidation of the metal layer on the side of the chip closest to the substrate.

[0053] The energy-absorbing layer 11 is fixedly covered on the passivation layer 10. The energy-absorbing layer 11 can be made of polyimide, which has a certain energy-absorbing effect. Therefore, when the substrate deforms and compresses the bump 3, the energy-absorbing layer 11 can absorb a certain amount of compressive force through its own partial deformation. This can further reduce the pressure value transmitted to the chip, thereby reducing the risk of breakage of the ELK isolation dielectric layer.

[0054] Multiple first mounting through holes 12 penetrate the energy-absorbing layer 11 and the passivation layer 10. The positions of the multiple first mounting through holes 12 correspond one-to-one with the positions of the first UBM pad and the second UBM pad. A connecting end of the first UBM pad and the second UBM pad is fixedly disposed in the corresponding first mounting through hole 12. Specifically, both the first UBM pad and the second UBM pad are cylindrical pads.

[0055] In the chip-substrate connection structure, the UBM pad 2 is the connection structure between the metal layer on the chip side closest to the substrate and the bump 3. Meanwhile, the size of the bump 3 is affected by the size of the corresponding UBM (underball metal) pad. Specifically, the size of the UBM pad 2 is positively correlated with the size of the bump 3. Therefore, controlling the size of the UBM pad 2 during the design phase allows for control of the bump 3's size.

[0056] Multiple first UBM pads and second UBM pads are fixed at intervals on the first connecting layer 1. The multiple first UBM pads are located in the region close to the center of the first connecting layer 1, and the multiple second UBM pads are located in the region far from the center of the first connecting layer 1. The first UBM pad is the UBM pad 2 with the smallest area in the connecting structure, and the second UBM pad is the UBM pad 2 with the largest area in the connecting structure.

[0057] The difference between the area of ​​the second UBM pad and the area of ​​the first UBM pad is less than or equal to a first preset threshold. Multiple second UBM pads are located in the four apex regions of the first connecting layer 1. The apex regions are rectangular or triangular.

[0058] Typically, when a substrate undergoes high-temperature deformation, the deformation is greater in areas farther from the center. Consequently, the edges and corners of the chip become areas with higher stress values. Higher bump density is required in these high-stress areas, so multiple second UBM pads are placed at the four corners of the first interconnect layer 1.

[0059] Existing chip structures typically include multiple functional modules, corresponding to multiple functional PHY (Port Physical Layer) chips within the chip. Some of these PHY chips need to be externally sourced, and the dimensions of the UBM pad 2 used in the design of these externally sourced PHY chips usually differ.

[0060] In this embodiment, to ensure smooth chip mounting later, the size difference of all bumps 3 on the entire chip needs to be controlled within a reasonable range, such as within 10µm. That is, the difference between the height of the second connecting bump 32 and the height of the first connecting bump 31 is less than or equal to a second preset threshold, which can be 10µm. Furthermore, since the second preset threshold is positively correlated with the first preset threshold, the size of the corresponding first preset threshold can be determined.

[0061] In this invention, a first UBM pad and a second UBM pad of different sizes are provided in the chip-substrate connection structure. The larger second UBM pad is placed in the edge and / or corner regions where the chip experiences greater stress when subjected to warping and compression. Therefore, when the larger second UBM pad is arranged in the corresponding high-stress region, the bump density in that region can be increased to meet the differentiated bump density requirements of high-performance chips in corner regions. This reduces the risk of breakage of the ELK isolation dielectric layer in high-stress regions and improves the operational stability of the chip.

[0062] Specifically, the following example illustrates the effect of improving the convex density in this embodiment:

[0063] The high-stress preset region in the entire chip is a 900um*900um rectangular corner area. The smallest bump 3 (first connecting bump 31) has a size of 80um, and the second preset threshold is 10um. The bump 3 spacing is 70um, and the distance between the outermost second UBM pad and the edge of the preset region is [50um, 200um]. The manufacturer requires a minimum bump density of 23% for the preset region and a minimum bump density of 21% for other high-stress areas.

[0064] Arrangement Method 1: Using the existing conventional design, the structure with the same bump 3 having a size of 80um is arranged to fill the entire chip area, such as... Figure 3 As shown, a total of 36 bumps 3 will be set in the entire high-stress preset area, and the corresponding bump density (bump density / preset area) is 22.34%. This bump density cannot meet the requirement of the lower limit value of bump density in the high-stress preset area.

[0065] Arrangement Method Two: Using the method described in this embodiment, 80µm bumps 3 are arranged in the area near the center of the first connecting layer 1, and 90µm bumps 3 are arranged in the area away from the center of the first connecting layer 1 (the apex corner area of ​​a 900µm * 900µm rectangle), such as... Figure 4 As shown, 36 protrusions 3 are also set in the entire high-stress preset area, and the corresponding protrusion density (protrusion density / preset area) is 28.27%. Compared with the existing protrusion 3 arrangement, the arrangement of the present invention significantly improves the protrusion density of the preset area, which can meet the requirements of the lower limit value of protrusion density.

[0066] Furthermore, during chip design, some sensors are placed in areas farther from the center, such as corners and / or edges. These areas are also the most susceptible to deformation and compression. To ensure sensor stability, bumps 3 cannot be placed in these pressure-sensitive areas. This further reduces the number of bumps 3 in high-stress areas, thus affecting the bump density in those areas. Consequently, existing bump 3 designs of the same size cannot meet the bump density requirements for these areas.

[0067] Correspondingly, if there is a pressure-sensitive area in the apex corner region of the 900um*900um rectangle in the example above, such as the pressure-sensitive area being... Figure 3 and Figure 4 The rectangular area in the upper left corner (shown by the dotted line) prevents the placement of the four protrusions 3 within this area. Therefore, in this case, both arrangement schemes in the above example can only accommodate 32 protrusions 3. Correspondingly, in arrangement scheme one, the protrusion density of the high-stress preset area is 19.86%, which does not meet the usage requirements. In arrangement scheme two, the protrusion density of the high-stress preset area is 25.13%, which meets the usage requirements.

[0068] The bump 3 design method described in this invention allows for the arrangement of smaller bumps 3 in the region near the center of the first interconnect layer 1, thereby increasing the number and density of bumps 3 and ensuring high integration of various functions within the chip. Simultaneously, the arrangement of larger bumps 3 in the high-stress preset region increases the coverage area and density of bumps 3 in the preset region, thus improving the operational stability of the chip.

[0069] Furthermore, by using larger-sized protrusions 3 within the high-stress preset region, not only can the corresponding protrusion density requirements within the region be met, but also, due to the increased size of protrusions 3, their volume also increases accordingly. Therefore, as... Figure 5As shown, the instant noodles increase their own energy absorption capacity and pressure. Through their own deformation, they can absorb more compressive stress energy, thereby reducing the compressive force transmitted to the ELK insulating medium layer. On the other hand, due to the increased contact area between them and the UBM pad 2, the pressure at that location is reduced, which further reduces the pressure on the ELK insulating medium layer at the connection of the protrusion 3 in the high-stress area, thus greatly reducing the risk of the ELK insulating medium layer being crushed.

[0070] like Figure 5 As shown, through finite element simulation analysis, the maximum stress values ​​on bumps 3 of three different diameters in the high-stress region (the triangular region in the upper right corner) were determined under high-temperature (240℃) warping deformation of the substrate. The maximum stress value was the stress value at the tip of bump 3 at the outermost edge of the upper right corner. Furthermore, the bumps 3 in other regions of the three experimental groups were all set with the same size (80µm) and arrangement; the only difference was the diameter of the bumps 3 arranged in the high-stress region, which were 80µm, 95µm, and 90µm respectively. Specifically, the results of the maximum stress values ​​on bumps 3 in these three experimental groups are shown in Table 1 below:

[0071] Table 1

[0072]

[0073] according to Figure 5 In the diagram, darker areas indicate lower stress, while lighter areas indicate higher stress. Therefore, the farther the bump 3 is from the center, the greater the stress it experiences. The closer the bump 3 is to the chip, the higher the stress value.

[0074] As can be seen from the experimental results in the table above, as the size of bump 3 increases, the maximum stress on bump 3 decreases, which means that the compressive force transmitted to the ELK insulating medium layer decreases.

[0075] Generally, it is common knowledge that when adding a corresponding bump 3 structure between two plates, a larger bump 3 will be more sensitive to deformation and compression of one side of the plate compared to a smaller bump 3, thus transmitting the compressive force more directly and significantly to the other side. Even under the same warpage deformation, a larger bump 3 will exert greater pressure on the other side of the plate, making it more prone to fracture of the ELK insulating dielectric layer. Due to this technical bias, those skilled in the art generally believe that, where bump density allows, the bump 3 size should be kept as consistent and small as possible, and in high-stress areas, smaller bump 3 sizes are preferred when permissible.

[0076] The way the protrusion 3 is set in this invention overcomes the existing technical bias by setting a larger protrusion 3 in a high-stress area, and further reduces the maximum stress on the protrusion 3.

[0077] Furthermore, a chip-substrate connection structure also includes: a plurality of first connection bumps 31, a plurality of second connection bumps 32, and a second connection layer.

[0078] Multiple first connection bumps 31 are respectively fixed to the first UBM pad layer, and the volume of the first connection bump 31 is positively correlated with the area of ​​the first UBM pad layer. Multiple second connection bumps 32 are respectively fixed to the second UBM pad layer, and the volume of the second connection bump 32 is positively correlated with the area of ​​the second UBM pad layer. The second connection layer is fixedly disposed on the side of the substrate close to the chip. Each first connection bump 31 and each second connection bump 32 is fixedly connected to the second connection layer. Specifically, the second connection layer includes: a protective layer 4 and multiple second mounting vias.

[0079] A protective layer 4 is fixedly applied to the metal layer on the side of the substrate closest to the chip. This protective layer 4 can be solder mask, which refers to the ink applied to the copper foil on the PCB. This ink can cover conductors other than solder pads, preventing short circuits during use and extending the PCB's lifespan. Multiple second mounting vias are disposed through the protective layer 4, and the positions of the multiple second mounting vias correspond one-to-one with the positions of the first mounting vias 12. The other connecting ends of the first connecting bump 31 and the second connecting bump 32 are fixedly disposed in the corresponding second mounting vias.

[0080] As another embodiment of the present invention, a method for determining the UBM in a chip-substrate connection structure is provided, used to determine the diameter of the second UBM pad layer in the aforementioned chip-substrate connection structure. Due to limitations in actual manufacturing processes, to ensure a more stable connection between the chip and the substrate, there are usually corresponding restrictions on the spacing between any two bumps 3, the size difference between the largest bump 3 and the smallest bump 3, and the distance between the outer bump 3 and the edge of the high-stress region. Therefore, determining a more suitable diameter for the second UBM pad layer becomes crucial to ensuring the operational stability of the chip.

[0081] The diameter of the second UBM pad is determined according to the following steps:

[0082] S100: Generate an initial diameter range based on the diameter of the first UBM pad and the first preset threshold.

[0083] Specifically, S100 includes:

[0084] S101: Obtain the first preset threshold Y1. The first preset threshold is related to the bump 3 connection process between the chip and the substrate (wafer-level bump process).

[0085] Typically, Y1 is related to the processing capabilities of the wafer-level bumping process used by the corresponding manufacturer, and the specific value can be determined based on the manufacturer's specifications. In recent years, with the evolution of chip mounting and bump growth processes, it is generally acceptable for the height difference of all bumps 3 on the same chip to be within 10µm. This makes it possible to grow bumps 3 of different sizes on the same chip. Therefore, to maximize the size of the bump 3, Y1 = 10µm is preferred.

[0086] S102: Based on the diameter F of the first UBM pad layer 1 The initial diameter value range [F] is generated by combining the first preset threshold Y1. 1 F 1 +Y1].

[0087] The diameter of the first UBM pad is the diameter of the smallest bump 3 in the entire chip. Taking 80um as an example, the corresponding initial diameter range is [80um, 90um].

[0088] S200: Obtain multiple initial diameter values ​​from the initial diameter value range.

[0089] Specifically, S200 includes:

[0090] S201: Obtain multiple initial diameter values ​​from the initial diameter value range according to the preset numerical interval.

[0091] The preset numerical interval can be determined according to the actual usage scenario. For example, it can be 5um intervals, and the initial diameter value range is [80um, 90um], finally obtaining multiple initial diameter values ​​of 80um, 85um and 90um.

[0092] S300: According to the first mapping table, obtain the arrangement interval value corresponding to each initial diameter value. Specifically, the arrangement interval value includes the spacing between two adjacent second UBM pads and the spacing between the outermost second UBM pad and the edge of the preset area.

[0093] The spacing between two adjacent second UBM pads is to prevent two adjacent protrusions 3 from sticking together during manufacturing. The spacing between the outermost second UBM pad and the edge of the preset area is to prevent two adjacent protrusions 3 inside and outside the preset area from sticking together during manufacturing. This spacing is typically a range value, which can be [50um, 300um]. The spacing between two adjacent second UBM pads is related to the specific size of the protrusion 3; the larger the size of the protrusion 3, the larger the required arrangement interval value, and different manufacturers have different settings for this correspondence. Therefore, a corresponding first mapping table can be generated to determine the correspondence between the size of each protrusion 3 and the arrangement interval value. Since the size of the protrusion 3 is also positively correlated with the size of the UBM pad 2, and this correspondence is also related to the manufacturer's production process, different manufacturers will have different correspondences. Therefore, the first mapping table can also include the correspondence between the initial diameter value of the UBM pad 2 and the arrangement interval value. Through collection and organization, a more complete first mapping table can be established.

[0094] S400: Based on each initial diameter value and the corresponding arrangement interval value, determine the number A1, A2, ..., A3 of the second UBM pads formed by each initial diameter value in the preset area. i A z Among them, A i The number of second UBM pads formed by the i-th initial diameter value in the preset area. z is the total number of initial diameter values, i = 1, 2, ..., z.

[0095] like Then determine Let be the target diameter, and multiple target diameters be generated. Here, ρ is the lower limit of the bump density of the preset region, which is usually provided by the manufacturing manufacturer. S is the total area of ​​the preset region. Let be the i-th initial diameter value.

[0096] In this invention, by using the diameter of the first UBM pad and a first preset threshold, a more accurate initial diameter range can be generated based on the size difference between the maximum and minimum bumps 3. After meeting this requirement, by using the arrangement interval value corresponding to each initial diameter value within the initial diameter range, the coverage area of ​​the second UBM pad formed by each initial diameter value in the preset region can be determined. This allows for determination of whether the bump density required for stress relief in that region is met. After the above processing, the usable diameter of the second UBM pad that meets the minimum bump density requirement for a certain region can be determined more accurately, satisfying the usage requirements of different bump densities in different regions and further ensuring the operational stability of the chip.

[0097] S500: Obtain the diameter of the second UBM pad from multiple target diameters.

[0098] Furthermore, the S500 includes:

[0099] S501: Select the minimum value among multiple target diameters as the diameter of the second UBM pad.

[0100] When multiple target diameters are available, the smallest diameter that meets the requirements can be selected as the diameter of the second UBM pad. This allows for a further reduction in the size difference between the largest bump 3 and the smallest bump 3 on the same chip, thereby reducing the requirements for the board mounting process.

[0101] S600: Based on the obtained diameter of the second UBM pad and the corresponding arrangement interval value, generate multiple corresponding pad setting positions in the preset area, and generate the second UBM pad.

[0102] After determining the diameter of the second UBM pad, the locations of multiple corresponding pads in the preset area can be determined, and the second UBM pad can be generated at the corresponding locations.

[0103] As another embodiment of the present invention, S500: obtaining the diameter of the second UBM pad from a plurality of target diameters includes:

[0104] S501: Based on the minimum value of the target diameter and Max(B1, B2, ..., B...), n B m For the target diameter, a secondary value range is generated. Where B... n Let m be the total coverage area of ​​the second UBM cushion layer formed by the nth target diameter within the preset area. m represents the total number of target diameters, n = 1, 2, ..., m, where m ≤ z. n The following conditions must be met:

[0105]

[0106] Among them, E n The total number of second UBM pads formed by the nth target diameter set in the preset area. This represents the diameter value of the nth target.

[0107] S502: Obtain the diameter of the second UBM pad from the secondary value range.

[0108] In actual bump 3 arrangement, larger bump 3 sizes typically correspond to larger spacing to prevent bump 3 adhesion during growth. Correspondingly, the spacing between the second UBM pads also increases. Therefore, as the diameter of the second UBM pad increases, the number of second UBM pads may decrease, leading to a reduction in coverage area and bump density. Thus, after further selection in this embodiment, it can be ensured that for each target diameter in the secondary value range, the bump density increases with the diameter value, showing a positive correlation. Therefore, while choosing a larger diameter increases the requirements for the bump 3 board mounting process, it yields greater benefits from increased bump density. This avoids the situation where increasing the requirements for the bump 3 board mounting process also reduces bump density. Furthermore, it can further reduce the risk of ELK isolation dielectric layer fracture in high-stress areas and improve chip operational stability.

[0109] S512: If any standard pad diameter belongs to the secondary value range, then the standard pad diameter shall be used as the diameter of the second UBM pad.

[0110] The standard padding diameter is the standard padding diameter commonly used by existing processing manufacturers. Selecting the standard padding diameter makes subsequent processing and production easier, allowing for processing in a more mature and commonly used manner to ensure the yield rate.

[0111] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A connection structure between a chip and a substrate, characterized in that, include: The first connection layer is fixedly disposed on the side of the chip close to the substrate; as well as Multiple first UBM pads and multiple second UBM pads are fixed to the first connecting layer at intervals. The multiple first UBM pads are located in the region close to the center of the first connecting layer, and the multiple second UBM pads are located in the region far from the center of the first connecting layer. The first UBM pad is the UBM pad with the smallest area in the connecting structure, and the second UBM pad is the UBM pad with the largest area in the connecting structure. The difference between the area of ​​the second UBM pad and the area of ​​the first UBM pad is less than or equal to a first preset threshold. Both the first UBM pad and the second UBM pad are cylindrical pads; The diameter of the second UBM pad is determined according to the following steps: Based on the diameter of the first UBM pad and the first preset threshold, an initial diameter value range is generated; According to a preset numerical interval, multiple initial diameter values ​​are obtained from the initial diameter value range; Based on the first mapping table, obtain the cushion layer interval value corresponding to each initial diameter value; Based on each initial diameter value and the corresponding pad spacing value, determine the number of second UBM pads formed by each initial diameter value in the preset area: A1, A2, ..., A1. i A z ; Among them, A i The number of second UBM pads formed by the i-th initial diameter value in the preset area; z is the total number of initial diameter values, i=1, 2, ..., z; like Then determine To generate multiple target diameters, where is the target diameter; The lower limit value of the protrusion density in the preset area; The total area of ​​the preset region; This is the i-th initial diameter value; The diameter of the second UBM pad is obtained from the plurality of target diameters.

2. The chip-substrate connection structure according to claim 1, characterized in that, Also includes: Multiple first connecting protrusions are respectively fixed on the first UBM pad, and the volume of the first connecting protrusion is positively correlated with the area of ​​the first UBM pad. Multiple second connecting protrusions are respectively fixed on the second UBM pad layer. The volume of the second connecting protrusion is positively correlated with the area of ​​the second UBM pad layer. The difference between the height of the second connecting protrusion and the height of the first connecting protrusion is less than or equal to a second preset threshold. as well as The second connection layer is fixedly disposed on the side of the substrate close to the chip; each of the first connection bumps and each of the second connection bumps is fixedly connected to the second connection layer.

3. The chip-substrate connection structure according to claim 2, characterized in that, The first connection layer includes: A passivation layer is fixedly applied to the metal layer on the side of the chip closest to the substrate. An energy-absorbing layer is fixedly applied to the passivation layer; and Multiple first mounting through holes penetrate the energy-absorbing layer and the passivation layer. The positions of the multiple first mounting through holes correspond one-to-one with the positions of the first UBM pad and the second UBM pad. A connecting end of the first UBM pad and the second UBM pad is fixedly disposed in the corresponding first mounting through hole.

4. The chip-substrate connection structure according to claim 3, characterized in that, The second connection layer includes: A protective layer is fixedly applied to the metal layer on the side of the substrate closest to the chip; and Multiple second mounting through holes are disposed through the protective layer, and the positions of the multiple second mounting through holes correspond one-to-one with the positions of the first mounting through holes. The other connecting ends of the first connecting protrusion and the second connecting protrusion are respectively fixedly disposed in the corresponding second mounting through holes.

5. The chip-substrate connection structure according to claim 1, characterized in that, The first connection layer is rectangular, and its shape is the same as that of the chip. Multiple second UBM pads are located in the four apex regions of the first connecting layer.

6. The chip-substrate connection structure according to claim 5, characterized in that, The apex region is a rectangle or a triangle.

7. The chip-substrate connection structure according to claim 2, characterized in that, The second preset threshold is 10μm.

8. The chip-substrate connection structure according to claim 2, characterized in that, The second preset threshold is positively correlated with the first preset threshold.

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