Semiconductor device

Abstract

A semiconductor device includes: a substrate including a logic cell region including active patterns spaced apart in a first direction and extending in a second direction different from the first direction, and an overlay key region including a backside key pattern and a front side key pattern; source / drain patterns on the active pattern of the logic cell region and spaced apart in the second direction; a channel pattern between the source / drain patterns; and a gate pattern extending in the first direction, traversing between the source / drain patterns, and surrounding at least a portion of the channel pattern, in which the substrate has an upper surface and a lower surface facing away from each other in a third direction different from the first direction and the second direction, and the backside key pattern of the overlay key region extends into the lower surface of the substrate.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, for example, a transistor including a nanowire or a nanosheet, or a fin-type transistor including a channel pattern in the shape of a fin-type pattern. Background Art

[0002] Semiconductors are materials that belong to the middle area classification between conductors and non-conductors, and refer to materials that conduct electricity under certain conditions. Various semiconductor devices, such as memory devices, etc., can be manufactured using semiconductor materials. Semiconductor devices can be used in various electronic devices.

[0003] As the electronics industry is highly developed, the demand for performance characteristics of semiconductor devices is increasing. For example, the demand for high reliability, high speed and / or multifunctionality of semiconductor devices is increasing. In order to meet these desired characteristics, the structures within semiconductor devices are becoming more complex and integrated. Summary of the invention

[0004] The present disclosure seeks to provide a semiconductor device which is more highly integrated and has reduced alignment errors between a lower contact on a back side and source / drain and gate patterns on a front side by applying a back side power distribution network (BSPDN) structure.

[0005] According to one aspect, a semiconductor device includes: a substrate, the substrate including a logic cell region and an overlay key region, the logic cell region including active patterns spaced apart in a first direction and extending in a second direction different from the first direction, the overlay key region including a back key pattern and a front key pattern; a source / drain pattern, the source / drain pattern being located on the active pattern of the logic cell region and spaced apart in the second direction; a channel pattern, the channel pattern being located between the source / drain patterns; and a gate pattern, the gate pattern extending in the first direction, crossing between the source / drain patterns and surrounding at least a portion of the channel pattern, wherein the substrate has an upper surface and a lower surface that diverge from each other in a third direction different from the first direction and the second direction, and the back key pattern of the overlay key region extends into the lower surface of the substrate.

[0006] According to another aspect, a semiconductor device comprises: a substrate, the substrate comprising a logic cell region and an overlay key region, the logic cell region comprising active patterns spaced apart in a first direction and extending in a second direction different from the first direction, the overlay key region comprising a front key pattern and a back key pattern, the substrate having an upper surface and a lower surface diverging from each other in a third direction different from the first direction and the second direction; a source / drain pattern, the source / drain pattern being located on the active pattern of the logic cell region and spaced apart in the second direction; a channel pattern, the channel pattern being located between the source / drain patterns; a gate pattern, the gate pattern extending in the first direction, crossing between the source / drain patterns and surrounding at least a portion of the channel pattern; and a lower active contact A lower active contact, wherein the lower active contact is located below the source / drain pattern in the third direction when the lower surface of the substrate is the basic reference plane, extends into the active pattern and is electrically connected to the source / drain pattern; and a lower gate contact, wherein the lower gate contact is located below the gate pattern in the third direction when the lower surface of the substrate is the basic reference plane, extends into the active pattern and is electrically connected to the gate pattern; and a first lower interlayer insulating layer, wherein the first lower interlayer insulating layer is located below the lower active contact and the lower gate contact in the third direction when the lower surface of the substrate is the basic reference plane, and includes a first lower metal layer, wherein the lower surface of the back side key pattern of the overlay key area contacts the first lower interlayer insulating layer.

[0007] According to another aspect, a semiconductor device includes a substrate and a sacrificial layer and an active layer, the substrate including: active patterns, which are spaced apart in a first direction and extend in a second direction different from the first direction; device isolation patterns, which are located between the active patterns in the first direction; and back side key patterns and front side key patterns, which are located on the device isolation patterns, the sacrificial layers and the active layers are located on the active patterns and are alternately stacked in a third direction different from the first direction and the second direction, wherein the back side key pattern extends into a lower surface of the device isolation pattern, and wherein the front side key pattern extends into an upper surface of the device isolation pattern and is spaced apart from the lower surface of the substrate.

[0008] According to some embodiments, by applying a backside power distribution network (BSPDN) structure, a semiconductor device may be more integrated and may reduce alignment errors between a lower contact at the backside and source / drain and gate patterns at the frontside. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a top view illustrating a semiconductor device according to some embodiments.

[0010] Figure 2 It is shown Figure 1 A top view of the logic cell area.

[0011] Figure 3 It is along Figure 2 A cross-sectional view taken along line AA'.

[0012] Figure 4 It is along Figure 2 A cross-sectional view taken along line BB'.

[0013] Figure 5 It is along Figure 2 A cross-sectional view taken along line CC'.

[0014] Figure 6 It is along Figure 2 A cross-sectional view taken along line D-D'.

[0015] Figure 7 It is shown Figure 1 A cross-sectional view of the second set of keying areas.

[0016] Figures 8 to 42 are cross-sectional views illustrating intermediate operations of methods of fabricating a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0017] Hereinafter, with reference to the accompanying drawings, various embodiments of the present disclosure will be described in detail so that those skilled in the art can easily practice the present disclosure. In the accompanying drawings, the same reference numerals are used for the same constituent elements, and their repeated descriptions are omitted. As used herein, the term "and / or" includes any and all combinations of one or more items in the associated listed items. Note that the various aspects described with respect to one embodiment can be combined in different embodiments, although not specifically described. That is, the features of all embodiments and / or any embodiment can be combined in any manner and / or combination. The present disclosure can be embodied in many different forms and is not limited to the embodiments set forth herein.

[0018] In addition, since the size and thickness of each component shown in the drawings are arbitrarily shown for the convenience of description, the present disclosure is not limited to those shown. In the drawings, the thickness of layers, panels, regions, etc. are exaggerated for clarity. In addition, in the drawings, the thickness of some layers and regions is exaggerated for the convenience of description.

[0019] Furthermore, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or intervening elements may also be present. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, "above" or "on" a reference portion means above or below the reference portion, and does not necessarily mean "above" or "on" in the opposite direction of gravity.

[0020] In addition, throughout the specification, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0021] Additionally, throughout the specification, observation “on a plane” or in a plan view means when an object portion is observed from above, and observation “on a cross section” means when a cross section obtained by vertically cutting the object portion is observed from the side.

[0022] In addition, throughout the specification, two directions parallel to the upper surface of the substrate and intersecting each other are respectively defined as a first direction D1 and a second direction D2, and a direction perpendicular to the upper surface of the substrate is described as a third direction D3. For example, the first direction D1 and the second direction D2 may be perpendicular to each other.

[0023] In addition, throughout the specification, the front surface or upper portion may refer to a surface or portion positioned in the direction of positioning the front wiring unit (the positive third direction D3 in the figure), and the back surface or lower portion may refer to a surface or portion positioned in the direction of positioning the rear wiring unit (the negative third direction D3 in the figure).

[0024] In the drawings related to the semiconductor device according to the embodiment, a transistor including a nanowire or a nanosheet, a multi-bridge channel field effect transistor (MBCFET™) and a semiconductor device including a nanowire or a nanosheet are shown as examples. TM ) and a fin transistor (FinFET) including a channel region in the shape of a fin pattern, but the present disclosure is not limited thereto. The semiconductor device according to some embodiments may include a tunneling FET, a 3D stacked field effect transistor (3DSFET), or a complementary FET (CFET).

[0025] In the following, reference will be made to Figures 1 to 7 Semiconductor devices according to some embodiments are described in detail.

[0026] Figure 1 is a top view showing a semiconductor device according to an embodiment. Figure 2 It is shown Figure 1 A top view of the logic cell region CER. Figure 3 It is along Figure 2 A cross-sectional view taken along line AA'. Figure 4It is along Figure 2 A cross-sectional view taken along line BB'. Figure 5 It is along Figure 2 A cross-sectional view taken along line CC'. Figure 6 It is along Figure 2 A cross-sectional view taken along line D-D'. Figure 7 It is shown Figure 1 A cross-sectional view of the second set of key engraving areas KER2. Figure 7 It can be Figure 6 As shown in Figure 2 The cross-sectional view shown in the second set of key engraving area KER2 when the line D-D' is taken.

[0027] For the sake of clarity and simplicity, Figure 2 , a separation structure DB, a first cell boundary CB1, a second cell boundary CB2, a first upper metal layer M1, a second upper metal layer M2, a gate pattern GE, an upper active contact AC, an upper gate contact GC, a lower active contact ACb, and a lower gate contact GCb are mainly shown.

[0028] refer to Figure 1 , the semiconductor device may include a main chip MC and a cutting scribe line CSL surrounding the main chip MC in a plan view. The main chip MC may include first to fifth functional units FE1 to FE5 located on a substrate 100. The substrate 100 may be a cut semiconductor wafer. The substrate 100 may support the first to fifth functional units FE1 to FE5.

[0029] The main chip MC may include first to fourth cell boundaries CB1 to CB4. The first to fourth cell boundaries CB1 to CB4 may be defined between the cutting scribe line CSL and the main chip MC. The cutting scribe line CSL may surround the first to fourth cell boundaries CB1 to CB4 of the main chip MC in a plan view. For example, the cutting scribe line CSL may include a first set of key regions KER1 adjacent to the first cell boundary CB1 of the main chip MC. In other words, the first set of key regions KER1 may remain on the cutting scribe line CSL even after the wafer cutting process.

[0030] Each of the first to fifth functional units FE1 to FE5 may be a functional block constituting an integrated circuit. Each of the first to fifth functional units FE1 to FE5 may include a memory block, an analog logic block, an input / output (I / O) logic block, a central processing unit (CPU) block, a radio frequency block, or a combination of these blocks.

[0031] For example, the first functional unit FE1 may include a logic unit region CER and a second key region KER2. In other words, the key region may be disposed not only in the dicing lane but also in the functional block. The third key region KER3 may be disposed in the region between the first functional unit FE1 and the second functional unit FE2.

[0032] In the semiconductor device (ie, semiconductor chip), at least one of the first set of keying regions KER1 , the second set of keying regions KER2 , and the third set of keying regions KER3 may be omitted.

[0033] refer to Figures 2 to 7 The semiconductor device includes: a substrate 100, including a logic cell region CER and a second set of keying regions KER2, the logic cell region CER including a first active pattern AP1 and a second active pattern AP2, the second set of keying regions KER2 including a back key pattern BK and a front key pattern FK; a first source / drain pattern SD1 and a second source / drain pattern SD2, located on the first active pattern AP1 and the second active pattern AP2 of the logic cell region CER; a first channel pattern CH1 and a second channel pattern CH2, located between the first source / drain pattern SD1 and the second source / drain pattern SD2; and a gate pattern GE, crossing between the first source / drain pattern SD1 and the second source / drain pattern SD2 and surrounding at least a portion of the first channel pattern CH1 and the second channel pattern CH2.

[0034] The substrate 100 includes a logic cell region CER and a second set of key regions KER2.

[0035] Logic transistors constituting the logic cell LC may be disposed in a logic cell region CER of the substrate 100. The logic cell LC may include a PMOSFET region PR and an NMOSFET region NR.

[0036] The PMOSFET region PR and the NMOSFET region NR may be defined by first and second active patterns AP1 and AP2 constituting the substrate 100. In other words, the first and second active patterns AP1 and AP2 may be disposed in the PMOSFET region PR and the NMOSFET region NR, respectively.

[0037] The first active pattern AP1 and the second active pattern AP2 are parts of the substrate 100 and may be parts protruding in the third direction D3. The first active pattern AP1 and the second active pattern AP2 may be spaced apart in the first direction D1. The first active pattern AP1 and the second active pattern AP2 may extend in the second direction D2.

[0038] The first active pattern AP1 and the second active pattern AP2 may each include silicon (Si) or germanium (Ge) as an elemental semiconductor material. In addition, the first active pattern AP1 and the second active pattern AP2 may each include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound containing carbon (C), silicon (Si), germanium (Ge), tin (Sn), or a combination thereof. The group III-V compound semiconductor may be, for example, a binary compound, a ternary compound, or a quaternary compound formed by combining a group III element such as aluminum (Al), gallium (Ga), indium (In), or a combination thereof and a group V element such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof.

[0039] The device isolation layer ST may be located between the first active pattern AP1 and the second active pattern AP2. In other words, the device isolation layer ST may be located close to the first active pattern AP1 and the second active pattern AP2 in the first direction D1. The device isolation layer ST may be in the trench between the first active pattern AP1 and the second active pattern AP2 and at least partially fill the trench.

[0040] The upper portions of the first active pattern AP1 and the second active pattern AP2 may protrude in the third direction D3 compared to the device isolation layer ST. In other words, the device isolation layer ST may not cover the upper portions of the first active pattern AP1 and the second active pattern AP2 in the third direction D3 or overlap with the upper portions of the first active pattern AP1 and the second active pattern AP2 in the third direction D3. The device isolation layer ST may cover the sidewalls of the first active pattern AP1 and the second active pattern AP2 in the first direction D1.

[0041] For example, the device isolation layer ST may include an insulating material such as silicon nitride (SiN), silicon oxynitride (SiON), or a combination thereof. Although the device isolation layer ST is illustrated as a single layer, the present disclosure is not limited thereto.

[0042] The first active pattern AP1 may include a first channel pattern CH1 on an upper portion thereof. The second active pattern AP2 may include a second channel pattern CH2 on an upper portion thereof. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked sequentially. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in the third direction D3.

[0043] For example, in Figure 4 and Figure 6In the embodiment, three semiconductor patterns (e.g., a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3) are spaced apart and stacked in a third direction D3, but the embodiments of the present disclosure are not limited thereto. For example, two semiconductor patterns may be spaced apart and stacked in the third direction D3, or four or more semiconductor patterns may be spaced apart and stacked in the third direction D3.

[0044] In addition, for example, Figure 4 and Figure 6 In the embodiment, the side surfaces of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 are flat surfaces, but the embodiments of the present disclosure are not limited thereto. For example, the side surfaces of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be a combination of a curved surface and a flat surface, or may be all curved.

[0045] Each of the first channel pattern CH1 and the second channel pattern CH2 may include an elemental semiconductor material such as silicon (Si), silicon germanium (SiGe), a group IV-IV compound semiconductor, or a group III-V compound semiconductor. Each of the first channel pattern CH1 and the second channel pattern CH2 may include the same material as each of the first active pattern AP1 and the second active pattern AP2, and may include a different material from each of the first active pattern AP1 and the second active pattern AP2.

[0046] A plurality of first recesses RS1 may be formed in an upper portion of the first active pattern AP1. A first source / drain pattern SD1 may be disposed in the first recess RS1. The first source / drain pattern SD1 may be an impurity region of a first conductivity type (e.g., p-type). The first channel pattern CH1 may be disposed between the paired first source / drain patterns SD1. In other words, the stacked first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may electrically connect the paired first source / drain patterns SD1 to each other.

[0047] A plurality of second recesses RS2 may be formed in an upper portion of the second active pattern AP2. A second source / drain pattern SD2 may be disposed in the second recess RS2. The second source / drain pattern SD2 may be an impurity region of a second conductivity type (e.g., n-type). The second channel pattern CH2 may be disposed between the paired second source / drain patterns SD2. In other words, the stacked first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may electrically connect the paired second source / drain patterns SD2 to each other.

[0048] For example, the first source / drain pattern SD1 and the second source / drain pattern SD2 may be epitaxial patterns formed by a selective epitaxial growth (SEG) process. An upper surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be located at substantially the same height as an upper surface of the third semiconductor pattern SP3 in the third direction D3. In some embodiments, an upper surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than an upper surface of the third semiconductor pattern SP3 in the third direction D3.

[0049] For example, the first source / drain pattern SD1 may include a first semiconductor layer and a second semiconductor layer on the first semiconductor layer.

[0050] The first semiconductor layer may be on the inner wall of the first recess RS1 and at least partially cover the inner wall of the first recess RS1. The thickness of the first semiconductor layer may become thinner from the lower portion thereof to the upper portion thereof. For example, the thickness of the first semiconductor layer at the bottom of the first recess RS1 in the second direction D2 may be greater than the thickness of the first semiconductor layer at the top of the first recess RS1 in the second direction D2. The first semiconductor layer may have a U-shape along the profile of the first recess RS1.

[0051] The second semiconductor layer may be in the remaining area of ​​the first recess RS1 except the first semiconductor layer and at least partially fill the remaining area of ​​the first recess RS1 except the first semiconductor layer. The volume of the second semiconductor layer may be greater than the volume of the first semiconductor layer. In other words, the ratio of the volume of the second semiconductor layer to the total volume of the first source / drain pattern SD1 may be greater than the ratio of the volume of the first semiconductor layer to the total volume of the first source / drain pattern SD1.

[0052] Each of the first semiconductor layer and the second semiconductor layer may include silicon germanium (SiGe). For example, the first semiconductor layer may include a relatively low concentration of germanium (Ge). In some embodiments, the first semiconductor layer may include only silicon (Si) without germanium (Ge). The concentration of germanium (Ge) in the first semiconductor layer may be 0 at% to 10 at%.

[0053] The second semiconductor layer may include a relatively high concentration of germanium (Ge). For example, the concentration of germanium (Ge) in the second semiconductor layer may be 30 at% to 70 at%. The concentration of germanium (Ge) in the second semiconductor layer may increase in the third direction D3. For example, the second semiconductor layer adjacent to the first semiconductor layer may include germanium (Ge) with a concentration of about 40 at%, but the upper portion of the second semiconductor layer may include germanium (Ge) with a concentration of about 60 at%.

[0054] The first and second semiconductor layers may each include impurities (eg, boron) so that the first source / drain pattern SD1 has a p-type. The concentration (eg, atomic percent) of the impurities in the second semiconductor layer may be greater than that in the first semiconductor layer.

[0055] The gate patterns GE extend across the first and second active patterns AP1 and AP2 in the first direction D1. The gate patterns GE may be spaced apart at a first pitch P1 in the second direction D2. Each gate pattern GE may overlap the first and second channel patterns CH1 and CH2 in the third direction D3.

[0056] For example, the gate pattern GE may include: a first portion PO1, disposed between the first active pattern AP1 and the second active pattern AP2 and the first semiconductor pattern SP1; a second portion PO2, disposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2; a third portion PO3, disposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3; and a fourth portion PO4, located above the third semiconductor pattern SP3 in the third direction D3.

[0057] The gate pattern GE may be disposed on the top surface TS, the bottom surface BS, and both sidewalls SW of each of the first, second, and third semiconductor patterns SP1, SP2, and SP3. In other words, the gate pattern GE may surround at least a portion of the first and second channel patterns CH1 and CH2.

[0058] A pair of gate spacers GS may be disposed on both sidewalls of the fourth portion PO4 of the gate pattern GE. The gate spacer GS may extend along the gate pattern GE in the first direction D1. The upper surface of the gate spacer GS may be higher than the upper surface of the gate pattern GE in the third direction D3. The upper surface of the gate spacer GS may be located at substantially the same height as the upper surface of the first interlayer insulating layer 110 to be described below. The gate spacer GS may include SiCN, SiCON, SiN, or a combination thereof. In addition, the gate spacer GS may include a multilayer including SiCN, SiCON, SiN, or a combination thereof.

[0059] The gate capping pattern GP may be disposed on the gate pattern GE. The gate capping pattern GP may extend along the gate pattern GE in the first direction D1. The gate capping pattern GP may include a material having an etching selectivity with respect to a first interlayer insulating layer 110 and a second interlayer insulating layer 120 to be described below. For example, the gate capping pattern GP may include SiON, SiCN, SiCON, SiN, or a combination thereof.

[0060] The gate insulating layer GI may be disposed between the gate pattern GE and the first channel pattern CH1 and between the gate pattern GE and the second channel pattern CH2. The gate insulating layer GI may at least partially cover the top surface TS, the bottom surface BS, and both sidewalls SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate insulating layer GI may at least partially cover the upper surface of the device isolation layer ST under the gate pattern GE.

[0061] The gate insulating layer GI may include a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer, or a combination thereof. The high-k dielectric layer may include a high dielectric constant material having a dielectric constant higher than that of the silicon oxide layer. For example, the high dielectric constant material may include hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, tantalum scandium lead oxide, lead zinc niobate, or a combination thereof.

[0062] In some embodiments, the gate pattern GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and adjacent to the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The first metal pattern may include a work function metal that adjusts the threshold voltage of the transistor. The desired threshold voltage of the transistor may be achieved by adjusting the thickness and composition of the first metal pattern. For example, the first portion PO1, the second portion PO2, and the third portion PO3 of the gate pattern GE may include the first metal pattern as a work function metal.

[0063] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), molybdenum (Mo), or a combination thereof. In addition, the first metal pattern may also include carbon (C). The first metal pattern may include a plurality of stacked work function metal layers.

[0064] The second metal pattern may include a metal having a lower resistance than the first metal pattern. For example, the second metal pattern may include a metal such as tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), or a combination thereof. For example, the fourth portion PO4 of the gate pattern GE may include a first metal pattern and a second metal pattern on the first metal pattern.

[0065] Although not shown, an inner spacer may be located on the NMOSFET region NR. The inner spacers may be disposed between the first portion PO1, the second portion PO2, and the third portion PO3 of the gate pattern GE and the second source / drain pattern SD2, respectively. The inner spacer may directly contact the second source / drain pattern SD2. Each of the first portion PO1, the second portion PO2, and the third portion PO3 of the gate pattern GE may be spaced apart from the second source / drain pattern SD2 by the inner spacer.

[0066] The first interlayer insulating layer 110 may be disposed on the substrate 100. The first interlayer insulating layer 110 may at least partially cover the gate spacer GS and the first and second source / drain patterns SD1 and SD2. An upper surface of the first interlayer insulating layer 110 may be located at substantially the same height as an upper surface of the gate capping pattern GP and an upper surface of the gate spacer GS in the third direction D3.

[0067] A second interlayer insulating layer 120 at least partially covering the gate capping pattern GP may be disposed on the first interlayer insulating layer 110 .

[0068] For example, the first interlayer insulating layer 110 and the second interlayer insulating layer 120 may each include a silicon oxide layer.

[0069] Reference again Figures 2 to 4 , a pair of separation structures DB facing each other in the second direction D2 may be disposed on both sides of the logic cell LC. The separation structure DB may extend parallel to the gate pattern GE in the first direction D1. A pitch between the separation structure DB and the gate pattern GE adjacent thereto may be the same as the first pitch P1.

[0070] The partition structure DB may penetrate or extend into the first interlayer insulating layer 110 and the second interlayer insulating layer 120, and extend into the first active pattern AP1 and the second active pattern AP2. The partition structure DB may penetrate or extend into an upper portion of each of the first active pattern AP1 and the second active pattern AP2. The partition structure DB may separate the PMOSFET region PR and the NMOSFET region NR of the logic cell LC from the active region of the adjacent logic cell.

[0071] The upper portion of each of the first active pattern AP1 and the second active pattern AP2 may further include a sacrificial layer SAL adjacent to the separation structure DB. The sacrificial layers SAL may be stacked to be spaced apart from each other. The sacrificial layer SAL may be located at the same height as the first portion PO1, the second portion PO2, and the third portion PO3 of the gate pattern GE in the third direction D3, respectively. The separation structure DB may penetrate or extend into the sacrificial layer SAL.

[0072] The sacrificial layers SAL may include silicon germanium (SiGe). The concentration of germanium (Ge) in each sacrificial layer SAL may be 10 to 30 at%. The concentration of germanium (Ge) in the sacrificial layers SAL may be higher than that in the first semiconductor layer described above.

[0073] The upper active contacts AC may penetrate or extend into the first interlayer insulating layer 110 and the second interlayer insulating layer 120 and be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. For example, a pair of upper active contacts AC may be disposed between the gate patterns GE. From a plan view, the upper active contacts AC may be in the shape of a strip extending in the first direction D1.

[0074] The silicide patterns SC may be disposed between the upper active contact AC and the first source / drain pattern SD1 and between the upper active contact AC and the second source / drain pattern SD2, respectively. The upper active contact AC may be electrically connected to each of the first source / drain pattern SD1 and the second source / drain pattern SD2 through the silicide pattern SC. The silicide pattern SC may include a metal silicide, such as titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide, or a combination thereof.

[0075] The upper gate contact GC may penetrate or extend into the second interlayer insulating layer 120 and the gate capping pattern GP and be electrically connected to the gate pattern GE. Figure 4 , an upper portion of each upper active contact AC adjacent to the upper gate contact GC may be at least partially filled with the upper insulating pattern UIP. Therefore, a process defect of short circuit due to the upper gate contact GC contacting the adjacent upper active contact AC may be reduced or prevented.

[0076] The upper active contact AC and the upper gate contact GC may each include a conductive pattern FM and a barrier pattern BM at least partially surrounding the conductive pattern FM. For example, the conductive pattern FM may include aluminum, copper, tungsten, molybdenum, or a combination thereof. The barrier pattern BM may at least partially cover the sidewall and bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal layer or a metal nitride layer. The metal layer may include titanium, tantalum, tungsten, nickel, cobalt, platinum, or a combination thereof. The metal nitride layer may include a titanium nitride layer (TiN), a tantalum nitride layer (TaN), a tungsten nitride layer (WN), a nickel nitride layer (NiN), a cobalt nitride layer (CoN), a platinum nitride layer (PtN), or a combination thereof.

[0077] The first upper interlayer insulating layer 130 may be located over the upper active contact AC and the upper gate contact GC in the third direction D3 , and at least partially cover the upper active contact AC and the upper gate contact GC.

[0078] The first upper metal layer M1 may be disposed within the first upper interlayer insulating layer 130. The first upper metal layer M1 may include a first upper power wiring M1_R, a first upper wiring M1_I, and a first upper via VI1.

[0079] The first upper via VI1 may be disposed under the first upper power wiring M1_R and the first upper wiring M1_I in the third direction D3 .

[0080] Each of the first upper power wirings M1_R may extend across the logic cells LC in the second direction D2. Each of the first upper power wirings M1_R may be a power wiring. For example, a drain voltage VDD or a source voltage VSS may be applied to the first upper power wirings M1_R.

[0081] refer to Figure 2 , a first cell boundary CB1 extending in the second direction D2 may be defined in the logic cell LC. In the logic cell LC, the second cell boundary CB2 extending in the second direction D2 may be defined on the opposite side of the first cell boundary CB1. A first upper power wiring M1_R to which a drain voltage VDD (i.e., a power supply voltage) is applied may be disposed on the first cell boundary CB1. The first upper power wiring M1_R to which the drain voltage VDD is applied may extend in the second direction D2 along the first cell boundary CB1. The first upper power wiring M1_R to which a source voltage VSS (i.e., a ground voltage) is applied may be disposed on the second cell boundary CB2. The first upper power wiring M1_R to which the source voltage VSS is applied may extend in the second direction D2 along the second cell boundary CB2.

[0082] The first upper wiring M1_I may be disposed in the first direction D1 between the first upper power wiring M1_R to which the drain voltage VDD is applied and the first upper power wiring M1_R to which the source voltage VSS is applied. Each of the first upper wirings M1_I may have a line shape or a bar shape extending in the second direction D2. The first upper wirings M1_I may be arranged along the first direction D1 at a second pitch P2. The second pitch P2 may be smaller than the first pitch P1.

[0083] The first upper via VI1 may be disposed below the first upper power wiring M1_R and the first upper wiring M1_I. The first upper via VI1 may be disposed between the upper active contact AC and the first upper power wiring M1_R and between the upper active contact AC and the first upper wiring M1_I, respectively. In addition, the first upper via VI1 may be disposed between the upper gate contact GC and the first upper wiring M1_I, respectively.

[0084] The second upper interlayer insulating layer 140 may be located on the first upper interlayer insulating layer 130 and at least partially cover the first upper interlayer insulating layer 130 .

[0085] The second upper metal layer M2 may be disposed within the second upper interlayer insulating layer 140. The second upper metal layer M2 may include second upper wirings M2_I. Each second upper wiring M2_I may have a linear or bar shape extending in the first direction D1. In other words, the second upper wirings M2_I may extend parallel to each other in the first direction D1. From a plan view, the second upper wirings M2_I may be parallel to the gate pattern GE. The second upper wirings M2_I may be disposed along the second direction D2 at a third pitch P3. The third pitch P3 may be smaller than the first pitch P1. The third pitch P3 may be greater than the second pitch P2.

[0086] The second upper metal layer M2 may further include a second upper via VI2. The second upper via VI2 may be disposed below the second upper wiring M2_I in the third direction D3. The second upper via VI2 may be disposed between the first upper power wiring M1_R and the second upper wiring M2_I and between the first upper wiring M1_I and the second upper wiring M2_I, respectively.

[0087] The first upper power wiring M1_R and the first upper wiring M1_I of the first upper metal layer M1 and the second upper wiring M2_I of the second upper metal layer M2 may include the same conductive material as each other or conductive materials different from each other. For example, the first upper power wiring M1_R, the first upper wiring M1_I and the second upper wiring M2_I may include aluminum, copper, tungsten, molybdenum, cobalt or a combination thereof.

[0088] Although not shown, in some embodiments, upper metal layers (eg, M3, M4, M5, etc.) stacked on the second upper interlayer insulating layer 140 may be additionally provided. The stacked upper metal layers may each include routing wires.

[0089] The lower active contact ACb may be located under the first and second source / drain patterns SD1 and SD2 in the third direction D3 and electrically connected to the first and second source / drain patterns SD1 and SD2, respectively. The lower active contact ACb may have a bar shape extending in the first direction D1 in a plan view.

[0090] For example, the lower active contact ACb may penetrate or extend into the first and second active patterns AP1 and AP2 and be electrically connected to the first and second source / drain patterns SD1 and SD2 , respectively.

[0091] The silicide patterns SC may be disposed between the lower active contact ACb and the first source / drain pattern SD1 and between the lower active contact ACb and the second source / drain pattern SD2, respectively. The lower active contact ACb may be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2 through the silicide pattern SC. The silicide pattern SC may include a metal silicide, such as titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, cobalt silicide, or a combination thereof.

[0092] The lower gate contact GCb may be located below the gate pattern GE in the third direction D3 and electrically connected to the gate pattern GE. For example, the lower gate contact GCb may penetrate or extend into the first active pattern AP1 and be electrically connected to the first source / drain pattern SD1. However, embodiments of the present disclosure are not limited thereto, and the lower gate contact GCb may penetrate or extend into the second active pattern AP2 and be electrically connected to the second source / drain pattern SD1.

[0093] The lower active contact ACb and the lower gate contact GCb may each include a conductive pattern FM and a barrier pattern BM at least partially surrounding the conductive pattern FM. For example, the conductive pattern FM may include a metal, and the metal includes aluminum, copper, tungsten, molybdenum, or a combination thereof. The barrier pattern BM may at least partially cover the sidewall and bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal layer or a metal nitride layer. The metal layer may include titanium, tantalum, tungsten, nickel, cobalt, platinum, or a combination thereof. The metal nitride layer may include a titanium nitride layer (TiN), a tantalum nitride layer (TaN), a tungsten nitride layer (WN), a nickel nitride layer (NiN), a cobalt nitride layer (CoN), a platinum nitride layer (PtN), or a combination thereof.

[0094] The first lower interlayer insulating layer 130 b may be located under the lower active contact ACb and the lower gate contact GCb in the third direction D3 , and at least partially cover the lower active contact ACb and the lower gate contact GCb.

[0095] The first lower metal layer M1b may be disposed in the first lower interlayer insulating layer 130b. The first lower metal layer M1b may include a first lower power wiring M1_Rb, a first lower wiring M1_Ib, and a first lower via VI1b. The first lower via VI1b may be disposed on the first lower power wiring M1_Rb and the first lower wiring M1_Ib.

[0096] Each of the first lower power wirings M1_Rb may extend across the logic cells LC in the second direction D2. The first lower power wirings M1_Rb may be power wirings. For example, a drain voltage VDD or a source voltage VSS may be applied to the first lower power wirings M1_Rb.

[0097] The first lower power wiring M1_Rb to which the drain voltage VDD is applied may extend in the second direction D2. In addition, the first lower power wiring M1_Rb to which the source voltage VSS is applied may extend in the second direction D2.

[0098] The first lower wiring M1_Ib may be disposed in the first direction D1 between the first lower power wiring M1_Rb to which the drain voltage VDD is applied and the first lower power wiring M1_Rb to which the source voltage VSS is applied. Each of the first lower wirings M1_Ib may have a line shape or a bar shape extending in the second direction D2. The first lower wirings M1_Ib may be disposed in the first direction D1 at a second pitch P2. The second pitch P2 may be smaller than the first pitch P1.

[0099] The first lower via VI1b may be disposed above the first lower power wiring M1_Rb and the first lower wiring M1_Ib in the third direction D3. The first lower via VI1b may be disposed between the lower active contact ACb and the first lower power wiring M1_Rb and between the lower active contact ACb and the first lower wiring M1_Ib, respectively. In addition, the first lower via VI1b may be disposed between the lower gate contact GCb and the first lower wiring M1_Ib, respectively.

[0100] The second lower interlayer insulating layer 140 b may be located below the first lower interlayer insulating layer 130 b in the third direction D3 and at least partially cover the first lower interlayer insulating layer 130 b .

[0101] The second lower metal layer M2b may be disposed within the second lower interlayer insulating layer 140b. The second lower metal layer M2b may include second lower wirings M2_Ib. Each second lower wiring M2_Ib may have a linear or bar shape extending in the first direction D1. In other words, the second lower wirings M2_Ib may extend parallel to each other in the first direction D1. From a plan view, the second lower wirings M2_Ib may be parallel to the gate pattern GE. The second lower wirings M2_Ib may be disposed at a third pitch P3 in the second direction D2. The third pitch P3 may be smaller than the first pitch P1. The third pitch P3 may be greater than the second pitch P2.

[0102] The second lower metal layer M2b may further include a second lower via VI2b. The second lower via VI2b may be disposed above the second lower wiring M2_Ib in the third direction D3. The second lower via VI2b may be disposed between the first lower power wiring M1_Rb and the second lower wiring M2_Ib and between the first lower wiring M1_Ib and the second lower wiring M2_Ib, respectively.

[0103] The first lower power wiring M1_Rb and the first lower wiring M1_Ib of the first lower metal layer M1b and the second lower wiring M2_Ib of the second lower metal layer M2b may include the same conductive material as each other or conductive materials different from each other. For example, the first lower power wiring M1_Rb, the first lower wiring M1_Ib and the second lower wiring M2_Ib may include aluminum, copper, tungsten, molybdenum, cobalt or a combination thereof.

[0104] refer to Figure 7 The second set of key regions KER2 of the substrate 100 includes a backside key pattern BK and a frontside key pattern FK.

[0105] The backside key pattern BK and the frontside key pattern FK may be located within the substrate 100. For example, the backside key pattern BK and the frontside key pattern FK may be located within the device isolation layer ST.

[0106] The back key pattern BK and the front key pattern FK may be portions extending in the third direction D3 within the device isolation layer ST. On a plane, a plurality of back key patterns BK may be spaced apart at a constant pitch and arranged two-dimensionally. For example, the back key pattern BK may be arranged in a chessboard shape in the first direction D1 and the second direction D2. Similarly, on a plane, a plurality of front key patterns FK may be spaced apart at a constant pitch and arranged two-dimensionally. For example, the front key pattern FK may be arranged in a chessboard shape in the first direction D1 and the second direction D2. For example, the back key pattern BK and the front key pattern FK may each include silicon oxide.

[0107] The substrate 100 may have a first surface and a second surface that are separated from each other in the third direction D3. The first surface of the substrate 100 is positioned closer to the first lower interlayer insulating layer 130b than the second surface. In other words, the first surface of the substrate 100 may be the lower surface LS_100, and the second surface of the substrate 100 may be the upper surface US_100.

[0108] In addition, the back side key pattern BK may have a first surface and a second surface that are separated from each other in the third direction D3. The first surface of the back side key pattern BK is positioned closer to the first lower interlayer insulating layer 130b than the second surface. In other words, the first surface of the back side key pattern BK may be the lower surface LS_BK, and the second surface of the back side key pattern BK may be the upper surface US_BK.

[0109] In addition, the front key pattern FK may have a first surface and a second surface that are separated from each other in the third direction D3. The first surface of the front key pattern FK is positioned closer to the first lower interlayer insulating layer 130b than the second surface. In other words, the first surface of the front key pattern FK may be the lower surface LS_FK, and the second surface of the back key pattern BK may be the upper surface US_FK.

[0110] For example, relative to the first lower interlayer insulating layer 130b, the lower surface LS_BK of the backside key pattern BK may be located at substantially the same height as the lower surface LS_100 of the substrate 100 in the third direction D3, that is, the lower surface LS_BK of the backside key pattern BK and the lower surface LS_100 of the substrate 100 may be substantially coplanar. That is, the lower surface LS_BK of the backside key pattern BK may penetrate or extend into the lower surface LS_100 of the substrate 100 and contact the upper surface US_130b of the first lower interlayer insulating layer 130b.

[0111] Relative to the first lower interlayer insulating layer 130 b, the upper surface US_BK of the backside key pattern BK may be located at substantially the same height as the upper surface US_100 of the substrate 100 in the third direction D3. That is, the upper surface US_BK of the backside key pattern BK may penetrate or extend into the upper surface US_100 of the substrate 100 and contact the lower surface LS_120 of the second interlayer insulating layer 120.

[0112] In other words, the backside key pattern BK may extend from the lower surface LS_100 to the upper surface US_100 of the substrate 100 in the third direction D3 , and the backside key pattern BK may completely penetrate or extend from the lower surface LS_100 to the upper surface US_100 of the substrate 100 in the third direction D3 .

[0113] Therefore, when using the back side key pattern BK exposed on the lower surface LS_100 of the substrate 100, the lower gate contact GCb can be aligned with the gate pattern GE located on the front surface when formed, and the lower active contact ACb can be aligned with the first source / drain pattern SD1 and the second source / drain pattern SD2 located on the front surface when formed, when the lower active contact ACb is formed after the lower gate contact GCb is first formed, the lower gate contact GCb and the lower active contact ACb can be aligned, or when the lower gate contact GCb is formed after the lower active contact ACb is first formed, the lower active contact ACb and the lower gate contact GCb can be aligned. Therefore, when the back side power distribution network (BSPDN) structure is applied, the alignment error between the lower active contact ACb and the lower gate contact GCb located on the back surface and the first source / drain pattern SD1 and the second source / drain pattern SD2 and the gate pattern GE located on the front surface can be reduced.

[0114] The front side key pattern FK may be spaced apart from the lower surface LS_100 of the substrate 100. In other words, relative to the first lower interlayer insulating layer 130b, the lower surface LS_FK of the front side key pattern FK may be located at a height higher than the lower surface LS_100 of the substrate 100 in the third direction D3. That is, the lower surface LS_FK of the front side key pattern FK may be positioned farther away from the first lower interlayer insulating layer 130b than the lower surface LS_100 of the substrate 100. Therefore, the lower surface LS_FK of the front side key pattern FK does not penetrate or extend into the lower surface LS_100 of the substrate 100, and does not contact the upper surface US_130b of the first lower interlayer insulating layer 130b.

[0115] Relative to the first lower interlayer insulating layer 130b, the upper surface US_FK of the front side key pattern FK may be located at substantially the same height as the upper surface US_100 of the substrate 100 in the third direction D3, that is, the upper surface US_FK of the front side key pattern FK and the upper surface US_100 of the substrate 100 may be substantially coplanar. That is, the upper surface US_FK of the front side key pattern FK may penetrate or extend into the upper surface US_100 of the substrate 100 and contact the lower surface LS_120 of the second interlayer insulating layer 120.

[0116] Therefore, when using the front side key pattern FK exposed on the upper surface US_100 of the substrate 100, the upper gate contact GC can be aligned with the gate pattern GE when formed, and the upper active contact AC can be aligned with the first source / drain pattern SD1 and the second source / drain pattern SD2 when formed, and when the upper active contact AC is formed after the upper gate contact GC is first formed, the upper gate contact GC and the upper active contact AC can be aligned, or when the upper gate contact GC is formed after the upper active contact AC is first formed, the upper active contact AC and the upper gate contact GC can be aligned.

[0117] As described above, relative to the first lower interlayer insulating layer 130b, the lower surface LS_BK of the back side key pattern BK is located at substantially the same height as the lower surface LS_100 of the substrate 100 in the third direction D3, and the lower surface LS_FK of the front side key pattern FK is located at a height higher than the lower surface LS_100 of the substrate 100 in the third direction D3, and therefore, the lower surface LS_BK of the back side key pattern BK can be positioned to be closer to the lower surface LS_100 of the substrate 100 than the lower surface LS_FK of the front side key pattern FK.

[0118] In addition, with respect to the first lower interlayer insulating layer 130b, the length H_BK of the back side key pattern BK in the third direction D3 may be substantially the same as the length H_100 of the substrate 100 in the third direction D3. The length H_BK of the back side key pattern BK in the third direction D3 may be greater than the length H_FK of the front side key pattern FK in the third direction D3. With respect to the first lower interlayer insulating layer 130b, the length H_FK of the front side key pattern FK in the third direction D3 may be less than the length H_100 of the substrate 100 in the third direction D3.

[0119] Here, the length H_100 of the substrate 100 in the third direction D3 may be the shortest length in the third direction D3 from the lower surface LS_100 to the upper surface US_100 of the substrate 100, the length H_BK of the back side key pattern BK in the third direction D3 may be the shortest length in the third direction D3 from the lower surface LS_BK of the back side key pattern BK to the upper surface US_BK, and the length H_FK of the front side key pattern FK in the third direction D3 may be the shortest length in the third direction D3 from the lower surface LS_FK of the front side key pattern FK to the upper surface US_FK.

[0120] The third active pattern AP3 may be disposed on the second set keying region KER2 of the substrate 100 .

[0121] The third active pattern AP3 is a portion of the substrate 100 and may be a portion protruding in the third direction D3. The third active pattern AP3 may be spaced apart in the first direction D1. The third active pattern AP3 may extend in the second direction D2.

[0122] The third active pattern AP3 may include silicon (Si) or germanium (Ge) as an elemental semiconductor material. In addition, the third active pattern AP3 may include a compound semiconductor, such as a group IV-IV compound semiconductor or a group III-V compound semiconductor. The group IV-IV compound semiconductor may be, for example, a binary compound or a ternary compound containing carbon (C), silicon (Si), germanium (Ge), tin (Sn), or a combination thereof. The group III-V compound semiconductor may be, for example, a binary compound, a ternary compound, or a quaternary compound formed by combining a group III element such as aluminum (Al), gallium (Ga), indium (In), or a combination thereof and a group V element such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof.

[0123] For example, in the second set of key regions KER2, the device isolation layer ST may at least partially cover the third active pattern AP3. In other words, in the second set of key regions KER2, the device isolation layer ST of the substrate 100 may extend from the lower surface LS_100 of the substrate 100 to the upper surface US_100 in the third direction D3, and the device isolation layer ST may contact the lower surface LS_120 of the second interlayer insulating layer 120. As described above, the back side key pattern BK and the front side key pattern FK may be located within the device isolation layer ST.

[0124] The device isolation layer ST may be located between the third active patterns AP3. In other words, the device isolation layer ST may be located close to the third active patterns AP3 in the first direction D1. The device isolation layer ST may at least partially fill the trench between the third active patterns AP3.

[0125] exist Figure 7 In the embodiment, the back key pattern BK and the front key pattern FK are located on both sides of the third active pattern AP3 in the first direction D1, but the embodiments of the present disclosure are not limited thereto, and the arrangement order and shape of the third active pattern AP3, the back key pattern BK and the front key pattern FK are not limited thereto. For example, the third active pattern AP3 may be located only on one side of the back key pattern BK, or may be located only on one side of the front key pattern FK, etc. In addition, in Figure 7 In the embodiment, the third active pattern AP3, the back key pattern BK and the front key pattern FK are each disposed one by one, but the embodiments of the present disclosure are not limited thereto, and a plurality of third active patterns AP3, a plurality of back key patterns BK and a plurality of front key patterns FK may be disposed in the first direction D1.

[0126] For example, in the second set key region KER2, the sacrificial layer SAL and the active layer ACL may be disposed on the third active pattern AP3.

[0127] The sacrificial layers SAL and the active layers ACL may be alternately stacked in the third direction D3. The sacrificial layers SAL may be stacked to be spaced apart from each other in the third direction D3, and the active layers ACL may be stacked to be spaced apart from each other in the third direction D3. The sacrificial layers SAL may be located at the same height as the first portion PO1, the second portion PO2, and the third portion PO3 of the gate pattern GE of the logic cell region CER in the third direction D3, respectively.

[0128] The sacrificial layer SAL may include silicon (Si), germanium (Ge), or silicon germanium (SiGe), and the active layer ACL may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, the sacrificial layer SAL may include silicon germanium (SiGe), and the active layer ACL may include silicon (Si). The concentration of germanium (Ge) in each sacrificial layer SAL may be 10 at % to 30 at %.

[0129] For example, the lower surface LS_FK of the front side key pattern FK may be located at a lower height than the sacrificial layer SAL in the third direction D3. Here, relative to the first lower interlayer insulating layer 130b, the height of the sacrificial layer SAL in the third direction D3 may be the height in the third direction D3 of the portion where the sacrificial layer SAL located at the lowest end contacts the third active pattern AP3.

[0130] Figures 8 to 42 are cross-sectional views illustrating intermediate operations of methods of fabricating a semiconductor device according to some embodiments.

[0131] Figure 8 , Fig.11 , Fig.16 , Fig.18 , Fig.21 , Fig.25 , Fig.29 , Fig.33 and Fig.38 It is along Figure 2 A cross-sectional view taken along line AA'. Fig. 22 , Fig.26 , Fig.30 , Fig.34 and Fig.39 It is along Figure 2 A cross-sectional view taken along line BB'. Fig. 9 , Fig.12 , Fig.17 , Fig.19 , Fig.23 , Fig. 27 , Fig.31 , Fig.35 and Fig.40 It is along Figure 2 A cross-sectional view taken along line CC'. Fig. 20 , Fig.24 , Fig.28 , Fig.32 , Fig.36 and Fig.41 It is along Figure 2 A cross-sectional view taken along line D-D'. Fig.10 , Fig.13 , Fig.14 , Fig.15 , Fig.37 and Fig.42 It is shown Figure 1 A cross-sectional view of the second set of key engraving areas KER2.

[0132] refer to Figures 8 to 10 , a substrate 100 including a PMOSFET region PR and an NMOSFET region NR is formed.

[0133] First, alternately stacked sacrificial layers SAL and active layers ACL are formed on a substrate 100. The sacrificial layers SAL may include silicon (Si), germanium (Ge), or silicon germanium (SiGe), and the active layers ACL may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). For example, the sacrificial layers SAL may include silicon germanium (SiGe), and the active layers ACL may include silicon (Si). The concentration of germanium (Ge) in each sacrificial layer SAL may be 10 at % to 30 at %.

[0134] Mask patterns may be respectively formed on the PMOSFET region PR, the NMOSFET region NR, and the second set key region KER2 of the substrate 100. The mask pattern may have a line shape or a stripe shape extending in the second direction D2.

[0135] By performing a patterning process using the mask pattern as an etching mask, trenches defining the first active pattern AP1, the second active pattern AP2, and the third active pattern AP3 may be formed, and the lower substrate 101 may be formed on the bottom surfaces of the trenches. Therefore, in the logic cell region CER, the first active pattern AP1 and the second active pattern AP2 may be formed in the PMOSFET region PR and the NMOSFET region NR, respectively, and the first active pattern AP1, the second active pattern AP2, and the third active pattern AP3 may be formed on the second set key region KER2.

[0136] Each of the first, second, and third active patterns AP1, AP2, and AP3 may include sacrificial layers SAL and active layers ACL alternately stacked on an upper portion thereof.

[0137] refer to Figures 11 to 13 , a device isolation layer ST is formed on the lower substrate 101 to at least partially fill the trench.

[0138] For example, the device isolation layer ST may be formed to cover the entire first, second, and third active patterns AP1, AP2, and AP3.

[0139] The device isolation layer ST may include an insulating material such as a silicon oxide layer.

[0140] refer to Fig.14 , a back side key pattern recess BKR and a front side key pattern recess FKR are formed in the second set key engraving area KER2.

[0141] First, a mask pattern may be formed on the first and second active patterns AP1 and AP2 of the logic cell region CER and the third active pattern AP3 of the second set key region KER2, respectively. The mask pattern may have a line shape or a stripe shape extending in the second direction D2.

[0142] By performing a patterning process using the mask pattern as an etching mask, the first and second active patterns AP1 and AP2 of the second set key region KER2 are removed, and a backside key pattern recess BKR and a frontside key pattern recess FKR are formed in the second set key region KER2.

[0143] refer to Fig.15 , a back side key pattern BK and a front side key pattern FK are formed in the second set key engraving area KER2.

[0144] For example, the back side key pattern BK and the front side key pattern FK may be formed in the second set key region KER2 by filling the back side key pattern recess BKR and the front side key pattern recess FKR of the second set key region KER2 with an insulating material such as silicon oxide.

[0145] refer to Fig.16 and Fig.17 , exposing the sacrificial layer SAL located on upper portions of the first and second active patterns AP1 and AP2.

[0146] For example, a mask pattern is formed on the first and second active patterns AP1 and AP2 of the logic cell region CER, a patterning process is performed using the mask pattern as an etching mask, and the device isolation layer ST is recessed until the sacrificial layer SAL is exposed.

[0147] Therefore, an upper portion of each of the first and second active patterns AP1 and AP2 may be exposed above the device isolation layer ST. In other words, an upper portion of each of the first and second active patterns AP1 and AP2 may protrude from the device isolation layer ST in the third direction D3.

[0148] At this time, a mask pattern is formed on the entire second set of key regions KER2, and the device isolation layer ST located in the second set of key regions KER2 may not be etched. Figure 7 As shown, in the second set of key regions KER2 , the device isolation layer ST of the substrate 100 may be formed to extend from the lower surface LS_100 to the upper surface US_100 of the substrate 100 in the third direction D3 .

[0149] refer to Fig.18 and Fig. 20 , a sacrificial pattern PP is formed crossing the first and second active patterns AP1 and AP2 , and first and second recesses RS1 and RS2 are formed in upper portions of the first and second active patterns AP1 and AP2 , respectively.

[0150] First, the sacrificial pattern PP may be formed by forming a sacrificial layer on the entire surface of the lower substrate 101 , forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etch mask.

[0151] For example, the sacrificial pattern PP may be formed in a line shape or a bar shape extending in the first direction D1. The sacrificial pattern PP may be arranged at a certain pitch in the second direction D2. The sacrificial layer may include polysilicon.

[0152] At this time, the hard mask pattern MP may cover the entire surface of the second set key region KER2, and therefore, a sacrificial layer is not formed in the second set key region KER2, and as shown in FIG. Fig.15 As shown, the device isolation layer ST may cover the third active pattern AP3.

[0153] Next, a pair of gate spacers GS may be formed on both sidewalls of each of the sacrificial patterns PP.

[0154] For example, the gate spacer GS may be formed by conformally forming a gate spacer layer on the entire surface of the lower substrate 101 and anisotropically etching the gate spacer layer.

[0155] For example, the gate spacer layer may include SiCN, SiCON, SiN, or a combination thereof. In addition, the gate spacer layer may include a multilayer including SiCN, SiCON, SiN, or a combination thereof.

[0156] Next, a first recess RS1 may be formed in an upper portion of the first active pattern AP1, and a second recess RS2 may be formed in an upper portion of the second active pattern AP2. While forming the first recess RS1 and the second recess RS2, the upper surface of the device isolation layer ST at both sides of each of the first active pattern AP1 and the second active pattern AP2 may be recessed (see Fig.19 ).

[0157] For example, the first recess RS1 may be formed by etching the upper portion of the first active pattern AP1 using the hard mask pattern MP and the gate spacer GS as an etching mask. The first recess RS1 may be formed between the pair of sacrificial patterns PP. The second recess RS2 in the upper portion of the second active pattern AP2 may be formed in the same manner as the first recess RS1.

[0158] As described above, the hard mask pattern MP may cover the entire surface of the second set keying region KER2, and thus, the recess may not be formed in the third active pattern AP3 of the second set keying region KER2.

[0159] refer to Figure 21 to Figure 24, a first source / drain pattern SD1 is formed in the first recess RS1 , and a second source / drain pattern SD2 is formed in the second recess RS2 .

[0160] For example, the first semiconductor layer may be formed by performing a first selective epitaxial growth (SEG) process using the inner wall of the first recess RS1 as a seed layer. The first semiconductor layer may be grown using the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 and the first active pattern AP1 exposed by the first recess RS1 as seeds. For example, the first SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0161] The first semiconductor layer may include a semiconductor element (e.g., SiGe) having a lattice constant greater than that of the semiconductor element of the first active pattern AP1. The first semiconductor layer may contain a relatively low concentration of germanium (Ge). For another example, the first semiconductor layer may contain only silicon (Si) but not germanium (Ge). The concentration of germanium (Ge) in the first semiconductor layer may be 0 at % to 10 at %.

[0162] The second semiconductor layer may be formed by performing a second SEG process on the first semiconductor layer. The second semiconductor layer may be formed in the first recess RS1. The second semiconductor layer may contain a relatively high concentration of germanium (Ge). For example, the concentration of germanium (Ge) in the second semiconductor layer may be 30 at % to 70 at %.

[0163] The first semiconductor layer and the second semiconductor layer may constitute a first source / drain pattern SD1. During the first SEG process and the second SEG process, impurities may be implanted in situ. For another example, after forming the first source / drain pattern SD1, impurities may be implanted into the first source / drain pattern SD1. The first source / drain pattern SD1 may be doped to have a first conductivity type (e.g., p-type).

[0164] Next, the second source / drain pattern SD2 may be formed by performing a SEG process using the inner wall of the second recess RS2 as a seed layer. For example, the second source / drain pattern SD2 may be grown using the first, second, and third semiconductor patterns SP1, SP2, and SP3 and the second active pattern AP2 exposed by the second recess RS2 as seeds.

[0165] For example, the second source / drain pattern SD2 may include the same semiconductor element (eg, Si) as the second active pattern AP2. The second source / drain pattern SD2 may be doped to have a second conductivity type (eg, n type).

[0166] refer to Figure 25 to Figure 28, after forming the first interlayer insulating layer 110 , the sacrificial pattern PP is removed, and the exposed sacrificial layer SAL is removed.

[0167] First, a first interlayer insulating layer 110 covering the first and second source / drain patterns SD1 and SD2, the hard mask pattern MP, and the gate spacer GS is formed. For example, the first interlayer insulating layer 110 may include a silicon oxide layer.

[0168] Next, the first interlayer insulating layer 110 may be planarized until the upper surface of the sacrificial pattern PP is exposed. The planarization of the first interlayer insulating layer 110 may be performed using an etch-back or chemical mechanical polishing (CMP) process. During the planarization process, the hard mask pattern MP may be completely removed. As a result, the upper surface of the first interlayer insulating layer 110 may be located at substantially the same height as the upper surface of the sacrificial pattern PP and the upper surface of the gate spacer GS in the third direction D3.

[0169] The exposed sacrificial pattern PP may be selectively removed. The sacrificial pattern PP is removed, and thus, a first empty space ET1 exposing the first and second active patterns AP1 and AP2 may be formed.

[0170] Meanwhile, some sacrificial patterns PP may not be removed. For example, sacrificial patterns PP located at cell boundaries may not be removed. For example, a mask pattern is formed on sacrificial patterns PP that do not need to be removed, and thus, the sacrificial patterns PP may remain without being removed. The sacrificial patterns PP are removed, and thus, the sacrificial layer SAL of each of the first active pattern AP1 and the second active pattern AP2 may be exposed through the first empty space ET1.

[0171] Next, the sacrificial layer SAL exposed through the first empty space ET1 may be selectively removed.

[0172] For example, by performing an etching process to selectively etch the sacrificial layer SAL, only the sacrificial layer SAL may be removed while the first, second, and third semiconductor patterns SP1, SP2, and SP3 remain substantially intact.

[0173] For example, the etching process can have a high etching rate relative to silicon germanium having a relatively high germanium concentration.For example, the etching process can have a high etching rate relative to silicon germanium having a germanium concentration greater than 10 at %.

[0174] During the etching process, the sacrificial layer SAL on the PMOSFET region PR and the NMOSFET region NR may be removed. The etching process may be wet etching. The etching material used in the etching process may relatively quickly remove the sacrificial layer SAL having a relatively high germanium concentration.

[0175] The sacrificial layer SAL is selectively removed, and thus, only the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may remain on each of the first active pattern AP1 and the second active pattern AP2. A second empty space ET12 may be formed by the region from which the sacrificial layer SAL has been removed. The second empty space ET12 may be located between the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0176] refer to Figure 29 to Figure 32 , a gate pattern GE is formed in the first empty space ET1 and the second empty space ET12.

[0177] First, a gate insulating layer GI is conformally formed in the first and second empty spaces ET1 and ET12. Thereafter, a gate pattern GE may be formed on the gate insulating layer GI. The gate pattern GE may be formed in the first and second empty spaces ET1 and ET12 and at least partially fill the first and second empty spaces ET1 and ET12.

[0178] For example, the gate pattern GE may include a first portion PO1, a second portion PO2, and a third portion PO3 at least partially filling the second empty space ET12. The gate pattern GE may further include a fourth portion PO4 filling the first empty space ET1.

[0179] Next, a gate capping pattern GP covering the gate pattern GE may be formed on the gate pattern GE.

[0180] refer to Figure 33 to Figure 37 , an upper active contact AC, an upper gate contact GC and a first upper interlayer insulating layer 130 are formed.

[0181] First, the second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include a silicon oxide layer.

[0182] An upper active contact AC penetrating or extending into the first and second interlayer insulating layers 110 and 120 and electrically connected to the first and second source / drain patterns SD1 and SD2 may be formed.

[0183] In addition, an upper gate contact GC penetrating or extending into the second interlayer insulating layer 120 and the gate capping pattern GP and electrically connected to the gate pattern GE may be formed.

[0184] At this time, when the front side key pattern FK exposed on the upper surface US_100 of the substrate 100 is used, the upper gate contact GC can be aligned with the gate pattern GE when formed, and the upper active contact AC can be aligned with the first source / drain pattern SD1 and the second source / drain pattern SD2 when formed, and when the upper active contact AC is formed after the upper gate contact GC is first formed, the upper gate contact GC and the upper active contact AC can be aligned, or when the upper gate contact GC is formed after the upper active contact AC is first formed, the upper active contact AC and the upper gate contact GC can be aligned.

[0185] For example, a contact hole penetrating or extending into the first and second interlayer insulating layers 110 and 120 and exposing the first and second source / drain patterns SD1 and SD2 may be formed. Next, an upper active contact AC at least partially filling the contact hole and electrically connected to the first and second source / drain patterns SD1 and SD2 is formed. For example, a barrier pattern BM and a conductive pattern FM may be sequentially formed within the contact hole.

[0186] Next, an upper gate contact GC is formed within the second interlayer insulating layer 120 and the gate capping pattern GP.

[0187] First, a contact hole penetrating or extending into the second interlayer insulating layer 120 and the gate capping pattern GP and exposing the fourth portion PO4 of the gate pattern GE may be formed.

[0188] Next, an upper gate contact GC at least partially filling the contact hole and electrically connected to the fourth portion PO4 of the gate pattern GE is formed. For example, a barrier pattern BM and a conductive pattern FM may be sequentially formed within the contact hole.

[0189] In addition, a pair of separation structures DB may be formed at both sides of the logic cell LC. The separation structure DB may penetrate or extend into the second interlayer insulating layer 120, the remaining sacrificial pattern PP, and an upper portion of the first active pattern AP1 or the second active pattern AP2 under the sacrificial pattern PP.

[0190] The separation structure DB may include an insulating material such as silicon oxide or silicon nitride.

[0191] Next, a first upper interlayer insulating layer 130 including a first upper metal layer M1 electrically connected to the upper active contact AC and the upper gate contact GC is formed on an upper surface of each of the second interlayer insulating layer 120 and the gate capping pattern GP.

[0192] In addition, a second upper interlayer insulating layer 140 including a second upper metal layer M2 electrically connected to the first upper metal layer M1 is formed on an upper surface of the first upper interlayer insulating layer 130 .

[0193] like Fig.38 and Fig.42 As shown, the lower substrate 101 is removed.

[0194] First, the semiconductor device can be rotated. However, Fig.38 and Fig.42 A state in which the semiconductor device is not rotated is shown.

[0195] For example, the rotated semiconductor device may be disposed on a carrier substrate (not shown). At this time, the upper surface of the semiconductor device may be positioned to face the carrier substrate, and then attached to the carrier substrate. That is, the second upper interlayer insulating layer 140 located on the upper surface of the semiconductor device may be attached to the carrier substrate. An adhesive member (not shown) may be disposed between the second upper interlayer insulating layer 140 and the carrier substrate.

[0196] The carrier substrate may have substantially the same area as the semiconductor device or an area larger than the semiconductor device. The carrier substrate may be, for example, a semiconductor wafer, a ceramic substrate, or a glass substrate. The bonding member may be in the form of a film.

[0197] The bonding member may include a base film and an adhesive layer attached to both sides of the base film. The base film may be, for example, a polyethylene film, such as polyethylene terephthalate (PET) or polyethylene 2,6-naphthalate (PEN), or a polyolefin film. The base film may be formed by coating siloxane or Teflon on the polyethylene film or the polyolefin film. The adhesive layer may include, for example, an acrylic polymer resin, an epoxy resin, or a mixture thereof.

[0198] Next, the lower substrate 101 may be removed by performing an etching process. The etching process may be performed by, for example, a wet etching method, but is not limited thereto.

[0199] The lower substrate 101 is removed, and thus, the lower surface LS_BK of the back side key pattern BK may penetrate or extend into the lower surface LS_100 of the substrate 100 and be exposed.

[0200] Therefore, when the back side key pattern BK exposed on the lower surface LS_100 of the substrate 100 is used, the lower gate contact GCb can be aligned with the gate pattern GE located on the front surface when formed, and the lower active contact ACb can be aligned with the first source / drain pattern SD1 and the second source / drain pattern SD2 located on the front surface when formed, and when the lower active contact ACb is formed after the lower gate contact GCb is first formed, the lower gate contact GCb and the lower active contact ACb can be aligned, or when the lower gate contact GCb is formed after the lower active contact ACb is first formed, the lower active contact ACb and the lower gate contact GCb can be aligned. Therefore, when the BSPDN structure is applied, the alignment error between the lower active contact ACb and the lower gate contact GCb located on the back surface and the first source / drain pattern SD1 and the second source / drain pattern SD2 and the gate pattern GE located on the front surface can be reduced.

[0201] For example, a patterning process may be performed to remove a portion of the first active pattern AP1 and form a contact hole exposing the first source / drain pattern SD1. At this time, the contact hole may penetrate or extend into the first active pattern AP1. In other words, a side surface of the contact hole may be at least partially surrounded by the first active pattern AP1. However, embodiments of the present disclosure are not limited thereto, and the contact hole may expose the second source / drain pattern SD2 by removing a portion of the second active pattern AP2.

[0202] Next, a lower active contact ACb that at least partially fills the contact hole and is electrically connected to the first source / drain pattern SD1 is formed. For example, a barrier pattern BM and a conductive pattern FM may be sequentially formed within the contact hole. However, the embodiments of the present disclosure are not limited thereto, and the lower active contact ACb may be electrically connected to the second source / drain pattern SD2.

[0203] Next, a patterning process may be performed to remove a portion of the first active pattern AP1 and form a contact hole exposing the first portion PO1 of the gate pattern GE. At this time, the contact hole may penetrate or extend into the first active pattern AP1. In other words, a side surface of the contact hole may be at least partially surrounded by the first active pattern AP1. However, the embodiments of the present disclosure are not limited thereto, and the contact hole may remove a portion of the second active pattern AP2 and expose the first portion PO1 of the gate pattern GE.

[0204] Next, a lower gate contact GCb at least partially filling the contact hole and electrically connected to the first portion PO1 of the gate pattern GE is formed. For example, a barrier pattern BM and a conductive pattern FM may be sequentially formed within the contact hole.

[0205] In the above, a case has been described in which the lower active contact ACb and the lower gate contact GCb are formed in separate processes, but the embodiments of the present disclosure are not limited thereto, and the lower active contact ACb and the lower gate contact GCb may be formed simultaneously, and the lower gate contact GCb may be formed first, and then the lower active contact ACb may be formed.

[0206] Next, a first lower interlayer insulating layer 130b including a first lower metal layer M1b electrically connected to the lower active contact ACb and the lower gate contact GCb is formed on the lower surface of the device isolation layer ST and the first and second active patterns AP1 and AP2.

[0207] In addition, a second lower interlayer insulating layer 140 b including a second lower metal layer M2 b electrically connected to the first lower metal layer M1 b is formed on a lower surface of the first lower interlayer insulating layer 130 b .

[0208] Although the embodiments of the present disclosure have been described in detail above, the scope of the present disclosure is not limited thereto, and various modifications and improvements made by a person of ordinary skill in the art to which the present disclosure belongs also belong to the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a substrate comprising: a logic cell region comprising active patterns spaced apart in a first direction and extending in a second direction different from the first direction; and an overlay key region comprising a backside key pattern and a frontside key pattern; a source / drain pattern, the source / drain pattern being located on the active pattern of the logic cell region and spaced apart in the second direction; a channel pattern, the channel pattern being located between the source / drain patterns; and a gate pattern extending in the first direction, crossing between the source / drain patterns, and surrounding at least a portion of the channel pattern, The substrate has an upper surface and a lower surface which are separated from each other in a third direction different from the first direction and the second direction, and the backside key pattern of the overlay key area extends into the lower surface of the substrate.

2. The semiconductor device according to claim 1, wherein: A lower surface of the backside key pattern and the lower surface of the substrate are substantially coplanar.

3. The semiconductor device according to claim 1, wherein: The backside key pattern extends from the lower surface to the upper surface of the substrate in the third direction.

4. The semiconductor device according to claim 1, wherein: The front side key pattern is spaced apart from the lower surface of the substrate.

5. The semiconductor device according to claim 1, wherein: A lower surface of the backside key pattern is located closer to the lower surface of the substrate than a lower surface of the frontside key pattern.

6. The semiconductor device according to claim 1, wherein: An upper surface of the backside key pattern extends into the upper surface of the substrate, and An upper surface of the front side key pattern extends into the upper surface of the substrate.

7. The semiconductor device according to claim 6, wherein: The upper surface of the back side key pattern and the upper surface of the substrate are located at the same height in the third direction, and The upper surface of the front side key pattern and the upper surface of the substrate are substantially coplanar.

8. The semiconductor device according to claim 1, wherein: The length of the back side key pattern in the third direction is greater than the length of the front side key pattern in the third direction.

9. The semiconductor device according to claim 1, further comprising: an upper active contact, the upper active contact being located above the source / drain pattern in the third direction when the lower surface of the substrate is a base reference plane and connected to the source / drain pattern; as well as An upper gate contact is located above the gate pattern in the third direction when the lower surface of the substrate is the base reference plane and is connected to the gate pattern.

10. The semiconductor device according to claim 9, further comprising: A first upper interlayer insulating layer is located above the upper active contact and the upper gate contact in the third direction when the lower surface of the substrate is the base reference plane, and includes a first upper metal layer.

11. The semiconductor device according to claim 1, further comprising: an interlayer insulating layer, the interlayer insulating layer being located on the substrate, wherein the upper surface of the back side key pattern contacts the lower surface of the interlayer insulating layer, and An upper surface of the front side key pattern contacts the lower surface of the interlayer insulating layer.

12. The semiconductor device according to claim 1, further comprising: a lower active contact located below the source / drain pattern, extending into the active pattern and electrically connected to the source / drain pattern; as well as A lower gate contact is located under the gate pattern, extends into the active pattern, and is electrically connected to the gate pattern.

13. The semiconductor device according to claim 1, further comprising: A first lower interlayer insulating layer is located below the lower active contact and the lower gate contact in the third direction when the lower surface of the substrate is a base reference plane, and includes a first lower metal layer.

14. The semiconductor device according to claim 13, wherein: A lower surface of the backside key pattern contacts an upper surface of the first lower interlayer insulating layer.

15. The semiconductor device according to claim 1, wherein: The backside key pattern includes silicon oxide, and The front side key pattern includes silicon oxide.

16. A semiconductor device, comprising: A substrate comprising: a logic unit region including active patterns spaced apart in a first direction and extending in a second direction different from the first direction; and an overlay key region including a front key pattern and a back key pattern, the substrate having an upper surface and a lower surface diverging from each other in a third direction different from the first direction and the second direction; a source / drain pattern, the source / drain pattern being located on the active pattern of the logic cell region and spaced apart in the second direction; a channel pattern, wherein the channel pattern is located between the source / drain patterns; a gate pattern extending in the first direction, crossing between the source / drain patterns, and surrounding at least a portion of the channel pattern; a lower active contact, the lower active contact being located below the source / drain pattern in the third direction when the lower surface of the substrate is the base reference plane, extending into the active pattern and electrically connected to the source / drain pattern; and a lower gate contact, the lower gate contact being located below the gate pattern in the third direction when the lower surface of the substrate is the base reference plane, extending into the active pattern and electrically connected to the gate pattern; and a first lower interlayer insulating layer, the first lower interlayer insulating layer being located below the lower active contact and the lower gate contact in the third direction when the lower surface of the substrate is the base reference plane, and comprising a first lower metal layer, Wherein, a lower surface of the back side key pattern of the overlay key area contacts the first lower interlayer insulating layer.

17. The semiconductor device according to claim 16, further comprising: an upper active contact, the upper active contact being located above the source / drain pattern in the third direction when the lower surface of the substrate is the base reference plane, and connected to the source / drain pattern; an upper gate contact, the upper gate contact being located above the gate pattern in the third direction and connected to the gate pattern when the lower surface of the substrate is the base reference plane; as well as A first upper interlayer insulating layer is located above the upper active contact and the upper gate contact in the third direction when the lower surface of the substrate is the base reference plane, and includes a first upper metal layer.

18. The semiconductor device according to claim 17, wherein: An upper surface of the back side key pattern contacts a lower surface of the first upper interlayer insulating layer, and An upper surface of the front side key pattern contacts the lower surface of the first upper interlayer insulating layer.

19. A semiconductor device, comprising: a substrate comprising: active patterns spaced apart in a first direction and extending in a second direction different from the first direction; a device isolation pattern located between the active patterns in the first direction; and a backside key pattern and a frontside key pattern located on the device isolation pattern; and a sacrificial layer and an active layer, the sacrificial layer and the active layer being located on the active pattern and alternately stacked in a third direction different from the first direction and the second direction, wherein the backside key pattern extends into the lower surface of the device isolation pattern, and The front side key pattern extends into an upper surface of the device isolation pattern and is spaced apart from a lower surface of the substrate.

20. The semiconductor device according to claim 19, wherein: In a case where the lower surface of the substrate is a base reference plane, a lower surface of the front side key pattern is at a lower height than the sacrificial layer in the third direction.

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