Integrated circuit device and manufacturing method thereof

Abstract

The invention provides an integrated circuit device and a manufacturing method thereof. In one embodiment, a method for fabricating an integrated circuit device includes depositing an epitaxial stack over a substrate, where the epitaxial stack includes a bottom epitaxial stack including a bottom semiconductor layer and a bottom doped sacrificial layer, a sacrificial semiconductor layer over the bottom epitaxial stack, a top epitaxial stack over the sacrificial semiconductor layer, the top epitaxial stack comprises a top semiconductor layer and a top doped sacrificial layer; replacing the doped bottom sacrificial layer, the sacrificial semiconductor layer, and a first portion of the top doped sacrificial layer with a gate structure; and replacing the second portion of the sacrificial semiconductor layer with a dielectric isolation layer.

Description

Technical Field

[0001] This disclosure relates to an integrated circuit device and a method of manufacturing the same. Background Art

[0002] Due to the continuous increase in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.), the semiconductor industry has experienced rapid growth. In most cases, this increase in integration density comes from the repeated reduction of the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0003] According to some embodiments of the present disclosure, a method for manufacturing an integrated circuit device is provided. The method includes depositing an epitaxial stack over a substrate, wherein the epitaxial stack includes a bottom epitaxial stack, a sacrificial semiconductor layer over the bottom epitaxial stack, and a top epitaxial stack over the sacrificial semiconductor layer, the bottom epitaxial stack includes a bottom semiconductor layer and a bottom doped sacrificial layer, and the top epitaxial stack includes a top semiconductor layer and a top doped sacrificial layer; replacing the doped bottom sacrificial layer, the sacrificial semiconductor layer, and a first portion of the top doped sacrificial layer with a gate structure; and replacing a second portion of the sacrificial semiconductor layer with a dielectric isolation layer.

[0004] According to some embodiments of the present disclosure, a method for manufacturing an integrated circuit device is provided. The method includes depositing an epitaxial stack over a substrate, wherein the epitaxial stack includes a bottom epitaxial stack, a sacrificial semiconductor layer over the bottom epitaxial stack, and a top epitaxial stack over the sacrificial semiconductor layer, the bottom epitaxial stack includes a bottom semiconductor layer and a bottom doped sacrificial layer, and the top epitaxial stack includes a top semiconductor layer and a top doped sacrificial layer; removing a first portion of the bottom doped sacrificial layer, the sacrificial semiconductor layer, and the top doped sacrificial layer while exposing a channel region of the top semiconductor layer and a channel region of the bottom semiconductor layer; performing an annealing process to diffuse dopants in a second portion of the bottom doped sacrificial layer into a peripheral region of the bottom semiconductor layer and to diffuse dopants in a second portion of the top doped sacrificial layer into a peripheral region of the top semiconductor layer; and forming a gate structure around the exposed channel regions of the top semiconductor layer and the bottom semiconductor layer.

[0005] According to some embodiments of the present disclosure, an integrated circuit device includes a bottom channel layer, a top channel layer, a gate structure, a first bottom source / drain region, an isolation layer, and a first top source / drain region. The top channel layer is over the bottom channel layer and spaced apart from the bottom channel layer. The gate structure surrounds the bottom channel layer and the top channel layer. The first bottom source / drain region is on a side surface of the bottom channel layer. The isolation layer is over the first bottom source / drain region. The first top source / drain region is over the isolation layer and on a side surface of the top channel layer. Brief Description of the Drawings

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1A to 5B Illustrates a method at various stages of manufacturing an integrated circuit device according to some embodiments;

[0008] Figures 6A to 7B Illustrates a method at various stages of manufacturing an integrated circuit device according to some embodiments;

[0009] Figures 8A to 20B Illustrates a method at various stages of manufacturing an integrated circuit device according to some embodiments;

[0010] Figure 21A And Figure 21B Illustrates the p-type dopant distribution and level in the epitaxial stack before and after an annealing process according to some embodiments, respectively;

[0011] Figures 22 to 25 Illustrates a method at various stages of manufacturing an integrated circuit device according to some embodiments.

[0012] [Symbol Description]

[0013] 110: Substrate

[0014] 112: Substrate portion

[0015] 120: Epitaxial stack

[0016] 120B: Bottom epitaxial stack

[0017] 120T: Top epitaxial stack

[0018] 121: Layer

[0019] 122: Layer, nanosheet

[0020] 123: Layer

[0021] 124: Layer

[0022] 125: Layer, nanosheet

[0023] 130: Isolation structure

[0024] 140: Dielectric layer

[0025] 152:Dummy gate electrode

[0026] 154: Gate spacer

[0027] 160: Interlayer dielectric layer

[0028] 180: Gate structure

[0029] 182: Gate dielectric layer

[0030] 182a: Interface layer

[0031] 182b: High-k gate dielectric layer

[0032] 184: Gate metal layer

[0033] 190: Dielectric isolation layer

[0034] 190A~190B: Dielectric isolation layer

[0035] 190AB~190BB: Isolation layer

[0036] 190V: Void

[0037] 192: Bottom part

[0038] 194: Top part

[0039] 196: Side part

[0040] 198: Side part

[0041] 200: Dielectric barrier layer

[0042] 212~214: Contact socket

[0043] BR1~BR2: Lateral groove

[0044] FS: Fin

[0045] GT: Gate trench

[0046] O1~O2: Opening / Space

[0047] O21~O22: Opening / Space

[0048] S1~S2: Sidewall

[0049] SDB: Source / drain region

[0050] SDT: Source / drain region

[0051] T1: Trench

[0052] TH1~TH2: Trench opening Detailed implementation manner

[0053] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first feature is formed in direct contact with the second feature, and may also include embodiments where additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. Further, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0054] In addition, for ease of description, spatially relative terms, such as "below", "beneath", "lower", "above", "upper", and the like, may be used herein to describe the relationship of one element or feature shown in the figures to another (or others). Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0055] A gate all around (GAA) transistor structure can be patterned by any suitable method. For example, one or more optical lithography processes, including double patterning or multiple patterning processes, can be used to pattern the structure. Generally, double patterning or multiple patterning processes combine optical lithography with self-alignment processes, thereby allowing the generation of patterns having a pitch smaller, for example, than that obtainable using a single direct optical lithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0056] The term "multi-gate device" is used to describe a device (e.g., a semiconductor transistor) having at least some gate material on multiple sides of at least one channel disposed in the device. In some instances, a multi-gate device may be referred to as a GAA device or a nanosheet device having gate material on at least four sides of at least one channel disposed in the device. The channel region may be referred to as a "nanowire" as used herein, which includes channel regions of various geometries (e.g., cylindrical, bar-shaped) and various dimensions. In some instances, a multi-gate device may be referred to as a FinFET device. However, one of ordinary skill in the art will recognize that this teaching can be applied to a single channel (e.g., a single nanosheet) or any number of channels. One of ordinary skill in the art may recognize other examples of semiconductor devices that may benefit from aspects of this disclosure.

[0057] Figures 1A to 5B FIG. illustrates a method of manufacturing an integrated circuit device at various stages according to some embodiments. Figure 1A 、 Figure 2A 、 Figure 3A 、 Figure 4A 、and Figure 5A are top views of an integrated circuit device at various stages according to some embodiments. Figure 1B is along Figure 1A A cross-sectional view of the integrated circuit device taken along line B-B. Figure 2B 、 Figure 3B 、 Figure 4B 、and Figure 5B are respectively along Figure 2A 、 Figure 3A 、 Figure 4A 、and Figure 5A A cross-sectional view of the integrated circuit device taken along line A-A. It can be understood that additional steps can be provided before, during, and after the steps shown in Figures 1A to 5B And for additional embodiments of the method, some of the following steps can be replaced or cancelled. The order of operations / processes can be interchanged.

[0058] Refer to Figure 1A and Figure 1BAn epitaxial stack 120 is formed over a substrate 110. In some embodiments, the substrate 110 may include silicon (Si). Alternatively, the substrate 110 may include germanium (Ge), silicon germanium (SiGe), III-V materials (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaAnAs, InAs, GaInP, InP, InSb, and / or GaInAsP; or combinations thereof) or other suitable semiconductor materials. In some embodiments, the substrate 110 may include a semiconductor-on-insulator (SOI) structure such as a buried dielectric layer. Additionally, the substrate 110 may include a buried dielectric layer such as a buried oxide (BOX) layer, such as a BOX layer formed by a technique called separation by implantation of oxygen (SIMOX), wafer bonding, selective epitaxial growth (SEG), or another suitable method.

[0059] The epitaxial stack 120 includes a bottom epitaxial stack 120B, a sacrificial semiconductor layer 123 over the bottom epitaxial stack 120B, and a top epitaxial stack 120T over the sacrificial semiconductor layer 123, wherein each of the bottom epitaxial stack 120B and the top epitaxial stack 120T includes a semiconductor sacrificial layer and one or more semiconductor channel layers alternately disposed with the semiconductor sacrificial layer. For example, in the present embodiment, the bottom epitaxial stack 120B includes a lower semiconductor sacrificial layer 121, a semiconductor channel layer 122 over the lower semiconductor sacrificial layer 121, and an upper semiconductor sacrificial layer 121 over the semiconductor channel layer 122. For example, the top epitaxial stack 120T includes a lower semiconductor sacrificial layer 124, a semiconductor channel layer 125 over the lower semiconductor sacrificial layer 124, and an upper semiconductor sacrificial layer 124 over the semiconductor channel layer 125. In some embodiments, the semiconductor layers 121-125 may include suitable semiconductor materials such as group-IV semiconductors (e.g., Si, Ge, Sn, SiGe, GeSn), group-III-V semiconductors (e.g., GaAs), analogs, or combinations thereof. The thicknesses of any two or more of the semiconductor layers 121-125 may be different from each other.

[0060] In some embodiments, the material of semiconductor layer 122 is selected for use as the p-type channel of a p-type transistor, and the material of semiconductor layer 125 is selected for use as the n-type channel of an n-type transistor. In some alternative embodiments, the material of semiconductor layer 122 is selected for use as the n-type channel of an n-type transistor, and the material of semiconductor layer 125 is selected for use as the p-type channel of a p-type transistor. Layers 121, 122, and 123 may have different semiconductor compositions from each other, and layers 124, 125, and 123 may have different semiconductor compositions from each other. For example, channel semiconductor layers 122 and 125 are Si x Ge 1-x , sacrificial semiconductor layers 121 and 124 are Si y Ge 1-y , sacrificial semiconductor layer 123 is Si z Ge 1-z , where x, y, z are in the range of 0 to 1, and x > y > z. In some other embodiments, channel semiconductor layers 122 and 125 are Si x Ge 1-x , sacrificial semiconductor layers 121 and 124 are Si y Ge 1-y , sacrificial semiconductor layer 123 is Si z Ge 1-z , where x, y, z are in the range of 0 to 1, and x > z > y.

[0061] Semiconductor channel layers 122 and 125 or portions thereof may form the nanosheet channels of a multi-gate transistor. The term nanosheet is used herein to denote any material portion having nanoscale or even micron-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of this portion. Thus, this term denotes both circular and substantially circular cross-section elongated material portions, and beam-shaped or strip-shaped material portions including, for example, cylindrical shapes or substantially rectangular cross-sections. Channel layers 122 and 125 may be referred to as semiconductor channels in context. The use of channel layers 122 and 125 to define one or more channels of a device is further discussed below.

[0062] For example, the epitaxial growth of the layers of stack 120 can be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial growth layers, such as epitaxial layers 121-125, include suitable crystalline semiconductor materials, such as Si, Ge, Sn, SiGe, GeSn, III-V semiconductors, the like, or combinations thereof. In some embodiments, semiconductor layers 122 and 125 are intrinsic semiconductor layers. For example, semiconductor layers 122 and 125 are substantially free of dopants (i.e., have a non-intrinsic dopant concentration of about 0 cm -3 to about 1×10 18 cm -3 ), where, for example, no intentional doping is performed during the epitaxial growth process. In some embodiments where the PMOS is stacked above the NMOS, the semiconductor sacrificial layer 121 can be intentionally doped with an n-type dopant (e.g., phosphorus), for example, having a dopant concentration of about 1×10 18 cm -3 to about 1×10 22 cm -3 , and the semiconductor sacrificial layer 124 can be intentionally doped with a p-type dopant (e.g., boron), for example, having a dopant concentration of about 1×10 18 cm -3 to about 1×10 22 cm -3 . In some embodiments where the NMOS is stacked above the PMOS, the semiconductor sacrificial layer 121 can be intentionally doped with a p-type dopant (e.g., boron), for example, having a dopant concentration of about 1×10 18 cm -3 to about 1×10 22 cm -3 , and the semiconductor sacrificial layer 124 can be intentionally doped with an n-type dopant (e.g., phosphorus), for example, having a dopant concentration of about 1×10 18 cm -3 to about 1×10 22 cm -3 . The sacrificial layer 123 can be substantially free of dopants, or intentionally doped with an n-type dopant or a p-type dopant.

[0063] It should be noted that as Figure 1BAs shown, a semiconductor channel layer 122 is alternately disposed with two semiconductor sacrificial layers 121, and a semiconductor channel layer 125 is alternately disposed with two semiconductor sacrificial layers 124. This is for illustrative purposes only and is not intended to limit what is specifically recited in the claims. It is understood that any number of semiconductor channel layers 122 can be formed in the bottom epitaxial stack 120B, and any number of semiconductor channel layers 125 can be formed in the top epitaxial stack 120T. In some embodiments, the number of semiconductor channel layers 122 is between 1 and 8, and the number of semiconductor channel layers 125 is between 1 and 8. For example, in Figure 1A and Figure 1B the number of semiconductor channel layers 122 is 1, and the number of semiconductor channel layers 125 is 1.

[0064] At least one semiconductor fin FS extending from the substrate 110 is formed. The semiconductor fin FS can extend substantially along the direction X. In various embodiments, each of the fins FS includes a substrate portion 112 formed by the substrate 110 and portions of each of the epitaxial layers of the epitaxial stack 120 (including epitaxial layers 121-125).

[0065] The fins FS can be fabricated using suitable processes, including optical lithography and etching processes. The optical lithography process can include forming a photoresist layer, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the resist to form a patterned mask including the resist. In some embodiments, patterning the resist to form the patterned mask element can be performed using an electron beam (e-beam) lithography process or an extreme ultraviolet (EUV) lithography process. Subsequently, the patterned mask can be used to protect regions of the substrate 110 and the layers formed thereon, while an etching process forms trenches T1 in the unprotected regions, through the epitaxial stack 120, and into the substrate 110, thereby leaving multiple extended fins FS. The trenches T1 can be etched using dry etching (e.g., reactive ion etching), wet etching, and / or a combination thereof. Many other embodiments of methods for forming fins on a substrate can also be used, including, for example, defining fin regions (e.g., by mask regions or isolation regions) and epitaxially growing the epitaxial stack 120 in the form of fins FS.

[0066] The fin FS can be fabricated using suitable processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine optical lithography with self-alignment processes, thereby allowing the generation of patterns having a smaller pitch, for example, than that achievable using a single direct optical lithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. A spacer is formed adjacent to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the fin FS can then be patterned by etching the initial epitaxial stack 120 using the remaining spacer or mandrel. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.

[0067] An isolation structure 130 is formed in the trench T1 between the fins FS. The isolation structure 130 can be a single-layer structure or a multi-layer structure. In some embodiments, the isolation structure 130 includes a low-k dielectric material, SiN, SiCN, SiOC, SiOCN, or the like. The formation of the isolation structure 130 can include depositing a dielectric material, followed by a etch-back process. Via the etch-back process, the top surface of the isolation structure 130 can be flush with or lower than the bottom surface of the epitaxial stack 120. In some alternative embodiments, the top surface of the isolation structure 130 can be higher than the bottom surface of the epitaxial stack 120.

[0068] Reference Figure 2A and Figure 2B A gate structure 180 is formed to surround each of the nanosheets (e.g., semiconductor channel layers 122 and 125). The gate structure GS can be the final gate of the GAA-FET. The final gate structure can be a high-k / metal gate stack, although other compositions are possible. In some embodiments, the gate structure 180 is formed to be associated with the channel regions of the semiconductor channel layer 122 and the semiconductor channel layer 125. For example, the high-k / metal gate structure 180 is formed within the openings / spaces provided by releasing the semiconductor channel layers 122 and 125. In some embodiments, the high-k / metal gate structure 180 surrounding the channel region of the semiconductor channel layer 122 is continuously connected to the high-k / metal gate structure 180 surrounding the channel region of the semiconductor channel layer 125.

[0069] In various embodiments, the high-k / metal gate structure 180 includes a gate dielectric layer 182 and a gate metal layer 184 formed around the gate dielectric layer 182. The formation of the high-k / metal gate structure 180 may include one or more deposition processes (e.g., ALD, CVD, physical vapor deposition (PVD), the like, or a combination thereof) to form various gate materials, resulting in the high-k / metal gate structure GS. In some embodiments, a dummy gate structure, gate spacers 154, and an interlayer dielectric layer 160 are first formed, and a gate replacement process is performed to replace the dummy gate structure with the high-k / metal gate structure 180.

[0070] Reference Figure 3A and Figure 3B . A selective etching process is performed to remove the sacrificial semiconductor layer 123. In some embodiments, the selective etching process may etch the material of the sacrificial semiconductor layer 123 at a faster rate than the materials of layers 121, 122, 124, and 125, thereby creating an opening / space O2 between the bottom epitaxial stack 120B and the top epitaxial stack 120T. The selective etching process may include dry etching, wet etching, or a combination thereof. In the present embodiment, the selective etching process may use a suitable etching recipe to remove a portion of the sacrificial semiconductor layer 123 (forming the opening O2) without substantially damaging layers 121, 122, 124, and 125. For example, the selective etching process may be a dry etching process using a fluorine-based gas (e.g., SF 6 ).

[0071] Reference Figure 4A and Figure 4B . A dielectric isolation layer 190 is deposited into the opening O2. The dielectric isolation layer 190 may include a suitable dielectric material, such as silicon oxide, silicon oxynitride, and silicon nitride. The deposition process may include ALD, CVD, the like, or a combination thereof. In some embodiments, regions of the bottom epitaxial stack 120B on opposite sides of the gate structure 180 may form source / drain regions SDB of the bottom transistor, and regions of the top epitaxial stack 120T on opposite sides of the gate structure 180 may form source / drain regions SDT of the top transistor. In the presence of the dielectric isolation layer 190, the source / drain regions SDB and SDT of the two stacked transistors may be electrically isolated from each other and independently controlled.

[0072] Reference Figure 5A and Figure 5B。The contact sockets 212 and 214 can be formed to penetrate through the interlayer dielectric layer 160 and contact the source / drain regions SDB and SDT of two stacked transistors, respectively. The formation of the contact socket 212 can include etching a hole / openning through the layers 160, 124, 125, and 190 to expose the source / drain region SDB, depositing a conductive material into the hole / openning, and then performing a chemical mechanical planarization (CMP) process on the excess conductive material from the hole / openning after depositing the conductive material. In some embodiments, before depositing the conductive material, a dielectric barrier layer 200 is formed in the hole / openning through the layers 160, 124, 125, and 190 to isolate the conductive material from the source / drain region SDB. The formation of the dielectric barrier layer 200 can include depositing a suitable dielectric material (e.g., silicon nitride, silicon oxynitride, analogs, or combinations thereof) into the hole / openning, and then performing an etching process to remove the bottom portion of the dielectric barrier layer 200, thereby exposing the source / drain region SDB. Similarly, the formation of the contact socket 214 can include etching a hole / openning through the layer 160 to expose the source / drain region SDT, depositing a conductive material into the hole / openning, and then performing a CMP process on the excess conductive material from the hole / openning after depositing the conductive material. In some embodiments, to reduce capacitance, the contact socket 214 is closer to the gate structure 180 than the contact socket 212.

[0073] Figures 6A to 7B FIG. illustrates a method for manufacturing an integrated circuit device at various stages according to some embodiments. Figure 6A and Figure 7A is a top view of an integrated circuit device at various stages according to some embodiments. Figure 6B and Figure 7B is Figure 6A and Figure 7A A cross-sectional view of the integrated circuit device taken along line A-A of. The details of this embodiment are similar to Figures 6A to 7B The details shown, except that there is a void 190V in the dielectric isolation layer 190.

[0074] Reference Figure 6A and Figure 6B。The dielectric isolation layer 190 is deposited into the opening O2. The dielectric isolation layer 190 may include a suitable dielectric material deposited by ALD, CVD, the like, or a combination thereof, such as silicon oxide, silicon oxynitride, and silicon nitride. The deposited dielectric material in the opening O2 may coalesce and form one or more voids 190V. Thus, the formed dielectric isolation layer 190 has voids 190V therein. For example, the formed dielectric isolation layer 190 has a bottom portion 192 adjacent to the bottom epitaxial stack 120B, a top portion 194 adjacent to the top epitaxial stack 120T, side portions 196 adjacent to the gate structure 180, and side portions 198 remote from the gate structure 180, wherein the bottom portion 192, the top portion 194, and the side portions 196 and 198 surround the void 190V. The dielectric isolation layer 190 having voids 190V may space apart the source / drain regions SDB and SDT of the two stacked transistors from each other. As a result, the source / drain regions SDB and SDT of the two stacked transistors may be electrically isolated from each other and independently controlled.

[0075] Reference Figure 7A and Figure 7B 。The contact sockets 212 and 214 may be formed to pass through the interlayer dielectric layer 160 and contact the source / drain regions SDB and SDT of the two stacked transistors, respectively. The formation of the contact socket 212 may include etching a hole / openings through the layers 160, 124, 125, and 190 to expose the source / drain region SDB, forming a dielectric barrier layer 200 in the hole / openings, and depositing a conductive material into the hole / openings, and then performing a CMP process on the excess conductive material from the hole / openings after depositing the conductive material. The hole / openings etched through the layers 160, 124, 125, and 190 may expose the void 190V in the dielectric isolation layer 190. The formation of the dielectric barrier layer 200 may include depositing a suitable dielectric material (e.g., silicon nitride, silicon oxynitride, the like, or a combination thereof) into the opening, and then performing an etching process to remove the bottom portion of the dielectric barrier layer 200, thereby exposing the source / drain region SDB. The formed dielectric barrier layer 200 may seal the void 190V in the dielectric isolation layer 190 without filling the void 190V in the dielectric isolation layer 190. In some embodiments, the dielectric barrier layer 200 may not substantially extend into the bottom and top portions of the dielectric isolation layer 190. In some alternative embodiments, the dielectric barrier layer 200 may have portions that extend into the bottom and top portions of the dielectric isolation layer 190. In some alternative embodiments, the dielectric barrier layer 200 may fill the void 190V in the dielectric isolation layer 190. The formation of the contact socket 214 may be similar to Figure 5A and Figure 5B as shown and will not be repeated here. Other details of this embodiment are omitted here.

[0076] Figures 8A to 20BA method for manufacturing an integrated circuit device at various stages according to some embodiments. Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 17A , Figure 18A , and Figure 20A are top views of various stages of an integrated circuit device according to some embodiments. Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 17B , Figure 18B , and Figure 20B are cross-sectional views of the integrated circuit device taken along line A-A along Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 17A , Figure 18A , and Figure 20A respectively. Figure 16 And Figure 19 are cross-sectional views of the integrated circuit device taken along the same line as line A-A of Figure 15A and Figure 18A . It can be understood that additional steps can be provided before, during, and after the steps shown in Figures 8A to 20B , and for additional embodiments of the method, some of the following steps can be replaced or cancelled. The order of operations / processes can be interchanged.

[0077] Refer to Figure 8A and Figure 8B . As Figure 1A and Figure 1BAs shown, an epitaxial stack 120 is formed above a substrate 110. The epitaxial stack 120 includes a bottom epitaxial stack 120B, a sacrificial semiconductor layer 123 above the bottom epitaxial stack 120, and a top epitaxial stack 120T above the sacrificial semiconductor layer 123. For example, in the present embodiment, the bottom epitaxial stack 120B includes three semiconductor sacrificial layers 121 and two semiconductor channel layers 122 alternately disposed above the substrate 110. For example, the top epitaxial stack 120T includes three semiconductor sacrificial layers 124 and two semiconductor channel layers 125 alternately disposed above the sacrificial semiconductor layer 123. Layers 121, 122, and 123 may have different semiconductor compositions from each other, and layers 124, 125, and 123 may have different semiconductor compositions from each other. For example, the channel semiconductor layers 122 and 125 are Si x Ge 1-x , the sacrificial semiconductor layers 121 and 124 are Si y Ge 1-y , the sacrificial semiconductor layer 123 is Si z Ge 1-z , where x, y, and z are in the range of 0 to 1, and x > y > z. In some embodiments, the thicknesses of any two or more of the semiconductor layers 121 to 125 may be different from each other. Moreover, the thicknesses of the semiconductor layers 121 / 122 / 124 / 125 may be different from each other.

[0078] At least one semiconductor fin FS extending from the substrate 110 is formed. The semiconductor fin FS may extend substantially along the direction X. In various embodiments, each of the fins FS includes a substrate portion 112 formed by the substrate 110 and portions of each of the epitaxial layers of the epitaxial stack 120 (including the epitaxial layers 121 to 125). Moreover, an isolation structure 130 is formed in the trench T1 between the fins FS.

[0079] Refer to Figure 9A and Figure 9B。A dielectric layer 140 is formed over the fin FS, and one or more dummy gate electrodes 152 are formed over the dielectric layer 140 and the fin FS. The dielectric layer 140 may include one or more layers of dielectric materials, such as silicon oxide, silicon nitride, high-k dielectric materials, and / or other suitable dielectric materials. The dielectric layer 140 may also be referred to as a dummy dielectric layer or a sacrificial dielectric layer in context. In some embodiments, the dielectric layer 140 may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, an FCVD process, an ALD process, a PVD process, or other suitable processes. In some embodiments, the dummy gate electrode 152 includes polysilicon (polysilicon). The dummy gate electrode 152 may be formed by first depositing a gate electrode layer and then performing patterning and etching processes. For example, the patterning process includes an optical lithography process (e.g., optical lithography or e-beam lithography), which may further include a photoresist coating layer (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE), wet etching, other etching methods, and / or combinations thereof. By patterning the gate electrode layer, the fin FS is partially exposed on the opposite sides of the dummy gate electrode 152.

[0080] Reference Figure 10A and Figure 10B 。Gate spacers 154 are formed on the opposite sidewalls of the dummy gate electrode 152. The gate spacers 154 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof. The gate spacers 154 may be formed by a self-aligned method. For example, the gate spacers 154 may be formed by first depositing one or more conformal spacer material layers and then etching back the one or more spacer materials to form the gate spacers 154. The one or more conformal spacer material layers may be formed by an ALD or CVD process. The etching-back process may include an anisotropic dry etching process. During the anisotropic dry etching process, most of the one or more spacer material layers are removed from the horizontal surfaces, such as the top of the fin FS, leaving the gate spacers 154 on the vertical surfaces, such as the sidewalls of the dummy gate electrode 152. The formed spacers 154 may include a single layer or multiple layers.

[0081] Reference Figure 11A and Figure 11B 。In Figure 10A and Figure 10BAn interlayer dielectric (ILD) layer 160 is formed over the structure. In some embodiments, the ILD layer 160 includes materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicon glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and / or other suitable dielectric materials. The ILD layer 160 can be deposited by a CVD process or other suitable deposition techniques. The ILD layer 160 can fill the trenches between the fins FS. After depositing the ILD layer 160, a CMP process can be performed to remove the top portion of the ILD layer 160, thereby exposing the top surface of the dummy gate electrode 152. In some embodiments, the CMP process can terminate when the top surface of the dummy gate electrode 152 is exposed.

[0082] Reference Figure 12A and Figure 12B . Remove the dummy gate electrode 152 (reference Figure 11A and Figure 11B ), and then remove the portions of the sacrificial layers 121 and 124 under the dummy gate electrode 152 (reference Figure 11A and Figure 11B ). In the illustrated embodiment, the dummy gate electrode 152 (reference Figure 11A and Figure 11B ) is removed by using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof), and the selective etching process etches the material in the dummy gate electrode 152 (reference Figure 11A and Figure 11B ) at a faster etching rate than other materials (e.g., the gate spacers 154 and the dielectric layer 140), thereby creating a gate trench GT between the corresponding gate spacers 154 and exposing the dielectric layer 140. The dielectric layer 140 exposed by the gate trench GT can be etched and removed by a suitable etching process, thereby exposing the topmost sacrificial layer 124 of the epitaxial stack 120.

[0083] Subsequently, by using another selective etching process, the portions of the sacrificial layers 124, 123, and 121 in the channel region that are below the gate trench GT are etched. The selective etching process etches the sacrificial layers 124, 123, and 121 at an etching rate faster than that of the semiconductor layers 125 and 122, thereby forming an opening / space O1 between the adjacent semiconductor layers 125 and 122. In this way, the portions of the semiconductor layers 122 and 125 in the channel region that are below the gate trench GT become nanosheets suspended above the substrate 110. This step is also referred to as the channel release process. In this temporary processing step, the opening / space O1 surrounding the nanosheets 122 and 125 may be filled with ambient conditions (e.g., air, nitrogen, etc.). In some embodiments, the nanosheets 122 and 125 may be interchangeably referred to as nanowires, nanoplates, and nanorings, depending on their geometries.

[0084] In some embodiments, the sacrificial layers 124, 123, and 121 are removed by using a selective dry etching process. In some embodiments, the sacrificial layers 124, 123, and 121 are SiGe, and the semiconductor layers 125 and 122 are silicon, thereby allowing the selective removal of the sacrificial layers 124, 123, and 121. In some embodiments, the selective dry etching may use a fluorine-based gas (e.g., SF 6 、CF 4 、C 4 F 8 ), a chlorine-based gas, an analogue, or a combination thereof. In some embodiments, the selective removal includes SiGe oxidation, followed by SiGeO x removal. For example, oxidation may be provided by O 2 plasma, and then SiGeO 4 / C 4 F 8 plasma) to remove SiGeO x , which selectively etches SiGeO x at an etching rate faster than that of Si etching and terminates at SiGe. The steps of SiGe oxidation and SiGeO x removal may be repeated until the portions of the sacrificial layers 124, 123, and 121 below the gate trench GT are removed. Additionally, since the oxidation rate of Si is much lower (sometimes 30 times lower) than that of SiGe, the semiconductor layers 125 and 122 can remain substantially intact during the channel release process.

[0085] In some embodiments, the selective etching process may use the same etching recipe to remove portions of the sacrificial layers 124, 123, and 121 without substantially damaging the semiconductor layers 125 and 122. For example, the selective etching process may be using a fluorine-based gas (e.g., SF 6) dry etching process. The selective etching process can be a (substantially) isotropic etching process. For example, the selective etching process can use a fluorine-based plasma without substrate bias for substantially isotropic etching of materials. Using an isotropic etching process, the plasma can laterally etch the materials under the semiconductor layers 125 and 122.

[0086] In some alternative embodiments, the removal of a portion of the sacrificial layer 124 can be separated from the removal of a portion of the semiconductor sacrificial layer 121. For example, a first selective etching process can use a first etching recipe to remove a portion of the sacrificial layer 124 (forming an upper opening O1), while a second selective etching process can use a second etching recipe to remove a portion of the semiconductor sacrificial layer 121 (forming a lower opening O1), where the first etching recipe is different from the second etching recipe.

[0087] Reference Figure 13A and Figure 13B . An annealing process is performed to drive dopant diffusion and activation for low source / drain resistance. Through the annealing process, the dopants in the remaining portion of the sacrificial layer 121 diffuse into the edge portion of the semiconductor layer 122, thereby forming source / drain regions SDB. Additionally, through the annealing process, the dopants in the remaining portion of the sacrificial layer 124 diffuse into the edge portion of the semiconductor layer 125, thereby forming source / drain regions SDT. In other words, an annealing process is performed to convert the second portion of the doped sacrificial layer 121 and the peripheral region of the semiconductor layer 122 into source / drain regions SDB, and to convert the second portion of the doped sacrificial layer 124 and the peripheral region of the semiconductor layer 125 into top source / drain regions SDT. The diffusion behavior is further illustrated later in Figure 21A and Figure 21B . Since the doped sacrificial layer in the channel region has been removed in Figure 12A and Figure 12B , the semiconductor layers 125 and 122 in the channel region can remain substantially intrinsic, for example, substantially dopant-free (i.e., having an intrinsic dopant concentration of about 0 cm -3 to about 1×10 18 cm -3 ).

[0088] Reference Figure 14A and Figure 14B。The replacement gate structures 180 are respectively formed in the gate trenches GT to surround each of the suspended nanosheets 122 and 125 suspended in the gate trenches GT. The gate structure 180 can be the final gate of the GAA-FET. The final gate structure can be a high-k / metal gate stack, although other compositions are possible. In some embodiments, each of the gate structures 180 forms a gate associated with the multiple channels provided by the multiple nanosheets 122 and 125. For example, the high-k / metal gate structure 180 is formed within the opening / space O1 provided by releasing the nanosheets 122 and 125. The high-k / metal gate structure 180 can be between the source / drain regions SDB and between the source / drain regions SDT.

[0089] In various embodiments, the high-k / metal gate structure 180 includes a gate dielectric layer 182 formed around the nanosheets 122 and 125 and a gate metal layer 184 formed around the gate dielectric layer 182 and filling the remaining portion of the gate trench GT. The formation of the high-k / metal gate structure 180 can include one or more deposition processes to form various gate materials, followed by a CMP process to remove the excess gate materials, thereby producing the high-k / metal gate structure 180 having a top surface flush with the top surface of the ILD layer 160. Thus, a transistor (e.g., GAA-FET) is formed, and the high-k / metal gate structure 180 surrounds each of the nanosheets 122 and 125 and is thus referred to as the gate of the transistor (e.g., GAA-FET).

[0090] The gate dielectric layer 182 can include an interface layer 182a and a high-k gate dielectric layer 182b above the interface layer. In some embodiments, the interface layer 182a is a semiconductor oxide formed on the exposed surface of the semiconductor material in the gate trench GT by using, for example, thermal oxidation, chemical oxidation, wet oxidation, or the like. As a result, the surface portions of the layers 121 to 125 and the substrate 110 exposed to the gate trench GT are partially oxidized into oxides to form the interface layer. In some embodiments, the high-k gate dielectric layer 182b includes a dielectric material such as hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO; HZO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), strontium titanate (SrTiO3, STO), barium titanate (BaTiO 3, barium titanate (BTO), barium zirconate (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicate (LaSiO), aluminum silicate (AlSiO), aluminum oxide (Al 2 O 3 ), analogs, or combinations thereof.

[0091] In some embodiments, the gate metal layer 184 includes one or more metal layers. For example, the gate metal layer 184 may include one or more work function metal layers stacked layer by layer and a fill metal that fills the remaining portion of the gate trench GT. One or more of the work function metal layers in the gate metal layer 184 provide a suitable work function for the high-k / metal gate structure 180. For an n-type GAA FET, the gate metal layer 184 may include one or more n-type work function metal (N-metal) layers. Exemplary n-type work function metals may include, but are not limited to, titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HX), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, titanium nitride (TiN), tungsten (W), and / or other suitable materials. On the other hand, for a p-type GAA FET, the gate metal layer 184 may include one or more p-type work function metal (P-metal) layers. Exemplary p-type work function metals may include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and / or other suitable materials. In some embodiments, the fill metal in the gate metal layer 184 may include, but is not limited to, tungsten, aluminum, copper, nickel, cobalt, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials.

[0092] Reference Figure 15A and Figure 15B . The ILD layer 160 and the dielectric layer 140 are etched to expose the sidewalls S1 of the fins FS. For example, trench openings TH1 are etched in the ILD layer 160 and the dielectric layer 140 to expose the sidewalls of the layers 121-125 at the first side of the gate structure 180. In some embodiments, before etching the trench openings TH1, a patterned mask is formed over the structures of Figure 14A and Figure 14B . The optical lithography process may include forming a photoresist layer, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the resist to form a patterned mask including the resist. The patterned mask can be used to protect regions of the substrate 110 and the layers formed thereon during the etching of the trench openings TH1.

[0093] Reference Figure 16 。An etch selectivity process is performed to remove a portion of the sacrificial semiconductor layer 123 that is exposed by the trench opening TH1. In some embodiments, the etch selectivity process may etch the material of the sacrificial semiconductor layer 123 at a faster rate than the materials of the layers 121, 122, 124, and 125, thereby creating an opening / gap O21 between the bottom source / drain region SDB and the top source / drain region SDT. The etch selectivity process may include dry etching, wet etching, or a combination thereof. In the present embodiment, the etch selectivity process may use a suitable etch recipe to remove a portion of the sacrificial semiconductor layer 123 (forming the opening O21) without substantially damaging the layers 121, 122, 124, and 125. For example, the etch selectivity process may be a dry etching process using a fluorine-based gas (e.g., SF 6 ).

[0094] Reference Figure 17A and Figure 17B 。A dielectric isolation layer 190A is deposited into the opening O21. The dielectric isolation layer 190A may include a suitable dielectric material, such as silicon oxide, silicon oxynitride, and silicon nitride. The deposition process may include ALD, CVD, the like, or a combination thereof. In the presence of the dielectric isolation layer 190A, the two stacked source / drain regions SDB and SDT may be electrically isolated from each other and controlled independently.

[0095] In some embodiments, in Figure 17A and Figure 17B an integrated circuit device is formed. One of the source / drain regions SDB is electrically isolated from one of the source / drain regions SDT, and the other of the source / drain regions SDB is electrically connected to the other of the source / drain regions SDT, for example, by doping the sacrificial semiconductor layer 123. That is, in a stacked integrated circuit device, one node of the PMOS is electrically connected to one node of the NMOS, and the other node of the PMOS is electrically isolated from the other node of the NMOS. This integrated circuit device may be implemented in a Static Random-Access Memory (SRAM) cell. The following steps in Figures 18A to 20B are optionally performed next. For example, in some embodiments where it is desired to separate one node of the PMOS from one node of the NMOS and connect the other node of the PMOS to the other node of the NMOS in a stacked integrated circuit device, Figures 18A to 20B the following steps in may be skipped, and then contact sockets are formed. In some embodiments where it is desired to separate the two nodes of the PMOS from the two nodes of the NMOS, the following steps in Figures 18A to 20B are performed.

[0096] ReferenceFigure 18A and Figure 18B 。The ILD layer 160 and the dielectric layer 140 are etched to expose the sidewalls S2 of the fin FS. For example, trench openings TH2 are etched in the ILD layer 160 and the dielectric layer 140 to expose the sidewalls of layers 121-125 at the second side of the gate structure 180. In some embodiments, before etching the trench openings TH2, a patterned mask is formed over the structures of Figure 17A and Figure 17B . The optical lithography process may include forming a photoresist layer, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the resist to form a patterned mask including the resist. The patterned mask can be used to protect regions of the substrate 110 and the layers formed thereon during the etching of the trench openings TH2.

[0097] Refer to Figure 19 . A selective etching process is performed to remove a portion of the sacrificial semiconductor layer 123 exposed by the trench opening TH2. In some embodiments, the selective etching process can etch the material of the sacrificial semiconductor layer 123 at a faster rate than the materials of layers 121, 122, 124, and 125, thereby creating an opening / space O22 between the bottom source / drain region SDB and the top source / drain region SDT. The selective etching process may include dry etching, wet etching, or a combination thereof. In this embodiment, the selective etching process can use a suitable etching recipe to remove a portion of the sacrificial semiconductor layer 123 (forming the opening O22) without substantially damaging layers 121, 122, 124, and 125. For example, the selective etching process can be a dry etching process using a fluorine-based gas (e.g., SF 6 ).

[0098] Refer to Figure 20A and Figure 20B . The dielectric isolation layer 190B is deposited into the opening O22. The dielectric isolation layer 190B can include a suitable dielectric material such as silicon oxide, silicon oxynitride, and silicon nitride. The deposition process may include ALD, CVD, the like, or a combination thereof. In the presence of the dielectric isolation layer 190B, the two stacked source / drain regions SDB and SDT can be electrically isolated from each other and controlled independently.

[0099] Return to reference Figure 7A and Figure 7B . The contact sockets 212 and 214 can be formed to pass through the interlayer dielectric layer 160 and contact the source / drain regions SDB and SDT of the two stacked transistors, respectively. In some embodiments, a dielectric barrier layer 200 is formed before depositing the conductive material to isolate the contact socket 212 from the source / drain region SDB. Other details of this embodiment are similar to those described previously and thus will not be repeated here.

[0100] Figure 21A and Figure 21B FIGS. illustrate the p - type dopant distribution and levels in an epitaxial stack before and after an annealing process. The epitaxial stack before and after annealing is analyzed using Secondary - ion mass spectrometry (SIMS) techniques. As Figure 21A shown, before the annealing process, the p - type concentration in the SiGe epitaxial stack is in the range of about 4E17 cm -3 to ∼2E18 cm -3 . After the annealing process, as Figure 21B shown, the p - type concentration in the SiGe epitaxial stack is in the range of about 1E18 cm -3 to ∼3E18 cm -3 , which is beneficial for forming low source / drain resistance. In Figure 21A and Figure 21B , the epitaxial stack includes a doped Ge sacrificial layer and a Ge 0.95 Si 0.05 channel layer. The semiconductor compositions of the sacrificial layer and the channel layer can be changed according to manufacturing / device requirements. The annealing conditions can be optimized according to the semiconductor composition of the epitaxial stack for lower S / D resistance.

[0101] In some embodiments, the annealing process can be performed at an annealing temperature of about 250 degrees Celsius to about 1200 degrees Celsius. If the annealing temperature is lower than about 250 degrees Celsius, dopant diffusion may not occur. If the annealing temperature is greater than about 1200 degrees Celsius, the temperature can be higher than the melting point of the semiconductor (e.g., Si). The annealing process can be performed for a duration greater than about 1 minute to achieve suitable diffusion properties.

[0102] Figures 22 to 25 FIGS. illustrate a method for various stages of manufacturing an integrated circuit device. Except for forming a bottom isolation layer 190AB / 190BB under the gate structure 180, the details of this embodiment are similar to Figures 8A to 20B shown. In the presence of the isolation layer 190AB / 190BB, current leakage from the bottom transistor to the semiconductor substrate can be reduced. It can be understood that additional steps can be provided before, during, and after the steps Figures 22 to 25 shown, and for additional embodiments of the method, some of the following steps can be replaced or eliminated. The order of operations / processes can be interchanged.

[0103] Refer to Figure 22 . In forming Figure 15A and Figure 15BAfter the trench opening TH1 in, a lateral etching process can be performed to remove the top portion of the isolation structure 130 and the top portion of the substrate portion 112, leaving a lateral groove BR1 between the gate structure 180 and the substrate portion 112. Then, perform Figure 16 the selective etching process in to form the opening / space O21.

[0104] Refer to Figure 23 . The dielectric isolation layer 190A is deposited into the opening O21 and the lateral groove BR1, and then a CMP process is performed to remove the excess portion of the dielectric isolation layer 190A outside the trench opening TH1. The dielectric isolation layer 190A can include a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, analogs, or a combination thereof. By filling the lateral groove BR1, the dielectric isolation layer 190A has a bottom isolation layer 190AB, which is located between the gate structure 180 and the substrate portion 112 and between one of the source / drain regions SDB of the bottom transistor and the substrate portion 112. The dielectric isolation layer 190A can also fill the opening / space O21, thereby providing isolation between the top and bottom transistors.

[0105] Refer to Figure 24 . After forming the bottom isolation layer 190AB, a trench opening TH2 is formed as previously Figure 18A and Figure 18B shown. Subsequently, after forming the trench opening TH2 in Figure 18A and Figure 18B , a lateral etching process can be performed to remove the top portion of the isolation structure 130 and the top portion of the substrate portion 112, leaving a lateral groove BR2 between the gate structure 180 and the substrate portion 112. Then, a selective etching process is performed to form Figure 19 the opening / space O22 in.

[0106] Refer to Figure 25 . The dielectric isolation layer 190B is deposited into the opening O22 and the lateral groove BR2, and then a CMP process is performed to remove the excess portion of the dielectric isolation layer 190B outside the trench opening TH2. The dielectric isolation layer 190B can include a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, analogs, or a combination thereof. The dielectric isolation layer 190B can include a dielectric material that is the same as or different from the dielectric material of the dielectric isolation layer 190A. By filling the lateral groove BR2, the dielectric isolation layer 190B has a bottom isolation layer 190BB, which is located between the gate structure 180 and the substrate portion 112 and between the other of the source / drain regions SDB of the bottom transistor and the substrate portion 112. The dielectric isolation layer 190B can also fill the opening / space O22, thereby providing isolation between the top and bottom transistors. Other details of this embodiment are similar to Figures 8A to 20B shown, and thus will not be repeated here.

[0107] Based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, not all advantages need to be disclosed herein, and no specific advantage is required for all embodiments. One advantage may be that a monolithic transistor stack with isolated source / drain can be achieved without a source / drain regrowth process and a complex etch-back process. Another advantage may be that the annealing conditions can be optimized according to the semiconductor composition of the epitaxial stack for lower S / D resistance.

[0108] According to some embodiments of the present disclosure, a method for manufacturing an integrated circuit device is provided. The method includes depositing an epitaxial stack over a substrate, wherein the epitaxial stack includes a bottom epitaxial stack, a sacrificial semiconductor layer over the bottom epitaxial stack, and a top epitaxial stack over the sacrificial semiconductor layer, the bottom epitaxial stack includes a bottom semiconductor layer and a bottom doped sacrificial layer, and the top epitaxial stack includes a top semiconductor layer and a top doped sacrificial layer; replacing a first portion of the doped bottom sacrificial layer, the sacrificial semiconductor layer, and the top doped sacrificial layer with a gate structure; and replacing a second portion of the sacrificial semiconductor layer with a dielectric isolation layer.

[0109] In some embodiments, the depositing of the epitaxial stack is performed such that a germanium concentration of the sacrificial semiconductor layer is greater than a germanium concentration of the top and bottom doped sacrificial layers, and the germanium concentration of the top and bottom doped sacrificial layers is greater than a germanium concentration of the top and bottom semiconductor layers.

[0110] In some embodiments, the depositing of the epitaxial stack is performed such that the bottom doped sacrificial layer is of a first conductivity type, and the top doped sacrificial layer has a second conductivity type opposite to the first conductivity type.

[0111] In some embodiments, the step of replacing the first portions of the bottom doped sacrificial layer, the sacrificial semiconductor layer, and the top doped sacrificial layer with the gate structure includes selectively etching the first portions of the bottom doped sacrificial layer, the sacrificial semiconductor layer, and the top doped sacrificial layer while exposing a channel region of the top semiconductor layer and a channel region of the bottom semiconductor layer; and forming the gate structure around the exposed channel regions of the top semiconductor layer and the bottom semiconductor layer.

[0112] In some embodiments, the same etch recipe is used to selectively etch the first portion of the bottom doped sacrificial layer and the first portion of the top doped sacrificial layer.

[0113] In some embodiments, the method further includes performing an annealing process to convert a second portion of the bottom doped sacrificial layer and a peripheral region of the bottom semiconductor layer into a bottom source / drain region, and converting a second portion of the top doped sacrificial layer and a peripheral region of the top semiconductor layer into a top source / drain region.

[0114] In some embodiments, the method further includes forming a contact socket over the bottom source / drain region via the dielectric isolation layer.

[0115] In some embodiments, the method further includes removing a portion of the substrate under the gate structure after replacing the first portions of the doped bottom sacrificial layer, the sacrificial semiconductor layer, and the top doped sacrificial layer with the gate structure; and forming a bottom dielectric isolation layer under the gate structure.

[0116] According to some embodiments of the present disclosure, a method for manufacturing an integrated circuit device is provided. The method includes depositing an epitaxial stack over a substrate, where the epitaxial stack includes a bottom epitaxial stack, a sacrificial semiconductor layer over the bottom epitaxial stack, and a top epitaxial stack over the sacrificial semiconductor layer, the bottom epitaxial stack includes a bottom semiconductor layer and a bottom doped sacrificial layer, and the top epitaxial stack includes a top semiconductor layer and a top doped sacrificial layer; removing the first portions of the bottom doped sacrificial layer, the sacrificial semiconductor layer, and the top doped sacrificial layer while exposing the channel regions of the top semiconductor layer and the bottom semiconductor layer; performing an annealing process to diffuse dopants in the second portion of the bottom doped sacrificial layer into the peripheral region of the bottom semiconductor layer, and diffusing dopants in the second portion of the top doped sacrificial layer into the peripheral region of the top semiconductor layer; and forming a gate structure around the exposed channel regions of the top semiconductor layer and the bottom semiconductor layer.

[0117] In some embodiments, the annealing process is performed before forming the gate structure.

[0118] In some embodiments, the method further includes forming a first contact socket over the peripheral region of the bottom semiconductor layer, where the first contact socket extends through the peripheral region of the top semiconductor layer.

[0119] In some embodiments, the method further includes forming a dielectric barrier layer that separates the first contact socket from the peripheral region of the top semiconductor layer.

[0120] In some embodiments, the method further includes forming a second contact socket over the peripheral region of the top semiconductor layer, where the second contact socket is closer to the gate structure than the first contact socket.

[0121] In some embodiments, the deposition of the epitaxial stack is performed such that the bottom doped sacrificial layer is of a first conductivity type and the top doped sacrificial layer has a second conductivity type opposite to the first conductivity type.

[0122] In some embodiments, the method further includes replacing a second portion of the sacrificial semiconductor layer with a dielectric isolation layer.

[0123] According to some embodiments of the present disclosure, an integrated circuit device includes a bottom channel layer, a top channel layer, a gate structure, a first bottom source / drain region, a dielectric isolation layer, and a first top source / drain region. The top channel layer is above and spaced apart from the bottom channel layer. The gate structure surrounds the bottom channel layer and the top channel layer. The first bottom source / drain region is on a side surface of the bottom channel layer. An isolation layer (such as a dielectric isolation layer) is above the first bottom source / drain region. The first top source / drain region is above the isolation layer (such as a dielectric isolation layer) and on a side surface of the top channel layer.

[0124] In some embodiments, the integrated circuit device further includes another isolation layer under the gate structure and the first bottom source / drain region.

[0125] In some embodiments, the first bottom source / drain region has a first doped semiconductor layer and a second doped semiconductor layer, the first doped semiconductor layer having a material the same as that of the bottom channel layer, and the second doped semiconductor layer having a material different from that of the bottom channel layer.

[0126] In some embodiments, the isolation layer has a void.

[0127] In some embodiments, the integrated circuit device further includes a second bottom source / drain region on another side surface of the bottom channel layer; and a second top source / drain region above the second bottom source / drain region and on another side surface of the top channel layer.

[0128] The foregoing outlines the features of several embodiments such that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or achieving the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and such equivalent structures can be made various changes, substitutions, and alternations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing an integrated circuit device, characterized in that Include: Depositing an epitaxial stack on a substrate, wherein the epitaxial stack comprises a bottom epitaxial stack, a sacrificial semiconductor layer on the bottom epitaxial stack, and a top epitaxial stack on the sacrificial semiconductor layer, wherein the bottom epitaxial stack comprises a bottom semiconductor layer and a bottom doped sacrificial layer, and the top epitaxial stack comprises a top semiconductor layer and a top doped sacrificial layer; replacing the doped bottom sacrificial layer, the sacrificial semiconductor layer, and first portions of the top doped sacrificial layer with a gate structure; and A second portion of the sacrificial semiconductor layer is replaced with a dielectric isolation layer.

2. The method according to claim 1, characterized in that Depositing the epitaxial stack is performed such that the sacrificial semiconductor layer has a germanium concentration greater than a germanium concentration of the top and bottom doped sacrificial layers, and the germanium concentration of the top and bottom doped sacrificial layers is greater than a germanium concentration of the top and bottom semiconductor layers.

3. The method according to claim 1, characterized in that The deposition of the epitaxial stack is performed such that the bottom doped sacrificial layer is of a first conductivity type and the top doped sacrificial layer has a second conductivity type opposite to the first conductivity type.

4. A method for manufacturing an integrated circuit device, characterized in that Include: Depositing an epitaxial stack on a substrate, wherein the epitaxial stack comprises a bottom epitaxial stack, a sacrificial semiconductor layer on the bottom epitaxial stack, and a top epitaxial stack on the sacrificial semiconductor layer, wherein the bottom epitaxial stack comprises a bottom semiconductor layer and a bottom doped sacrificial layer, and the top epitaxial stack comprises a top semiconductor layer and a top doped sacrificial layer; removing the bottom doped sacrificial layer, the sacrificial semiconductor layer, and a plurality of first portions of the top doped sacrificial layer while exposing a channel region of the top semiconductor layer and a channel region of the bottom semiconductor layer; Performing an annealing process to diffuse dopants in a second portion of the bottom doped sacrificial layer into a peripheral region of the bottom semiconductor layer, and diffuse dopants in a second portion of the top doped sacrificial layer into a peripheral region of the top semiconductor layer; and A gate structure is formed around the exposure channel region of the top semiconductor layer and the exposure channel region of the bottom semiconductor layer.

5. The method according to claim 4, characterized in that The annealing process is performed before forming the gate structure.

6. The method according to claim 4, characterized in that Further including: A first contact socket is formed on the peripheral region of the bottom semiconductor layer, wherein the first contact socket extends through the peripheral region of the top semiconductor layer.

7. An integrated circuit device, characterized in that: Include: a bottom channel layer; a top channel layer above and spaced apart from the bottom channel layer; A gate structure, covering the bottom channel layer and the top channel layer; a first bottom source / drain region on one side of the bottom channel layer; an isolation layer over the first bottom source / drain region; and A first top source / drain region is above the isolation layer and on one side of the top channel layer.

8. The integrated circuit device according to claim 7, wherein: Further including: Another isolation layer is below the gate structure and the first bottom source / drain region.

9. The integrated circuit device according to claim 7, wherein: The first bottom source / drain region has a first doped semiconductor layer and a second doped semiconductor layer, the first doped semiconductor layer has the same material as the bottom channel layer, and the second doped semiconductor layer has a material different from the bottom channel layer.

10. The integrated circuit device according to claim 7, wherein: The isolation layer has a gap therein.

Images