Method of forming dynamic random access memory device without trench filling voids

Abstract

Methods for forming dynamic DRAM devices without trench fill voids are disclosed herein. A method may include providing a plurality of trenches in a substrate, the plurality of trenches defining a plurality of device structures; and depositing a plurality of layers over the device structure. The layers may include a first layer over the device structure, a second layer over the first layer, and a third layer over the second layer. The method may also include forming a plurality of contact trenches through the plurality of layers to expose one or more device structures of the plurality of device structures; and directing ions into sidewalls of the trench at a non-zero angle, wherein the ions strike the third layer and not strike the second layer. The method may also include forming a fill material within the trench after directing the ions into the sidewalls of the trench.

Description

Technical Field

[0001] This disclosure relates to semiconductor structures, and more particularly to methods for forming dynamic random access memory (DRAM) devices that are free of voids in trench fills. Background Art

[0002] Currently, the density of dynamic random access memory (DRAM) is continuously increasing. Therefore, it is necessary to scale down the bit-line node contact (BLC) used in cell transistors for high-density DRAM devices. This part affects the resistance of the cell transistor and thus affects cell performance (such as write recovery time and refresh time). Generally, the BLC plug is n+-doped polysilicon filled in a trench and used as the electrode plate of a capacitor. However, after the polysilicon filling process, seams or voids often remain in the trench, which leads to an increase in resistance and a decrease in reliability and DRAM scaling performance. In some prior arts, a series of deposition steps and etching steps are used to solve this problem. However, this leads to device damage, an increase in particle problems, and it is difficult to continuously scale down smaller features.

[0003] This disclosure is provided to address these and other drawbacks of the current technology. Summary of the Invention

[0004] This Summary of the Invention is provided to introduce a series of concepts in a simplified form that are further described in the Detailed Description below. This Summary of the Invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to help determine the scope of the claimed subject matter.

[0005] In one aspect, a method may include: providing a plurality of trenches in a substrate, the plurality of trenches defining a plurality of device structures; and depositing a plurality of layers over the plurality of device structures. The plurality of layers may include a first layer over the plurality of device structures, a second layer over the first layer, and a third layer over the second layer. The method may further include: forming a plurality of contact trenches through the plurality of layers to expose one or more of the plurality of device structures; directing ions into sidewalls of the plurality of contact trenches at a non-zero angle relative to a perpendicular line extending from a top surface of the plurality of layers, wherein the ions strike the third layer and do not strike the second layer; and forming a filling material in the plurality of contact trenches after directing the ions into the sidewalls of the plurality of contact trenches.

[0006] In another aspect, a method of forming a DRAM device may include forming source trench isolation (STI) material in a substrate over a plurality of trenches that define a plurality of device structures. The method may further include depositing a plurality of layers over the plurality of device structures, the plurality of layers including a first layer over the STI material, a second layer over the first layer, and a third layer over the second layer, wherein the second layer and the third layer are different materials. The method may further include: forming a plurality of contact trenches through the plurality of layers to expose one or more of the plurality of device structures; directing ions into sidewalls of the plurality of contact trenches at a non-zero angle relative to a perpendicular line extending from a top surface of the plurality of layers, wherein the ions strike the third layer and do not strike the second layer; and forming a fill material in the plurality of contact trenches after directing the ions into the sidewalls of the plurality of contact trenches.

[0007] In yet another aspect, a method of forming bit line contacts of a DRAM device may include: providing a plurality of trenches in a substrate, the plurality of trenches defining a plurality of device structures; and depositing a plurality of layers over the plurality of device structures, wherein the plurality of layers includes a first layer over the plurality of device structures, a second layer over the first layer, and a third layer over the second layer, and wherein the second layer and the third layer are different materials. The method may further include: forming a plurality of contact trenches through the plurality of layers to expose one or more of the plurality of device structures; forming a passivation layer along the sidewalls of the plurality of trenches by directing ions into the sidewalls of the plurality of contact trenches at a non-zero angle relative to a perpendicular line extending from a top surface of the plurality of layers, wherein the ions strike the third layer and do not strike the second layer; and forming a fill material in the plurality of contact trenches after directing the ions into the sidewalls of the plurality of contact trenches. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The drawings illustrate exemplary methods of the present disclosure, including practical applications of their principles, as follows:

[0009] Figure 1 is a side cross-sectional view of a device according to an embodiment of the present disclosure, the device including a plurality of layers over a plurality of trenches and over a plurality of device structures.

[0010] Figure 2 is a side cross-sectional view of a device showing the device after forming a plurality of contact trenches according to an embodiment of the present disclosure.

[0011] Figure 3 is a side cross-sectional view of a device showing the device during inclined ion implantation according to an embodiment of the present disclosure.

[0012] Figures 4-5 is a side cross-sectional view of a device during the formation of a trench fill material according to an embodiment of the present disclosure.

[0013] Figure 6 is a schematic diagram of a processing apparatus according to an embodiment of the present disclosure.

[0014] The drawings are not necessarily to scale. The drawings are merely representative and are not intended to depict specific parameters of the present disclosure. The drawings are intended to illustrate exemplary embodiments of the present disclosure and should not therefore be considered as limiting the scope. In the drawings, like numbers represent like elements.

[0015] In addition, for clarity of illustration, some elements in some of the figures may be omitted or not drawn to scale. For clarity of illustration, cross-sectional views may be in the form of "slice" or "close-up" cross-sectional views, thereby omitting some background lines that would otherwise be visible in a "true" cross-sectional view. In addition, for clarity, some reference numerals may be omitted in some of the drawings. DETAILED DESCRIPTION

[0016] The methods and devices according to the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. The methods and devices may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the methods to those skilled in the art.

[0017] To address the above deficiencies of the prior art, embodiments of the present disclosure advantageously use inclined ion implantation to modify desired portions of the trench surfaces of DRAM plugs, which standardizes the growth rate of subsequently formed trench fills. In this way, voids or gaps within the trench fills are avoided. As a result, resistance is reduced while reliability and DRAM scaling performance are improved.

[0018] Figure 1 is a side cross-sectional view of a portion of a semiconductor device (hereinafter referred to as a "device") 100 (e.g., a DRAM device) according to one or more embodiments. As shown, the device 100 may include a substrate or base 102 that includes a plurality of trenches 104 and a plurality of device structures 106. Although non-limiting, the plurality of device structures 106 may correspond to a plurality of source-trench-isolation (STI) structures. An STI fill material 108 may be formed over the device structures 106 and within the trenches 104. The STI fill material 108 may be planarized to the upper surface 109 of the device structures 106.

[0019] As further shown, a plurality of layers 110 may be formed over the STI fill material 108 and over the device structure 106. In some embodiments, a first layer 111 may be formed over the STI fill material 108, a second layer 112 may be formed over the first layer 111, a third layer 113 may be formed over the second layer 112, and a fourth layer 114 may be formed over the third layer 113. The third layer 113 and the second layer 112 may be of different materials, while the first layer 111 and the fourth layer 114 may be of the same material. In this non-limiting example, the first layer 111 is an oxide material, the second layer 112 is a silicon nitride layer, the third layer 113 is a polysilicon layer, and the fourth layer 114 is an oxide material. It should be understood that there may be fewer or more layers in the plurality of layers 110. It should also be understood that the materials of each of the plurality of layers 110 may be different in alternative embodiments.

[0020] As Figure 2 shown, a plurality of contact trenches 118 may then be formed (e.g., etched) through the plurality of layers 110 to expose one or more of the device structures 106. In some embodiments, the etching process may recess the upper surface 109 of one or more of the device structures 106 and the STI fill material 108. Each of the plurality of contact trenches 118 is defined by a first sidewall 121 and a second sidewall 122 extending between a trench bottom 123 and an upper surface 124 of the plurality of layers 110. An exposed portion of the first layer 111, an exposed portion of the second layer 112, an exposed portion of the third layer 113, and an exposed portion of the fourth layer 114 are present within each of the plurality of contact trenches 118.

[0021] As Figure 3As shown, portions of the first sidewall 121 and the second sidewall 122 of each of the plurality of contact trenches 118 may then be passivated by ions 132, which are directed / delivered into the plurality of contact trenches 118 at a non-zero angle "θ" relative to a perpendicular line 134 extending from the upper surface 124 of the plurality of layers 110. In other words, a passivation layer 130 may be formed over the plurality of layers 110 (including along upper portions of the first sidewall 121 and the second sidewall 122 of each of the plurality of contact trenches 118). In an exemplary embodiment, the ions 132 may strike the third layer 113 and the fourth layer 114 without striking the second layer 112 or the first layer 111. Accordingly, the passivation layer 130 may be formed over the third layer 113 and the fourth layer 114 without being formed over the first layer 111 or the second layer 112. In some embodiments, in addition to along the third layer 113 and the fourth layer 114, the passivation layer 130 will also be formed along the second layer 112 and the first layer 111, but not along the trench bottom 123. In some embodiments, the passivation layer 130 may be formed partially within the plurality of contact trenches 118 along the second layer 112.

[0022] In various embodiments, the ions 132 may be oxygen ions and / or nitrogen ions delivered at an angle of approximately 25° to 65°. It should be understood that the implantation angle may vary in other embodiments, e.g., ±10°. An angle that can be selected to prevent the ions from striking the second layer 112, the first layer 111, and the trench bottom 123 implants the ions into the plurality of contact trenches 118.

[0023] It should be understood that the degree to which the physical and / or chemical composition of the first sidewall 121 and the second sidewall 122 of each of the plurality of contact trenches 118 is modified may be determined by one or more variables including, but not limited to, the type of ions selected, the material properties of the surface being modified, the rotational orientation of the device 100, the temperature of the ion implantation, the concentration and / or dose of the ion implantation, and the energy of the ions being implanted into the surface being modified. Additionally, the device 100 may be rotated during or between successive implantations such that each of the first sidewall 121 and the second sidewall 122 of the device 100 is struck. For example, the device 100 may be rotated 45°, 90°, 180°, etc. between each implantation process. The embodiments herein are not limited in this context.

[0024] As Figure 4As shown, after forming the passivation layer 130, fill material 142 can then be formed within the plurality of contact trenches 118. More specifically, polysilicon can be grown epitaxially within each of the plurality of contact trenches 118 (including over each of the first layer 111, second layer 112, third layer 113, and fourth layer 114). As shown, fill material 142 can be in direct contact with one or more of the device structures 106. Generally, the Si growth rate on the Si surface is higher than the Si growth rate on the SiN surface, resulting in the middle part being pinched off by polysilicon, which creates gaps or voids within the polysilicon fill material. However, in the present disclosure, due to surface modification by ions 132 along the upper portions of the plurality of contact trenches 118 (e.g., along the third layer 113 and fourth layer 114), the growth rate of fill material 142 along the third layer 113 is delayed or inhibited. Thus, fill material 142 generally grows at the same or similar rate along both the second layer 112 and third layer 113 of the plurality of layers 110. As Figure 5 shown, once fill material 142 completely fills the plurality of contact trenches 118 (and is subsequently planarized), there are no voids or seams within fill material 142.

[0025] Figure 6 FIG. shows a schematic diagram of a processing apparatus 200 for implementing the processes set forth herein. An example of a beamline ion implantation processing apparatus is the Varian Trident series, which is available from Applied Materials Inc., Santa Clara, Calif. Processing apparatus 200 can include an ion source 201 for generating ions. For example, ion source 201 can provide ion implantation, such as Figure 3 the implantation of ions 132 as shown. Ion source 201 can also provide ion etching, such as for etching to form the plurality of contact trenches 118.

[0026] Processing apparatus 200 can also include a series of beamline components. Examples of beamline components can include an extraction electrode 203, a magnetic mass analyzer 211, a plurality of lenses 213, and a beam parallelizer 217. Processing apparatus 200 can also include a platen 219 for supporting a substrate 202 to be processed. Substrate 202 can be the same as substrate 102 described above. Substrate 202 can be moved in one or more dimensions (e.g., translated, rotated, tilted, etc.) by a component sometimes referred to as a “roplat” (not shown). It is also contemplated that processing apparatus 200 can be configured to implement a heated implantation process to improve control over implantation characteristics (such as ion trajectories and implantation energy for doping the substrate).

[0027] In operation, ions of a desired species, such as dopant ions, are generated and extracted from the ion source 201. Thereafter, the extracted ions 235 travel along the beam line assembly in a beam-like state and may be implanted into the substrate 202. Similar to a series of optical lenses that manipulate a light beam, the beam line assembly manipulates the extracted ions 235 along the ion beam. In this way, the extracted ions 235 are manipulated by the beam line assembly while being directed towards the substrate 202. It is contemplated that the apparatus 200 can provide improved mass selection for implanting the desired ions while reducing the likelihood that undesired ions (impurities) are implanted into the substrate 202.

[0028] In some embodiments, the processing apparatus 200 may be controlled by a processor-based system controller, such as the controller 230. For example, the controller 230 may be configured to control the beam line assembly and the processing parameters associated with the beam line ion implantation process. The controller 230 may include a programmable central processing unit (CPU) 232, which may operate in conjunction with a memory 234 and a mass storage device, an input control unit, and a display unit (not shown) (such as a power supply, a clock, a cache, input / output (I / O) circuitry, and similar components) that are coupled to various components of the processing apparatus 200 to facilitate control of substrate processing. The controller 230 also includes hardware for monitoring substrate processing through sensors in the processing apparatus 200, the sensors including sensors for monitoring the position of the substrate and sensors configured to receive feedback from and control a heating device coupled to the processing apparatus 200. Other sensors that measure system parameters, such as substrate temperature and similar parameters, may also provide information to the controller 230.

[0029] To facilitate the control of the above-described processing apparatus 200, the CPU 232 can be one of any form of general computer processor, and the general computer processor can be used in industrial settings (e.g., a programmable logic controller (PLC) for controlling various chambers and sub-processors). The memory 234 is coupled to the CPU 232, and the memory 234 is non-transitory and can be one or more readily available memories, such as random access memory (RAM), read only memory (ROM), floppy disk drive, hard disk, or any other form of local or remote digital storage device. The support circuitry 236 can be coupled to the CPU 232 to support the processor in a conventional manner. Generally, the implantation process and other processes are typically stored in the memory 234 as software routines. The software routines can also be stored and / or executed by a second CPU (not shown) that is located remotely from the hardware controlled by the CPU 232.

[0030] The memory 234 is in the form of a computer-readable storage medium containing instructions that, when executed by the CPU 232, facilitate the operation of the apparatus 200. The instructions in the memory 234 are in the form of a program product, such as a program implementing the method of the present disclosure. The program code can conform to any of a variety of different programming languages. In one example, the present disclosure can be implemented as a program product stored on a computer-readable storage medium for use with a computer system. The program of the program product defines the functions of the embodiments, including the methods set forth herein. Exemplary computer-readable storage media include, but are not limited to: (i) non-writable storage media on which information is permanently stored (e.g., read-only memory devices within a computer, such as CD-ROM disks readable by a compact disk read only memory (CD-ROM) drive, flash memory, ROM chips, or any type of solid-state non-volatile semiconductor memory); and (ii) writable storage media on which changeable information is stored (e.g., floppy disks in a floppy disk drive or hard disk drive, or any type of solid-state random access semiconductor memory). Such computer-readable storage media are embodiments of the present disclosure when carrying computer-readable instructions that direct the functions of the methods set forth herein.

[0031] It should be understood that the various layers, structures, and regions shown in the figures are merely illustrative examples. For ease of illustration, one or more layers, structures, and regions of the type typically used to form semiconductor devices or structures may not be explicitly shown in a given figure. This does not mean that any layer, structure, and / or region not explicitly shown is omitted from the actual semiconductor structure.

[0032] In various embodiments, a design tool may be provided and configured to create a data set for patterning a semiconductor layer of a device 100 as described herein, for example. For example, a data set may be created to generate a photomask used during a lithography operation to pattern a layer of a structure described herein. Such a design tool may include a collection of one or more modules and may also include hardware, software, or a combination thereof. Thus, for example, the tool may be a collection of one or more software modules, hardware modules, software / hardware modules, or any combination or arrangement thereof. As another example, the tool may be a computing device or other apparatus that runs software or is implemented in hardware.

[0033] Modules used herein may be implemented using any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, application specific integrated circuits (ASICs), programmable logic arrays (PLAs), logic components, software routines, or other mechanisms may be implemented to constitute a module. In an embodiment, the various modules described herein may be implemented as discrete modules, or the functions and features described may be partially or fully shared between one or more modules. In other words, to those of ordinary skill in the art, after reading the detailed description, it will be apparent that the various features and functions described herein may be implemented in any given application and may be implemented in one or more separate or shared modules in various combinations and arrangements. Although the various features or elements of the functions may be separately described or claimed as separate modules, those of ordinary skill in the art will understand that these features and functions may be shared between one or more common software and hardware elements.

[0034] For convenience and clarity, terms such as "top", "bottom", "upper", "lower", "vertical", "horizontal", "lateral", and "longitudinal" will be understood to describe the relative placement and orientation of components and their constituent parts as they appear in the various figures. The terms will include the specifically mentioned words, their derivatives, and words of similar meaning.

[0035] Unless explicitly stated to exclude plural elements or operations, an element or operation recited in the singular and preceded by the word "a" or "an" herein will be understood to include plural elements or operations. Additionally, reference to "one embodiment" of the present disclosure is not intended to be limiting. Additional embodiments may also include the recited features.

[0036] In addition, in some embodiments, the terms "substantial" or "substantially" and the terms "approximate" or "approximately" may be used interchangeably and may be elaborated using any relative measure acceptable to a person of ordinary skill in the art. For example, these terms may be used as a comparison with a reference parameter to indicate a deviation that can provide the desired function. Although non-limiting, the deviation from the reference parameter may be, for example, an amount less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, and so on.

[0037] Furthermore, those of ordinary skill in the art will understand that when an element such as a layer, region, or substrate is referred to as being formed on, deposited on, or disposed on another element "on", "above", or "over" the other element, the element may be directly on the other element, or there may also be intervening elements. In contrast, when an element is referred to as being "directly" on another element "on", "directly" on another element "above", or "directly" on another element "over", there are no intervening elements.

[0038] As used herein, "depositing" and / or "being deposited" may include any currently known or later developed techniques suitable for the material to be deposited, including but not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), and plasma-enhanced CVD (PECVD). Additional techniques may include semi-atmosphere CVD (SACVD), high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), and sputter deposition. Additional techniques may include ion beam deposition, electron beam deposition, laser-assisted deposition, thermal oxidation, thermal nitridation, spin coating methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.

[0039] Although certain embodiments of the present disclosure have been set forth herein, the present disclosure is not limited thereto, as the scope of the present disclosure is as broad as the art will permit and as the specification may set forth. Accordingly, the foregoing description should not be construed as limiting. Rather, the foregoing description is merely exemplary of particular embodiments. Those skilled in the art will envision other modifications that are within the scope and spirit of the appended claims.

Claims

1. A method, comprising: forming a plurality of trenches in a substrate, the plurality of trenches defining a plurality of device structures; depositing a plurality of layers over the plurality of device structures, the plurality of layers including a first layer over the plurality of device structures, a second layer over the first layer, and a third layer over the second layer; forming a plurality of contact trenches through the plurality of layers to expose one or more of the plurality of device structures; directing ions into sidewalls of the plurality of contact trenches at a non-zero angle relative to a perpendicular line extending from a top surface of the plurality of layers, wherein the ions strike the third layer and do not strike the second layer; and forming a fill material in the plurality of contact trenches after directing the ions into the sidewalls of the plurality of contact trenches.

2. The method according to claim 1, further comprising: forming the fill material outside the top surface of the plurality of layers; and planarizing the fill material.

3. The method according to claim 1, further comprising forming a fourth layer over the third layer in the plurality of layers, wherein the fourth layer is of the same material as the first layer.

4. The method according to claim 3, further comprising directing ions into the sidewalls of the plurality of contact trenches to form a passivation layer along the sidewalls of the plurality of contact trenches, wherein the passivation layer is formed over the fourth layer and the third layer and not over the second layer or the first layer, and wherein the passivation layer prevents the fill material from growing along the third layer.

5. The method according to claim 3, wherein the first layer is an oxide material, the second layer is a silicon nitride layer, the third layer is a polysilicon layer, and the fourth layer is the oxide material.

6. The method according to claim 1, wherein the fill material is formed directly on top of the one or more of the plurality of device structures.

7. The method according to claim 1, wherein forming the fill material in the plurality of contact trenches includes epitaxially growing polysilicon in the plurality of contact trenches.

8. A method of forming a dynamic random access memory device, the method comprising: forming source trench isolation (STI) material over a plurality of trenches in a substrate, the plurality of trenches defining a plurality of device structures; depositing a plurality of layers over the plurality of device structures, the plurality of layers including a first layer over the source trench isolation material, a second layer on top of the first layer, and a third layer on top of the second layer, wherein the second layer and the third layer are of different materials; forming a plurality of contact trenches through the plurality of layers to expose one or more of the plurality of device structures; directing ions into sidewalls of the plurality of contact trenches at a non-zero angle relative to a perpendicular line extending from a top surface of the plurality of layers, wherein the ions strike the third layer and do not strike the second layer; and forming a fill material in the plurality of contact trenches after directing the ions into the sidewalls of the plurality of contact trenches.

9. The method according to claim 8, further comprising: forming the filling material over the top surface of the plurality of layers; and planarizing the filling material to the top surface of the plurality of layers.

10. The method according to claim 8, further comprising forming a fourth layer over the third layer among the plurality of layers, wherein the fourth layer is of the same material as the first layer.

11. The method according to claim 10, wherein ions are directed into the sidewalls of the plurality of contact trenches such that a passivation layer is formed along the sidewalls of the plurality of trenches, wherein the passivation layer is formed over the fourth layer and the third layer, and not over the second layer or the third layer, and wherein the passivation layer prevents the filling material from growing along the third layer.

12. The method according to claim 10, wherein the first layer is an oxide material, wherein the second layer is a silicon nitride layer, wherein the third layer is a polysilicon layer, and wherein the fourth layer is the oxide material.

13. The method according to claim 8, wherein the filling material is directly formed over one or more of the plurality of device structures.

14. The method according to claim 8, wherein forming the filling material within the plurality of contact trenches comprises epitaxially growing polysilicon within the plurality of contact trenches.

15. A method of forming bit line contacts of a dynamic random access memory device, the method comprising: providing a plurality of trenches in a substrate, the plurality of trenches defining a plurality of device structures; depositing a plurality of layers over the plurality of device structures, the plurality of layers including a first layer over the plurality of device structures, a second layer over the first layer, and a third layer over the second layer, wherein the second layer and the third layer are of different materials; forming a plurality of contact trenches through the plurality of layers to expose one or more of the plurality of device structures; forming a passivation layer along the sidewalls of the plurality of contact trenches by directing ions into the sidewalls of the plurality of contact trenches at a non-zero angle relative to a perpendicular line extending from the top surface of the plurality of layers, wherein the ions impinge on the third layer and not on the second layer; and forming a filling material within the plurality of contact trenches after directing the ions into the sidewalls of the plurality of contact trenches.

16. The method according to claim 15, further comprising forming a fourth layer over the third layer among the plurality of layers, wherein the fourth layer is of the same material as the first layer.

17. The method according to claim 16, wherein the passivation layer is formed only over the fourth layer and the third layer, and wherein the passivation layer prevents the filling material from growing along the third layer.

18. The method according to claim 16, wherein the first layer is an oxide material, wherein the second layer is a silicon nitride layer, wherein the third layer is a polysilicon layer, and wherein the fourth layer is the oxide material.

19. The method according to claim 15, wherein the filling material is directly formed on top of one or more of the plurality of device structures.

20. The method according to claim 15, wherein forming the filling material in the plurality of contact trenches includes epitaxially growing polysilicon in the plurality of contact trenches, and wherein preventing the polysilicon from epitaxially growing along the third layer relative to the second layer would prevent voids from forming in the filling material after the filling material reaches the top surface of the plurality of layers.

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