High-surge MOS structure and preparation method thereof

Abstract

The invention relates to a high-surge MOS (Metal Oxide Semiconductor) structure and a preparation method thereof, and the structure comprises at least two gate structures, at least two gate transverse strips which are arranged between the two adjacent gate structures, and second conduction type body regions which are arranged between the two adjacent gate structures, the second conduction type body regions on the two sides of the grid transverse strips are connected, the first conduction type first source regions are arranged in the second conduction type body regions, make contact with the grid structures and extend in the length direction of the grid structures, and the first conduction type second source regions are arranged in the second conduction type body regions and make contact with the grid structures. And the first conduction type first source region and the first conduction type second source region are in transverse contact with the grid electrode and extend along the length direction of the grid electrode transverse strip, and the first conduction type first source region and the first conduction type second source region are connected, so that the junction area of the second conduction type body region in the MOS device is obviously increased, the junction area of a P / N junction is effectively increased, and the reliability of the MOS device is improved. And the anti-surge capability of the MOS device is effectively enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a high-surge MOS structure and a manufacturing method thereof. Background Art

[0002] MOS (Metal Oxide Semiconductor) devices are important power semiconductor devices, which are widely used in power electronic equipment, industrial control systems, and consumer electronic products. They have attracted wide attention due to their high switching efficiency, low power consumption, and excellent current control performance. In practical applications, MOS devices usually need to work in an environment of high voltage and high surge current, so their surge resistance directly affects the reliability and service life of the devices.

[0003] Existing MOS devices, such as Figure 1 shown, usually adopt a strip cell structure. A strip-shaped source region structure 15 is arranged in a body region structure 16, and the performance of the device is improved by optimizing the doping parameters and layout of the body region structure 16 and the source region structure 15.

[0004] However, in this design, the junction area of the body region structure is relatively small, resulting in a relatively small P / N junction area. When it is required to be used in an environment of high surge current and high voltage impact, the carrier capacity of the P / N junction is limited and cannot effectively disperse surge charges, thus easily leading to local overheating or even device breakdown, significantly affecting the surge resistance performance of the MOS device. Therefore, it is necessary to provide a MOS device that can significantly improve the surge resistance ability of the device to adapt to the application environment of high surge current and high voltage impact. Summary of the Invention

[0005] In view of this, the purpose of the present invention is to provide a high-surge MOS structure and a manufacturing method thereof, so as to solve the technical problems in the prior art that the junction area of the body region is relatively small, the P / N junction area is relatively small, and the surge resistance performance is poor.

[0006] The present invention provides a high-surge MOS structure, including:

[0007] A gate structure, with at least two provided;

[0008] A gate bar, arranged between two adjacent gate structures and with at least two provided;

[0009] A body region of a second conductivity type, arranged between two adjacent gate structures, and the body regions of the second conductivity type on both sides of the gate bar are connected;

[0010] A first source region of a first conductivity type, arranged in the body region of the second conductivity type, in contact with the gate structure, and extending along the length direction of the gate structure;

[0011] A second source region of the first conductivity type is disposed in the body region of the second conductivity type, in lateral contact with the gate and extending along the length direction of the gate bar;

[0012] The first source region of the first conductivity type and the second source region of the first conductivity type are connected.

[0013] Optionally, there are two first source regions of the first conductivity type and two second source regions of the first conductivity type located between two gate bars, and they are connected to form a ring.

[0014] Optionally, the width of the gate bar in the first direction is less than the width of the gate structure in the second direction.

[0015] Optionally, the width of the first source region of the first conductivity type in the second direction is the same as the width of the second source region of the first conductivity type in the first direction.

[0016] Optionally, it further includes:

[0017] A substrate of the first conductivity type;

[0018] An epitaxial layer of the first conductivity type is disposed on the front surface of the substrate of the first conductivity type. The gate structure is disposed on the front surface of the epitaxial layer of the first conductivity type. The body region of the second conductivity type is disposed on the front surface of the epitaxial layer of the first conductivity type and within the epitaxial layer of the first conductivity type. The first source region of the first conductivity type and the second source region of the first conductivity type are located within the body region of the second conductivity type.

[0019] Optionally, a high-resistance region of the first conductivity type is disposed on the back surface of the body region of the second conductivity type, and the resistivity of the high-resistance region of the first conductivity type is higher than the resistivity of the epitaxial layer of the first conductivity type.

[0020] Optionally, it further includes an extension column of the second conductivity type. The extension column of the second conductivity type is disposed within the high-resistance region of the first conductivity type, and the extension column of the second conductivity type is connected to the body region of the second conductivity type and the epitaxial layer of the first conductivity type respectively.

[0021] Optionally, there are at least two extension columns of the second conductivity type corresponding to each body region of the second conductivity type, and multiple extension columns of the second conductivity type are spaced along the first direction within the high-resistance region of the first conductivity type.

[0022] Optionally, it further includes:

[0023] An insulating dielectric layer is disposed on the front surface of the epitaxial layer of the first conductivity type and covers the gate structure;

[0024] A front metal layer is disposed on the front surface of the insulating dielectric layer;

[0025] A back metal layer is disposed on the back surface of the first-conductive-type substrate.

[0026] The present invention also provides a method for manufacturing a high-surge MOS structure, which includes:

[0027] Select a first-conductive-type substrate, and grow a first-conductive-type epitaxial layer on the first-conductive-type substrate;

[0028] Through photolithographic masking, deposit polysilicon in partial regions on the front surface of the first-conductive-type epitaxial layer to form a plurality of gate structures, and form a plurality of gate bars between two adjacent gate structures;

[0029] Inject first-conductive-type ions with high resistivity into the front surface of the first-conductive-type epitaxial layer without a gate structure to form a first-conductive-type high-resistance region;

[0030] Inject second-conductive-type ions at the first-conductive-type high-resistance region to form a second-conductive-type extension column and a second-conductive-type body region, and perform high-temperature drive to connect the second-conductive-type body regions on both sides of the gate bar;

[0031] By placing a photolithographic mask plate at the centers of two gate bars and the second-conductive-type body region between the two gate bars, and injecting first-conductive-type ions into the region on the front surface of the second-conductive-type body region without a photolithographic mask plate, to form a first-conductive-type first source region and a first-conductive-type second source region;

[0032] Form an insulating dielectric layer and a front metal layer on the front surface of the first-conductive-type epitaxial layer, and form a back metal layer on the back surface of the first-conductive-type substrate.

[0033] The technical solution of the present invention has the following advantages:

[0034] In the high-surge MOS structure provided by the present invention, by arranging a plurality of gate bars between two gate structures, a first-conductive-type first source region is arranged at the gate structure, and a first-conductive-type second source region is arranged at the gate bar, so that the junction area of the second-conductive-type body region in the MOS structure can be significantly increased, and further the junction area of the P / N junction can be effectively increased, effectively enhancing the surge resistance of the MOS device, so as to be able to adapt to application environments with higher surge currents and high-voltage impacts, and having a wider adaptability. Description of the Drawings

[0035] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and thus should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0036] Figure 1 Schematic diagram of the prior art in the background art of the present invention;

[0037] Figure 2 Schematic diagram of the high-surge MOS structure in the present invention;

[0038] Figure 3 Schematic diagram of the internal structure of the high-surge MOS structure in the present invention;

[0039] Figure 4 Step diagram of the preparation method of the high-surge MOS structure in the present invention.

[0040] Explanation of reference numerals:

[0041] 1. Gate structure; 2. Gate bar; 3. Body region of the second conductivity type; 4. First source region of the first conductivity type; 5. Second source region of the first conductivity type; 6. Substrate of the first conductivity type; 7. Epitaxial layer of the first conductivity type; 8. Gate oxide layer; 9. High-resistance region of the first conductivity type; 10. Extension column of the second conductivity type; 11. Insulating dielectric layer; 12. Front metal layer; 13. Back metal layer; 14. Metal contact via; 15. Source region structure; 16. Body region structure. Specific embodiments

[0042] The following will describe in detail specific embodiments of the present invention in conjunction with the drawings. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the description of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present invention.

[0043] Unless otherwise clearly specified and limited, terms such as "arranged", "installed", "connected", etc. should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific situations.

[0044] The orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the inventive product is customarily placed during use. It is only for the convenience of description and to simplify the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the present invention.

[0045] Terms such as "first", "second", "third", etc. are merely used to distinguish elements with similar attributes, rather than indicating or implying relative importance or a specific order.

[0046] The term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion. In addition to the listed elements, it may also include other elements not expressly listed.

[0047] Embodiment 1

[0048] The MOS structure includes an N-type MOS structure and a P-type MOS structure. For the N-type MOS structure, the first conduction type is N-type and the second conduction type is P-type; for the P-type MOS structure, the first conduction type is P-type and the second conduction type is N-type. In this embodiment, the N-type MOS structure is taken as an example.

[0049] Referring to Figure 2 and Figure 3 As shown, the present invention provides a high-surge MOS structure, which includes a gate structure 1, a gate bar 2, a body region 3 of the second conduction type, a first source region 4 of the first conduction type, and a second source region 5 of the first conduction type. Among them, at least two gate structures 1 are provided, and a gap is left between two adjacent gate structures 1 to provide the body region 3 of the second conduction type, the first source region 4 of the first conduction type, and the second source region 5 of the first conduction type. The gate bar 2 is provided between two adjacent gate structures 1 and at least two are provided. The two gate bars 2 are arranged in parallel, and both ends of the gate bar 2 are respectively connected to the adjacent gate structures 1;

[0050] The body region 3 of the second conduction type is provided between two adjacent gate structures 1 and is located on the back of the gate structure 1 and the gate bar 2. And the body region 3 of the second conduction type is provided between two adjacent gate structures 1. The body regions 3 of the second conduction type on both sides of the gate bar 2 are connected below the gate bar 2. The first source region 4 of the first conduction type is provided at the gate structure 1 and extends along the length direction of the gate structure 1. The second source region 5 of the first conduction type is provided at the gate bar 2 and extends along the length direction of the gate bar 2. Both ends of the second source region 5 of the first conduction type are respectively connected to the first source regions 4 at the two ends of the gate structure 1.

[0051] Between two gate bars 2, there are provided two first-conduction-type first source regions 4 arranged in parallel and two first-conduction-type second source regions 5 arranged in parallel, corresponding to two gate structures 1 and two gate bars 2 respectively. The two first-conduction-type first source regions 4 and the first-conduction-type second source regions 5 are arranged in a rectangular layout, and the two ends of the first-conduction-type first source region 4 are respectively connected to the ends of the first-conduction-type second source region 5, and the two ends of the first-conduction-type second source region 5 are respectively connected to the ends of the first-conduction-type first source region 4, thereby forming an annular structure.

[0052] By arranging a plurality of gate bars 2 between two gate structures 1, while arranging the first-conduction-type first source region 4 at the gate structure 1, the first-conduction-type second source region 5 is arranged at the gate bar 2, thereby significantly increasing the junction area of the second-conduction-type body region 3 in the MOS structure, further effectively increasing the junction area of the P / N junction, effectively enhancing the surge resistance of the MOS device, and thus being able to adapt to application environments with higher surge currents and high-voltage impacts, with a wider adaptability.

[0053] Further, the width of the gate bar 2 in the first direction is less than the width of the gate structure 1 in the second direction. The width of the first-conduction-type first source region 4 in the second direction is the same as the width of the first-conduction-type second source region 5 in the first direction. After injecting second-conduction-type ions on both sides of the gate bar 2, through high-temperature drive, the second-conduction-type body regions 3 on both sides of the gate bar 2 can be brought into contact and connected. In addition, the direction of arrow x in the figure is the first direction, and the direction of arrow Y is the second direction.

[0054] As a specific implementation manner, referring to Figure 3 As shown, the high-surge MOS device further includes a first-conduction-type substrate 6, a first-conduction-type epitaxial layer 7, an insulating dielectric layer 11, a front metal layer 12, and a back metal layer 13. Among them, the first-conduction-type substrate 6 selects N-type silicon as the substrate, the first-conduction-type epitaxial layer 7 is arranged on the front surface of the first-conduction-type substrate 6, the gate structure 1 is arranged on the front surface of the first-conduction-type epitaxial layer 7, a plurality of gate structures 1 are arranged at intervals on the front surface of the first-conduction-type epitaxial layer 7, the second-conduction-type body region 3 is arranged on the front surface of the first-conduction-type epitaxial layer 7 and is arranged within the first-conduction-type epitaxial layer 7. The second-conduction-type body region 3 is arranged between adjacent two gate structures 1. The first-conduction-type first source region 4 and the first-conduction-type second source region 5 are located within the second-conduction-type body region 3. The insulating dielectric layer 11 is arranged on the front surface of the first-conduction-type epitaxial layer 7 and covers the gate structure 1. The front metal layer 12 is arranged on the front surface of the insulating dielectric layer 11, and the back metal layer 13 is arranged on the back surface of the first-conduction-type substrate 6.

[0055] Further, a first-conductivity-type high-resistance region 9 is provided on the back surface of the second-conductivity-type body region 3. The first-conductivity-type high-resistance region 9 is located within the first-conductivity-type epitaxial layer 7. The resistivity of the first-conductivity-type high-resistance region is higher than that of the first-conductivity-type epitaxial layer 7. A second-conductivity-type extension pillar 10 is provided within the first-conductivity-type high-resistance region 9. The second-conductivity-type extension pillar 10 extends towards the second-conductivity-type body region 3 until it is connected to the second-conductivity-type body region 3. Additionally, the second-conductivity-type extension pillar 10 also extends towards the first-conductivity-type substrate 6 until it extends into the first-conductivity-type epitaxial layer 7 and is connected to the first-conductivity-type epitaxial layer 7;

[0056] Through the provision of the first-conductivity-type high-resistance region 9, under high-current conditions, a considerable portion of the electron current will flow through the first-conductivity-type high-resistance region 9. There is a parasitic resistance within the first-conductivity-type high-resistance region 9. Therefore, a lateral voltage drop will be generated within the first-conductivity-type high-resistance region 9, resulting in a significant reduction in the potential below the center of the second-conductivity-type body region 3. The P / N junction within the device can be opened more effectively, achieving a higher current-carrying capacity, thereby enabling the device to have a higher surge current resistance and further enhancing the surge resistance.

[0057] Embodiment 2

[0058] Referring to Figures 2-4 As shown, this embodiment provides a method for fabricating a high-surge MOS structure, including:

[0059] S1, select a first-conductivity-type substrate 6, and grow a first-conductivity-type epitaxial layer 7 on the first-conductivity-type substrate 6. The first-conductivity-type substrate 6 selects N-type silicon as the substrate, and the first-conductivity-type epitaxial layer 7 is grown by an epitaxial process;

[0060] S2, grow a gate oxide layer 8 on the front surface of the first-conductivity-type epitaxial layer 7, and etch away a part of the gate oxide layer 8 through photolithographic masking. Through photolithographic masking again, deposit polysilicon on the front surface of the gate oxide layer 8, that is, on a partial region of the first-conductivity-type epitaxial layer 7, to form a plurality of gate structures 1, and deposit polysilicon between two gate structures 1 to form a plurality of gate crossbars 2;

[0061] S3, inject first-conductivity-type ions with a high resistivity into the front surface of the first-conductivity-type epitaxial layer 7 without the gate structure 1, and perform high-temperature drive-in to form a first-conductivity-type high-resistance region 9;

[0062] S4, inject second-conductivity-type ions at the first-conductivity-type high-resistance region 9, and perform high-temperature drive-in to form a second-conductivity-type extension pillar 10 and a second-conductivity-type body region 3, and the second-conductivity-type body regions 3 on both sides of the gate crossbar 2 are in contact and connected;

[0063] S5. Place a photolithography mask at the two gate bars 2 and at the center of the front surface of the body region 3 of the second conductivity type between the two gate bars 2. Inject ions of the first conductivity type into the regions of the front surface of the body region 3 of the second conductivity type without the photolithography mask, and perform high-temperature drive-in to form a first source region 4 of the first conductivity type and a second source region 5 of the first conductivity type. The first source region 4 of the first conductivity type and the second source region 5 of the first conductivity type are connected;

[0064] S6. Deposit an insulating dielectric layer 11 on the front surface of the epitaxial layer 7 of the first conductivity type so that the insulating dielectric layer 11 wraps the gate structure 1. Then, etch the insulating dielectric layer 11 to etch out a plurality of through holes in the insulating dielectric layer 11, thereby forming metal contact through holes 14. The metal contact through holes 14 are located above the body region 3 of the second conductivity type. And during etching, an additional 0.3 mm to 0.4 mm is etched into the epitaxial layer 7 of the first conductivity type to ensure that the insulating dielectric layer 11 can be completely removed, exposing the metal contact points, ensuring the stability and reliability of the electrical connection. Deposit metal on the front surface of the insulating dielectric layer 11 and fill the metal contact through holes 14 to form a front metal layer 12, and deposit metal on the back surface of the substrate 6 of the first conductivity type to form a back metal layer 13.

[0065] By arranging a plurality of gate bars 2 between the two gate structures 1, a first source region 4 of the first conductivity type is arranged at the gate structure 1, and a second source region 5 of the first conductivity type is arranged at the gate bars 2, so that the junction area of the body region 3 of the second conductivity type in the MOS structure can be significantly increased, and further the junction area of the P / N junction can be effectively increased, effectively enhancing the surge resistance of the MOS device, so as to be able to adapt to an application environment with higher surge current and high-voltage impact, and having a wider adaptability.

[0066] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other.

[0067] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A high surge MOS structure, characterized in that: include: A gate structure, at least two of which are provided; A gate horizontal bar, which is arranged between two adjacent gate structures and at least two gate horizontal bars are arranged; A second conductive type body region is disposed between two adjacent gate structures and below the gate bar; A first source region of the first conductivity type is disposed in the body region of the second conductivity type, corresponds to the gate structure, and extends along the length direction of the gate structure; A first conductive type second source region, disposed in the second conductive type body region, corresponding to the gate laterally and extending along the length direction of the gate horizontal strip; The first conductive type first source region and the first conductive type second source region are connected.

2. The high surge MOS structure according to claim 1, characterized in that: Two first conductive type first source regions and two first conductive type second source regions are provided between the two gate horizontal bars and are connected to each other in a ring shape.

3. The high surge MOS structure according to claim 1, characterized in that: The width of the gate bar along the first direction is smaller than the width of the gate structure along the second direction.

4. The high surge MOS structure according to claim 1, characterized in that: The width of the first conductive type first source region along the second direction is the same as the width of the first conductive type second source region along the first direction.

5. The high surge MOS structure according to claim 1, characterized in that: Also includes: a first conductive type substrate; A first conductive type epitaxial layer is arranged on the front side of the first conductive type substrate, the gate structure is arranged on the front side of the first conductive type epitaxial layer, the second conductive type body region is arranged on the front side of the first conductive type epitaxial layer and is arranged in the first conductive type epitaxial layer, and the first conductive type first source region and the first conductive type second source region are located in the second conductive type body region.

6. The high surge MOS structure according to claim 5, characterized in that: A first conductivity type high resistance region is disposed on the back side of the second conductivity type body region, and the resistivity of the first conductivity type high resistance region is higher than the resistivity of the first conductivity type epitaxial layer.

7. The high surge MOS structure according to claim 6, characterized in that: It also includes a second conductive type extension column, which is arranged in the first conductive type high resistance region and is respectively connected to the second conductive type body region and the first conductive type epitaxial layer.

8. The high surge MOS structure according to claim 7, characterized in that: At least two second conductivity type extension columns are correspondingly arranged at each second conductivity type body region, and a plurality of second conductivity type extension columns are arranged in the first conductivity type high resistance region at intervals along the first direction.

9. The high surge MOS structure according to claim 5, characterized in that: Also includes: An insulating dielectric layer, disposed on the front side of the first conductive type epitaxial layer and covering the gate structure; A front metal layer, arranged on the front side of the insulating dielectric layer; The back metal layer is arranged on the back side of the first conductive type substrate.

10. A method for preparing a high surge MOS structure, characterized in that: include: Selecting a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate; Depositing polysilicon on a partial area of ​​the front surface of the first conductive type epitaxial layer by photolithography shielding to form a plurality of gate structures, and forming a plurality of gate horizontal bars between two adjacent gate structures; Implanting first conductivity type ions with high resistivity into the front surface of the first conductivity type epitaxial layer without a gate structure to form a first conductivity type high resistance region; Implanting second conductive type ions at the first conductive type high resistance region to form second conductive type extension columns and second conductive type body regions, and advancing at high temperature to connect the second conductive type body regions on both sides of the gate bar; Placing a photolithography shield at the center of the second conductive type body region between two gate horizontal bars and the two gate horizontal bars, and implanting first conductive type ions in a region on the front side of the second conductive type body region without the photolithography shield to form a first conductive type first source region and a first conductive type second source region; An insulating dielectric layer and a front metal layer are formed on the front side of the first conductive type epitaxial layer, and a back metal layer is formed on the back side of the first conductive type substrate.

Images