Forming connection structures in memory systems

Abstract

Three-dimensional (3D) memory devices, methods, and memory systems for connecting vertical transistors and capacitors using connection structures are disclosed. An exemplary method includes forming a first structure including a plurality of vertical transistors. A connection layer is formed over the first structure. The connection layer is etched to form connection structures, where each of the connection structures is coupled to a corresponding one of the vertical transistors. A plurality of capacitors is formed over the connection layer, where each capacitor of the plurality of capacitors is coupled to a respective connection structure.

Description

Technical Field

[0001] The present disclosure relates to forming connection structures in three-dimensional (3D) memory devices and memory systems. Background Art

[0002] The memory system may include a switching device and a storage element connected by a connection structure. A vertical transistor may be used as a switching device to simplify the layout of word lines and bit lines of metal wiring. A 3D memory device may include a memory array of memory cells and peripheral circuits for facilitating the operation of the memory array. The memory cell may include a vertical transistor. Summary of the invention

[0003] The present disclosure relates to a three-dimensional (3D) memory device, method, and memory system for connecting vertical transistors and capacitors using a connection structure. An exemplary method includes: forming a first structure including a plurality of vertical transistors. Forming a connection layer on the first structure. Etching the connection layer to form a connection structure, wherein each of the connection structures is coupled to a corresponding vertical transistor in the vertical transistors. Forming a plurality of capacitors on the connection layer, wherein each of the plurality of capacitors is coupled to a corresponding connection structure.

[0004] The details of one or more implementations of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1A A schematic diagram showing a cross-section of a 3D memory device according to some aspects of the present disclosure.

[0006] Figure 1B A schematic diagram showing a cross section of another 3D memory device according to some aspects of the present disclosure.

[0007] Figure 2 A schematic diagram of a memory device 200 including peripheral circuitry and an array of memory cells, each having a vertical transistor, is shown according to some aspects of the present disclosure.

[0008] Figure 3A and Figure 3B A plan view and a side view, respectively, of an array of memory cells in a memory device according to some aspects of the present disclosure, each memory cell including a vertical transistor.

[0009] 4A to 4H An exemplary process for forming a connection structure between a vertical transistor and a capacitor according to some aspects of the present disclosure is shown.

[0010] Figure 5 An exemplary structure including a one transistor one capacitor (1T1C) array and a unit capacitor region according to some aspects of the present disclosure is shown.

[0011] FIG. 6A to FIG. 6C Three types of capacitors are shown in accordance with some aspects of the present disclosure.

[0012] 7A to 7E Another exemplary process of forming a connection structure between a vertical transistor and a capacitor according to some aspects of the present disclosure is shown.

[0013] Figure 8 An example of a flow chart of a method for forming a connection structure connecting a vertical transistor and a capacitor according to some aspects of the present disclosure is shown.

[0014] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0015] This specification relates to a 3D memory device, method, and memory system for connecting a vertical transistor and a capacitor using a connection structure. In some cases, due to the size limitations associated with the vertical transistor, it may be challenging to form a connection structure between the vertical transistor and the capacitor. In order to mitigate the impact of the size limitations associated with the vertical transistor, a connection layer can first be formed over a plurality of vertical transistors, and then an etching process can be applied to the connection layer to form a plurality of connection structures, each connecting the vertical transistor and a corresponding capacitor. The connection layer can be formed by sequentially depositing a plurality of layers, each layer having a different material.

[0016] Embodiments of the present disclosure may provide one or more of the following technical advantages and / or benefits. For example, a polysilicon layer may be formed as part of a connection layer prior to an etching process to avoid inconsistencies in polysilicon in a single connection structure. A silicide layer may also be formed as part of a connection layer prior to an etching process to avoid inconsistencies in silicide in a single connection structure. In addition, processing associated with interfaces between different components of a memory cell may be simplified.

[0017] In some embodiments, vertical transistors can be used as switches and selection devices in memory cell arrays of memory devices (e.g., DRAM, PCM, and ferroelectric DRAM (FRAM)). Compared with planar transistors, vertically arranged transistors (i.e., the drain and source overlap in a plan view) can reduce the area of ​​the transistor and simplify the layout of the interconnect structure (e.g., metal wiring of word lines and bit lines), which can reduce manufacturing complexity and improve yield. For example, the spacing of word lines and / or bit lines can be reduced for ease of manufacturing. The vertical structure of the transistor also allows the bit line and the storage element (e.g., capacitor) to be arranged on opposite sides of the transistor in the vertical direction (e.g., one above the transistor and one below the transistor), so that the process margin of the bit line can be increased, and the coupling capacitance between the bit line and the storage element can be reduced.

[0018] In some embodiments, the vertical transistor may include a multi-gate transistor (e.g., a gate-all-around (GAA) transistor, a tri-gate transistor, or a dual-gate transistor), which may have a larger gate control region, thereby achieving better channel control with a smaller subthreshold swing. During the off state, the leakage current of the multi-gate transistor may also be significantly reduced due to the complete depletion of the channel. Therefore, using a multi-gate transistor instead of a planar transistor may achieve enhanced speed (saturated drain current) / leakage current performance.

[0019] In some embodiments, due to the use of trench isolation extending in the word line direction to divide the multi-gate transistor (e.g., double-gate transistor), the vertical transistor can include a single-gate transistor (also known as a single-side gate transistor) arranged in a mirror-symmetrical manner relative to the adjacent transistor in the bit line direction. Therefore, compared with using a process such as self-aligned double patterning (SADP), the memory cell density in the bit line direction can be significantly increased (e.g., doubled) without making the manufacturing process too complicated. Moreover, compared with planar transistors or multi-gate vertical transistors (e.g., with double-sided or full-surround gates), the mirror-symmetrical single-gate transistor has a larger process window for reducing the word line, bit line and transistor spacing.

[0020] Figure 1AA schematic diagram of a cross section of a 3D memory device 100 according to some aspects of the present disclosure is shown. The 3D memory device 100 represents an example of a bonded chip. The components of the 3D memory device 100 (e.g., the memory cell array and the peripheral circuits) can be formed separately on different substrates and then bonded to form a bonded chip. The 3D memory device 100 may include a first semiconductor structure 102, which includes the peripheral circuits of the memory cell array. The 3D memory device 100 may also include a second semiconductor structure 104, which includes the memory cell array. The peripheral circuits (e.g., control and sensing circuits) may include any suitable digital, analog, and / or mixed signal circuits for facilitating the operation of the memory cell array. For example, the peripheral circuit may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), an input / output (I / O) circuit, a charge pump, a voltage source or a voltage generator, a current reference or a voltage reference, any part (e.g., a subcircuit) of the functional circuit mentioned above, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). According to some embodiments, the peripheral circuit in the first semiconductor structure 102 uses complementary metal oxide semiconductor (CMOS) technology, for example, it can be implemented using a logic process (e.g., a technology node of 90nm, 65nm, 60nm, 45nm, 32nm, 28nm, 22nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.).

[0021] like Figure 1A As shown, the 3D memory device 100 may also include a second semiconductor structure 104, which includes an array of memory cells (memory cell array) that can use transistors as switches and selection devices. In some embodiments, the memory cell array includes an array of DRAM cells. For ease of description, a DRAM cell array may be used as an example to describe the memory cell array in the present disclosure. However, it should be understood that the memory cell array is not limited to a DRAM cell array, and may include any other suitable type of memory cell array that can use transistors as switches and selection devices, such as a PCM cell array, a static random access memory (SRAM) cell array, a FRAM cell array, a resistive memory cell array, a magnetic memory cell array, a spin transfer torque (STT) memory cell array, or any combination thereof, to name a few.

[0022] The second semiconductor structure 104 may be a DRAM device that provides memory cells in the form of an array of DRAM cells. In some embodiments, each DRAM cell includes a capacitor for storing a data bit as a positive charge or a negative charge and one or more transistors (e.g., a turn-on transistor) that control (e.g., switch and select) access to it. In some embodiments, each DRAM cell is a transistor, a capacitor (1T1C) cell. Since the transistor may leak a small amount of charge, the capacitor may discharge slowly, causing the information stored therein to be exhausted. Thus, according to some embodiments, for example, the DRAM cell may be refreshed by the peripheral circuit in the first semiconductor structure 102 to maintain the data.

[0023] like Figure 1A As shown, the 3D memory device 100 also includes a vertically located (in the vertical direction, for example, Figure 1A The bonding interface 106 between the first semiconductor structure 102 and the second semiconductor structure 104 is formed in a manner that is in the z-direction (in the z-direction) of the first semiconductor structure 102 and the second semiconductor structure 104. As described in detail below, the first semiconductor structure 102 and the second semiconductor structure 104 can be manufactured separately (and in some embodiments, in parallel) so that the thermal budget of manufacturing one of the first semiconductor structure 102 and the second semiconductor structure 104 does not limit the process of manufacturing the other of the first semiconductor structure 102 and the second semiconductor structure 104. In addition, in contrast to the long-distance (e.g., millimeter or centimeter-level) chip-to-chip data bus on a circuit board such as a printed circuit board (PCB), a large number of interconnects (e.g., bonding contacts) can be formed across the bonding interface 106 to form a direct, short-distance (e.g., micrometer-level) electrical connection between the first semiconductor structure 102 and the second semiconductor structure 104, thereby eliminating chip interface delays and achieving high-speed I / O throughput with reduced power consumption. Data transmission between the memory cell array in the second semiconductor structure 104 and the peripheral circuit in the first semiconductor structure 102 can be performed through the interconnects (e.g., bonding contacts) across the bonding interface 106. By vertically integrating the first semiconductor structure 102 with the second semiconductor structure 104 , the chip size may be reduced and the memory cell density may be increased.

[0024] It should be understood that the relative positions of the stacked first semiconductor structure 102 and the second semiconductor structure 104 are not limited. Figure 1B Schematic diagram showing a cross section of another 3D memory device 101 according to some aspects of the present disclosure. Figure 1A 3D memory device 100 in which a second semiconductor structure 104 including a memory cell array is located above a first semiconductor structure 102 including a peripheral circuit, Figure 1BIn the 3D memory device 101 in FIG. 1 , a first semiconductor structure 102 including a peripheral circuit is located above a second semiconductor structure 104 including a memory cell array. Nevertheless, according to some embodiments, a bonding interface 106 is vertically formed between the first semiconductor structure 102 and the second semiconductor structure 104 in the 3D memory device 101, and the first semiconductor structure 102 and the second semiconductor structure 104 are vertically joined by bonding (e.g., hybrid bonding). Hybrid bonding, also known as "metal / dielectric hybrid bonding", is a direct bonding technology (e.g., forming a bond between surfaces without using an intermediate layer (e.g., solder or adhesive)), and can simultaneously obtain metal-metal (e.g., copper-copper) bonding and dielectric-dielectric (e.g., silicon oxide-silicon oxide) bonding. Data transmission between the memory cell array in the second semiconductor structure 104 and the peripheral circuit in the first semiconductor structure 102 can be performed through an interconnect (e.g., bonding contact) across the bonding interface 106.

[0025] It should be noted that the x, y and z axes are included in Figure 1A and Figure 1B , to further illustrate the spatial relationship of components in 3D memory devices 100 and 101. The substrate of the 3D memory device includes two lateral surfaces extending laterally in the xy plane: a top surface located on the front side of the wafer on which a semiconductor device can be formed, and a bottom surface located on the back side of the wafer opposite to the front side. The z-axis is perpendicular to both the x-axis and the y-axis. As used herein, when the substrate is located in the lowest plane of the 3D memory device in the z direction, it is determined relative to the substrate of the 3D memory device in the z direction (a vertical direction perpendicular to the xy plane, for example, the thickness direction of the substrate) whether a component (e.g., a layer or device) is located "on", "above", or "below" another component (e.g., a layer or device) of the 3D memory device. The same concepts used to describe spatial relationships apply throughout the present disclosure.

[0026] Figure 2A schematic diagram of a memory device 200 including an array of peripheral circuits and memory cells, each memory cell having a vertical transistor, according to some aspects of the present disclosure is shown. The memory device 200 may include a memory cell array 201 and a peripheral circuit 202 coupled to the memory cell array 201. The 3D memory devices 100 and 101 may be examples of a memory device 200 in which the memory cell array 201 and the peripheral circuit 202 may be included in the second semiconductor structure 104 and the first semiconductor structure 102, respectively. The memory cell array 201 may be any suitable memory cell array in which each memory cell 208 includes a vertical transistor 210 and a storage element 212 coupled to the vertical transistor 210. In some embodiments, the memory cell array 201 is a DRAM cell array, and the storage element 212 is a capacitor for storing charge as binary information stored by the corresponding DRAM cell. In some embodiments, the memory cell array 201 is a PCM cell array, and the storage element 212 is a PCM element (e.g., including a chalcogenide alloy) for storing binary information of a corresponding PCM cell based on different resistivities of the PCM element in an amorphous phase and a crystalline phase. In some embodiments, the memory cell array 201 is a FRAM cell array, and the storage element 212 is a ferroelectric capacitor for storing binary information of a corresponding FRAM cell based on switching between two polarization states of a ferroelectric material under an external electric field.

[0027] like Figure 2 As shown, the memory cells 208 may be arranged in a two-dimensional (2D) array having rows and columns. The memory device 200 may include: word lines 204, which couple the peripheral circuit 202 with the memory cell array 201, so as to control the switching of the vertical transistors 210 in the memory cells 208 located in a row; and bit lines 206, which couple the peripheral circuit 202 with the memory cell array 201, so as to send data to the memory cells 208 located in a column and / or receive data from the memory cells 208 located in a column. That is, each word line 204 is coupled to the memory cells 208 of the corresponding row, and each bit line is coupled to the memory cells 208 of the corresponding column.

[0028] Consistent with the scope of the present disclosure, as described in detail below, vertical transistors 210 (e.g., vertical metal oxide semiconductor field effect transistors (MOSFETs)) may replace planar transistors as pass transistors of memory cell 208 to reduce the area occupied by the pass transistors, coupling capacitance, and complexity of interconnect wiring. Figure 2As shown, in some embodiments, unlike a planar transistor in which an active region is formed in a substrate, a vertical transistor 210 includes a semiconductor body 214 extending vertically (in the z-direction) above a substrate (not shown). That is, the semiconductor body 214 can extend above the top surface of the substrate, thereby exposing not only the top surface of the semiconductor body 214 but also one or more side surfaces thereof. Figure 2 As shown, for example, the semiconductor body 214 can have a rectangular parallelepiped shape to expose its four sides. It should be understood that the semiconductor body 214 can have any appropriate 3D shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor body 214 in a plan view (e.g., in an xy plane) can have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape), or any other appropriate shape. It should be understood that, consistent with the scope of the present disclosure, for a semiconductor body having a circular or elliptical cross-section in a plan view, the semiconductor body can still be considered to have multiple sides, so that the gate structure contacts more than one side of the semiconductor body. As described below with respect to the manufacturing process, the semiconductor body 214 can be formed from a substrate (e.g., by etching or epitaxy), and therefore, has the same semiconductor material (e.g., crystalline silicon) as the substrate (e.g., a silicon substrate).

[0029] like Figure 2 As shown, the vertical transistor 210 may further include a gate structure 216 in contact with one or more sides of the semiconductor body 214, i.e., the gate structure 216 is located in one or more planes of the side surface (s) of the active region. In other words, the active region (i.e., the semiconductor body 214) of the vertical transistor 210 may be at least partially surrounded by the gate structure 216. The gate structure 216 may include a gate structure 216 located on one or more sides of the semiconductor body 214 (e.g., Figure 2, in contact with four side surfaces of the semiconductor body 214. The gate structure 216 may also include a gate electrode 220 located above the gate dielectric 218 and in contact with the gate dielectric 218. The gate dielectric 218 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric 218 may include silicon oxide, i.e., gate oxide. The gate electrode 220 may include any suitable conductive material, such as polysilicon, a metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), a metal compound (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or a silicide. For example, the gate electrode 220 may include doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 220 includes a plurality of conductive layers, such as a W layer located above the TiN layer. It should be understood that in some examples, the gate electrode 220 and the word line 204 may be a continuous conductive structure. In other words, the gate electrode 220 may be considered as a portion of the word line 204 forming the gate structure 216 , or the word line 204 may be considered as an extension of the gate electrode 220 to be coupled to the peripheral circuit 202 .

[0030] like Figure 2 As shown, the vertical transistor 210 may further include a pair of source and drain (S / D doped regions, also referred to as source electrode and drain electrode) formed at both ends of the semiconductor body 214 in the vertical direction (z direction), respectively. The source and drain may be doped with any suitable P-type dopant (e.g., boron (B) or gallium (Ga)), or any suitable N-type dopant (e.g., phosphorus (P) or arsenic (As)). The source and drain may be separated by a gate structure 216 in the vertical direction (z direction). In other words, the gate structure 216 is vertically formed between the source and the drain. Therefore, when the gate voltage applied to the gate electrode 220 of the gate structure 216 is higher than the threshold voltage of the vertical transistor 210, one or more channels (not shown) of the vertical transistor 210 may be vertically formed in the semiconductor body 214 between the source and the drain. That is, according to some embodiments, each channel of the vertical transistor 210 is also formed in the vertical direction along which the semiconductor body 214 extends.

[0031] In some embodiments, Figure 2 As shown, vertical transistor 210 is a multi-gate transistor. That is, gate structure 216 can be connected to more than one side of semiconductor body 214 (e.g., Figure 2In other words, unlike a planar transistor that includes only a single planar gate (and causes a single planar channel), due to the 3D structure of the semiconductor body 214 and the gate structure 216 surrounding multiple sides of the semiconductor body 214, Figure 2 The vertical transistor 210 shown may include multiple vertical gates located on multiple sides of the semiconductor body 214. Therefore, compared to a planar transistor, Figure 2 The vertical transistor 210 shown can have a larger gate control area, thereby achieving better channel control with a smaller subthreshold swing. During the off state, since the channel is fully depleted, the leakage current of the vertical transistor 210 can also be significantly reduced. Multi-gate vertical transistors can include dual-gate vertical transistors (e.g., dual-side gate vertical transistors), tri-gate vertical transistors (e.g., tri-side gate vertical transistors), and GAA vertical transistors.

[0032] It should be understood that although the vertical transistor 210 is Figure 2 214, but the vertical transistors disclosed herein may also include single-gate transistors as described in detail below. That is, for example, for the purpose of increasing the density of transistors and memory cells, the gate structure 216 may contact a single side of the semiconductor body 214. It should also be understood that although the gate dielectric 218 is shown as being separated (i.e., a separation structure) from other gate dielectrics of adjacent vertical transistors (not shown), the gate dielectric 218 may be part of a continuous dielectric layer having multiple gate dielectrics of the vertical transistors.

[0033] In planar transistors and some lateral multi-gate transistors (e.g., FinFETs), an active region (e.g., a semiconductor body (e.g., a fin)) extends laterally (in an xy plane), and the source and drain are disposed at different locations in the same lateral plane (xy plane). In contrast, in accordance with some embodiments, in a vertical transistor 210, a semiconductor body 214 extends vertically (in the z direction), and the source and drain are disposed in different lateral planes. In some embodiments, the source and drain are formed at both ends of the semiconductor body 214 in a vertical direction (z direction), respectively, so as to overlap in a plan view. Therefore, the area occupied by the vertical transistor 210 (in the xy plane) can be reduced compared to planar transistors and lateral multi-gate transistors. Moreover, because the interconnects can be routed in different planes, the metal wiring coupled to the vertical transistor 210 can also be simplified. For example, the bit line 206 and the storage element 212 can be formed on opposite sides of the vertical transistor 210. In one example, the bit line 206 may be coupled to a source or a drain at an upper end of the semiconductor body 214 , and the memory element 212 may be coupled to another source or a drain at a lower end of the semiconductor body 214 .

[0034] Figure 3A and Figure 3B A plan view and a side view, respectively, of an array of memory cells in a memory device according to some aspects of the present disclosure, each memory cell comprising a vertical transistor. Each vertical transistor comprises a gate electrode that may be part of a word line 302, a gate dielectric 304, and a semiconductor body 306. Figure 2 Details of the components of the vertical transistor are described in .

[0035] like Figure 3A and Figure 3B As shown, according to some embodiments, two adjacent vertical transistors of a memory cell in the bit line direction can be mirror-symmetrical to each other. By using a trench isolation 308 extending in the word line direction and parallel to the word line 302 to separate the semiconductor column into two parts, a semiconductor body 306 of each pair of two adjacent vertical transistors in the bit line direction of the memory cell can be formed. The trench isolation 308 and the word line 302 can be arranged in a staggered manner in the bit line direction. In some embodiments, the trench isolation 308 can be formed in the middle of the semiconductor column (not shown) so that the resulting pair of semiconductor bodies 306 are mirror-symmetrical to each other with respect to the trench isolation 308, and when the corresponding gate structures are also mirror-symmetrical to each other with respect to the trench isolation 308, the same is true for a pair of vertical transistors having a semiconductor body 306.

[0036] 4A to 4H An exemplary process for forming a connection structure between a vertical transistor and a capacitor according to some aspects of the present disclosure is shown. FIG. 4A to FIG. 4D shows how to form a connection layer above multiple vertical transistors, and Figure 4E-1 to Figure 4H shows how to use the connection layer to Figure 4H A corresponding connection structure is formed between each vertical transistor in the one transistor one capacitor (1T1C) array 416 shown in FIG.

[0037] like Figure 4A As shown, the exemplary process includes depositing a polysilicon layer 402 on the plurality of vertical transistors (on the source terminals or drain terminals of the plurality of vertical transistors). Figure 4A An example of a vertical transistor in Figure 3B , and includes a word line 302 , a gate dielectric 304 , and a semiconductor body 306 .

[0038] like Figure 4B As shown, the exemplary process includes ion implanting a deposited polysilicon layer and subsequently activating the implanted dopants in the deposited polysilicon layer 402 to form an activated polysilicon layer 404 .

[0039] like Figure 4C As shown, the exemplary process includes forming a silicide layer 406 over the activated polysilicon layer 404 .

[0040] like Figure 4D As shown, the exemplary process includes depositing a metal layer 408 (e.g., a tungsten layer) on top of the silicide layer 406. An exemplary material in the metal layer 408 may be tungsten (W). Figure 4E-1 to Figure 4H As shown, the connection layer between the plurality of vertical transistors and their corresponding capacitors may include the three layers described above (ie, the activated polysilicon layer 404, the silicide layer 406, and the metal layer 408), and may be used to connect the plurality of vertical transistors and their corresponding capacitors. Figure 4H A corresponding connection structure is formed between each vertical transistor and a corresponding capacitor in the 1T1C array 416 shown in FIG. In some embodiments, the connection layer between the plurality of vertical transistors and their corresponding capacitors may include an activated polysilicon layer 404 and a silicide layer 406 without a metal layer 408.

[0041] Figure 4E-1 and Figure 4E-2 4 and 5 show a plan view and a side view of a plurality of vertical transistors and a connection structure 410, respectively. Figure 4E-1 and Figure 4E-2 As shown, the exemplary process includes etching through the connection layer to form a connection structure 410 that can be used to connect each vertical transistor to a corresponding capacitor. Figure 4E-2 As shown, after etching through the connection layer, a plurality of connection structures 410 are formed. The connection structures 410 may include a plurality of layers in the connection layer, for example, Figure 4E-2 4. The active polysilicon layer 404 coupled to the plurality of vertical transistors, the silicide layer 406 formed on the activated polysilicon layer 404, and the metal layer 408 formed on the silicide layer 406. An exemplary material in the metal layer 408 may be tungsten (W). In some embodiments, the shape of the cross section of the connection structure 410 may be a trapezoid. Therefore, the size of one end (e.g., the second interface) of the connection structure 410 coupled to the vertical transistor may be greater than the size of the opposite end (e.g., the first interface) of the connection structure 410. The opposite end of the connection structure 410 may be connected to a capacitor.

[0042] In some embodiments, the etching process can be a two-step process, where the connection layer is first etched through in a first direction (eg, a word line direction) and then etched through in a second direction (eg, a bit line direction). Figure 4E-1 The resulting pattern of the conductive surface at the top of the connection structures 410 is shown in a plan view of the multiple vertical transistors and connection structures 410 in FIG. 4 , which shows that the shape of the top conductive surface of each connection structure 410 is a triangle.

[0043] In some embodiments, the etching process can be a one-step process in which a mask is used to etch through the connection layer in a single step to form a Figure 4E-1 The pattern of the conductive surface at the top of the connection structure 410 is shown in the plan view of the multiple vertical transistors and the connection structure 410.

[0044] like Figure 4F As shown, an exemplary process includes: forming a connection structure between a vertical transistor and a capacitor, which includes: filling a dielectric material 412 into an air gap formed after the etching process described above in the connection layer. An example of dielectric material 412 is silicon nitride. Other exemplary dielectric materials 412 may include silicon oxide, silicon oxynitride, or a high-k dielectric.

[0045] Figure 4G-1 and Figure 4G-2 A plan view and a side view of a plurality of vertical transistors, a connection structure 410, and a dielectric material 412 are shown, respectively. Figure 4G-1 and Figure 4G-2 As shown, an exemplary process includes exposing the top conductive surface of the plurality of connection structures 410 by removing excess portions of the filled dielectric material 412 using a planarization process. An example of a planarization process is a chemical mechanical polishing (CMP) process. Figure 4G-1 and 4G-2 The resulting structure after the planarization process is shown in FIG. Figure 4G-1 As shown, the top exposed conductive surface of each connection structure 410 is rectangular in shape.

[0046] like Figure 4H As shown, the exemplary process includes forming a corresponding capacitor 414 on each connection structure 410 connecting each capacitor 414 and a corresponding vertical transistor. Thus, a 1T1C array 416 including a plurality of connection structures 410 connecting capacitors 414 and corresponding vertical transistors can be formed. Fig. 6A , Figure 6B and Figure 6C An exemplary type of capacitor is shown in FIG. According to some aspects of the present disclosure, Fig. 6A shows a cup type capacitor, Figure 6B shows a cylindrical capacitor, and Figure 6C A pillar type capacitor is shown.

[0047] Figure 5 An exemplary structure including a 1T1C array 502 and a unit capacitor region 504 according to some aspects of the present disclosure is shown. The unit capacitor region 504 includes a plurality of capacitors connected to a common connection layer deposited on a substrate 506. In some embodiments, the common connection layer may include an activated polysilicon layer 404, a silicide layer 406, and a metal layer 408. Thus, the layered structure of the common connection layer enables all capacitors in the unit capacitor region 504 to be connected to the metal layer 408 at their bottom plates.

[0048] 7A to 7E Another exemplary process for forming a connection structure 712 between a vertical transistor and a capacitor according to some aspects of the present disclosure is shown. Fig. 7A As shown, the exemplary process includes etching through a dielectric layer 702 deposited over a plurality of vertical transistors to form a corresponding hole over a source terminal or a drain terminal of each vertical transistor. In some embodiments, a top surface of each hole has a circular shape.

[0049] like Figure 7B As shown, an exemplary process includes filling the previously formed holes with polysilicon 704. Excess portions of the filled polysilicon 704 may then be removed using a planarization process such as a CMP process.

[0050] like Figure 7C As shown, the exemplary process includes etching the portion of the filled polysilicon 704 located in each hole to make room for additional layers of the connection structure to be subsequently deposited.

[0051] like Fig.7D As shown, the exemplary process includes performing an ion implantation process on the remaining polysilicon in each hole and activating the implanted dopants in the remaining polysilicon to form activated polysilicon 706 in each hole.

[0052] like Fig. 7E As shown, the exemplary process includes: depositing a silicide material 708 and a metal material 710 on the activated polysilicon 706 in each hole to form a corresponding connection structure 712 in each hole. An example of the metal material 710 may be tungsten (W). Because the cross-section of each hole may have an inverted trapezoidal shape, the connection structure in each hole may also have an inverted trapezoidal shape. Therefore, the size of one end of the connection structure 712 coupled to the vertical transistor may be smaller than the size of the opposite end of the connection structure 712. The opposite end of the connection structure 712 may be connected to a capacitor.

[0053] Figure 8 An example 800 of a flow chart of a method for forming a connection structure connecting vertical transistors and capacitors according to some aspects of the present disclosure is shown. At 802, a first structure including a plurality of vertical transistors is formed. At 804, a connection layer is formed over the first structure. At 806, the connection layer is etched to form connection structures, wherein each of the connection structures is coupled to a corresponding vertical transistor in the vertical transistors. At 808, a plurality of capacitors are formed over the connection layer, wherein each of the plurality of capacitors is coupled to a corresponding connection structure.

[0054] Certain aspects of the subject matter described herein can be implemented as a three-dimensional (3D) memory device. The 3D memory device includes a vertical transistor, a capacitor, and a connection structure, wherein the capacitor is coupled to the vertical transistor through the connection structure, the connection structure includes a first interface and a second interface, the first interface is coupled to the capacitor, the second interface is coupled to the vertical transistor, and the size of the first interface is smaller than the size of the second interface.

[0055] The 3D memory device may include one or more of the following features.

[0056] In some embodiments, a cross-section of the connection structure along the first direction is rectangular.

[0057] In some embodiments, a vertical transistor includes a semiconductor body and a gate structure, the semiconductor body extending in the same direction as the vertical transistor, and the gate structure contacting one or more side surfaces of the semiconductor body.

[0058] In some embodiments, two ends of the semiconductor body extend beyond the gate structure, respectively.

[0059] In some embodiments, the vertical transistor is a gate-all-around (GAA) transistor in which the gate structure completely surrounds the semiconductor body in plan view.

[0060] In some implementations, a bit line and a capacitor are coupled to opposite ends of the vertical transistor.

[0061] In some embodiments, a cross-section of the connection structure along the second direction is trapezoidal in shape.

[0062] In some implementations, a dielectric medium is filled between adjacent connection structures in a 3D memory device.

[0063] In some embodiments, the connecting structure includes a tungsten layer.

[0064] Certain aspects of the subject matter described herein can be implemented as a method. The method includes: forming a first structure including a plurality of vertical transistors. Forming a connection layer over the first structure. Etching the connection layer to form a connection structure, wherein each of the connection structures is coupled to a corresponding vertical transistor in the vertical transistors. Forming a plurality of capacitors over the connection layer, wherein each of the plurality of capacitors is coupled to a corresponding connection structure.

[0065] The method may include one or more of the following features.

[0066] In some embodiments, etching the connection layer includes etching a plurality of holes through the connection layer and filling the plurality of holes with a dielectric medium.

[0067] In some embodiments, etching the connection layer to form the connection structure includes etching through the connection layer along a first direction, and etching through the connection layer along a second direction to form the connection structure, wherein the first direction is perpendicular to the second direction.

[0068] In some embodiments, the connection layer includes a polysilicon layer, a silicide layer, and a tungsten layer.

[0069] In some implementations, the method further includes forming a bit line coupled to one or more vertical transistors of the plurality of vertical transistors.

[0070] In some embodiments, forming a connection layer on the first structure includes: forming a polysilicon layer on the first structure, and forming a silicide layer on the polysilicon layer, wherein the connection layer includes the polysilicon layer and the silicide layer.

[0071] Certain aspects of the subject matter described herein can be implemented as a memory system. The memory system includes a 3D memory device and a controller, the controller being coupled to the 3D memory device and configured to initiate operation of the 3D memory device. The 3D memory device includes a vertical transistor, a capacitor, and a connection structure, wherein the capacitor is coupled to the vertical transistor through the connection structure, the connection structure includes a first interface and a second interface, the first interface is coupled to the capacitor, the second interface is coupled to the vertical transistor, and the size of the first interface is smaller than the size of the second interface.

[0072] The memory system may include one or more of the following features.

[0073] In some embodiments, a cross-section of the connection structure along the first direction is rectangular.

[0074] In some embodiments, a vertical transistor includes a semiconductor body and a gate structure, the semiconductor body extending in the same direction as the vertical transistor, and the gate structure contacting one or more side surfaces of the semiconductor body.

[0075] In some embodiments, a cross-section of the connection structure along the second direction is trapezoidal in shape.

[0076] In some implementations, a bit line and a capacitor are coupled to opposite ends of the vertical transistor.

[0077] Although this specification contains many specific implementation details, these details should not be interpreted as limitations on the scope of the claims, but should be used as descriptions of features that may be specific to a particular embodiment. In the context of separate embodiments, certain features described in this specification may also be implemented in combination in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented individually or in any sub-combination in multiple embodiments. In addition, although the aforementioned features may be described as acting in certain combinations and even initially claimed as such, one or more features from the claimed combination may be deleted from the combination in some cases, and the claimed combination may be directed to a sub-combination or a variation of the sub-combination.

[0078] As used in this disclosure, the terms "a", "an" or "the" are used to include one or more than one, unless the context clearly indicates otherwise. Unless otherwise indicated, the term "or" is used to refer to a non-exclusive "or". The statement "at least one of A and B" has the same meaning as "A, B, or A and B". In addition, the words or terms used in this disclosure without additional definition are used for descriptive purposes only and not for limiting purposes. Any use of section headings is intended to aid in reading this document and should not be construed as limiting; information related to the section heading may appear inside or outside that particular section.

[0079] As used in this disclosure, the terms "about" or "approximately" can allow for a degree of variability in values ​​or ranges, for example, within 10%, within 5%, or within 1% of the stated value or stated range limit.

[0080] As used in this disclosure, the term "substantially" refers to a majority or majority, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999% or more.

[0081] Values ​​expressed in range format should be interpreted in a flexible manner to include not only the values ​​explicitly stated as the limits of the range, but also all individual values ​​or sub-ranges encompassed within the range, as if each value and sub-range were explicitly stated. For example, a range of "0.1% to about 5%" or "0.1% to 5%" should be interpreted to include about 0.1% to about 5%, as well as individual values ​​(e.g., 1%, 2%, 3% and 4%) and sub-ranges (e.g., 0.1% to 0.5%, 1.1% to 2.2%, 3.3% to 4.4%) included within the range shown. Unless otherwise specified, the statement "X to Y" has the same meaning as "about X to about Y". Similarly, unless otherwise specified, the statement "X, Y or Z" has the same meaning as "about X, about Y or about Z".

[0082] Specific embodiments of the subject matter have been described. As will be apparent to those skilled in the art, other embodiments, alternatives and permutations of the described embodiments are within the scope of the following claims. Although operations are described in a particular order in the drawings and claims, it is not required to perform these operations in the particular order shown or in a sequential order in order to achieve the desired results, or it is not required to perform all of the operations shown (some operations may be considered optional). In some cases, multitasking or parallel processing (or a combination of multitasking and parallel processing) may be advantageous and is performed when deemed appropriate.

[0083] Furthermore, the separation or integration of the various system modules and components in the previously described embodiments is not required in all embodiments, and the described components and systems may generally be integrated together or packaged into multiple products.

[0084] Therefore, the exemplary embodiments described above do not limit or restrict the present disclosure. Other changes, substitutions and alterations are also possible without departing from the spirit and scope of the present disclosure.

Claims

1. A three-dimensional (3D) memory device, include: A vertical transistor, a capacitor, and a connection structure, wherein the capacitor is coupled to the vertical transistor through the connection structure, the connection structure includes a first interface and a second interface, the first interface is coupled to the capacitor, the second interface is coupled to the vertical transistor, and the size of the first interface is smaller than the size of the second interface.

2. The 3D memory device according to claim 1, in, The cross-section of the connection structure along the first direction is in a rectangular shape.

3. The 3D memory device according to claim 1 or 2, in, The vertical transistor includes a semiconductor body and a gate structure, the semiconductor body extending in the same direction as the vertical transistor, and the gate structure contacting one or more side surfaces of the semiconductor body.

4. The 3D memory device according to claim 3, in, Two ends of the semiconductor body extend beyond the gate structure respectively.

5. The 3D memory device according to claim 3 or 4, in, The vertical transistor is a gate-all-around (GAA) transistor in which the gate structure completely surrounds the semiconductor body in a plan view.

6. The 3D memory device according to any one of claims 1 to 5, in, A bit line and the capacitor are coupled to opposite ends of the vertical transistor.

7. The 3D memory device according to any one of claims 1 to 6, in, A cross-section of the connection structure along the second direction is a trapezoid.

8. The 3D memory device according to any one of claims 1 to 7, in, A dielectric medium is filled between adjacent connection structures in the 3D memory device.

9. The 3D memory device according to any one of claims 1 to 8, in, The connecting structure includes a tungsten layer.

10. A method, include: forming a first structure including a plurality of vertical transistors; forming a connection layer on the first structure; etching the connection layer to form connection structures, wherein each of the connection structures is coupled to a corresponding one of the vertical transistors; and A plurality of capacitors are formed over the connection layer, wherein each capacitor of the plurality of capacitors is coupled to a corresponding connection structure.

11. The method according to claim 10, in, Etching the connection layer comprises: etching a plurality of holes through the connecting layer; and The plurality of holes are filled with a dielectric medium.

12. The method according to claim 10, in, Etching the connection layer to form the connection structure comprises: etching through the connection layer along a first direction; and The connection layer is etched through along a second direction to form the connection structure, wherein the first direction is perpendicular to the second direction.

13. The method according to any one of claims 10 to 12, in, The connection layer includes a polysilicon layer, a silicide layer and a tungsten layer.

14. The method according to any one of claims 10 to 13, in, The method also includes forming a bit line coupled to one or more vertical transistors of the plurality of vertical transistors.

15. The method according to any one of claims 10 to 14, in, Forming the connection layer on the first structure includes: forming a polysilicon layer over the first structure; and A silicide layer is formed on the polysilicon layer, wherein the connection layer includes the polysilicon layer and the silicide layer.

16. A memory system, include: A three-dimensional (3D) memory device, the three-dimensional (3D) memory device comprising: A vertical transistor, a capacitor, and a connection structure, wherein the capacitor is coupled to the vertical transistor through the connection structure, the connection structure comprises a first interface and a second interface, the first interface is coupled to the capacitor, the second interface is coupled to the vertical transistor, and a size of the first interface is smaller than a size of the second interface; and A memory controller is coupled to the 3D memory device and is configured to initiate operation of the 3D memory device.

17. The memory system according to claim 16, in, The cross-section of the connection structure along the first direction is in a rectangular shape.

18. The memory system according to claim 16 or 17, in, The vertical transistor includes a semiconductor body and a gate structure, the semiconductor body extending in the same direction as the vertical transistor, and the gate structure contacting one or more side surfaces of the semiconductor body.

19. The memory system according to any one of claims 16 to 18, in, A cross-section of the connection structure along the second direction is a trapezoid.

20. The memory system according to any one of claims 16 to 19, in, A bit line and the capacitor are coupled to opposite ends of the vertical transistor.

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