Method for manufacturing electronic chip

Abstract

The invention relates to a manufacturing method of an electronic chip. The present specification relates to a method of manufacturing electronic chips having passivated flanks from a semiconductor substrate, a first face of which is covered by a connection region and in which chips are formed, the method comprising the steps of: forming a trench or cavity between the chips; depositing an insulating material in the groove or the cavity; and separating the chip by cutting at least the insulating material.

Description

[0001] Cross-reference to related application(s)

[0002] This application claims the benefit of priority of French Patent Application No. 2313734, filed on December 7, 2023, entitled "Procédé de fabrication de puces électroniques", which is hereby incorporated by reference in its entirety to the maximum extent permitted by law. Field of the Invention

[0003] This specification relates to the field of CSP ('chip-scale package') chips. More particularly, this specification relates to a method for manufacturing dies (also referred to as 'bare chips'). Background of the Invention

[0004] A bare chip includes a substrate made of semiconductor-conductor material in which an electronic circuit has been fabricated. The substrate is covered with connection areas so that the chip can be assembled with, for example, a printed circuit board. During chip assembly, the connection areas are soldered or brazed to metal tracks or components on the printed circuit board. However, during assembly, the solder may travel upwards along the flanks of the chip. Since the flanks of the chip are made of semiconductor material, this may lead to a degradation of electrical performance (short circuits, leakage currents, etc.). Therefore, it is necessary to avoid this phenomenon.

[0005] Such chips are of particular interest in many industrial fields, such as in the automotive field. Summary of the Invention

[0006] It is necessary to improve at least some aspects of known chip manufacturing methods. This is achieved by a method for manufacturing an electronic chip with passivated flanks from a semiconductor substrate, the first face of which is covered with connection areas and in which a chip is formed, the method comprising the steps of:

[0007] - forming trenches or cavities between the chips,

[0008] - depositing an insulating material in the trenches or cavities,

[0009] - separating the chips by cutting at least the insulating material.

[0010] According to an embodiment, trenches are formed that extend from the first face of the substrate to the second face of the substrate.

[0011] According to an embodiment, cavities are formed by partially cutting the substrate from the first face, the depth of the cavities preferably being between 10% and 75% of the thickness of the substrate.

[0012] According to an embodiment, the width of the trench or cavity is between 20 and 80 μm.

[0013] According to an embodiment, before the step of separating the chip, the method includes a step of thinning the substrate from the second side until reaching the cavity during which.

[0014] According to an embodiment, the insulating material includes a polymer or resin and an electrically insulating filler, the polymer or resin being preferably an epoxy resin or a phenolic resin, the electrically insulating filler such as alumina or silica particles.

[0015] According to an embodiment, the insulating material is deposited by inkjet printing.

[0016] This is achieved by an electronic chip with passivated flanks, the electronic chip including a semiconductor substrate having a first side, a second side and flanks covered by connection regions, at least a part of the flanks being formed by an insulating material layer extending from the first side of the substrate.

[0017] According to an embodiment, the insulating material layer extends from the first side to the second side.

[0018] According to an embodiment, a notch starting from the first side of the substrate is formed in the flank, and the notch is filled with the insulating material layer. Description of the Drawings

[0019] The foregoing features and advantages, as well as other features and advantages, will be described in detail with reference to the accompanying drawings in the description of specific embodiments given in an illustrative but non-limiting manner, wherein:

[0020] Figure 1A , Figure 1B , Figure 1C and Figure 1D are cross-sectional views illustrating steps in a method of manufacturing a chip with passivated flanks according to a specific embodiment;

[0021] Figure 2A , Figure 2B , Figure 2C and Figure 2D are cross-sectional views illustrating steps in a method of manufacturing an electronic chip with passivated flanks according to another specific embodiment; and

[0022] Figure 3A , Figure 3B , Figure 3C , Figure 3D and Figure 3E are cross-sectional views illustrating steps in a method of manufacturing a chip with passivated flanks in another specific embodiment. Detailed Description

[0023] Like features in the respective figures have been denoted by like reference numerals. In particular, structural and / or functional features common to the respective embodiments may have the same reference numerals and may be deployed with the same structural, dimensional, and material characteristics.

[0024] For clarity, only the operations and elements useful for understanding the embodiments described herein are illustrated and described in detail.

[0025] Unless otherwise specified, when referring to two elements connected together, this means a direct connection without any intermediate elements other than conductors, and when referring to two elements coupled together, this means that the two elements may be connected or they may be coupled via one or more other elements.

[0026] In the following disclosure, unless otherwise specified, when referring to absolute position determiners such as the terms "front", "back", "top", "bottom", "left", "right", etc., or relative position determiners such as the terms "above", "below", "higher", "lower", etc., or orientation determiners such as "horizontal", "vertical", etc., they refer to the orientation shown in the respective figures or the orientation during normal use.

[0027] Unless otherwise specified, the expressions "about", "approximate", "substantially", and "about" mean within 10%, preferably within 5%.

[0028] Now we will refer to Figures 1A to 1D 、 Figures 2A to 2D and Figures 3A to 3E to describe in more detail a method for manufacturing a bare chip (also referred to as a "die") with passivated flanks.

[0029] The method includes the following steps:

[0030] a) Providing a semiconductor substrate 110, whose first surface 111 is covered by a connection region 107, and forming a chip 100 ( Figure 1A 、 2A 、3A) in the semiconductor substrate 110,

[0031] b) Forming trenches or cavities 120 ( Figure 1B 、 2B 、3B) between the chips 100 in the substrate 110 (wafer),

[0032] c) Depositing an insulating material 121 ( Figure 1C 、 2C 、3C) in the trenches or cavities 120,

[0033] - Optionally, performing the step of thinning the substrate 110 on the back side ( Figure 3D ),

[0034] d) Separating the chip 100 by cutting through the insulating material layer 121 ( Figure 1D , 2D , 3E).

[0035] Using this method, the flanks 113 of the resulting chip 100 are passivated by means of the insulating layer 121. Thus, potential contamination (due to a defective assembly with the board) is avoided and the electrical performance is not degraded.

[0036] In step a), the fabrication of one or more discrete components and / or one or more integrated circuits has been completed. The chip 100 is formed from a single substrate 110 and has not yet been individualized.

[0037] The substrate 110 includes a first face 111 (top or front face) and a second face 112 (bottom or back or active face). The two faces 111 and 112 are parallel to each other. They are connected to each other by side walls.

[0038] The substrate 110 is, for example, a semiconductor substrate such as silicon. It can also be made of SiC.

[0039] The thickness of the substrate 110 is between 100 and 900 μm, preferably between 300 and 900 μm. For example, the thickness is about 725 μm.

[0040] One or more connection regions 107 (also referred to as electrical contacts) are formed on the upper face 111 of the substrate 110 of the electronic chip 100, enabling it to be connected to other components (e.g., chips or printed circuits). Preferably, there are at least two connection regions.

[0041] The electrical connection regions 107 are, for example, 10 to 30 μm away from the chip side walls. The electrical connection regions 107 can be located on the top surface 111 of the chip 100 or flush with the top surface 111 (i.e., flush with the top surface 111 of the chip 100).

[0042] The electrical connection regions 107 are also referred to as "UBM" (under bump metallization). The electrical connection regions 107 are made of a conductive material. Advantageously, the electrical connection regions 107 include at least one of the following elements: gold, titanium, nickel, copper, or tungsten. Preferably, they include gold.

[0043] Connection pads can be formed on the connection regions 107.

[0044] The chip 100 can include one or more discrete components. The one or more discrete components are, for example, selected from transistors, diodes, thyristors, triacs, etc. The chip 100 can include one or more electronic circuits. The chip 100 can be used to implement a variety of electronic functions.

[0045] The substrate provided in step a) is positioned on the support 200. The support 200 is adhesively bonded.

[0046] In step b), the substrate 110 between the chips 100 is at least partially cut to form cavities or trenches. The cavities or trenches 120 define the lateral profile of the chips 100. More particularly, the cavities or trenches 120 extend from the top surface 111 of the substrate 110.

[0047] According to a first alternative embodiment, for example Figure 1B and 3B as shown in, cavities 120 are formed. Their depth is less than the thickness of the substrate 110.

[0048] The depth of the cavities 120 is, for example, between 10 and 300 μm, preferably between 20 and 250 μm.

[0049] The depth of the cavities 120 is preferably between 10% and 75% of the thickness of the substrate 110. The trench depth can be adjusted to suit the application.

[0050] The width of the cavities 120 is, for example, between 20 and 80 μm.

[0051] The bottom of the cavity can be flat or concave.

[0052] According to a second alternative embodiment, for example as Figure 2B shown in, the trenches travel completely through the substrate 110, i.e., the substrate 110 is cut from the first side 111 to the second side 112.

[0053] The width of the trenches 120 is, for example, between 20 μm and 80 μm.

[0054] This step b) is carried out using a cutting device. The cutting device is, for example, a mechanical cutting / engraving tool such as a saw, or a laser engraving tool. According to a preferred embodiment, the cutting / engraving device is a laser.

[0055] To form trenches that cut completely through the 110 substrate, a stealth cutting step can first be carried out, followed by an expansion step. In the stealth cutting step, dislocations are generated within the silicon substrate along the cutting path using a special laser. These dislocations are defects in the substrate thickness which, under the action of mechanical stress, will enable the chips to be separated. It is only necessary to stretch the adhesive backing 200 to pull the chips apart and deposit an insulating material.

[0056] In step c), the trenches or cavities 120 are filled from the front side 111 with an insulating material 121.

[0057] Preferably, the material 121 is deposited by inkjet printing using a nozzle 300. Several passes of the nozzle may be required to fill the trenches or cavities 120.

[0058] In various embodiments, the insulating material 121 is deposited only in the cavity 120 or the trench. The front face 111 is not covered by the insulating material 121.

[0059] The material is an electrically insulating material. More particularly, the material 121 includes a base material (polymer or resin) and preferably electrically insulating particles. The resin is selected from the group consisting of: epoxy-type resins, phenolic-type resins, acrylic-type resins. The base material can be polyvinylpyrrolidone (PVP), silicone (also known as polysiloxane), polyamic acid, tripropylene glycol diacrylate (TPGDA). The particles are, for example, oxide particles, especially alumina or silica particles.

[0060] Preferably, the resin is a thermosetting resin or a photosensitive resin (UV). Such resins have high stability and are resistant to a variety of chemicals.

[0061] The polymerization of the resin is, for example, a UV polymerization step. It can also be carried out by heating or any other polymerization process selected according to the nature of the materials used.

[0062] An annealing step can be carried out after step c).

[0063] The method may also include a step of thinning from the back side ( Figure 3D ). This step is preferably carried out after step c). To this end, the structure is flipped and attached to the support 201 through its front face 111. The support 201 is, for example, an adhesive tape. The structure is then thinned from the back side 112 so that the substrate 110 has its final thickness. When the cavity has been formed in step b), the thinning step is preferably carried out in order to thin the substrate 110 to the cavity 120.

[0064] In step d), the chip 100 is singulated. This singulation step can be carried out by cutting through the insulating material 121 ( Figure 3E ), and if necessary, can also be carried out by cutting through the substrate 110 ( Figure 1D , 2D ). The cutting line is centered with respect to the cavity / trench.

[0065] The cutting device is, for example, a mechanical engraving tool such as a saw, or a laser engraving tool. According to a preferred embodiment, the cutting device is a laser.

[0066] The trench formed in step d) is narrower than the trench or cavity formed in step b). The trench is centered on the cavity formed in step b).

[0067] At the end of the method, the resulting chip 100 includes passivated side wings 113. The passivation is due to the presence of the insulating material 121. The welding material does not wet the insulating material 121.

[0068] According to the first variant embodiment, only a part of the flank 113 is passivated ( Figure 1D ). The flank includes a first part made of semiconductor material formed in the substrate 110, and a second part made of the insulating material 121. The insulating material 121 is received in a notch formed in the substrate 110. The notch is a corner notch located at the intersection of the first face 111 and the flank 113. The notch starts from the first face 111 and extends towards the second face 112 in a plane perpendicular to the first face 111 and the second face 112. A part of the flank 113 is formed from the insulating material 121, and a part of the first face 111 is formed from the insulating material 121.

[0069] According to the second variant embodiment, the entire flank 113 is passivated ( Figure 2D , 3E ).

[0070] By adopting this method, the height of the flank 113 covered by the insulating material 121 can be easily adjusted.

[0071] Then, the chip 100 can be attached to an external device, such as a printed circuit board or other components, through its top face 111.

[0072] For this purpose, a brazing material is positioned between the chip 100 and the external device. During soldering, even if the solder travels upward along the wettable flank 113 of the chip 100, the chip 100 will still work properly.

[0073] Such CSP-type electronic chips have applications in a wide range of industrial fields, especially in the fields of telephones, automobiles, and medical treatment.

[0074] Multiple embodiments and variant embodiments have been described. Those skilled in the art will understand that certain features of these embodiments can be combined, and those skilled in the art will readily think of other variant embodiments.

[0075] Finally, based on the functional descriptions provided above, the actual implementation of the embodiments and variant embodiments described herein is within the capabilities of those skilled in the art.

Claims

1. A method for producing an electronic chip with passivated flanks from a semiconductor substrate, the first face of which is covered by a connection region and in which the chip is formed, the method comprising: forming trenches or cavities between chips; depositing insulating material in the trench or cavity; as well as The chips are separated by cutting at least the insulating material. 2 . The method of claim 1 , wherein a groove is formed, the groove running from a first side of the substrate to a second side of the substrate.

3. The method of claim 1, wherein the cavity is formed by partially cutting the substrate from the first face, the depth of the cavity preferably being between 10% and 75% of the thickness of the substrate. The method of claim 1 , wherein the width of the groove or cavity is between 20 and 80 μm.

5. The method of claim 1, wherein a cavity is formed, the method further comprising: Before separating the chips, the substrate is thinned from the second side until the cavity is reached.

6. The method of claim 1, wherein the insulating material comprises a polymer or resin, preferably an epoxy resin or a phenolic resin, and an electrically insulating filler such as alumina or silica particles. The method of claim 1 , wherein the insulating material is deposited by inkjet printing.

8. The method of claim 1, wherein the insulating material is deposited only in the cavity or the trench and the first side is not covered by the insulating material.

9. The method of claim 1, wherein a groove or a cavity is formed between the chips; wherein separating the chips by cutting at least the insulating material comprises cutting through the insulating material and cutting through the substrate, such that after separating the chips, only a portion of the flanks of the chips are passivated; and The wing includes a first portion formed in the substrate and a second portion including an insulating material starting from a first side of the substrate.

10. An electronic chip with passivated flanks, comprising a semiconductor substrate having a first face covered by a connection region, a second face and flanks, wherein at least a portion of the flanks is formed by a layer of insulating material extending from the first face of the substrate. The electronic chip of claim 10 , wherein the layer of insulating material extends from the first side to the second side. 12 . The electronic chip of claim 10 , wherein a recess is formed in the wing starting from the first side of the substrate, the recess being filled with a layer of insulating material. The electronic chip of claim 10 , wherein the first side is not covered by insulating material.

14. The electronic chip of claim 1, wherein the wing comprises a first portion formed in the substrate and a second portion comprising an insulating material starting from the first side of the substrate.

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