A method for suppressing leakage current of three-phase four-leg grid-connected inverter based on DPWMAX

Abstract

The present invention discloses a method for suppressing leakage current of a three-phase four-bridge-leg grid-connected inverter based on DPWMAX, belonging to the technical field of inverters in the field of new energy. The method refers to a carrier modulation strategy for suppressing leakage current of a three-phase four-bridge-leg inverter, which is achieved by a switching signal modulation mode. The three-phase symmetrical sine wave is converted into a DPWMMAX waveform, which is compared with a triangular carrier VC through a comparator to obtain three-phase logic signals A, B, and C; the three-phase logic signal is combined with a mathematical logic operation, and the common-mode voltage can be stabilized at a certain value by changing the logic signal in the three phases. Regardless of the mode of the circuit, the common-mode voltage is maintained constant, so that the leakage current is controlled within an allowable range. The patent utilizes the waveform characteristics of DPWMAX to reduce the number of switches and simplify the control difficulty. The present invention adopts mathematical logic control to eliminate the leakage current of the three-phase four-bridge-leg inverter, without a complex calculation process, and the implementation process is simple.

Description

Technical Field

[0001] The present invention belongs to the technical field of inverters in the field of new energy, and particularly relates to a method for suppressing leakage current of a three-phase four-bridge-arm grid-connected inverter based on DPWMAX. Background Art

[0002] In grid-connected systems, transmission systems are generally categorized as isolated or non-isolated. If a transformer is included in the transmission system, it is called an isolated grid-connected system; otherwise, it is called a non-isolated grid-connected system. Non-isolated grid-connected systems, characterized by their compact size, high efficiency, and low cost, have attracted extensive research. Transformerless inverters, with their advantages of small size, low cost, and high efficiency, are gaining increasing attention. However, due to the lack of galvanic isolation, leakage current presents a problem. This leakage current can cause electromagnetic interference and potential safety issues. The German VDE-0126-1-1 standard stipulates that if the peak leakage current of a photovoltaic system exceeds 300mA, the photovoltaic grid-connected inverter must be disconnected from the grid within 0.3s.

[0003] There are three types of modulation waves that are commonly used, namely SPWM, SVPWM, and DPWM. The three modulation waves have their own advantages and disadvantages. The advantage of DPWM is that when the waveforms of SPWM and SVPWM intersect with the carrier of the same frequency, the Figure 2 As shown in the figure, DPWM has fewer switching times, and fewer switching times means less energy loss.

[0004] In the prior art, one solution to grid-connected system leakage current is to maintain a constant common-mode voltage through modulation strategies. Control strategies for maintaining a constant common-mode voltage can be categorized into three types: space vector modulation, carrier modulation, and model predictive control. Regarding the carrier modulation strategy, Chinese patent application number 201410131070.0, entitled "A Method for Suppressing Leakage Current in a Three-Phase Four-Leg Photovoltaic Grid-Connected Inverter," incorporates a time signal, determines the time signal interval, and implements specialized logic control to suppress the presence of common-mode voltage. However, the inclusion of the time signal necessitates its determination and division, making control more difficult. Regarding the carrier modulation strategy, Chinese patent application number 202010233077.9, entitled "A Method for Suppressing Leakage Current in a Three-Phase Four-Leg Z-Source Inverter," utilizes sector determination to replace the time signal. This application is similar to the invention patent application number 201410131070.0, except that the sector signal replaces the time signal. Furthermore, three carriers are added and the carrier phase shifted, without reducing the control difficulty. Regarding the carrier modulation strategy, Chinese patent application number 202311413436.9, entitled "A Method for Suppressing Leakage Current in a Three-Phase Four-Leg Grid-Connected Inverter Based on DPWMAX," does not require time or sector signals, significantly reducing the control difficulty. However, according to the article "Research on Leakage Current Suppression in a Three-Phase Four-Leg Transformerless Inverter Based on Mathematical Logic," the article is consistent with the patent. Furthermore, the article explicitly states in actual simulations that this method cannot be used with DPWM waveforms. The advantage of the DPWMAX waveform is that the number of switching times is reduced. This patent uses the principles and advantages of DPWMAX to construct a method of using the DPWMAX waveform to suppress leakage current, which is inconsistent with the above patent.

[0005] Therefore, this patent has developed a method based on DPWMAX to suppress the leakage current of the three-phase four-leg grid-connected inverter, which specifically uses the DPWMAX waveform to make the control simpler and the implementation process simpler. Summary of the Invention

[0006] The present invention provides a method for suppressing leakage current of a three-phase four-bridge-arm grid-connected inverter based on DPWMAX, which mainly suppresses the leakage current problem of a transformerless inverter and utilizes the characteristics of the DPWMAX waveform to make control simpler and reduce the number of switching times.

[0007] A method for suppressing leakage current of a three-phase four-leg grid-connected inverter based on DPWMAX, comprising:

[0008] The carrier modulation strategy for leakage current suppression of three-phase four-leg transformerless inverter is realized by switching signal modulation. The DPWMMAX waveform is converted into a triangular carrier VC and compared with the comparator to obtain the three-phase logic signals A, B, and C; by combining the three-phase logic signal with mathematical logic operations and changing the three-phase logic signal, the common-mode voltage can be stabilized at a certain value. No matter what mode the circuit is in, the common-mode voltage remains constant, so that the leakage current is controlled within the allowable range.

[0009] In one possible implementation, the comparator includes a comparator 1 (when the output is greater than 0, the output is 1; when the output is less than 0, the output is 0), a comparator 2 (when the output is greater than 0, the output is 1; when the output is less than 0, the output is 0), a comparator 3 (when the output is greater than 0, the output is 1; when the output is less than 0, the output is 0), a comparator 4 (when the input is 1, the output is 1; when the output is less than 1, the output is 0), a comparator 5 (when the input is 1, the output is 1; when the output is less than 1, the output is 0), and a comparator 6 (when the input is 1, the output is 1; when the output is less than 1, the output is 0), and the three-phase logic signal includes a first logic signal S a , the second logic signal S b and the third logic signal S c ; The mathematical logic operations are respectively performed by addition and subtraction operator 1, addition and subtraction operator 2, addition and subtraction operator 3, addition and subtraction operator 4, multiplication operator 1, multiplication operator 2 and multiplication operator 3.

[0010] In one possible implementation, a three-phase symmetrical sine wave The DPWMMAX waveform is compared with the triangular carrier VC through the comparator to obtain the three-phase logic signals A, B, and C, including:

[0011] Comparator 1, Comparator 2, and Comparator 3 process the three-phase symmetrical sine waves one by one. The corresponding DPWMMAX wave and the triangular carrier VC are used to obtain the three-phase logic signals A, B, and C; wherein the three-phase logic signals A, B, and C include the first logic signal S a , the second logic signal S b , the third logic signal S c .

[0012] In a possible implementation, the first logic signal S a , the second logic signal S b , the third logic signal S c The logic circuit after the comparator obtains the first switching signal S 1a , the second switching signal S 2a , the third switch signal S 1b , the fourth switch signal S 2b , the fifth switch signal S 1c, the sixth switch signal S 2c , the seventh switch signal S 1d and the eighth switching signal S 2d The specific process includes:

[0013] Comparator 4, comparator 5, and comparator 6 process the three-phase symmetrical sine waves one by one. Obtaining a fourth logic signal a, a fifth logic signal b, and a sixth logic signal c;

[0014] The first logic signal S a , the second logic signal S b , the third logic signal S c , the fourth logic signal a, the fifth logic signal b and the sixth logic signal c are processed by multiplier 1, multiplier 2 and multiplier 3 to obtain a seventh logic signal d, an eighth logic signal e and a ninth logic signal f;

[0015] The first logic signal S a , the second logic signal S b , the third logic signal S c , the seventh logic signal d, the eighth logic signal e and the ninth logic signal f are processed by adder-subtractor 1, adder-subtractor 2, adder-subtractor 3 and adder-subtractor 4 to obtain the first switching signal to the eighth switching signal.

[0016] In a possible implementation manner, the first logic signal S a , the second logic signal S b , the third logic signal S c , the fourth logic signal a, the fifth logic signal b, and the sixth logic signal c are processed by multiplier 1, multiplier 2, and multiplier 3 to obtain a seventh logic signal d, an eighth logic signal e, and a ninth logic signal f, including:

[0017] The first logic signal S a , the second logic signal S b , the third logic signal S c and the fourth logic signal a as an input of the multiplier 1 to obtain a seventh logic signal d;

[0018] The first logic signal S a , the second logic signal S b , the third logic signal S c and the fifth logic signal b as an input of the multiplier 1 to obtain an eighth logic signal e;

[0019] The first logic signal Sa , the second logic signal S b , the third logic signal S c The sixth logic signal c is used as the input of the multiplier 1 to obtain the ninth logic signal f.

[0020] In a possible implementation manner, the first logic signal S a , the second logic signal S b , the third logic signal S c , the seventh logic signal d, the eighth logic signal e and the ninth logic signal f are processed by the adder-subtractor 1, the adder-subtractor 2, the adder-subtractor 3 and the adder-subtractor 4 to obtain the first switching signal to the eighth switching signal, including:

[0021] The first logic signal S is processed by the adder-subtractor 1 a and the seventh logic signal d to obtain the first switch signal S 1a ;

[0022] The first logic signal S is processed by the adder-subtractor 1 a After processing the seventh logic signal d, it is processed by the NOT gate 1 to obtain the second switch signal S 2a ;

[0023] The second logic signal S is processed by the adder-subtractor 2 b and the eighth logic signal e to obtain the third switch signal S 1b ;

[0024] The second logic signal S is processed by the adder-subtractor 2 b After processing the eighth logic signal e, it is processed by the NOT gate 2 to obtain the fourth switch signal S 2b ;

[0025] The third logic signal S is processed by the adder-subtractor 3. c and the ninth logic signal f to obtain the fifth switch signal S 1c ;

[0026] The third logic signal S is processed by the adder-subtractor 3. c After processing the ninth logic signal f, it is processed by the NOT gate 3 to obtain the sixth switch signal S 2c ;

[0027] The value 2 and the first switch signal S are connected by the adder and subtractor 4. 1a , the third switch signal S 1b and the fifth switching signal S 1c Processing is performed to obtain the seventh switch signal S 1d ;

[0028] The value 2 and the first switch signal S are connected by the adder and subtractor 4. 1a , the third switch signal S 1b and the fifth switching signal S 1c After processing, it is processed by the NOT gate 4 to obtain the eighth switch signal S 2d .

[0029] In a possible implementation, the carrier used can be either a single carrier or a dual carrier, and there is no need to determine the sector where the reference vector is located, nor to calculate the vector action time.

[0030] The present invention provides a method for suppressing leakage current of a three-phase four-bridge-arm grid-connected inverter based on DPWMAX. The method refers to a carrier modulation strategy for suppressing leakage current of a three-phase four-bridge-arm inverter, which is achieved by switching signal modulation to convert a three-phase symmetrical sine wave into a carrier wave. The waveform is converted into DPWMMAX and compared with the triangular carrier VC through a comparator to obtain the three-phase logic signals A, B, and C; the three-phase logic signal is combined with the mathematical logic operation, and the common-mode voltage can be stabilized at a certain value by changing the logic signal in the three phases. No matter what mode the circuit is in, the common-mode voltage is maintained constant, so that the leakage current is controlled within the allowable range. In addition, the present invention adopts mathematical logic control to eliminate the leakage current of the three-phase four-bridge-leg inverter. There is no complicated calculation process, and the implementation process is simple. Figure 2 As shown, we can conclude that in the interval S1, S6 ( =1), at this time, the C-phase modulation wave and the carrier wave cannot intersect, so the number of switches is greatly reduced, and the waveform characteristics of DPWMAX are used to make the switching signal S 1a 、S 1b 、S 1c There is no switch state of (0, 0, 0); similarly, we can conclude that in the interval S2 and S3 ( 1), and the carrier cannot be greater than 1. At this time, the A-phase modulation wave and the carrier cannot intersect, so the number of switches is greatly reduced, and the waveform characteristics of DPWMAX are used to make the switching signal S 1a 、S 1b 、S 1c There is no switch state of (0, 0, 0); similarly, we can conclude that in the interval S4 and S5 ( =1), at this time, the B-phase modulation wave and the carrier cannot intersect, so the number of switches is greatly reduced, and the waveform characteristics of DPWMAX are used to make the switching signal S 1a 、S 1b 、S 1c There is no switching state of (0, 0, 0); this patent uses the waveform characteristics of DPWMAX to reduce the number of switches and simplify the control difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0032] Figure 1 A schematic diagram of a switching signal carrier modulation strategy for a three-phase four-leg grid-connected inverter is provided for an embodiment of the present invention.

[0033] Figure 2 This is the DPWMAX graph in the embodiment of the present invention.

[0034] Figure 3 4 is a circuit diagram of a three-phase four-leg grid-connected inverter according to an embodiment of the present invention.

[0035] The above drawings illustrate specific embodiments of the present invention, which will be described in more detail below. These drawings and the accompanying description are not intended to limit the scope of the present invention in any way, but rather to illustrate the concept of the present invention to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0036] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. In the following description, when referring to the drawings, like numbers in different figures represent like or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present invention, as detailed in the appended claims.

[0037] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] like Figure 1 As shown, an embodiment of the present invention provides a method for suppressing leakage current of a three-phase four-leg grid-connected inverter based on DPWMAX, including:

[0039] The carrier modulation strategy for leakage current suppression of three-phase four-leg transformerless inverter is realized by switching signal modulation. The DPWMMAX waveform is converted into a triangular carrier VC and compared with the comparator to obtain the three-phase logic signals A, B, and C; by combining the three-phase logic signal with mathematical logic operations and changing the three-phase logic signal, the common-mode voltage can be stabilized at a certain value. No matter what mode the circuit is in, the common-mode voltage remains constant, so that the leakage current is controlled within the allowable range.

[0040] In a possible implementation manner, the comparator includes comparator 1, comparator 2, comparator 3, comparator 4, comparator 5, and comparator 6, and the three-phase logic signal includes a first logic signal S a , the second logic signal S b and the third logic signal S c ; The mathematical logic operations are respectively performed by addition and subtraction operator 1, addition and subtraction operator 2, addition and subtraction operator 3, addition and subtraction operator 4, multiplication operator 1, multiplication operator 2 and multiplication operator 3.

[0041] In one possible implementation, a three-phase symmetrical sine wave The DPWMMAX waveform is compared with the triangular carrier VC through the comparator to obtain the three-phase logic signals A, B, and C, including:

[0042] Comparator 1, Comparator 2, and Comparator 3 process the three-phase symmetrical sine waves one by one. The corresponding DPWMMAX wave and the triangular carrier VC are used to obtain the three-phase logic signals A, B, and C; wherein the three-phase logic signals A, B, and C include the first logic signal S a , the second logic signal S b , the third logic signal S c .

[0043] In a possible implementation, the first logic signal S a , the second logic signal S b , the third logic signal S c The logic circuit after the comparator obtains the first switching signal S 1a , the second switching signal S 2a , the third switch signal S 1b , the fourth switch signal S 2b , the fifth switch signal S 1c , the sixth switch signal S 2c , the seventh switch signal S 1d and the eighth switching signal S 2d The specific process includes:

[0044] Comparator 4, comparator 5, and comparator 6 process the three-phase symmetrical sine waves one by one. Obtaining a fourth logic signal a, a fifth logic signal b, and a sixth logic signal c;

[0045] The first logic signal S a , the second logic signal S b , the third logic signal S c, the fourth logic signal a, the fifth logic signal b and the sixth logic signal c are processed by multiplier 1, multiplier 2 and multiplier 3 to obtain a seventh logic signal d, an eighth logic signal e and a ninth logic signal f;

[0046] The first logic signal S a , the second logic signal S b , the third logic signal S c , the seventh logic signal d, the eighth logic signal e and the ninth logic signal f are processed by adder-subtractor 1, adder-subtractor 2, adder-subtractor 3 and adder-subtractor 4 to obtain the first switching signal to the eighth switching signal.

[0047] In a possible implementation manner, the first logic signal S a , the second logic signal S b , the third logic signal S c , the fourth logic signal a, the fifth logic signal b, and the sixth logic signal c are processed by multiplier 1, multiplier 2, and multiplier 3 to obtain a seventh logic signal d, an eighth logic signal e, and a ninth logic signal f, including:

[0048] The first logic signal S a , the second logic signal S b , the third logic signal S c and the fourth logic signal a as an input of the multiplier 1 to obtain a seventh logic signal d;

[0049] The first logic signal S a , the second logic signal S b , the third logic signal S c and the fifth logic signal b as an input of the multiplier 1 to obtain an eighth logic signal e;

[0050] The first logic signal S a , the second logic signal S b , the third logic signal S c The sixth logic signal c is used as the input of the multiplier 1 to obtain the ninth logic signal f.

[0051] In a possible implementation manner, the first logic signal S a , the second logic signal S b , the third logic signal S c , the seventh logic signal d, the eighth logic signal e and the ninth logic signal f are processed by the adder-subtractor 1, the adder-subtractor 2, the adder-subtractor 3 and the adder-subtractor 4 to obtain the first switching signal to the eighth switching signal, including:

[0052] The first logic signal S is processed by the adder-subtractor 1 a and the seventh logic signal d to obtain the first switch signal S 1a ;

[0053] The first logic signal S is processed by the adder-subtractor 1 a After processing the seventh logic signal d, it is processed by the NOT gate 1 to obtain the second switch signal S 2a ;

[0054] The second logic signal S is processed by the adder-subtractor 2 b and the eighth logic signal e to obtain the third switch signal S 1b ;

[0055] The second logic signal S is processed by the adder-subtractor 2 b After processing the eighth logic signal e, it is processed by the NOT gate 2 to obtain the fourth switch signal S 2b ;

[0056] The third logic signal S is processed by the adder-subtractor 3. c and the ninth logic signal f to obtain the fifth switch signal S 1c ;

[0057] The third logic signal S is processed by the adder-subtractor 3. c After processing the ninth logic signal f, it is processed by the NOT gate 3 to obtain the sixth switch signal S 2c ;

[0058] The value 2 and the first switch signal S are connected by the adder and subtractor 4. 1a , the third switch signal S 1b and the fifth switching signal S 1c Processing is performed to obtain the seventh switch signal S 1d ;

[0059] The value 2 and the first switch signal S are connected by the adder and subtractor 4. 1a , the third switch signal S 1b and the fifth switching signal S 1c After processing, it is processed by the NOT gate 4 to obtain the eighth switch signal S 2d .

[0060] For ease of understanding, we will Figure 2 The DPWMAX graph shown is deduced.

[0061] like Figure 2 As shown, the three-phase symmetrical sine wave It becomes DPWMMAX waveform, in intervals S1 and S6 ( is 1), S c It is definitely 1. At this time, it passes through the comparator 6 (when the input is 1, the output is 1; when the output is less than 1, the output is 0), then the sixth logic signal c is definitely 1; If it is not 1, then the fourth logic signal a and the fifth logic signal b are 0. At this time, the first logic signal S a Equal to S 1a , the second logic signal S b Equal to S 1b Since the sixth logic signal c is always 1 in the intervals S1 and S6, when the logic signal S a 、S b 、S c When the three-phase logic signals are all 1 and in the intervals S1 and S6, the logic signal f must be 1, and the third logic signal S c Subtract the logic signal f. Get the switching signal S 1a 、S 1b 、S 1c is (1, 1, 0), the switching signal S 1d =2-S 1a -S 1b -S 1c is 0, the number of switches is 2, and the constant common mode voltage of the system is When the logic signal S c When the logic signal is 1, S a 、S b When either of the two-phase logic signals is 1, the switching signal S 1d =2-S 1a -S 1b -S 1c is 0, the number of switches is 2, and the constant common mode voltage of the system is When the logic signal S c The logic signal is 1, S a 、S b When both phase logic signals are 0, the switching signal S 1d =2-S 1a -S 1b -S 1c is 1, the number of switches is 2, and the constant common-mode voltage of the system is

[0062] Similarly, in intervals S2 and S3, S a It is definitely 1. At this time, it passes through the comparator 4 (when the input is 1, the output is 1; when the output is less than 1, the output is 0), then the fourth logic signal a is definitely 1; If it is not 1, then the fifth logic signal b and the sixth logic signal c are 0. At this time, the second logic signal S b Equal to S 1b , the third logic signal S c Equal to S 1c Since the fourth logic signal a is always 1 in the intervals S2 and S3, when the logic signal S a 、S b 、S c When the three-phase logic signals are all 1 and in intervals S2 and S3, the logic signal d must be 1. The first logic signal S a Subtract the logic signal d. Get the switching signal S 1a 、S 1b 、S 1c is (0, 1, 1), the switch signal S 1d =2-S 1a -S 1b -S 1c is 0, the number of switches is 2, and the constant common mode voltage of the system is When the logic signal S a When the logic signal is 1, S b 、S c When either of the two-phase logic signals is 1, the switching signal S 1d =2-S 1a -S 1b -S 1c is 0, the number of switches is 2, and the constant common mode voltage of the system is When the logic signal S a The logic signal is 1, S b 、S c When both phase logic signals are 0, the switching signal S 1d =2-S 1a -S 1b -S 1c is 1, the number of switches is 2, and the constant common-mode voltage of the system is

[0063] Similarly, in intervals S4 and S5, S b It is definitely 1. At this time, it passes through the comparator 5 (when the input is 1, the output is 1; when the output is less than 1, the output is 0), then the fifth logic signal b is definitely 1; If it is not 1, then the fourth logic signal a and the sixth logic signal c are 0. At this time, the first logic signal S a Equal to S 1a , the third logic signal S c Equal to S 1c Since the third logic signal a is always 1 in the intervals S2 and S3, when the logic signal S a 、Sb 、S c When the three-phase logic signals are all 1 and in intervals S2 and S3, the logic signal e must be 1. The first logic signal S a Subtract the logic signal d. Get the switching signal S 1a 、S 1b 、S 1c is (1, 0, 1), the switching signal S 1d =2-S 1a -S 1b -S 1c is 0, the number of switches is 2, and the constant common mode voltage of the system is When the logic signal S b When the logic signal is 1, S a 、S c When either of the two-phase logic signals is 1, the switching signal S 1d =2-S 1a -S 1b -S 1c is 0, the number of switches is 2, and the constant common mode voltage of the system is When the logic signal S b The logic signal is 1, S b 、S c When both phase logic signals are 0, the switching signal S 1d =2-S 1a -S 1b -S 1c is 1, the number of switches is 2, and the constant common-mode voltage of the system is

[0064] like Figure 3 As shown, V an , V bn , V cn , V dn , respectively represent the voltage difference between point A, point B, point C, point D and point N, V dc Indicates the power supply voltage, V cm Indicates the common mode voltage. According to the above reasoning, in the intervals S1 and S6, the logic signals e and f must be 1; the logic signals a, b, d, and e must be 0, and S c Definitely 1.

[0065] Table 1 Switching state results obtained by using DPWMAX for carrier modulation control in intervals S1 and S6

[0066] e f <![CDATA[S a ]]> <![CDATA[S b ]]> <![CDATA[S c ]]> <![CDATA[S 1a ]]> <![CDATA[S 1b ]]> <![CDATA[S 1c ]]> <![CDATA[S 1d ]]> <![CDATA[V an ]]> <![CDATA[V bn ]]> <![CDATA[V cn ]]> <![CDATA[V dn ]]> <![CDATA[V cm ]]> 1 1 0 0 1 0 0 1 1 0 0 <![CDATA[V dc ]]> <![CDATA[V dc ]]> <![CDATA[V dc / 2]]> 1 1 1 0 1 1 0 1 0 <![CDATA[V dc ]]> 0 <![CDATA[V dc ]]> 0 <![CDATA[V dc / 2]]> 1 1 0 1 1 0 1 1 0 0 <![CDATA[V dc ]]> <![CDATA[V dc ]]> 0 <![CDATA[V dc / 2]]> 1 1 1 1 1 1 1 0 0 <![CDATA[V dc ]]> <![CDATA[V dc ]]> 0 0 <![CDATA[V dc / 2]]>

[0067] As can be seen from Table 1 above, the three-phase four-leg grid-connected inverter leakage current suppression method provided by this application is used to perform carrier modulation control in intervals S1 and S6, which realizes the system common mode voltage V cm is constant, V dc / 2, thus ensuring that the leakage current is effectively suppressed. In the intervals S1 and S6 ( =1), at this time the C phase modulated wave and the carrier wave cannot intersect, so S 1c It is always 1, so S 1a 、S 1b 、S 1c The switching state does not exist in the (0, 0, 0) state, and the patent uses the waveform characteristics of DPWMAX to reduce the number of switches and simplify the control difficulty.

[0068] According to the above reasoning, in intervals S2 and S3, the logic signals a and d are definitely 1; the logic signals b, c, e, and f are definitely 0, and S a Definitely 1

[0069] Table 2 Switching state results obtained by using DPWMAX for carrier modulation control in intervals S2 and S3

[0070] a d <![CDATA[S a ]]> <![CDATA[S b ]]> <![CDATA[S c ]]> <![CDATA[S 1a ]]> <![CDATA[S 1b ]]> <![CDATA[S 1c ]]> <![CDATA[S 1d ]]> <![CDATA[V an ]]> <![CDATA[V bn ]]> <![CDATA[V cn ]]> <![CDATA[V dn ]]> <![CDATA[V cm ]]> 1 1 1 0 0 1 0 0 1 <![CDATA[V dc ]]> 0 0 <![CDATA[V dc ]]> <![CDATA[V dc / 2]]> 1 1 1 0 1 1 0 1 0 <![CDATA[V dc ]]> 0 <![CDATA[V dc ]]> 0 <![CDATA[V dc / 2]]> 1 1 1 1 0 1 1 1 0 <![CDATA[V dc ]]> <![CDATA[V dc ]]> 0 0 <![CDATA[V dc / 2]]> 1 1 1 1 1 0 1 0 0 0 <![CDATA[V dc ]]> <![CDATA[V dc ]]> 0 <![CDATA[V dc / 2]]>

[0071] As can be seen from Table 2 above, the three-phase four-leg grid-connected inverter leakage current suppression method provided by this application is used to perform carrier modulation control in intervals S2 and S3, which realizes the system common mode voltage V cm is constant, V dc / 2, thus ensuring that the leakage current is effectively suppressed. In the intervals S2 and S3 ( =1), at this time the A phase modulated wave and the carrier wave cannot intersect, so S 1a It is always 1, so S 1a 、S 1b 、S 1c The switching state of (0, 0, 0) does not exist. This patent uses the waveform characteristics of DPWMAX to reduce the number of switches and simplify the control difficulty.

[0072] According to the above reasoning, in intervals S4 and S5, the logic signals b and e are definitely 1; the logic signals a, c, d, and f are definitely 0, and S b Definitely 1

[0073] Table 3 Switching state results obtained by using DPWMAX for carrier modulation control in intervals S4 and S5

[0074] b e <![CDATA[S a ]]> <![CDATA[S b ]]> <![CDATA[S c ]]> <![CDATA[S 1a ]]> <![CDATA[S 1b ]]> <![CDATA[S 1c ]]> <![CDATA[S 1d ]]> <![CDATA[V an ]]> <![CDATA[V bn ]]> <![CDATA[V cn ]]> <![CDATA[V dn ]]> <![CDATA[V cm ]]> 1 1 0 1 0 0 1 0 1 0 <![CDATA[V dc ]]> 0 <![CDATA[V dc ]]> <![CDATA[V dc / 2]]> 1 1 1 1 0 1 1 0 0 <![CDATA[V dc ]]> 0 <![CDATA[V dc ]]> 0 <![CDATA[V dc / 2]]> 1 1 0 1 1 0 1 1 0 <![CDATA[V dc ]]> <![CDATA[V dc ]]> 0 0 <![CDATA[V dc / 2]]> 1 1 1 1 1 1 0 1 0 <![CDATA[V dc ]]> 0 <![CDATA[V dc ]]> 0 <![CDATA[V dc / 2]]>

[0075] As can be seen from Table 3 above, the three-phase four-leg grid-connected inverter leakage current suppression method provided by this application is used to perform carrier modulation control in intervals S4 and S5, which realizes the system common mode voltage V cm is constant, V dc / 2, thus ensuring that the leakage current is effectively suppressed. In the intervals S4 and S5 ( =1), at this time, the B-phase modulation wave and the carrier wave cannot intersect, S 1b It is always 1, so S 1a 、S 1b 、S 1c The switching state does not exist (0, 0, 0). This patent uses the waveform characteristics of DPWMAX to reduce the number of switches and simplify the control difficulty.

[0076] In summary, combined with the switch states shown in Tables 1, 2, and 3, Figure 1 The logic circuit shown and Figure 2 The DPWMAX waveform shown can stabilize the common-mode voltage at a certain value. Regardless of the mode of the circuit, the common-mode voltage remains constant, so that the leakage current is controlled within the allowable range. Those skilled in the art will easily think of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptive changes of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art that are not disclosed in the present invention. It should be understood that the present invention is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A method for suppressing leakage current of a three-phase four-leg grid-connected inverter based on DPWMAX, characterized in that: include: The carrier modulation strategy for leakage current suppression of three-phase four-leg transformerless inverter is realized by switching signal modulation. The DPWMMAX waveform is converted into a DPWMMAX waveform and compared with the triangular carrier VC through a comparator to obtain the three-phase logic signals A, B, and C. By combining the three-phase logic signals with mathematical logic operations and changing the three-phase logic signals, the common-mode voltage can be stabilized at a certain value. Regardless of the mode of the circuit, the common-mode voltage remains constant, so that the leakage current is controlled within the allowable range. The comparators include comparator 1, comparator 2, comparator 3, comparator 4, comparator 5 and comparator 6, and the three-phase logic signal includes a first logic signal , the second logic signal and the third logic signal The mathematical logic operations are respectively performed by the addition and subtraction unit 1, the addition and subtraction unit 2, the addition and subtraction unit 3, the addition and subtraction unit 4, the multiplication unit 1, the multiplication unit 2 and the multiplication unit 3; Among them, when the output of comparator 1 is greater than 0, the output is 1; when the output of comparator 1 is less than 0, the output is 0; when the output of comparator 2 is greater than 0, the output is 1; when the output of comparator 2 is less than 0, the output is 0; when the output of comparator 3 is greater than 0, the output is 1; when the output of comparator 3 is less than 0, the output is 0; when the input of comparator 4 is 1, the output is 1; when the output of comparator 4 is less than 1, the output is 0; when the input of comparator 5 is 1, the output is 1; when the output of comparator 5 is less than 1, the output is 0; when the input of comparator 6 is 1, the output is 1; when the output of comparator 6 is less than 1, the output is 0; The three-phase symmetrical sine wave The DPWMMAX waveform is compared with the triangular carrier VC through the comparator to obtain the three-phase logic signals A, B, and C, including: Comparator 1, Comparator 2, and Comparator 3 process the three-phase symmetrical sine waves one by one. The corresponding DPWMMAX wave and the triangular carrier VC are used to obtain the three-phase logic signals A, B, and C; wherein the three-phase logic signals A, B, and C include the first logic signal , the second logic signal , the third logic signal ; The first logic signal , the second logic signal , the third logic signal The logic circuit after the comparator gets the first switch signal , the second switch signal , the third switch signal , the fourth switch signal , the fifth switch signal , the sixth switch signal , the seventh switch signal and the eighth switch signal The specific process includes: Comparator 4, comparator 5, and comparator 6 process the three-phase symmetrical sine waves one by one. , obtaining a fourth logic signal a, a fifth logic signal b, and a sixth logic signal c; The first logic signal , the second logic signal , the third logic signal , the fourth logic signal a, the fifth logic signal b and the sixth logic signal c are processed by multiplier 1, multiplier 2 and multiplier 3 to obtain a seventh logic signal d, an eighth logic signal e and a ninth logic signal f; The first logic signal , the second logic signal , the third logic signal , the seventh logic signal d, the eighth logic signal e and the ninth logic signal f are processed by adder-subtractor 1, adder-subtractor 2, adder-subtractor 3 and adder-subtractor 4 to obtain the first switching signal to the eighth switching signal.

2. The method for suppressing leakage current of a three-phase four-leg grid-connected inverter based on DPWMAX according to claim 1, characterized in that: The first logic signal , the second logic signal , the third logic signal , the fourth logic signal a, the fifth logic signal b, and the sixth logic signal c are processed by multiplier 1, multiplier 2, and multiplier 3 to obtain a seventh logic signal d, an eighth logic signal e, and a ninth logic signal f, including: The first logic signal , the second logic signal , the third logic signal and the fourth logic signal a as an input of the multiplier 1 to obtain a seventh logic signal d; The first logic signal , the second logic signal , the third logic signal and the fifth logic signal b as an input of the multiplier 1 to obtain an eighth logic signal e; The first logic signal , the second logic signal , the third logic signal The sixth logic signal c is used as the input of the multiplier 1 to obtain the ninth logic signal f.

3. The method for suppressing leakage current of a three-phase four-leg grid-connected inverter based on DPWMAX according to claim 1, characterized in that: The first logic signal , the second logic signal , the third logic signal , the seventh logic signal d, the eighth logic signal e and the ninth logic signal f are processed by the adder-subtractor 1, the adder-subtractor 2, the adder-subtractor 3 and the adder-subtractor 4 to obtain the first switching signal to the eighth switching signal, including: The first logic signal is processed by the adder and subtractor 1 and the seventh logic signal d to obtain the first switch signal ; The first logic signal is processed by the adder and subtractor 1 After processing the seventh logic signal d, it is processed by the NOT gate 1 to obtain the second switch signal ; The second logic signal is processed by the adder and subtractor 2 and the eighth logic signal e to obtain the third switch signal ; The second logic signal is processed by the adder and subtractor 2 After processing the eighth logic signal e, it is processed by the NOT gate 2 to obtain the fourth switch signal ; The third logic signal is processed by the adder-subtractor 3 and the ninth logic signal f to obtain the fifth switch signal ; The third logic signal is processed by the adder-subtractor 3 After processing the ninth logic signal f, it is processed by the NOT gate 3 to obtain the sixth switch signal ; Through the addition and subtraction operator 4, the value 2 and the first switch signal , the third switch signal and the fifth switch signal Process and obtain the seventh switch signal ; Through the addition and subtraction operator 4, the value 2 and the first switch signal , the third switch signal and the fifth switch signal After processing, it is processed by the NOT gate 4 to obtain the eighth switch signal .

4. The method for suppressing leakage current of a three-phase four-leg grid-connected inverter based on DPWMAX according to claim 1, characterized in that: The carrier used is single carrier or dual carrier.

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