NOT gate layout optimization temperature measurement method based on FPGA ring oscillation circuit temperature measurement

Abstract

The invention discloses a NOT gate layout optimization temperature measurement method based on FPGA ring oscillation circuit temperature measurement, and designs a temperature sensor in order to measure the frequency of a ring oscillation circuit. The temperature sensor is composed of an annular oscillation circuit, a decline counter with a preset value of M, a decline counter output NOR gate, a temperature sensor enabling exclusive-OR gate, a first synchronous register, a second synchronous register and a temperature sensor output AND gate. NOT gate time delay is increased by optimizing NOT gate layout, and all temperature points are calibrated and fitted to obtain a curve of the relation between the output frequencies and the temperatures of annular oscillation circuits in all temperature sensors in the temperature measurement circuit and fitting coefficients corresponding to the curve; according to the invention, the frequency output of the ring oscillation circuit is more sensitive to the temperature change, so that the temperature measurement precision is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of thermal management of field programmable gate arrays (FPGAs), and particularly relates to a NOT gate layout optimization temperature measurement method based on temperature measurement of an FPGA ring oscillator circuit. Background Art

[0002] With the rapid development of semiconductor technology over the past few decades, continuous progress in process technology has made large-scale integrated circuits more compact and efficient. As the size of semiconductor devices continues to shrink, Moore's Law has continuously driven the rapid increase in the number of transistors in chips. However, when the transistor size is reduced to the nanometer level, the leakage current increases significantly, which not only leads to an increase in static power consumption but may also cause the formation of local temperature hotspots. These local temperature hotspots pose a serious threat to the performance and reliability of the chip. Specifically, local hotspots may cause chip timing errors because temperature changes affect the circuit delay. In addition, high temperatures accelerate the aging process of the chip, gradually reducing its performance. Eventually, the combined effect of these factors reduces the mean time to failure of the chip, meaning lower reliability and an increased risk of failure. In the field of field programmable gate arrays (FPGAs), as a highly flexible integrated circuit, FPGAs also face complex thermal management challenges. The programmable nature of FPGAs results in uneven internal structure and power consumption distribution, thus exacerbating the risk of local overheating of the chip. This not only affects the performance of FPGAs but also limits their application potential in high-performance computing, communication, and artificial intelligence and other fields.

[0003] Regarding the measurement of the internal temperature of FPGAs, there are various methods. For example, the FPGA product line of Xilinx uses the Xilinx analog-to-digital converter (XADC) to measure the junction temperature and power supply voltage of FPGAs. The XADC can measure the junction temperature of FPGAs with high precision. However, such temperature sensors are usually located at specific positions inside the chip, so they can only provide overall temperature information and cannot accurately measure the temperature of each local area inside the chip. At the same time, due to the limitation of the number of ADCs, this type of sensor cannot be deployed on a large scale inside the chip. Summary of the Invention

[0004] The purpose of the present invention is to provide a NOT gate layout optimization temperature measurement method based on temperature measurement of an FPGA ring oscillator circuit. This optimized temperature measurement method significantly improves the accuracy of temperature measurement of the ring oscillator (RO) circuit by optimizing the NOT gate layout.

[0005] The technical solution for achieving the purpose of the present invention is as follows:

[0006] A non-gate layout optimization temperature measurement method based on an FPGA ring oscillator circuit for temperature measurement, which performs temperature measurement through the following temperature measurement circuit:

[0007] The temperature measurement circuit includes a master control circuit, a temperature sensor array composed of N temperature sensors, an N-to-1 multiplexer, and a time-domain counter;

[0008] The N-bit enable signal and the N-bit temperature measurement signal output by the master control circuit will be respectively connected bit by bit to each temperature sensor in the temperature sensor array, and the bit temperature sensor chip select signal output by the master control circuit is connected to the 1-of-N multiplexer; the output OUTPUT of each temperature sensor in the temperature sensor array is connected to the 1-of-N multiplexer, and the output of the 1-of-N multiplexer is connected to the time-domain counter;

[0009] Among them, the temperature sensor includes a ring oscillator circuit, a decrement counter, a decrement counter output NOR gate, a temperature sensor enable XOR gate, a first synchronous register, a second synchronous register, and a temperature sensor output AND gate;

[0010] The enable input EN and the temperature sensor output OUTPUT of the temperature sensor are connected to the input pins of the temperature sensor enable XOR gate, and the output of the temperature sensor enable XOR gate is connected to the enable input EN of the ring oscillator circuit; the output OUT of the ring oscillator circuit is used as a clock signal to access the decrement counter, and the output of the decrement counter is connected to the decrement counter output NOR gate; the temperature measurement input START of the temperature sensor is inverted and then connected to the Load pin of the decrement counter and the CLR pins of the first and second synchronous registers; the output of the decrement counter output NOR gate is connected to the first synchronous register; the output OUT of the ring oscillator circuit is used as a clock signal to access the first synchronous register; the output of the first synchronous counter 5 is used as a clock signal to access the second synchronous register; the input D of the second synchronous register is locked at a high level; the output Q of the second synchronous register and the temperature measurement input START of the temperature sensor are connected to the temperature sensor output AND gate, and the output of the temperature sensor output AND gate is used as the output OUTPUT of the entire temperature sensor.

[0011] The ring oscillator circuit analyzes the delay results of each non-gate connection sequence and input pin combination, and selects the position and pin combination that result in the highest delay;

[0012] Among them, the output frequency measured by the ring oscillator circuit and the temperature are pre-calibrated.

[0013] Compared with the prior art, the significant advantages of the present invention are:

[0014] (1) Parameter influence analysis: The present invention systematically analyzes for the first time the influence of the key parameter of non-gate layout on the output frequency of the ring oscillator circuit, and quantifies the specific effects of these parameters on the temperature measurement accuracy.

[0015] (2) Optimization method: Based on the above analysis results, the present invention has developed an effective optimization method to improve the performance of the temperature sensor based on the ring oscillator circuit.

[0016] (3) Experimental verification: The present invention has verified the temperature measurement performance under different parameter combinations through experiments, providing an experimental basis for the future temperature measurement optimization scheme based on the ring oscillator circuit.

[0017] In summary, through systematic parameter analysis and strategy development, combined with experimental verification, the present invention provides a method for comprehensively optimizing the parameters of the ring oscillator circuit. This method not only improves the temperature measurement accuracy but also verifies its effectiveness through experiments, providing a new direction for the progress and application of temperature measurement technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is the circuit diagram of the ring oscillator circuit and its decrement counter used in the experiment of the present invention.

[0019] Figure 2 It is the circuit diagram of the multi-ring oscillator circuit counting, its multiplexer and TDC used in the experiment of the present invention.

[0020] Figure 3 It is the circuit diagram of the NOT gate used in the experiment of the present invention.

[0021] Figure 4 It is the comparison diagram of the circuits before and after layout optimization in the present invention.

[0022] Figure 5 It is the flow chart of temperature measurement of the ring oscillator circuit.

[0023] Figure 6 It is the layout diagram of the NOT gate used for the optimal parameter combination.

[0024] Figure 7 It is the layout diagram of the NOT gate used for the comparison parameter combination.

[0025] Figure 8 It is the actual layout diagram of the NOT gate of the device using the optimal parameter combination.

[0026] Figure 9 It is the actual wiring diagram of the NOT gate of the device using the optimal parameter combination.

[0027] Figure 10 It is the comparison diagram of the temperature measurement errors between the optimal parameter combination and the comparison parameter combination.

[0028] Figure 11 It is the comparison diagram of the temperature measurement resolutions between the optimal parameter combination and the comparison parameter combination. DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention will be further introduced below in conjunction with the accompanying drawings and specific embodiments.

[0030] The specific implementation manner of the present invention relates to a temperature measurement method for a ring oscillator circuit based on FPGA, which improves the temperature measurement accuracy by optimizing the layout and connection mode of NOT gates. The present invention is mainly based on the FPGA produced by Xilinx Corporation and uses the FPGA development software Vivado developed by Xilinx Corporation. The following are the detailed implementation steps based on the present invention:

[0031] (1) Circuit design:

[0032] The temperature sensor constituted by the temperature measurement method based on the ring oscillator circuit measures the output frequency of the ring oscillator circuit, and calculates the temperature at the location of the ring oscillator circuit through the output frequency. In order to measure the frequency of the ring oscillator circuit, a temperature sensor as shown in Figure 1 is designed. The temperature sensor consists of a ring oscillator circuit 1, a down-counter 2 with a preset value of M, a NOR gate 3 for the output of the down-counter, an XOR gate 4 for enabling the temperature sensor, a first synchronous register 5, a second synchronous register 6, and an AND gate 7 for the output of the temperature sensor.

[0033] Refer to Figure 1 , the enable input EN of the temperature sensor and the output OUTPUT of the temperature sensor are connected to the input pins of the XOR gate 4 for enabling the temperature sensor. At the same time, the output of the XOR gate 4 for enabling the temperature sensor will be connected to the enable input EN of the ring oscillator circuit 1. When the enable input EN of the temperature sensor is at a high level and the output OUTPUT of the temperature sensor is at a low level, the enable input EN of the ring oscillator circuit 1 will be pulled high to drive the ring oscillator circuit 1 to start oscillating. At this time, the output OUT of the ring oscillator circuit 1 will output a signal with continuously changing high and low levels, and the oscillation frequency of this output signal is related to the temperature. The output OUT of the ring oscillator circuit 1 will be used as a clock signal to access the down-counter 2, and the 16-bit output of the down-counter 2 will be connected to the NOR gate 3 for the output of the down-counter. The temperature measurement input START of the temperature sensor is inverted and then connected to the Load pin of the down-counter 2 and the CLR pins of the first and second synchronous registers. Therefore, when the temperature measurement input START of the temperature sensor is at a low level, the 16-bit output of the down-counter 4 will not enter the normal decreasing working state but will be maintained at its preset value M. When the temperature measurement input START of the temperature sensor is pulled high, the down-counter 2 and the first and second synchronous registers 5 and 6 will enter the working state and generate outputs.

[0034] After entering the normal working state, the decrement counter 2 will decrement as the output OUT of the ring oscillator circuit 1 oscillates continuously until the value of the decrement counter 2 decrements to 0. When the value of the decrement counter 2 is greater than 0, the 16-bit output of the decrement counter 2 is not all low level, that is, the output of the NOR gate 3 of the decrement counter output is low level. When the value of the decrement counter 2 is equal to 0, the 16-bit output of the decrement counter is all low level, that is, the output of the NOR gate 3 of the decrement counter output is high level. At the same time, since the output of the NOR gate 3 of the decrement counter output is inverted and connected to the enable EN pin of the decrement counter 2, when the value of the decrement counter 2 is equal to 0, the decrement counter 2 will immediately stop decrementing. The output of the decrement counter NAND gate 3 is then connected to the first synchronous register 5, and the output OUT of the ring oscillator circuit 2 is also connected to the first synchronous register 5 as a clock signal. The output of the first synchronous counter 5 (i.e., Q of DFF1) is used as a clock signal to be connected to the second synchronous register 6, and the input D of the second synchronous register 6 is locked at a high level. At the same time, the output Q of the second synchronous register and the temperature measurement input START of the temperature sensor are connected to the AND gate 7 of the temperature sensor output, and the output of the AND gate 7 of the temperature sensor output will be used as the output OUTPUT of the entire temperature sensor.

[0035] The working process of this temperature sensor is as follows:

[0036] 1) Pull up the enable input EN of the temperature sensor to start the ring oscillator circuit 1. At the same time, keep the temperature measurement input START of the temperature sensor START at a low level to ensure that the remaining circuits are not in a working state. At this time, the output OUTPUT of the temperature sensor is at a low level.

[0037] 2) Keep the enable input EN of the temperature sensor at a high level state, that is, maintain the oscillation state of the ring oscillator circuit. At the same time, pull up the temperature measurement output START of the temperature sensor to make the remaining circuits enter the working state, and the decrement counter starts to decrement. When the value of the decrement counter 2 is not 0, the output OUTPUT of the temperature sensor will remain at a high level.

[0038] 3) When keeping the enable input EN of the temperature sensor and the temperature measurement input START of the temperature sensor at a high level, the decrement counter 1 decrements to 0 as the ring oscillator circuit oscillates. At this time, the output of the decrement counter NAND gate 3 is pulled up. After two cycles of oscillation of the ring oscillator circuit, the output of the decrement counter NAND gate 3 is inverted and transmitted to the AND gate 7 of the temperature sensor output. At this time, the output of the AND gate 7 of the temperature sensor outputs a low level, that is, the temperature sensor completes a temperature measurement, and the temperature sensor outputs a time-domain signal.

[0039] In order to collect the output of each temperature sensor and convert the output time-domain signal into a digital signal, the design is as Figure 2The temperature measurement circuit includes a master control circuit 8, a temperature sensor array 9 composed of N temperature sensors, a 1-of-N multiplexer 10, and a Time-Digital-Counter (TDC) 11.

[0040] Reference Figure 2 , the N-bit enable signal and the N-bit temperature measurement signal output by the master control circuit 8 will be respectively connected bit by bit to each temperature sensor in the temperature sensor array 9, and the 4-bit temperature sensor chip select signal output by the master control circuit 8 will be connected to the 1-of-N multiplexer 10. The output OUTPUT of each temperature sensor in the temperature sensor array 9 will be connected to the 1-of-N multiplexer 10, and the output of the 1-of-N multiplexer 10 will be connected to the time domain counter 11. The main function of the master control circuit 8 is to sequentially pull up the enable signal and the temperature measurement signal of each temperature sensor according to the set sampling interval, and sequentially connect the output of each temperature sensor to the time domain counter 11, so as to realize the serial temperature measurement of N temperature sensors.

[0041] The working process of the sensors in this circuit is as follows:

[0042] 1) The master control circuit pulls down all the N-bit enable signals and all the N-bit temperature measurement signals it outputs.

[0043] 2) Individually pull up the enable signal of temperature sensor #1, and keep the temperature measurement signal of temperature sensor #1 at a low level. The ring oscillator circuit of temperature sensor #1 will start to oscillate, and the output of temperature sensor #1 is at a low level at this time.

[0044] 3) Individually pull up the temperature measurement signal of temperature sensor #1, keep the EN enable signal of temperature sensor #1 at a high level, and set the temperature sensor chip select signal 18 to 4'b0000 to connect the output of temperature sensor #1 to the time domain counter 11 through the 1-of-N multiplexer 10, and the time domain counter 11 will start to work and count.

[0045] 4) When the decrement counter inside temperature sensor #1 decrements to 0, the output OUTPUT of temperature sensor #1 will be pulled down. At this time, the time domain counter 11 stops counting and maintains the output of the time domain counter 11 at the current value.

[0046] 5) Read the output of the 16-bit time domain counter 11.

[0047] 6) Loop the above steps until all temperature sensors complete temperature measurement.

[0048] After the circuit design is completed, it will be saved as a circuit design file with the.v suffix for Verilog use.

[0049] (2) Optimization of the ring oscillator circuit based on the NOT gate layout:

[0050] The temperature measurement method based on a ring oscillator circuit measures the output frequency of the ring oscillator circuit and calculates the temperature accordingly. The ring oscillator circuit is usually composed of an odd number of NOT gates (as shown in Figure 3 ), and consists of a NOT gate feedback 14 formed by connecting the enable AND gate 12 of the ring oscillator circuit, the first NOT gate 13 of the ring oscillator circuit, and an even number of NOT gates head to tail.

[0051] Refer to Figure 3 , the input enable EN of the ring oscillator circuit and the output of the NOT gate feedback 14 will be connected to the enable AND gate 12 of the ring oscillator circuit, and the output of the enable AND gate 12 of the ring oscillator circuit will be connected to the first NOT gate 13 of the ring oscillator circuit. While the output of the first NOT gate 13 of the ring oscillator circuit is used as the output OUTPUT of the entire ring oscillator circuit, it will also be used as the input of the NOT gate feedback 14.

[0052] Assume that the output of the NOT gate feedback 14 is high level. At this time, when the input enable EN of the ring oscillator circuit is pulled high, the output of the enable AND gate 12 of the ring oscillator circuit will be pulled high. After this output is inverted by the first NOT gate 13 of the ring oscillator circuit and becomes low level, the output OUTPUT of the ring oscillator circuit also becomes low level. At the same time, the output OUTPUT of the ring oscillator circuit enters the NOT gate feedback 14, and the level state will not flip, so the output of the NOT gate feedback is also low level. At this time, the output of the enable AND gate 12 of the ring oscillator circuit will be pulled low, resulting in the output OUTPUT of the ring oscillator circuit becoming high level. Therefore, when the output enable EN of the ring oscillator circuit is high level, the output OUTPUT of the ring oscillator circuit will oscillate continuously between high and low levels. The design of the ring oscillator circuit will be saved as a ring oscillator circuit design file named temp_sensor.v.

[0053] The frequency of oscillation of the ring oscillator circuit is mainly related to the delay generated when the signal passes through the NOT gate and during signal transmission. When the signal passes through the NOT gate, a temperature-related delay t inv will be generated. When the output pin of one NOT gate is connected to the input pin of another NOT gate, the signal will pass through the interconnect structure used to connect the SLICEs in the FPGA during transmission. The delay generated when the signal passes through the interconnect structure is denoted as t conn . The delay t inv when passing through the NOT gate and the delay t conn when passing through the interconnect structure are both related to temperature according to the delay-temperature formula (1), where t is the delay, and P and a are coefficients independent of temperature and related to the manufacturing process. When different pins and positions are used for the input and output of the NOT gate, the delay t conn of the interconnect structure will change. Therefore, the total delay t RO of the ring oscillator circuit can be calculated by formula (2), where m is the number of NOT gates:

[0054] t = PT a (1)

[0055] t RO = m * t inv + Σt conn (2)

[0056] In order to reduce the power consumption generated by the oscillation of the internal ring oscillator circuit when the temperature sensor measures temperature, it is necessary to increase the delay of the internal ring oscillator circuit of the temperature sensor as much as possible with limited resources. Other temperature measurement methods based on the ring oscillator circuit mainly increase the internal delay of the ring oscillator circuit by adding NOT gates and do not pay attention to the delay generated by the interconnection structure. Therefore, the innovation of this method lies in using the interconnection structure to generate additional delay to reduce the resource consumption of NOT gates. For the purpose of increasing the delay and reducing the temperature measurement error, the present invention proposes an optimization method based on the layout of NOT gates. This method can optimize the layout of NOT gates, which includes the connection order and pin settings between NOT gates, so that the ring oscillator circuit inside the temperature sensor can increase the total number of times the signal passes through the interconnection structure between the internal NOT gates without increasing the number of NOT gates, thereby increasing the delay of the ring oscillator circuit and reducing the temperature measurement error.

[0057] The optimization method based on the layout of NOT gates proposed by the present invention is as follows:

[0058] 1) Analyze the design requirements and determine the maximum number of available NOT gates according to the design requirements

[0059] 2) Determine the set of all available connection orders of NOT gates on a single SLICE:

[0060] In the FPGA of Xilinx, SLICE, as the basic logic unit, is composed of 8 Look-Up-Tables (LUTs), namely A6LUT, A5LUT, B6LUT, B5LUT, C6LUT, C5LUT, D6LUT and D5LUT. Each look-up table can be instantiated as a NOT gate. Therefore, within the same SLICE, there are multiple connection orders for NOT gates. For example, in the NOT gate connection order {A6LUT, B6LUT, C6LUT}, A6LUT represents the first NOT gate on this SLICE, which is instantiated from the A6LUT look-up table. Its output is connected to the second NOT gate instantiated from B6LUT. The output of B6LUT is then connected to the third NOT gate instantiated from C6LUT. And the output of the last NOT gate C6LUT is connected to the first NOT gate instantiated from A6LUT in the next SLICE, and so on. Different connection orders will result in different routing paths for input and output signals, thus affecting the number of times the signal passes through the interconnect structure. The set of all possible NOT gate connection orders on a single SLICE is the set composed of all permutations of these 8 look-up tables.

[0061] 3) Determine all available input pin combinations:

[0062] When using different look-up tables as NOT gates, there are multiple pins that can be configured as inputs or outputs. The selection of different pins will affect the path length of the signal passing through the interconnect structure, and thus affect the signal delay and power consumption. Specifically, each of the look-up tables A6LUT, B6LUT, C6LUT and D6LUT is equipped with 6 input pins from A1 to A6, while each of the look-up tables A5LUT, B5LUT, C5LUT and D5LUT has 5 input pins from A1 to A5. Particularly, A6LUT and A5LUT share the pins A1 to A5, and the A6 pin is unique to A6LUT; the same is true for B6LUT and B5LUT, C6LUT and C5LUT, D6LUT and D5LUT. Taking the NOT gate connection order of {A6LUT, A5LUT} as an example, all available input pin combinations are {A6LUT:A1, A5LUT:A2}, which means that A6LUT uses the A1 pin. Since the A1 pin has been occupied by A6LUT, A5LUT can only use the pins A2 to A5. Therefore, all available input pin combinations are the combinations of all available look-up tables and their pins under a specific NOT gate connection order.

[0063] 4) Traverse all NOT gate connection combinations and input pin combinations:

[0064] Use nested loops to traverse all NOT gate connection orders and all input pin combinations under each connection order.

[0065] For each combination, use the "report_timeing" and "report_route_status" in Vivado

[0066] Two Tcl commands to calculate the total delay and the number of times passing through the interconnection structure, where the total delay will be used as an evaluation metric.

[0067] 5) Performance evaluation and selection of the optimal combination:

[0068] Analyze the delay results of each NOT gate connection order and input pin combination, filter out the configuration with the longest delay, and determine this NOT gate connection order and input pin combination as the result after NOT gate layout optimization.

[0069] To verify the optimization effect, the present invention conducts a comparative experiment on the optimized delay. This experiment will deploy 16 temperature sensors from #8 to #24. Each temperature sensor consists of 48 NOT gates. Among them, temperature sensors #8 - #15 use the layout optimization method, and temperature sensors #16 - #24 do not have layout optimization and are automatically synthesized by the synthesizer. Since temperature sensors #8 - #15 use the layout optimization method, their layouts and delay performances are consistent, and temperature sensor #14 is selected for comparison. While temperature sensors #16 - #24 are automatically synthesized by the synthesizer, so their layouts are different, and temperature sensor #23 with better delay performance is selected for comparison.

[0070] Layout comparison results for reference Figure 4 , in the figure, the orange part is the NOT gate, and the white connection lines are the connections between NOT gates. It can be seen that the synthesizer tends to deploy the NOT gates concentratedly during synthesis. The delay comparison results are shown in Table 2. It can be seen that after layout optimization, temperature sensors #8 - #15 have increased the number of times the signal passes through the interconnection structure by 46% and the total delay by 20% compared to temperature sensors #16 - #24 without layout optimization.

[0071] (3) Compilation:

[0072] The following are the compilation steps in the present invention:

[0073] a) Open the Vivado software and create a new project.

[0074] b) Import the circuit design file and the ring oscillator circuit design file in steps (1) and (2) respectively.

[0075] c) Create a clock constraint file.

[0076] d) Implement the layout optimization method for the ring oscillator circuits inside all temperature sensors.

[0077] e) Run "Generate Bitstreams" to generate the bitstream file.

[0078] (4) Temperature calibration:

[0079] As can be seen from formula (1), if you want to use the Figure 2 shown temperature measurement circuit for temperature measurement, multiple internal temperatures T of the FPGA chip and their corresponding output frequencies are required as reference points. In order to obtain these reference points, it is necessary to perform temperature calibration at 1 - 10 different temperature points before temperature measurement. In the example of the present invention, XADC is used to measure the junction temperature of the FPGA and this is used as the internal temperature of the chip. The following is the process of temperature calibration:

[0080] a) Place the FPGA board in an incubator, set the temperature of the incubator, and wait for the internal temperature of the incubator to stabilize.

[0081] b) Start the temperature measurement circuit.

[0082] c) Collect and record the output frequencies of each temperature sensor in the temperature measurement circuit and the XADC temperature within 15 minutes, that is, complete one temperature calibration, that is, the corresponding relationship between the output frequency and temperature.

[0083] d) Repeat the above steps until all temperature points are calibrated.

[0084] After all temperature points are calibrated, the curve of the relationship between the output frequency and temperature of the ring oscillator circuits in all temperature sensors in the temperature measurement circuit and the fitting coefficients P and a corresponding to the curve can be fitted based on formula (1).

[0085] (5) Temperature measurement:

[0086] After temperature calibration is completed, the temperature can be measured. The output frequency f RO measured from the ring oscillator circuits of all temperature sensors in the temperature measurement circuit and the fitted coefficients P and a are substituted into formula (1) to calculate the temperature T at the location of the ring oscillator circuits in each temperature sensor.

[0087] (6) Parameter experiment:

[0088] The complete temperature measurement process of a temperature sensor includes four stages: sampling interval, sampling, starting oscillation, and cooling, as Figure 5 shown, corresponding to four parameters: sampling interval, sampling time, starting oscillation time, and cooling time respectively. In order to optimize these parameters, the method of controlling variables is used for experiments, and temperature measurements are carried out and data is collected using different parameter combinations at different temperatures. Finally, based on the 3δ principle, the temperature measurement error and temperature measurement resolution of each parameter combination are calculated using the obtained experimental data, so as to determine the optimal parameter combination.

[0089] Experimental results and validation of effectiveness

[0090] Through the implementation of the present invention, the ring oscillator circuit on the FPGA of model xc7a100tfgg484-2 of Xilinx has been successfully optimized to achieve higher-precision temperature measurement. The obtained optimal parameter combination is shown in Table 1, and the obtained layout is as Figure 8 shown, and the obtained layout and routing are as Figure 9 shown. The experimental results show that by adopting the NOT gate connection sequence of Figure 6 shown, {A6LUT, C6LUT}, combined with a sampling interval of 0.1 second, smaller temperature measurement errors and higher temperature measurement resolutions can be provided under different temperature conditions. This layout utilizes the A6 input pin and O6 output pin of the LUT6. The NOT gate connection sequence of {A6LUT, C6LUT} (as Figure 6 shown) and the NOT gate connection sequence of {A6LUT, B6LUT, C6LUT, D6LUT} (as Figure 7 shown) are compared. The NOT gate connection sequence of {A6LUT, C6LUT} can enable the signal of the NOT gate to pass through the interconnection structure more times, increasing the delay t conn of the interconnection structure by at least 34%, achieving the connection method with the highest delay when the number of NOT gates is fixed, thus making the oscillation frequency more sensitive to temperature changes. The layout and routing situation on the actual FPGA chip is as Figure 7 and Figure 8 shown. The orange-red rhombus is the LUT6 acting as a NOT gate, and the blue connection is the actual routing.

[0091] Experiments were conducted on the same FPGA using the best parameter combination shown in Table 1 and the comparative parameter combination, and the temperature measurement errors and temperature measurement resolutions of the two parameter combinations were compared. Figure 10 and Figure 11 The experimental data clearly demonstrate the remarkable effect brought by the optimization measures. By adopting the layout of the NOT gate connection sequence of {A6LUT, C6LUT} and a sampling interval of 0.1 second, the present invention not only improves the resolution of temperature measurement but also reduces the temperature measurement error by an average of 40%. This achievement directly reflects the effectiveness of this optimization method, especially in improving the temperature measurement accuracy. Figure 10 and Figure 11 The comparative analysis further confirms that compared with the conventional layout and longer sampling interval, this optimization method can capture temperature changes more accurately, thus providing a more reliable temperature monitoring solution for the applications of FPGA in key fields such as high-performance computing, communication, and artificial intelligence. This improvement not only means progress at the technical level but also indicates higher system stability and performance in practical applications.

[0092]

[0093] Table 1

[0094]

[0095]

[0096] Table 2.

Claims

1. A temperature measurement method based on FPGA ring oscillator circuit temperature measurement by non-gate layout optimization, characterized in that: The temperature is measured by the following temperature measurement circuit: The temperature measurement circuit includes a master control circuit, a temperature sensor array consisting of N temperature sensors, an N-select multiplexer and a time domain counter; The N-bit enable signal and the N-bit temperature measurement signal output by the master control circuit will be respectively connected to each temperature sensor in the temperature sensor array in bit by bit, and the 1-bit temperature sensor chip select signal output by the master control circuit will be connected to the N-to-1 multiplexer; the output OUTPUT of each temperature sensor in the temperature sensor array will be connected to the N-to-1 multiplexer, and the output of the N-to-1 multiplexer will be connected to the time domain counter; The temperature sensor includes a ring oscillator circuit, a down counter, a down counter output NOR gate, a temperature sensor enable XOR gate, a first synchronization register, a second synchronization register, and a temperature sensor output AND gate; The enable input EN of the temperature sensor and the output OUTPUT of the temperature sensor are connected to the input pin of the enable XOR gate of the temperature sensor, and the output of the enable XOR gate of the temperature sensor is connected to the enable input EN of the ring oscillator circuit; the output OUT of the ring oscillator circuit is connected to the down counter as a clock signal, and the output of the down counter is connected to the output NOR gate of the down counter; the temperature measurement input START of the temperature sensor is reversed and connected to the Load pin of the down counter and the CLR pins of the first and second synchronization registers; the output of the down counter output NAND gate is connected to the first synchronization register; the output OUT of the ring oscillator circuit is connected to the first synchronization register as a clock signal; the output of the first synchronization counter 5 is connected to the second synchronization register as a clock signal; the input D of the second synchronization register is locked at a high level; the output Q of the second synchronization register and the temperature measurement input START of the temperature sensor are connected to the temperature sensor output AND gate, and the output of the temperature sensor output AND gate serves as the output OUTPUT of the entire temperature sensor; The ring oscillator circuit uses each NOT gate connection sequence and input pin combination for delay analysis, and selects the position and pin combination that results in the highest delay; The output frequency and temperature measured by the corona oscillation circuit are pre-calibrated.

2. The temperature measurement method based on FPGA ring oscillator circuit temperature measurement by non-gate layout optimization according to claim 1, characterized in that: The working process of the temperature sensor is: (1) Pull up the enable input EN of the temperature sensor to start the ring oscillation circuit; at the same time, keep the temperature sensor START temperature measurement input START at a low level. At this time, the output OUTPUT of the temperature sensor is at a low level; (2) Keep the enable input EN of the temperature sensor at a high level, that is, maintain the oscillation state of the ring oscillator circuit, and at the same time pull up the temperature measurement output START of the temperature sensor, and the down counter starts to decrement; when the value of the down counter is not 0, the output OUTPUT of the temperature sensor will remain at a high level; (3) When the enable input EN of the temperature sensor and the temperature measurement input START of the temperature sensor are kept at a high level, the down counter decreases to 0 with the oscillation of the ring oscillation circuit. At this time, the output of the down counter output NAND gate is pulled high; after two cycles of oscillation of the ring oscillation circuit, the output of the down counter output NAND gate 3 is reversed and transmitted to the output AND gate of the temperature sensor. At this time, the output AND gate 7 of the temperature sensor outputs a low level, that is, the temperature sensor completes one temperature measurement, and the temperature sensor outputs a time domain signal.

3. The temperature measurement method based on FPGA ring oscillator circuit temperature measurement by non-gate layout optimization according to claim 1, characterized in that: The working process of the temperature measurement circuit is as follows: (1) The master control circuit pulls down all N-bit enable signals and all N-bit temperature measurement signals output; (2) Pull up the enable signal of temperature sensor #1 alone to maintain the temperature measurement signal of temperature sensor #1 at a low level; the ring oscillator circuit of temperature sensor #1 will start to oscillate, and the output of temperature sensor #1 will be at a low level at this time; (3) Pull up the temperature measurement signal of temperature sensor #1 alone, maintain the EN enable signal of temperature sensor #1 at a high level, connect the output of temperature sensor #1 to the time domain counter through the N-to-1 multiplexer, and the time domain counter starts working and counting; (4) When the down counter inside temperature sensor #1 is decremented to 0, the output OUTPUT of temperature sensor #1 will be pulled low, and the time domain counter will stop counting and maintain the output of the time domain counter at the current value; (5) Read the output of the time domain counter; (6) Repeat the above steps until all temperature sensors complete temperature measurement.

4. The temperature measurement method based on FPGA ring oscillator circuit temperature measurement by non-gate layout optimization according to claim 1, characterized in that: The ring oscillator circuit is also optimized in layout by: (1) Determine the maximum number of available NOT gates; (2) Determine the set of all available NOT gate connection sequences on a single SLICE; (3) Determine all available input pin combinations; (4) Go through all NOT gate connection combinations and input pin combinations: Use nested loops to traverse all NOT gate connection sequences and all input pin combinations under each connection sequence; (5) Performance evaluation and selection of the optimal combination: Analyze the delay results of each NOT gate connection sequence and input pin combination, screen out the configuration with the longest delay, and determine this NOT gate connection sequence and input pin combination as the result after the NOT gate layout optimization.

5. The temperature measurement method based on FPGA ring oscillator circuit temperature measurement by non-gate layout optimization according to claim 1, characterized in that: The process of temperature calibration before the temperature measurement circuit is performed is as follows: Place the FPGA board in a constant temperature box, set the temperature of the constant temperature box, and wait for the temperature inside the constant temperature box to stabilize; Start the temperature measurement circuit, collect and record the output frequency and XADC temperature of each temperature sensor in the temperature measurement circuit within the set time, and complete a temperature calibration; Repeat the above steps until all temperature points are calibrated; After all temperature points are calibrated, a curve of the relationship between the output frequency and temperature of the ring oscillator circuit in all temperature sensors in the temperature measurement circuit and the fitting coefficient corresponding to the curve are fitted.

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