Bias control for memory devices

Abstract

The invention relates to bias control of a memory device. A memory system may store an indication of whether data is coherent. In some examples, the indication may be stored as metadata, with a first value indicating that the data is incoherent, and a second value or a third value indicating that the data is coherent. When a processing unit or other component of the memory system processes a command to access data, the memory system may operate according to a device bias mode when the indication is the first value, and according to a host bias mode when the indication is the second value or the third value.

Description

[0001] Relevant information of divisional application

[0002] This application is a divisional application of the patent application for invention titled "Bias Control of Memory Devices" with an application date of December 27, 2021, an application number of 202180095001.7.

[0003] Cross-reference

[0004] This patent application is the national phase application of International Patent Application No. PCT / US2021 / 073118, titled "Bias Control for a Memory Device", filed by Walker et al. on December 27, 2021, which claims the priority of U.S. Patent Application No. 17 / 198,084, titled "Bias Control for a Memory Device", filed by Walker et al. on March 10, 2021. Each of these documents is assigned to the assignee hereof and each is hereby incorporated by reference in its entirety.

[0005] The technical field relates to bias control of memory devices. Background Art

[0006] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, etc. Information is stored by programming memory cells within the memory device into various states. For example, binary memory cells can be programmed into one of two support states that often correspond to a logic 1 or a logic 0. In some instances, a single memory cell can support more than two possible states, any of which can be stored by the memory cell. To access the information stored in the memory device, components can read or sense the state of one or more memory cells within the memory device. To store information, components can write or program one or more memory cells within the memory device into corresponding states.

[0007] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), 3D cross-point memory (3D cross-point), "NOR" and "NAND" memory devices, etc. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power source. Non-volatile memory cells (e.g., NAND memory cells) may maintain their programmed state for a long time even in the absence of an external power source. Summary of the Invention

[0008] Describe a system. The system may include: a memory; and a controller coupled to the memory, wherein the controller is configured to: store a coherence state of a data set stored in the memory relative to a cache of a host device; and access the memory at least in part based on a bias state of the data set determined at least in part based on the stored coherence state of the data set in response to a command identifying an access operation to the data set stored in the memory, wherein the bias state is associated with control of access to the data set by the controller.

[0009] Describe a system. The system may include: a memory; and a controller coupled to the memory, wherein the controller is configured to: store a coherence state of a data set stored in the memory relative to a cache of a host device; and access the memory at least in part based on a bias state of the data set determined at least in part based on the stored coherence state of the data set in response to a command identifying an access operation to the data set stored in the memory, wherein the bias state is associated with control of access to the data set by the host device.

[0010] Describe a method. The method may include: storing a coherence state of a data set stored in a memory relative to a cache of a host device; accessing the memory at least in part based on a bias state of the data set determined at least in part based on the stored coherence state of the data set in response to a command identifying an access operation to the data set stored in the memory, wherein the bias state is associated with control of access to the data set by a controller associated with the memory.

[0011] Describe a method. The method may include: storing a coherence state of a data set stored in a memory relative to a cache store of a host device; and accessing the memory based at least in part on a bias state of the data set determined at least in part based on the stored coherence state of the data set according to a command identifying an access operation to the data set stored in the memory, wherein the bias state is associated with control of access to the data set by the host device.

[0012] Describe a non - transitory computer - readable medium storing code. The non - transitory computer - readable medium may include instructions that, when executed by a processor of an electronic device, cause the electronic device: to store a coherence state of a data set stored in a memory relative to a cache store of a host device; and to access the memory based at least in part on a bias state of the data set determined at least in part based on the stored coherence state of the data set according to a command identifying an access operation to the data set stored in the memory, wherein the bias state is associated with control of access to the data set by a controller associated with the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 Illustrate an example of a system supporting bias control of a memory device as disclosed herein.

[0014] Figure 2 Illustrate an example of a system supporting bias control of a memory device as disclosed herein.

[0015] Figure 3 Illustrate an example of a system supporting bias control of a memory device as disclosed herein.

[0016] Figure 4 Illustrate an example of a process flow diagram supporting bias control of a memory device as disclosed herein.

[0017] Figure 5 Illustrate an example of a process flow diagram supporting bias control of a memory device as disclosed herein.

[0018] Figure 6 Show a block diagram of a memory controller supporting bias control of a memory device as disclosed herein.

[0019] Figure 7 and 8 Show a flow chart depicting one or more methods supporting bias control of a memory device as disclosed herein. DETAILED DESCRIPTION

[0020] Some interfaces (e.g., Compute Express Link (CXL) interfaces) may provide mechanisms for a bias-based coherence model. Specifically, the CXL specification provides that device-attached memory may track a bias state to determine whether the device needs to send a request to a host device to resolve coherence when the device (e.g., a processing unit of the device) accesses memory. The two bias states are host bias, where the device needs to send a request to resolve coherence to the host device; and device bias, where the memory device may access memory independent of the host device.

[0021] The CXL specification indicates that the device will maintain a bias table for a block (e.g., a page) of memory and a transition agent for managing bias transitions. Bias transitions are typically managed by software by using commands between the memory device and the host device and are managed on a per-block basis. However, managing bias transitions on a per-block basis can be inefficient when parts of the block may have different coherence states.

[0022] Methods and systems for managing bias transitions at a relatively finer granularity are described herein. The CXL specification describes metadata that each row of data may maintain. One of the metadata fields described is the Meta0-state, which may hold one of three values: Invalid, Any, or Shared. The Invalid state indicates that the host does not have a cacheable copy of the row, the Any state indicates that the host may have a shared, exclusive, or modified copy of the row, and the Shared state indicates that the host may have at most a shared copy of the row. The CXL specification thus indicates that the bias state for synchronizing control for coherence is maintained separately from the Meta0-state indicating cache or coherence state. The Meta0-state for each row may be stored, and the Meta0-state may be stored with the row data.

[0023] As described herein, the Meta0-status field can be used to track the current bias state. Specifically, according to various aspects, the Meta0-status Invalid can be equivalent to the device bias, and both Any and Shared can be equivalent to the host bias. Tracking the device-attached media bias at a granularity corresponding to the cache line size of the host device can allow the device to transition the bias of the media on any component that has access to the media. This allows for complete hardware control of the bias and does not require software to perform the complex task of transitioning the device-attached media bias to achieve optimal device performance. In some instances, the Meta0-status can be stored with the data line in the memory media, or can be stored only in the device cache (e.g., maintained in the cache only for the line). If it is stored only in the cache, the device will present the Any state on a cache miss. In either case, using the Meta0-status of the CXL specification to track the bias state on a per-cache-line basis can improve the overall performance of the memory device while maintaining a relatively simple programming model.

[0024] First, the features of the present disclosure are described in the context of a system as described in reference Figures 1 to 3 The features of the present disclosure are described in the context of the process flow diagrams described in reference Figure 4 and 5 The features of the present disclosure are further illustrated and described with reference to the device diagrams and flowcharts related to bias control of a memory device as described in reference Figures 6 - 8 These and other features of the present disclosure are further illustrated and described with reference to the device diagrams and flowcharts related to bias control of a memory device as described in reference

[0025] Figure 1 FIG. 15 shows an example of a system 100 that supports bias control of a memory device as disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0026] The memory system 110 can be or include any device or collection of devices that includes at least one memory array. For example, the memory system 110 can be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), among other possibilities.

[0027] System 100 may be included in a computing device such as a desktop computer, laptop computer, network server, mobile device, vehicle (e.g., an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0028] System 100 may include a host system 105 that may be coupled to a memory system 110. In some instances, this coupling may include an interface with a host system controller 106, which may be an example of a control component configured to cause the host system 105 to perform various operations in accordance with the examples described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., a memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, such as to write data to and read data from the memory system 110. Although one memory system 110 is shown in Figure 1 FIG., the host system 105 may be coupled to any number of memory systems 110.

[0029] The host system 105 may be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 are configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory system 110 and the host system 105). Examples of the physical host interface may include (but are not limited to) SATA interface, UFS interface, eMMC interface, PCIe interface, USB interface, Fibre Channel interface, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Double Data Rate (DDR) interface, DIMM interface (e.g., a DIMM socket interface supporting DDR), Open NAND Flash Interface (ONFI), Low Power Double Data Rate (LPDDR) interface, and CXL interface. In some instances, one or more such interfaces may be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some instances, the host system 105 may be coupled to the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110 or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0030] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory devices 130 may include one or more memory arrays of any type of memory cell (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although Figure 1 two memory devices 130-a and 130-b are shown in the example, the memory system 110 may include any number of memory devices 130. Additionally, if the memory system 110 includes more than one memory device 130, the different memory devices 130 within the memory system 110 may include the same or different types of memory cells.

[0031] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface), and can be an instance of a control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute these commands (e.g., at a memory array within the one or more memory devices 130). For example, the storage system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to effect the desired access to the memory device 130. In some cases, the memory system controller 115 can exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 can convert a response (e.g., a data packet or other signal) associated with the memory device 130 into a corresponding signal for the host system 105.

[0032] The memory system controller 115 can be configured for other operations associated with the memory device 130. For example, the memory system controller 115 can perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refreshing, health monitoring, and address translation between a logical address (e.g., a logical block address (LBA)) associated with a command from the host system 105 and a physical address (e.g., a physical block address) associated with a memory cell within the memory device 130.

[0033] The memory system controller 115 can include hardware, such as one or more integrated circuits or discrete components, buffer memory, or combinations thereof. The hardware can include circuitry with dedicated (e.g., hard-wired) logic to perform the operations ascribed to the memory system controller 115 herein. The memory system controller 115 can be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0034] The memory system controller 115 may also include a local memory 120. In some cases, the local memory 120 may include a read-only memory (ROM) or other memory that may store operation codes (e.g., executable instructions) executable by the memory system controller 115 to perform the functions ascribed to the memory system controller 115 herein. In some cases, the local memory 120 may additionally or alternatively include a static random access memory (SRAM) or other memory that may be used by the memory system controller 115 for, e.g., internal storage or computations related to the functions ascribed to the memory system controller 115 herein. Additionally or alternatively, the local memory 120 may act as a cache for the memory system controller 115. For example, in the case of reading from or writing to the memory device 130, data may be stored in the local memory 120 and the data may be made available within the local memory 120 for subsequent retrieval or manipulation (e.g., update) by the host system 105 according to a cache policy (e.g., in the case of reduced latency with respect to the memory device 130).

[0035] Although Figure 1 the instance of the memory system 110 has been shown as including the memory system controller 115, in some cases the memory system 110 may not include the memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135 within the memory device 130 to perform the functions ascribed to the memory system controller 115 herein, respectively. Generally, one or more of the functions ascribed to the memory system controller 115 may, in some cases, be performed instead by the host system 105, the local controller 135, or any combination thereof. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device, but other types of managed memory devices are also supported. For example, a managed memory device may include any type or number of volatile or non-volatile memory devices.

[0036] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-selecting memory, other chalcogenide-based memories, ferroelectric random access memory (RAM) (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridge RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0037] In some instances, memory device 130 may include (e.g., on the same die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the corresponding memory device 130. Local controller 135 may operate in conjunction with memory system controller 115 or may perform one or more functions ascribed herein to memory system controller 115. For example, as Figure 1 shown, memory device 130-a may include local controller 135-a, and memory device 130-b may include local controller 135-b.

[0038] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package that includes one or more dies 160. In some instances, die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a corresponding set of blocks 170, where each block 170 may include a corresponding set of pages 175, and each page 175 may include a set of memory cells.

[0039] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as single-level cells (SLCs). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLCs) if configured to each store two bits of information, triple-level cells (TLCs) if configured to each store three bits of information, quad-level cells (QLCs) if configured to each store four bits of information, or more generally multi-level memory cells. The multi-level memory cells may provide a greater storage density relative to the SLC memory cells, but in some cases, may involve a narrower read or write margin or greater complexity for the support circuitry.

[0040] In some cases, a plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may be performed within different planes 165. For example, parallel operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175 having the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0041] In some cases, a block 170 may include memory cells organized in rows (pages 175) and columns (e.g., strings, not shown). For example, the memory cells within the same page 175 may share a common word line (e.g., coupled thereto), and the memory cells within the same string may share a common digit line (which may alternatively be referred to as a bit line) (e.g., coupled thereto).

[0042] For some NAND architectures, the memory cells may be read and programmed (e.g., written) at a first granularity level (e.g., at the page granularity level), but erased at a second granularity level (e.g., at the block granularity level). That is, a page 175 may be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and a block 170 may be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Additionally, in some cases, the NAND memory cells may be erased before they can be rewritten with new data. Thus, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing the page 175 has been erased.

[0043] System 100 may include any number of non - transitory computer - readable media that support bias control of a memory device. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise have access to one or more non - transitory computer - readable media that store instructions (e.g., firmware) to perform the functions ascribed herein to host system 105, memory system controller 115, or memory device 130. For example, if executed by host system 105 (e.g., by host system controller 106), by memory system controller 115, or by memory device 130 (e.g., by local controller 135), these instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0044] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include (e.g.) one or more memory arrays and associated circuitry in combination with a local (e.g., on - die or in - package) controller (e.g., local controller 135). An example of a managed memory system is a managed NAND (MNAND) system.

[0045] In some instances, host system 105 may include a cache that includes one or more pages (e.g., one or more pages for storing data). Each page may include one or more rows each associated with a certain amount of data. As described herein, memory system controller 115 may be configured to track the coherence of data shared between host system 105 and memory system 110. For example, memory system controller 115 may track the coherence of data shared between memory device 130 - a or memory device 130 - b and host system 105. The coherence of data may relate to one of three states indicating whether there is no coherent copy of the data at host system 105 and memory system 110 or whether there is a shared, exclusive, or modified copy of the data.

[0046] Memory system 110 may be an example of a CXL device, and memory system controller 115 may be an example of a processing unit configured to access memory devices 130-a and 130-b. For example, memory system controller 115 may be configured to access memory devices 130-a and 130-b according to a host bias mode or a device bias mode. When operating according to the device bias mode, memory system controller 115 may access memory device 130-a or memory device 130-b independently of host system 105 (e.g., after receiving an access request or access command). In contrast, when operating according to the host bias mode, memory system controller 115 may access memory device 130-a or memory device 130-b via host system 105. Additionally, when one or more pages are associated with the host bias mode, the host may modify the version of the one or more pages maintained by the host without having to notify memory system controller 115.

[0047] In some instances, each row of data stored to memory device 130-a or memory device 130-b may be associated with an optional 2-bit Meta0 field. As described herein, the 2-bit Meta0 field may be used to indicate the bias state of the associated data based on the three coherence states. For example, when the data is associated with a first coherence state (e.g., an "invalid" state; where there is no coherent copy of the data), the Meta0 field may indicate operation according to the device bias mode. Additionally or alternatively, when the data is associated with a second coherence state (e.g., an "any" state; where there is a coherent copy of the data) or a third coherence state (e.g., a "shared" state; where there is a coherent copy of the data), the Meta0 field may indicate operation according to the host bias mode. Thus, using Meta0-status to track device bias can allow for tracking of bias states with greater granularity.

[0048] Figure 2 An example of a system 200 that supports bias control of a memory device in accordance with an example disclosed herein is shown. System 200 may be an example of system 100 as described Figure 1 or aspects thereof. System 200 may include a memory system 210 configured to store data received from host system 205 and to send the data to host system 205 if requested by host system 205 using an access command (e.g., a read command or a write command). System 200 may implement aspects of system 100 as described Figure 1 therein. For example, memory system 210 and host system 205 may be examples of memory system 110 and host system 105, respectively.

[0049] As described herein, the memory system 210 may include a memory device 240 to store data transferred between the memory system 210 and the host system 205, e.g., in response to receiving an access command from the host system 205. The memory device 240 may include one or more memory devices as referred to in Figure 1 the description. For example, the memory device 240 may include NAND memory, PCM, select memory, 3D cross-point, other chalcogenide-based memories, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0050] The memory system 210 may include a storage controller 230 to control the transfer of data directly to and from the memory device 240, e.g., for storing data, retrieving data, and determining the memory locations in which to store data and from which to retrieve data. The storage controller 230 may communicate with the memory device 240 directly or via a bus (not shown) using a protocol specific to each type of memory device 240. In some cases, a single storage controller 230 may be used to control multiple memory devices 240 of the same or different types. In some cases, the memory system 210 may include multiple storage controllers 230, e.g., different storage controllers 230 for each type of memory device 240. In some cases, the storage controller 230 may implement aspects of the local controller 135 as referred to in Figure 1 the description.

[0051] The memory system 210 may further include an interface 220 for communicating with the host system 205 and a buffer 225 for temporarily storing data being transferred between the host system 205 and the memory device 240. The interface 220, buffer 225, and storage controller 230 may be used to translate data between the host system 205 and the memory device 240, e.g., as shown by the data path 250, and may be collectively referred to as data path components.

[0052] Temporarily storing data using the buffer 225 during transfer may allow buffering of data while processing commands, thereby reducing the latency between commands and allowing any data size associated with the commands. This may also allow processing of command bursts, and once the burst stops, the buffered data may be stored or transmitted (or both). The buffer 225 may include relatively fast memory (e.g., some types of volatile memory such as SRAM or DRAM) or a hardware accelerator or both to allow fast storage and retrieval of data to and from the buffer 225. The buffer 225 may include a data path switching component for bi-directional data transfer between the buffer 225 and other components.

[0053] The temporary storage of data within buffer 225 may refer to the storage of data in buffer 225 during the execution of an access command. That is, after the access command is completed, the associated data may no longer be maintained in buffer 225 (e.g., overwritten by data of an additional access command). Additionally, buffer 225 may be a non-cache buffer. That is, the host system 205 may not directly read data from buffer 225. For example, a read command may be added to a queue without an operation of matching an address with an address already in buffer 225 (e.g., without a cache address matching or lookup operation).

[0054] Memory system 210 may additionally include a memory system controller 215 for executing commands received from host system 205 and controlling data path components when moving data. Memory system controller 215 may be an instance of memory system controller 115 as described with reference to Figure 1 . Bus 235 may be used for communication between system components.

[0055] In some cases, one or more queues (e.g., command queue 260, buffer queue 265, and storage queue 270) may be used to control the processing of access commands and the movement of corresponding data. For example, this may be beneficial if memory system 210 processes more than one access command from host system 205 in parallel. As an example of a possible implementation, command queue 260, buffer queue 265, and storage queue 270 are depicted at interface 220, memory system controller 215, and storage controller 230, respectively. However, if used, the queues may be located anywhere within memory system 210.

[0056] Data transferred between host system 205 and memory device 240 may take a different path in memory system 210 than non-data information (e.g., commands, status information). For example, system components in memory system 210 may communicate with each other using bus 235, while data may use data path 250 that passes through data path components rather than bus 235. Memory system controller 215 may control how and whether data is transferred between host system 205 and memory device 240 by communicating with data path components via bus 235 (e.g., using a protocol specific to memory system 210).

[0057] If the host system 205 issues an access command to the memory system 210, the interface 220 may receive the command according to a protocol (e.g., UFS protocol, eMMC protocol, CXL protocol), for example. Thus, the interface 220 can be regarded as the front end of the memory system 210. After receiving each access command, the interface 220 may transmit the command to the memory system controller 215 via the bus 235, for example. In some cases, each command may be added to the command queue 260 by the interface 220 to transmit the command to the memory system controller 215.

[0058] The memory system controller 215 may determine that an access command has been received based on the communication from the interface 220. In some cases, the memory system controller 215 may determine that an access command has been received by retrieving the command from the command queue 260. After the command has been retrieved from the command queue 260 by the memory system controller 215, for example, the command may be removed from the command queue. In some cases, the memory system controller 215 may cause the interface 220 to remove the command from the command queue 260 via the bus 235, for example.

[0059] After determining that an access command has been received, the memory system controller 215 may execute the access command. For a read command, this may mean obtaining data from the memory device 240 and transmitting the data to the host system 205. For a write command, this may mean receiving data from the host system 205 and moving the data to the memory device 240.

[0060] In either case, the memory system controller 215 may use the buffer 225 for temporary storage of data received from or transmitted to the host system 205, in particular. The buffer 225 can be regarded as the middle end of the memory system 210. In some cases, buffer address management (e.g., a pointer pointing to an address location in the buffer 225) may be performed by hardware (e.g., a dedicated circuit) in the interface 220, the buffer 225, or the storage controller 230.

[0061] To process a write command received from the host system 205, the memory system controller 215 may first determine whether the buffer 225 has sufficient available space to store the data associated with the command. For example, the memory system controller 215 may determine, via firmware (e.g., controller firmware), for example, the amount of space within the buffer 225 available for storing the data associated with the write command.

[0062] In some cases, buffer queue 265 may be used to control a command stream associated with data stored in buffer 225, the command stream including write commands. Buffer queue 265 may include access commands associated with data currently stored in buffer 225. In some cases, commands in command queue 260 may be moved by memory system controller 215 to buffer queue 265 and may remain in buffer queue 265 while the associated data is stored in buffer 225. In some cases, each command in buffer queue 265 may be associated with an address at buffer 225. That is, a pointer indicating the location where data associated with each command is stored in buffer 225 may be maintained. Using buffer queue 265, multiple access commands may be received sequentially from host system 205 and at least some portions of the access commands may be processed in parallel.

[0063] If buffer 225 has sufficient space to store write data, memory system controller 215 may cause interface 220 to transmit an indication of availability (e.g., a "ready to transfer" indication) to host system 205, e.g., according to a protocol (e.g., the UFS protocol or the eMMC protocol). When interface 220 subsequently receives data associated with a write command from host system 205, interface 220 may use data path 250 to transfer the data to buffer 225 for temporary storage. In some cases, interface 220 may obtain the location of stored data within buffer 225 from buffer 225 or buffer queue 265. Interface 220 may indicate to memory system controller 215, e.g., via bus 235, whether the transfer of data to buffer 225 has been completed.

[0064] Once the write data has been stored in buffer 225 via interface 220, the data may be transferred out of buffer 225 and stored in memory device 240. This may be done using storage controller 230. For example, memory system controller 215 may cause storage controller 230 to retrieve data from buffer 225 using data path 250 and transfer the data to memory device 240. Storage controller 230 may be regarded as the backend of memory system 210. Storage controller 230 may indicate to memory system controller 215, e.g., via bus 235, that the transfer of data to the memory device in memory device 240 has been completed.

[0065] In some cases, the storage queue 270 can be used to assist in the transfer of write data. For example, the memory system controller 215 can push write commands from the buffer queue 265 to the storage queue 270 for processing (e.g., via bus 235). The storage queue 270 can contain entries for each access command. In some instances, the storage queue 270 can additionally contain: a buffer pointer (e.g., an address) that can indicate where in the buffer 225 to store data associated with the command; and a storage pointer (e.g., an address) that can indicate the location in the memory device 240 associated with the data. In some cases, the storage controller 230 can obtain the location within the buffer 225 from which to obtain data from the buffer 225, the buffer queue 265, or the storage queue 270. The storage controller 230 can manage the location in the memory device 240 where data is to be stored (e.g., perform wear leveling, garbage collection, etc.). Entries can be added to the storage queue 270, for example, by the memory system controller 215. After the transfer of data is complete, entries can be removed from the storage queue 270, for example, by the storage controller 230 or the memory system controller 215.

[0066] To process a read command received from the host system 205, the memory system controller 215 can similarly first determine whether the buffer 225 has sufficient available space to store data associated with the command. For example, the memory system controller 215 can determine, via firmware (e.g., controller firmware), for example, the amount of space within the buffer 225 available for storing data associated with the read command.

[0067] In some cases, the buffer queue 265 can be used to assist in the buffer storage of data associated with a read command in a manner similar to that discussed above with respect to write commands. For example, if the buffer 225 has sufficient space to store the read data, the memory system controller 215 can cause the storage controller 230 to retrieve data associated with the read command from the memory device 240 and store the data in the buffer 225 for temporary storage using the data path 250. The storage controller 230 can indicate to the memory system controller 215, via bus 235 for example, whether the transfer of data to the buffer 225 has been completed.

[0068] In some cases, the storage queue 270 can be used to assist in the transfer of read data. For example, the memory system controller 215 can push read commands into the storage queue 270 for processing. In some cases, the storage controller 230 can obtain the location within the memory device 240 from which data is to be retrieved from the buffer 225 or the storage queue 270. In some cases, the storage controller 230 can obtain the location within the buffer 225 where data is to be stored from the buffer queue 265. In some cases, the storage controller 230 can obtain the location within the buffer 225 where data is to be stored from the storage queue 270. In some cases, the memory system controller 215 can move the commands processed by the storage queue 270 back to the command queue 260.

[0069] Once the data has been stored in the buffer 225 by the storage controller 230, the data can be transferred out of the buffer 225 and sent to the host system 205. For example, the memory system controller 215 can cause the interface 220 to retrieve the data from the buffer 225 using the data path 250 and transmit the data to the host system 205 according to a protocol (e.g., UFS protocol, eMMC protocol, CXL protocol). For example, the interface 220 can process commands from the command queue 260 and can indicate to the memory system controller 215, via the bus 235 for example, that the transmission of data to the host system 205 has been completed.

[0070] The memory system controller 215 can execute the received commands in an order (e.g., first-in-first-out order according to the order of the command queue 260). For each command, the memory system controller 215 can cause the data corresponding to the command to move in and out of the buffer 225 as discussed above. When the data moves into the buffer 225 and is stored within the buffer 225, the command can remain in the buffer queue 265. If the processing of the command has been completed (e.g., if the data corresponding to the access command has been transferred from the buffer 225), the command can be removed from the buffer queue 265 by the memory system controller 215 for example. If the command is removed from the buffer queue 265, the address that previously stored the data associated with the command can be used to store the data associated with the new command.

[0071] The memory system controller 215 may be further configured for operations associated with the memory device 240. For example, the memory system controller 215 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 205 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 240. That is, the host system 205 may issue commands indicating one or more LBAs, and the memory system controller 215 may identify the one or more physical block addresses indicated by the LBA. In some cases, one or more adjacent LBAs may correspond to non - adjacent physical block addresses. In some cases, the storage controller 230 may be configured to perform one or more of the above operations in combination with or in place of the memory system controller 215. In some cases, the memory system controller 215 may perform the functions of the storage controller 230, and the storage controller 230 may be omitted.

[0072] In some instances, the host system 205 may include a cache that includes one or more pages (e.g., one or more pages for storing data). Each page may include one or more rows each associated with a certain amount of data. As described herein, the memory system controller 215 may be configured to track the coherence of data shared between the host system 205 and the memory system 210. For example, the memory system controller 215 may track the coherence of data shared between the device memory (not shown) and the host system 205 (not shown). For example, one or more of the memory devices 240 may be CXL devices configured to access data stored in a memory accessible by various devices (e.g., device memory). The memory system controller 215 may track the coherence of the data, which may involve one of three states indicating whether there is no coherent copy of the data at the host system 205 and the memory system 210 or whether there is a shared, exclusive, or modified copy of the data.

[0073] Memory system 210 can be an example of a CXL device that can be configured to access device memory (memory device 240). For example, the CXL device can include a processing device (not shown) configured to access the device memory according to a host bias mode or a device bias mode. When operating according to the device bias mode, the memory system controller 215 can access the device memory independently of the host system 205 (e.g., after receiving an access request or an access command). In contrast, when operating according to the host bias mode, the memory system controller 215 can access the device memory via the host system 205. Thus, when operating according to the host bias mode, the host system 205 can be configured to access the device memory for the corresponding CXL device.

[0074] In some instances, each row of data stored to the device memory can be associated with an optional 2-bit Meta0 field. As described herein, the 2-bit Meta0 field can be used to indicate the bias state of the associated data based on the three coherence states. For example, when the data is associated with a first coherence state (e.g., an "invalid" state; where there is no coherent copy of the data), the Meta0 field can indicate operation according to the device bias mode. Additionally or alternatively, when the data is associated with a second coherence state (e.g., an "any" state; where there is a coherent copy of the data) or a third coherence state (e.g., a "shared" state; where there is a coherent copy of the data), the Meta0 field can indicate operation according to the host bias mode. Thus, using Meta0 - state to track the device bias can allow for tracking the bias state with greater granularity.

[0075] Figure 3 An example of a system 300 that supports bias control of a memory device according to an example disclosed herein is shown. System 300 can include a memory system 305 and a host device 310. The memory system 305 can be coupled to the host device 310 via an interface 315, which can be a CXL interface. The memory system 305 can include a device memory 320, a cache 325, a controller 330, and a processing unit 335, and the host device 310 can include a cache 340. In some instances, system 300 can be configured to use one or more metadata fields (e.g., Meta0 - state) to track the coherence state of data. Additionally, using Meta0 - state to track the bias state on a per - cache - line basis can improve the overall performance of the memory system 305 while maintaining a relatively simple programming model.

[0076] The memory system 305 can be a CXL device. The device memory 320 can be accessed by one or more accelerators, which can include the processing unit 335 or be associated with the processing unit 335. Figure 3The processing unit 335 and the controller 330 shown in [description] can be a single logic component formed on the same field programmable gate array (FPGA) or application specific integrated circuit (ASIC). However, in some instances, the controller 330 and the processing unit 335 can be individual components. For example, the processing unit 335 can be associated with a graphics processing unit (GPU) or a general purpose graphics processing unit (GPGPU) of the memory system 305. The processing unit 335 can be configured to transmit signaling and / or commands for accessing the device memory 320 to the controller 330. As described herein, the controller 330 can access the device memory 320 independent of the host device 310 in the device bias state, while the controller 330 can access the device memory 320 via the host device 310 in the host bias state.

[0077] In some instances, the host device 310 can include a cache 340. The cache 340 can include a set of pages, and each of the pages can include 4 kB of data. Additionally, each page can include one or more blocks, which can be referred to as cache lines, and each cache line can include 64 B of data. Although the size of each page and cache line is only intended for exemplary purposes and each page and cache line can be configured to store a different amount of data, the memory system 305 can be configured to use Meta0 - states on a per - cache - line basis rather than a bias table maintained on a per - page basis to track bias states. That is, using Meta0 - states to track device bias can allow for tracking bias states with greater granularity.

[0078] The device memory 320 can be configured to store data that can be accessed by the processing unit 335 (e.g., via the controller 330) and the host device 310. Because the data can be accessed by both the processing unit 335 and the host device 310 (e.g., the data is shared), it is desirable to track the coherence of the data. That is, it is desirable for both the processing unit 335 and the host device 310 to know whether the data in the cache 340 is coherent with the corresponding data (for the same address) in the device memory 320. To track cache coherence, three states of metadata tracking cache coherence can be maintained and used. For example, the first state can be associated with an "invalid" state - e.g., the cache 340 of the host device 310 does not have a cacheable copy of the data. The second state can be associated with an "any" state - e.g., the cache 340 of the host device 310 can have a shared, exclusive, or modified copy of the data. The third state can be associated with a "shared" state - e.g., the cache 340 of the host device 310 can have at most a shared copy of the data. As the coherence state of the data changes, the updated metadata associated with the coherence state can be stored into the device memory 320.

[0079] In some instances, data stored to the device memory 320 may be accessed according to a device bias mode or a host bias mode. The host bias mode may prioritize coherent access from the host device 310 to the device memory 320. The host bias mode may be used during work submission (when data is being written from the host device 310 to the device memory 320) and during work completion (when data is being read by the host device 310 from the device memory 320). In the host bias mode, the device memory 320 may appear to the memory system (or to the processing unit 335) as if it were a memory attached to the host device 310. If the processing unit 335 needs to access the device memory 320 while operating in the host bias mode, the access operation is handled by first transmitting a request (e.g., a command; a signal) to the host device 310 through the controller 330.

[0080] Conversely, in the device bias mode, the processing unit 335 may directly access the device memory 320. That is, the processing unit 335 may access the device memory 320 without any interaction from the host device 310. Thus, if the processing unit 335 needs to access the device memory 320 while operating in the device bias mode, the access operation is handled by directly accessing the device memory 320 through the controller 330.

[0081] The CXL specification provides an optional 2-bit Meta0 field that may be associated with the device attachment medium. In accordance with various aspects described herein, the 2-bit Meta0 field may be used to convey the coherence state of data (e.g., data associated with the size of a cache line of the cache 340), and the coherence state may be used to determine the bias state of the associated data. In some instances, the Meta0 field may be configured to store a first value (e.g., a first bit value) associated with an “invalid” coherence state. When the Meta0 field contains the first value, the data associated with the Meta0 field may be accessed according to the device bias mode. Additionally or alternatively, the Meta0 field may be configured to store a second value (e.g., a second bit value) and a third value (e.g., a third bit value) associated with “shared” and “any” states. When the Meta0 field contains the second value or the third value, the data associated with the Meta0 field may be accessed according to the host bias mode.

[0082] In some instances, the corresponding Meta0 field may be associated with each row of data stored in the device memory 320 and may thus be determined when the processing unit 335 needs to access the device memory 320. For example, the processing unit 335 may transmit an access request (e.g., a command; a signal) to the controller 330, and the controller may determine the Meta0 value of the associated data. Depending on the Meta0 value (e.g., the coherence state), the controller 330 may be able to directly access the data row (e.g., according to the device bias mode), or may transmit a request (e.g., a command; a signal) to the host device 310 for resolving the coherence associated with the data (e.g., according to the host bias mode).

[0083] The host device 310 may periodically update the coherence state of the data and / or the Meta0 field associated with the data. For example, if the host device 310 performs any operation that affects the coherence of the data, the host device 310 may transmit the change to the memory system 305. In some instances, the host device 310 may transmit the updated coherence state to the memory system 305 (e.g., explicitly or implicitly from an access command), and the controller 330 may use the updated coherence state to update the Meta0 field of the associated data stored in the device memory 320 or the cache 325. In other instances, the host device 310 may transmit the updated Meta0 field to the memory system 305, and the controller 330 may update the Meta0 field of the associated data stored in the device memory 320 or the cache 325.

[0084] Additionally or alternatively, the cache 325 can be used to determine whether to access data according to the device bias state or the host bias state. For example, data and the associated Meta0 field can be stored in the cache 325. That is, in some instances, the Meta0 field can be stored only with the cached data rather than the data stored in the device memory 320. When the processing unit 335 needs to access data (e.g., when the processing unit 335 sends a command for the data to the controller 330), the controller 330 can determine whether the data is stored in the cache 325. If the data is stored in the cache (e.g., when there is a cache "hit"), the data can be accessed according to the coherence state indicated by the Meta0 field (e.g., by associating the coherence state with the bias state). In other instances, if the data is not stored in the cache (e.g., when there is a cache "miss"), the controller 330 can assume that the data is associated with the host bias state. Accordingly, when there is a cache "miss", the processing unit 335 can access the device memory 320 via the host device 310. Whether the Meta0 field is stored in the device memory 320 or in the cache 325, tracking the bias state on a per-cache-line basis using the Meta0-state can improve the overall performance of the memory system 305 while maintaining a relatively simple programming model.

[0085] Figure 4 An example of a process flow diagram 400 that illustrates bias control for a memory device in accordance with an example as disclosed herein is shown. The process flow diagram 400 can illustrate the operations of a processing unit 405, a controller 410, a device memory 415, and a cache 420. In some instances, the processing unit 405, the controller 410, the device memory 415, and the cache 420 can be examples of the processing unit 335, the controller 330, the device memory 320, and the cache 325, respectively, of the memory system 305 described Figure 3 above. The process flow diagram 400 can illustrate tracking the bias state on a per-cache-line basis using the Meta0-state, which can improve the overall performance of the memory system 305 while maintaining a relatively simple programming model.

[0086] At 425, the coherence state of a data row can be stored at the device memory 415. In some instances, the coherence states of multiple data rows can be stored. For example, the coherence state of each data row can be stored to the device memory 415. As described herein, the coherence state can correspond to an "invalid", "any", or "shared" state and can be stored in the Meta0 field associated with the corresponding data row. In other instances, at 425, the coherence state of the data can be updated. That is, the coherence states of one or more data rows may have been previously stored to the device memory 415, but due to a change in the coherence state, the stored state can be updated. In either case, the coherence state stored at 425 can be used to determine the bias state associated with the data. Although shown as being stored at the device memory 415, the coherence state can alternatively or additionally be stored at the cache 420, as described below.

[0087] At 430, the processing unit 405 can determine to access a data row. For example, the processing unit 405 can determine to read a data row from the device memory 415 or can determine to write a data row to the device memory 415. For illustrative purposes, the data row can be stored at the device memory 415. However, in some instances, the data row can be stored to the cache 420 (e.g., the data can be cached), and the processing unit 405 or the controller 410 can determine whether the data is stored to the cache 420 or the device memory 415.

[0088] At 435, the processing unit 405 can transmit a signal to the controller 410. The signal can be in response to determining to access a data row (e.g., at 425), and the signal can include a command (e.g., a read command, a write command), a request, or another type of communication. The signal can indicate to the controller 410 the type of access operation and the address of the device memory 415 for the data row (e.g., a memory address).

[0089] At 440, the controller 410 can transmit a signal to the cache 420. The signal can be in response to the signal indicating the type of access operation and the address of the device memory 415 (e.g., at 435), and the signal can include a command (e.g., a read command), a request, or another type of communication. The signal can initiate a read on the cache 420 to determine whether the associated data row is stored to the cache 420.

[0090] At 445, the controller 410 can receive a signal from the cache 420. The signal can be in response to the signal transmitted at 440 and can indicate whether the data row is stored to the cache (e.g., a cache "hit" or a cache "miss"). For illustrative purposes only, the signal can indicate a cache "miss".

[0091] At 450, the controller 410 may transmit signaling to the device memory 415. The signaling may be in response to the signaling indicating a cache "miss", and the signaling may include a command (e.g., a read command), a request, or another type of communication. The signaling may initiate a read on the device memory 415.

[0092] At 455, the controller 410 may receive signaling from the device memory 415. The signaling may be in response to the signaling transmitted at 450, and may include a data row read from the device memory 415. Additionally, the signaling may include a Meta0 state associated with the data row. As described herein, the Meta0 state may indicate a first value corresponding to an "invalid" coherence state, a second value corresponding to a "shared" coherence state, or a third value corresponding to an "any" state. Alternatively, the Meta0 state may not be stored in the device memory 415, and the controller 410 may present a Meta0 state of "any" or "shared" after a cache miss.

[0093] At 460, the controller 410 may determine the bias state of the data row read from the device memory 415. The controller 410 may determine the bias state of the data row in response to the signaling received by the controller 410 (e.g., at 455). For example, the signaling may have indicated that the Meta0 field contains a first value corresponding to an "invalid" coherence state. Thus, the controller 410 may determine the device bias state of the data row stored to the first memory address, and may complete the processing of the access operation without any interaction from the host device.

[0094] In other instances, the signaling (e.g., at 435) may indicate a write command at a second memory address of the device memory 415. In these instances, the controller 410 may determine the bias state for writing data to the second memory address based on the Meta0 field associated with the data row. For example, the controller 410 may transmit signaling to the device memory 415 to read the data row corresponding to the second memory address from the device memory 415. In response, the controller 410 may receive signaling indicating the Meta0 state of the data row. If the Meta0 state corresponds to an "invalid" coherence state, the controller 410 may operate according to the device bias. In this instance, the controller 410 may write data to the second memory address of the device memory 415 without any interaction from the host device.

[0095] In other instances, instead of transmitting signaling to cache 420 and / or device memory 415, controller 410 may instead maintain a table for tracking the Meta0 state of one or more data lines. For example, for both read operations and write operations, controller 410 may track the Meta0 value on a per-line basis such that when the processing unit determines to access data (e.g., at 430), the controller can determine the Meta0 state based on the table. Accordingly, based on the Meta0 state, controller 410 may operate in a device bias mode or a host bias mode.

[0096] At 465, data may be transferred to processing unit 405. In some instances, data may be transferred in response to determining the bias state of the data (e.g., at 450). In some instances, data may be transferred directly to processing unit 405, while in other instances, data may be transferred to controller 410 and controller 410 may transfer the data to processing unit 405.

[0097] At 470, processing unit 405 may determine to access a data line (e.g., another data line). For example, processing unit 405 may determine to read a data line stored in cache 420 (e.g., a cached data line). For illustrative purposes, the data line may be stored at cache 420. However, in some instances, the data line may not be stored at cache 420 (e.g., the data may not be cached), resulting in a cache "miss". When a cache "miss" occurs, controller 410 may determine to access the data according to the host bias mode.

[0098] At 475, processing unit 405 may transmit signaling to controller 410. The signaling may be in response to determining to access a data line (e.g., at 465), and the signaling may include a command (e.g., a read command, a write command), a request, or another type of communication. The signaling may indicate to controller 410 the type of access operation and the address of device memory 415 (e.g., a memory address).

[0099] At 480, controller 410 may transmit signaling to cache 420. The signaling may be in response to the signaling indicating the type of access operation and the address of device memory 415 (e.g., at 475), and the signaling may include a command (e.g., a read command), a request, or another type of communication. The signaling may initiate a read on cache 420 to determine whether the associated data line is stored at cache 420.

[0100] At 485, the controller 410 may receive signaling from the cache 420. The signaling may be in response to the signaling transmitted at 440 and may indicate whether a data line is stored in the cache (e.g., a cache "hit" or a cache "miss"). For illustrative purposes only, the signaling may indicate a cache "hit". Accordingly, the signaling may include the data line and an associated Meta0 state, where the associated Meta0 state may indicate a first value corresponding to an "invalid" coherence state, a second value corresponding to a "shared" coherence state, or a third value corresponding to an "any" state.

[0101] At 490, the controller 410 may determine the bias state of the data line read from the cache 420. The controller 410 may determine the bias state of the data line in response to the signaling received by the controller 410 (e.g., at 485). For example, the signaling may have indicated that the Meta0 field contains a first value corresponding to an "invalid" coherence state. Accordingly, the controller 410 may determine the device bias state of the data line stored in the cache and may complete the processing of the access operation without any interaction from the host device.

[0102] At 495, data may be transferred to the processing unit 405. In some instances, the data may be transferred in response to signaling transmitted from the controller 410 to the processing unit (e.g., at 475). In some instances, the data may be transferred directly to the processing unit 405, while in other instances, the data may be transferred to the controller 410 and the controller 410 may transfer the data to the processing unit 405. Regardless of whether the Meta0 field is stored in the device memory 415, stored in the cache 420, or tracked by the controller 410, tracking the bias state on a per-cache-line basis using the Meta0-state may improve the overall performance of the memory system while maintaining a relatively simple programming model.

[0103] Figure 5 An example of a process flow diagram 500 that supports bias control of a memory device in accordance with an example disclosed herein is shown. The process flow diagram 500 may illustrate the operation of a memory system 501 and a host device 525 that may be examples of the memory system 305 and the host device 310 described, respectively, as Figure 3 described. The memory system 501 may include a processing unit 505, a controller 510, a device memory 515, and a cache 520. The process flow diagram 500 may illustrate tracking the bias state on a per-cache-line basis using the Meta0-state, which may improve the overall performance of the memory system 501 while maintaining a relatively simple programming model.

[0104] At 530, the coherence state of a data row can be stored at the device memory 515. In some instances, the coherence states of multiple data can be stored. For example, the coherence state of each data row can be stored to the device memory 515. As described herein, the coherence state can correspond to an "invalid", "any", or "shared" state and can be stored in the Meta0 field associated with the corresponding data row. In other instances, at 530, the coherence state of the data can be updated. That is, the coherence states of one or more data rows may have been previously stored to the device memory 415, but due to a change in the coherence state, the stored state can be updated. In either case, the coherence state stored at 530 can be used to determine the bias state associated with the data.

[0105] At 535, the processing unit 505 can determine to access a data row. For example, the processing unit 505 can determine to read a data row from the device memory 515 or can determine to write a data row to the device memory 515. For illustrative purposes, the data row can be stored at the device memory 515. However, in some instances, the data row can be stored to the cache 520 (e.g., the data can be cached), and the processing unit 505 or the controller 510 can determine whether the data is stored to the cache 520 or the device memory 515.

[0106] At 540, the processing unit 505 can transmit a signal to the controller 510. The signal can be in response to determining to access a data row (e.g., at 535), and the signal can include a command (e.g., a read command, a write command), a request, or another type of communication. The signal can indicate to the controller 510 the type of access operation and the address of the device memory 515 (e.g., the memory address).

[0107] After 540, the controller 510 can transmit a signal to the cache 520, which is not shown in Figure 5 The signal can be in response to the signal indicating the type of access operation and the address of the device memory 515 (e.g., at 540), and the signal can include a command (e.g., a read command), a request, or another type of communication. The signal can initiate a read on the cache 520 to determine whether the associated data row is stored to the cache 520.

[0108] After transmitting the signal to the cache 520, the controller 510 can receive a signal from the cache 520, which is not shown in Figure 5 The signal can indicate whether the data row is stored to the cache (e.g., cache "hit" or cache "miss"). For illustrative purposes only, this signal indicates a cache "miss". In some instances, after a cache "miss", then the controller 510 can appear to operate in the host bias mode.

[0109] After the controller 510 receives the signaling, the controller 510 may transmit the signaling to the device memory 515, which is not shown in Figure 5 . The signaling may be in response to the signaling indicating a cache "miss", and the signaling may include a command (e.g., a read command), a request, or another type of communication. The signaling may initiate a read on the device memory 515.

[0110] After transmitting the signaling to the device memory 515, the controller 510 may receive the signaling from the device memory 515, which is not shown in Figure 5 . The signaling may include a data row read from the device memory 515. In addition, the signaling may include a Meta0 state associated with the data row. As described herein, the Meta0 state may indicate a first value corresponding to an "invalid" coherence state, a second value corresponding to a "shared" coherence state, or a third value corresponding to an "any" state.

[0111] At 545, the controller 510 may determine the bias state of the data row stored in the device memory 515 in response to receiving the data row and the associated Meta0 state. The controller 510 may determine the bias state based on the Meta0 state. For example, the Meta0 field may indicate a first value corresponding to an "invalid" coherence state and generate a device bias for the data row. Additionally or alternatively, the Meta0 field may indicate a second value corresponding to a "shared" state or a third value corresponding to an "any" state, both of which generate a host bias for the data row. For illustrative purposes only, the controller 510 may determine the host bias state of the data row stored at the first memory address.

[0112] At 550, the controller 510 may transmit the signaling to the host device 525. The signaling may be in response to determining access to the device memory 415 according to the host bias mode (e.g., at 545), and the signaling may include a command (e.g., a read command), a request, or another type of communication. For example, the signaling may include a request for the host device 525 to resolve the coherence of the data row, or may include a request for the host device 525 to grant access rights to the data row to the controller 510.

[0113] At 555, the host device 525 may transmit the signaling to the controller 510 (or to another component of the memory system 501). The signaling may be in response to the signaling transmitted to the host device 525 (e.g., at 550), and the signaling may include a command (e.g., a second command, a read command), a request, or another type of communication. For example, the second command may resolve the coherence of the data by granting direct access rights to the data row to the controller 510.

[0114] In other instances, a signaling (e.g., at 540) may indicate a write command at a second memory address of the device memory 515. In such instances, the controller 510 may determine a bias state for writing data to the second memory address based on the Meta0 field associated with the data row. For example, the controller 510 may transmit a signaling to the device memory 515 to read the data row corresponding to the second memory address from the device memory 515. In response, the controller 510 may receive a signaling indicating the Meta0 state of the data row. If the Meta0 state corresponds to an “invalid” coherence state, the controller 510 may operate according to the device bias operation. In this instance, the controller 510 may write data to the second memory address of the device memory 515 without any interaction from the host device.

[0115] In other instances, the controller 510 may not transmit a signaling to the cache 520 and / or the device memory 515, but instead may maintain a table for tracking the Meta0 state of one or more data rows. For example, for both read operations and write operations, the controller 510 may track the Meta0 value on a per-row basis such that when the processing unit determines to access data (e.g., at 530), the controller may determine the Meta0 state based on the table. Accordingly, based on the Meta0 state, the controller 410 may operate in the device bias mode or the host bias mode.

[0116] At 560, data may be transferred to the processing unit 505. In some instances, the data may be transferred in response to a signaling (e.g., at 555) transmitted from the host device 525 to the controller 510. In some instances, the data may be transferred directly to the processing unit 505, while in other instances, the data may be transferred to the controller 510 and the controller 510 may transfer the data to the processing unit 505.

[0117] At 565, the processing unit 505 may determine to access a data row (e.g., another data row). For example, the processing unit 505 may determine to read a data row (e.g., a cached data row) that may be stored in the cache 520. For illustrative purposes, the data row may not be stored at the cache 520. However, in some instances, the data row may be stored in the cache 520 (e.g., the data may be cached), resulting in a cache “hit”. When a cache “hit” occurs, the controller 510 may determine to access the data according to the coherence state (e.g., the Meta0 field) associated with the data row.

[0118] At 570, processing unit 505 may transmit signaling to controller 510. The signaling may be in response to determining access to a data row (e.g., at 565), and the signaling may include a command (e.g., read command, write command), a request, or another type of communication. The signaling may indicate to controller 510 the type of access operation and the address of device memory 515 (e.g., a memory address).

[0119] After 570, controller 510 may transmit signaling to cache 520, which is not shown in Figure 5 The signaling may be in response to the signaling indicating the type of access operation and the address of device memory 515 (e.g., at 540), and the signaling may include a command (e.g., read command), a request, or another type of communication. The signaling may initiate a read on cache 520 to determine whether the associated data row is stored in cache 520.

[0120] After transmitting the signaling to cache 520, controller 510 may receive signaling from cache 520, which is not shown in Figure 5 The signaling may indicate whether the data row is stored in the cache (e.g., cache "hit" or cache "miss"). For illustrative purposes only, this signaling indicates a cache "hit". Additionally, the signaling may include the data row read from cache 520, and may include the Meta0 state associated with the data row. As described herein, the Meta0 state may indicate a first value corresponding to an "invalid" coherence state, a second value corresponding to a "shared" coherence state, or a third value corresponding to an "any" state.

[0121] At 575, controller 510 may determine the bias state of the data row stored in device memory 520 in response to receiving the data row and the associated Meta0 state. Controller 510 may determine the bias state based on the Meta0 state. For example, the Meta0 field may indicate a first value corresponding to an "invalid" coherence state and result in a device bias for the data row. Additionally or alternatively, the Meta0 field may indicate a second value corresponding to a "shared" state or a third value corresponding to an "any" state, both of which result in a host bias for the data row. For illustrative purposes only, controller 510 may determine the host bias state of the data row stored in cache 520.

[0122] At 580, the controller 510 may transmit signaling to the host device 525. The signaling may be in response to determining access to the cache 520 according to a host bias mode (e.g., at 575), and the signaling may include a command (e.g., a read command), a request, or another type of communication. For example, the signaling may include a request for the host device 525 to resolve the coherence of a data line, or may include a request for the host device 525 to grant access rights to a data line to the controller 510.

[0123] At 585, the host device 525 may transmit signaling to the controller 510 (or to another component of the memory system 501). The signaling may be in response to the signaling transmitted to the host device 525 (e.g., at 580), and the signaling may include a command (e.g., a second command, a read command), a request, or another type of communication. For example, the second command may resolve the coherence of data by granting direct access rights to a data line to the controller 510.

[0124] At 590, data may be transferred to the processing unit 505. In some instances, the data may be transferred directly to the processing unit 505, while in other instances, the data may be transferred to the controller 510, and the controller 510 may transfer the data to the processing unit 505. Regardless of whether the Meta0 field is stored in the device memory 515, stored in the cache 520, or tracked by the controller 510, tracking the bias state on a per-cache-line basis using the Meta0-state can improve the overall performance of the memory system while maintaining a relatively simple programming model.

[0125] Figure 6 FIG. 600 is a block diagram showing a memory controller 620 that supports bias control of a memory device according to an example as disclosed herein. The memory controller 620 may be an example of aspects of a memory controller as described with reference to Figures 1 to 5 The memory controller 620 or its various components may be examples of components for performing aspects of bias control of a memory device as described herein. For example, the memory controller 620 may include a coherence component 625, a memory access component 630, a transmit component 635, a receive component 640, a determination component 645, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0126] The coherence component 625 may be configured to or otherwise support components for the coherence state of a data set stored in a memory relative to a cache store of a host device. In some instances, the coherence component 625 may be configured to or otherwise support components for the coherence state of a data set stored in a memory relative to a cache store of a host device.

[0127] The memory access component 630 may be configured to or otherwise support a component that accesses a memory according to a bias state of a data set determined at least in part based on a stored coherence state of the data set for an access operation that at least in part based on an identification executes a command to access the data set stored in the memory, where the bias state is associated with a control of access to the data set by a controller associated with the memory.

[0128] In some instances, the memory access component 630 may be configured to or otherwise support a component that accesses the memory at least in part based on the bias state independently of a host device. In some instances, the command includes a read command, and the memory access component 630 may be configured to or otherwise support a component that accesses a data set stored in a cache based at least in part on determining that the data set is stored in the cache associated with the memory.

[0129] In some instances, the memory access component 630 may be configured to or otherwise support a component that accesses the memory according to a bias state of a data set determined at least in part based on a stored coherence state of the data set for an access operation that at least in part based on an identification executes a command to access the data set stored in the memory, where the bias state is associated with a control of access to the data set by a host device. In some instances, the command includes a read command, and the memory access component 630 may be configured to or otherwise support a component that accesses the memory for the data set at least in part based on receiving a second command from the host device.

[0130] In some instances, the coherence state of the data set is stored independently of the command, and the transmit component 635 may be configured to or otherwise support a component that transmits an indication of an access operation to be performed on the data set to the host device at least in part based on determining that the command is processed according to the bias state. In some instances, the transmit component 635 may be configured to or otherwise support a component that transmits a data set received from the host device to the memory at least in part based on receiving the data set from the host device.

[0131] In some instances, the coherence state of the data set is stored independently of the command, and the receive component 640 may be configured to or otherwise support a component that receives from the host device a second command for indicating direct access to the data set for the access operation at least in part based on transmitting an indication of the access operation.

[0132] In some instances, the command includes a read command, and the determination component 645 may be configured to or otherwise support a component that determines that the data set is stored in the cache associated with the memory.

[0133] In some instances, the memory is configured to store a first value associated with a first coherent state of a data set, a second value associated with a second coherent state of the data set, or a third value associated with a third coherent state of the data set. In some instances, the first value indicates that the data set is incoherent. In some instances, the second value and the third value indicate that the data set is coherent, where the controller is configured to process the command based at least in part on the memory storing the first value of the data set according to a bias state.

[0134] In some instances, the data set is associated with a first quantity of data. In some instances, a cache line of a host device coupled to the memory is configured to store the first quantity of data. In some instances, the bias state corresponds to a first bias state. In some instances, a second bias state is associated with control of access to the data set by the host device. In some instances, the memory is configured to store a first value associated with a first coherent state of a data set, a second value associated with a second coherent state of the data set, or a third value associated with a third coherent state of the data set.

[0135] In some instances, the first value indicates that an invalid version of the data set is stored in a cache of the host device. In some instances, the second value indicates that a shared version or an exclusive version of the data set is stored in a cache of the host device. In some instances, the third value indicates that a shared version of the data set is stored in a cache of the host device. In some instances, the second value and the third value indicate that the data set is coherent. In some instances, the command is processed based at least in part on the memory storing the second value or the third value of the data set according to a bias state.

[0136] In some instances, the data set is associated with a first quantity of data. In some instances, a cache line of a host device coupled to the memory is configured to store the first quantity of data. In some instances, the first bias state is associated with control of access to the data set by the controller. In some instances, the bias state corresponds to a second bias state.

[0137] Figure 7 The figure shows a flow chart of a method 700 for supporting bias control of a memory device in accordance with an example as disclosed herein. Operations of method 700 may be implemented by a memory controller or components thereof as described herein. For example, operations of method 700 may be performed by a memory controller as described with reference to Figures 1 to 5 and 6. In some instances, the memory controller may execute an instruction set to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory controller may perform aspects of the described functions using dedicated hardware.

[0138] At 705, the method may include storing a coherence state of a data set stored in a memory relative to a cache store of a host device. The operations of 705 may be performed according to the examples disclosed herein. In some examples, aspects of the operations of 705 may be performed by a coherence component 625 as described with reference to Figure 6 The coherence component 625 described.

[0139] At 710, the method may include accessing the memory at least in part based on a bias state of the data set determined at least in part based on the stored coherence state of the data set, based at least in part on identifying a command to perform an access operation on the data set stored in the memory, where the bias state is associated with control of access to the data set by a controller associated with the memory. The operations of 710 may be performed according to the examples disclosed herein. In some examples, aspects of the operations of 710 may be performed by a memory access component 630 as described with reference to Figure 6 The memory access component 630 described.

[0140] In some examples, a device as described herein may perform one or more methods, such as method 700. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: storing a coherence state of a data set stored in a memory relative to a cache store of a host device, and accessing the memory at least in part based on a bias state of the data set determined at least in part based on the stored coherence state of the data set, based at least in part on identifying a command to perform an access operation on the data set stored in the memory, where the bias state is associated with control of access to the data set by a controller associated with the memory.

[0141] Some examples of method 700 and the device described herein may further include operations, features, circuitry, logic, components, or instructions for accessing the memory at least in part independently of the host device based on the bias state.

[0142] In some examples of method 700 and the device described herein, the command includes a read command, and the method, device, and non-transitory computer-readable medium may include additional operations, features, circuitry, logic, components, or instructions for: determining that the data set may be stored in a cache associated with the memory, and accessing the data set stored in the cache at least in part based on determining that the data set may be stored in a cache associated with the memory.

[0143] In some examples of method 700 and the device described herein, the memory may be configured to store a first value that may be associated with a first coherence state of a data set, a second value that may be associated with a second coherence state of the data set, or a third value that may be associated with a third coherence state of the data set.

[0144] In some examples of the method 700 and apparatus described herein, a first value indicates that a data set may be incoherent, and second and third values indicate that the data set may be coherent, where the controller may be configured to process the command based at least in part on the first value of the memory storing the data set according to a bias state.

[0145] In some examples of the method 700 and apparatus described herein, a data set may be associated with a first quantity of data, and a cache line of a host device coupled to the memory may be configured to store the first quantity of data.

[0146] In some examples of the method 700 and apparatus described herein, the bias state corresponds to a first bias state, and a second bias state may be associated with control of access to the data set by the host device.

[0147] Figure 8 A flowchart illustrating a method 800 for supporting bias control of a memory device in accordance with examples disclosed herein is shown. Operations of method 800 may be implemented by a memory controller or components thereof as described herein. For example, operations of method 800 may be performed by a memory controller as described with reference to Figures 1 to 5 and 6. In some examples, the memory controller may execute an instruction set to control functional elements of the device to perform the described functions. Additionally or alternatively, the memory controller may perform aspects of the described functions using dedicated hardware.

[0148] At 805, the method may include storing a coherence state of a data set stored in the memory relative to a cache store of the host device. The operation of 805 may be performed in accordance with examples disclosed herein. In some examples, aspects of the operation of 805 may be performed by a coherence component 625 as described with reference to Figure 6 and described.

[0149] At 810, the method may include accessing the memory based at least in part on a bias state of the data set determined at least in part based on a stored coherence state of the data set in response to identifying a command to perform an access operation on the data set stored in the memory, where the bias state is associated with control of access to the data set by the host device. The operation of 810 may be performed in accordance with examples disclosed herein. In some examples, aspects of the operation of 810 may be performed by a memory access component 630 as described with reference to Figure 6 and described.

[0150] In some instances, a device as described herein may perform one or more methods, such as method 800. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: storing a coherent state of a data set stored in a memory relative to a cache store of a host device, and accessing the memory based at least in part on a bias state of the data set determined at least in part based on the stored coherent state of the data set in accordance with a command identifying an access operation to the data set stored in the memory, wherein the bias state is associated with control of access to the data set by the host device.

[0151] In some instances of method 800 and the device described herein, the coherent state of the data set may be stored independently of the command, and the method, device, and non-transitory computer-readable medium may include additional operations, features, circuitry, logic, components, or instructions for: transmitting an indication of an access operation to be performed on the data set to the host device based at least in part on determining to process the command in accordance with the bias state, and receiving from the host device a second command for indicating direct access to the data set for the access operation based at least in part on transmitting the indication of the access operation.

[0152] In some instances of method 800 and the device described herein, the command includes a read command, and the method, device, and non-transitory computer-readable medium may include additional operations, features, circuitry, logic, components, or instructions for: accessing the memory for the data set based at least in part on receiving the second command from the host device.

[0153] Some instances of method 800 and the device described herein may further include operations, features, circuitry, logic, components, or instructions for: transmitting a data set received from the host device to the memory based at least in part on receiving the data set from the host device.

[0154] In some instances of method 800 and the device described herein, the memory may be configured to store a first value associated with a first coherent state of the data set, a second value associated with a second coherent state of the data set, or a third value associated with a third coherent state of the data set.

[0155] In some instances of method 800 and the device described herein, the first value indicates that an invalid version of the data set may be stored in a cache of the host device, the second value indicates that a shared or exclusive version of the data set may be stored in a cache of the host device, and the third value indicates that a shared version of the data set may be stored in a cache of the host device.

[0156] In some examples of the method 800 and apparatus described herein, the second and third values indicate that the data set may be coherent, and the command may be processed based on the bias state at least in part according to the second or third value of the memory storing the data set.

[0157] In some examples of the method 800 and apparatus described herein, the data set may be associated with a first quantity of data, and a cache line of the host device coupled to the memory may be configured to store the first quantity of data.

[0158] In some examples of the method 800 and apparatus described herein, the first bias state may be associated with the control of access to the data set by the controller, and the bias state corresponds to the second bias state.

[0159] Note that the method descriptions above describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Additionally, portions from two or more of the methods may be combined.

[0160] Any of a variety of different technologies and techniques may be used to represent the information and signals described herein. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some of the figures may show a signal as a single signal; however, the signal may represent a bus of signals, where the bus may have a variety of bit widths.

[0161] The terms "electrically connected," "electrically contacting," "connected," and "coupled" may refer to a relationship between components that supports the flow of signals between the components. Components are considered to be electrically connected (or electrically contacting or connected or coupled) to each other if there is any conductive path between the components that can support the flow of signals between the components at any time. At any given time, based on the operation of the device containing the connected components, the conductive path between components that are electrically connected (or electrically contacting or connected or coupled) to each other may be an open circuit or a closed circuit. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some examples, the flow of signals between the connected components may be interrupted for a period of time using, for example, one or more intermediate components such as switches or transistors.

[0162] The term "couple" refers to the condition of moving from an open-circuit relationship between components to a closed-circuit relationship, where in the open-circuit relationship, a signal cannot currently be transmitted between components via a conductive path, and in the closed-circuit relationship, a signal can be transmitted between components via a conductive path. If a component, such as a controller, couples other components together, then the component initiates a change that allows a signal to flow between the other components via a conductive path where signal flow was previously not permitted.

[0163] The term "isolate" refers to the relationship between components where a signal cannot currently flow between the components. If there is an open circuit between components, the components are isolated from each other. For example, the components separated by a switch positioned between two components are isolated from each other when the switch is open. If a controller isolates two components, the controller effects the following change: preventing a signal from flowing between the components using a conductive path where signal flow was previously permitted.

[0164] The terms "if", "when", "based on", or "at least partially based on" are used interchangeably. In some instances, if the terms "if", "when", "based on", or "at least partially based on" are used to describe a conditional action, a conditional process, or the connection between parts of a process, then the terms are interchangeable.

[0165] The term "responsive to" can mean that a condition or action occurs at least in part (if not completely) as a result of a previous condition or action. For example, a first condition or action can be executed, and as a result of the previous condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occur after the first condition or action), a second condition or action can occur at least in part.

[0166] Additionally, the terms "directly responsive to" or "directly respond to" can mean that a condition or action occurs as a direct result of a previous condition or action. In some instances, a first condition or action can be executed, and a second condition or action can occur directly as a result of the previous condition or action occurring, regardless of whether other conditions or actions occur. In some instances, a first condition or action can be executed, and a second condition or action can occur directly as a result of the previous condition or action occurring such that no other intermediate conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Unless otherwise specified, any condition or action described herein as being executed "based on", "at least partially based on", or "responsive to" some other step, action, event, or condition can alternatively or additionally (e.g., in an alternative instance) be executed "directly responsive to" or "directly respond to" this other condition or action.

[0167] The devices (including memory arrays) discussed herein may be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloy, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In some other instances, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or a sub-region of the substrate can be controlled by doping with various chemicals including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed by ion implantation or by any other doping means during the initial formation or growth of the substrate.

[0168] The switching components or transistors discussed herein may represent field effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals may be connected to other electronic components via a conductive material such as metal. The source and the drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and the drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive voltage or a negative voltage to an n-type FET or a p-type FET, respectively, can render the channel conductive. If a voltage greater than or equal to the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned on" or "activated". If a voltage less than the threshold voltage of the transistor is applied to the transistor gate, the transistor may be "turned off" or "deactivated".

[0169] The description set forth herein in conjunction with the drawings describes example configurations and does not represent all examples that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and does not mean "preferred over" or "better than" other examples. The detailed description includes specific details to provide an understanding of the described techniques. However, the techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0170] In the drawings, similar components or features may have the same reference label. Additionally, each of the same type of components may be distinguished by following the reference label by a dash and a second label that differentiates among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components that have the same first reference label, regardless of the second reference label.

[0171] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of the present disclosure and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwiring, or any combination thereof. The features implementing the functions may also be physically located at various positions, including being distributed such that portions of the functions are implemented at different physical locations.

[0172] For example, various illustrative blocks and components described in connection with the present disclosure may be implemented or performed using a general-purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0173] As used herein, including in the claims, the "or" used in a list of items (e.g., a list of items that begins with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C, for example, means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0174] A computer-readable medium includes both a non-transitory computer storage medium and a communication medium, where the communication medium includes any medium that facilitates transfer of a computer program from one place to another. The non-transitory storage medium can be any available medium that can be accessed by a general or special purpose computer. By way of example, and not limitation, the non-transitory computer-readable medium can include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD) ROM or other optical disc storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store the desired program code components in the form of instructions or data structures and that can be accessed by a general or special purpose computer or a general or special purpose processor.

[0175] Also, any connection is properly termed a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of the medium. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc, where disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable medium.

[0176] The description provided herein enables a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system, comprising: A memory; And A controller coupled to the memory, wherein the controller is configured to: Receive a first signaling, the first signaling including an indication of a type of access operation and an address of the memory associated with the data; Receive a second signaling, the second signaling including an indication of a coherence state of the data, wherein the coherence state indicates whether a copy of the data is stored at a host device; and Determine a bias state of the data at least in part based on the coherence state, wherein the bias state indicates whether to access the host device by the controller as part of the access operation.

2. The system according to claim 1, wherein the controller is further configured to: Access the data independent of the host device at least in part based on the bias state.

3. The system according to claim 1, wherein the controller is further configured to: Receive the data from the memory at least in part based on the bias state; and Transmit the data to a processing unit at least in part based on receiving the data from the memory.

4. The system according to claim 1, wherein the memory is configured to: Transmit the data to a processing unit at least in part based on the bias state of the data.

5. The system according to claim 1, wherein the memory is configured to: Store a plurality of coherence states, each coherence state corresponding to respective data, wherein the plurality of coherence states includes the coherence state of the data.

6. The system according to claim 1, further comprising: A cache coupled to the controller, wherein the cache is configured to: Store a plurality of coherence states, each coherence state corresponding to respective data, wherein the plurality of coherence states includes the coherence state of the data.

7. The system according to claim 1, further comprising: A processing unit coupled to the controller, wherein the processing unit is configured to: Determine to access the data at least in part based on the type of the access operation indicated by the first signaling.

8. The system according to claim 1, wherein the controller is further configured to: Transmit a third signaling to the cache at least in part based on the indication of the type of the access operation, the third signaling including a first access command; and Receive a fourth signaling from the cache at least in part based on transmitting the third signaling to the cache, the fourth signaling including an indication of whether the data is stored in the cache.

9. The system according to claim 8, wherein the controller is further configured to: Transmit a fifth signaling to the memory at least in part based on the indication of whether the data is stored in the cache, the fifth signaling including a second access command for accessing the memory.

10. The system according to claim 1, wherein the second signaling is received from the memory at least in part based on the data being stored in the memory.

11. The system according to claim 1, wherein the second signaling is received from the cache at least partially based on the data being stored in the cache.

12. The system according to claim 11, further comprising: a processing unit coupled to the cache, wherein the cache is further configured to: transfer the data to the processing unit at least partially based on the bias state of the data.

13. A system comprising: a memory; and a controller coupled to the memory, wherein the controller is configured to: receive a first signaling that includes an indication of a type of access operation and an address of the memory associated with the data; receive a second signaling that includes an indication of a coherence state of the data, wherein the coherence state indicates whether a copy of the data is stored at a host device; determine a bias state of the data at least partially based on the coherence state, wherein the bias state indicates whether the controller accesses the host device as part of the access operation; and transmit a third signaling to the host device at least partially based on determining the bias state of the data.

14. The system according to claim 13, wherein the controller is further configured to: receive a fourth signaling from the host device at least partially based on transmitting the third signaling to the host device, wherein the fourth signaling grants access rights to the data.

15. The system according to claim 14, wherein the memory is configured to: transfer the data to a processing unit at least partially based on receiving the fourth signaling that grants access rights to the data.

16. The system according to claim 13, wherein the controller is further configured to: receive a fifth signaling that includes a second type of a second access operation and a second indication of a second address of the memory associated with second data; transmit a sixth signaling to a cache to determine whether the second data is stored in the cache; receive a seventh signaling from the cache, the seventh signaling including an indication of whether the second data is stored in the cache and an indication of a coherence state of the second data; and determine a bias state of the second data at least partially based on the coherence state of the second data, wherein the bias state indicates whether the controller accesses the host device as part of the second access operation.

17. The system according to claim 16, wherein the controller is further configured to: transmit an eighth signaling to the host device at least partially based on determining the bias state of the second data; and receive a ninth signaling from the host device at least partially based on transmitting the eighth signaling, wherein the ninth signaling grants access rights to the second data.

18. The system according to claim 17, wherein the memory is configured to: Transmit the second data to the processing unit at least in part based on the ninth signaling that grants access rights to the second data.

19. The system according to claim 13, wherein determining the bias state of the data further comprises determining that the bias state is a host bias state and transmitting the third signaling to the host device at least in part based on the bias state being the host bias state.

20. A non-transitory computer-readable medium storing code, comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to perform the following operations: Receive a first signaling, the first signaling including an indication of a type of access operation and an indication of the memory address associated with the data; Receive a second signaling, the second signaling including an indication of a coherence state of the data, wherein the coherence state indicates whether a copy of the data is stored at the host device; and Determine a bias state of the data at least in part based on the coherence state, wherein the bias state indicates whether to control access to the host device as part of the access operation.

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