Interrupt program execution method for memory test and memory detection system

Abstract

The invention relates to an interrupt program execution method for memory testing and a memory detection system.The method comprises the steps that detection statements in a detection program are executed in sequence, a plurality of detection signals are configured based on the detection statements, and the detection signals are used for being input into a tested memory to conduct memory testing; when a preset target detection statement is executed and the plurality of detection signals are correspondingly configured, determining whether at least one target detection signal meets a preset judgment condition or not, the target detection signal being pre-selected from the plurality of detection signals; under the condition that the judgment condition is met, the detection program jumps to the interrupt program and is executed, and the interrupt signal input into the detected memory is generated based on the interrupt program, so that the alternate operation of the detection task and the refreshing task of the memory is flexibly controlled, the influence of different refreshing interval time on the characteristic parameters of the dynamically refreshed memory is reflected, and the reliability of the memory is improved. And the test items of the memory are expanded.

Description

Technical Field

[0001] This application relates to the technical field of storage device testing, and particularly to a method for executing an interrupt program in memory testing and a memory detection system. Background Art

[0002] In the testing of dynamic random access memories such as DDR (Double Data Rate SDRAM), it is necessary to dynamically refresh the memory to store the stored data. In DDR testing, it is necessary to test some characteristic parameters in the internal circuit of DDR by controlling and adjusting the refresh frequency of DDR. In the prior art, a timer is usually used to set the refresh frequency or interval time, and DDR is refreshed based on the set refresh frequency. However, during the DDR testing process, this method cannot flexibly set the refresh interval time according to the execution situation of the test tasks during the testing process, nor can it test the influence of refreshing during the execution of different test tasks on the characteristic parameters of DDR, which limits the testing function of DDR.

[0003] Regarding the problem that the refresh frequency set by a timer in the prior art cannot flexibly set the refresh interval time according to the execution situation of the test tasks during the testing process, no effective solution has been proposed yet. Summary of the Invention

[0004] In this embodiment, a method for executing an interrupt program in memory testing and a memory detection system are provided to solve the problem in the related art that the refresh frequency set by a timer cannot flexibly set the refresh interval time according to the execution situation of the test tasks during the testing process.

[0005] In a first aspect, in this embodiment, a method for executing an interrupt program in memory testing is provided. The memory test program includes a detection program and an interrupt program. The method includes:

[0006] Sequentially execute the detection statements in the detection program, and configure a plurality of detection signals based on the detection statements. The detection signals are used to input the memory under test for memory testing;

[0007] When a preset target detection statement is executed and the plurality of detection signals are configured correspondingly, determine whether at least one target detection signal meets a preset determination condition. The target detection signal is preselected from the plurality of detection signals;

[0008] In the case of meeting the determination condition, jump from the detection program to the interrupt program and execute it, and generate an interrupt signal input to the memory under test based on the interrupt program.

[0009] In some of these embodiments, the jump from the detection program to the interrupt program and the execution thereof include:

[0010] Determine whether the target detection statement allows a jump;

[0011] In the case where the target detection statement allows a jump, jump from the target detection statement to the interrupt program and execute;

[0012] In the case where the target detection statement does not allow a jump, determine the jump statement closest to the target detection statement based on the execution order of the detection program; when the detection program executes to the jump statement, jump from the jump statement to the interrupt program and execute.

[0013] In some of these embodiments, the jump from the detection program to the interrupt program and the execution thereof further include:

[0014] In the case where the target detection statement does not allow a jump, accumulate the number of non - jumped times corresponding to the target detection statement during the running of the detection program;

[0015] Based on the accumulated number of non - jumped times when the detection program executes to the jump statement, determine the continuous execution times of the interrupt program;

[0016] Based on the continuous execution times, jump from the jump statement to the interrupt program and execute continuously.

[0017] In some of these embodiments, the determination of whether at least one target detection signal meets a preset determination condition includes:

[0018] Determine whether the values of the at least one target detection signal are all equal to the corresponding preset reference values within the same command cycle;

[0019] In the case of equality, determine that the at least one target detection signal meets the determination condition.

[0020] In some of these embodiments, the controller includes a buffer, and the jump from the detection program to the interrupt program and the execution thereof include:

[0021] Stop converting the detection signal stream into corresponding timing signals, and store the detection signal stream in the buffer, where the detection signal stream is generated based on the detection program;

[0022] Based on the interrupt program, generate a corresponding interrupt signal stream and send the corresponding timing signals to the memory under test until the interrupt program finishes execution;

[0023] Read the detection signal stream from the buffer, convert it into a corresponding timing signal, and send the timing signal to the memory under test.

[0024] In some embodiments, the memory under test is divided into multiple memory blocks, and the interrupt program is used to refresh the memory under test. The process of jumping from the detection program to the interrupt program and executing includes:

[0025] Based on the interrupt program, determine the memory block to be refreshed in the memory under test; refresh the memory block.

[0026] In some embodiments, the process of jumping from the detection program to the interrupt program and executing further includes:

[0027] When the determination condition is met, increment the cumulative detection count of the memory under test by 1;

[0028] When the cumulative detection count reaches a pre-set test count threshold and the target detection statement allows jumping, jump from the target detection statement to the interrupt program and execute.

[0029] In a second aspect, a memory detection system is provided in this embodiment. The memory detection system includes a controller, and the controller includes an execution module and a determination module.

[0030] The execution module is configured to sequentially execute the detection statements in the detection program, configure multiple detection signals based on the detection statements, where the detection signals are used to input the memory under test for memory testing; and to jump from the detection program to the interrupt program and execute when the determination module determines that at least one target detection signal meets a pre-set determination condition, and generate an interrupt signal input to the memory under test based on the interrupt program.

[0031] The determination module is configured to determine whether at least one target detection signal meets the determination condition when a pre-set target detection statement is executed and the multiple detection signals are configured correspondingly, where the target detection signal is pre-selected from the multiple detection signals.

[0032] In some embodiments, the controller further includes a jump acceleration module.

[0033] The jump acceleration module is configured to, when jumping from the detection program to the interrupt program, accelerate the transmission of the interrupt signal corresponding to the interrupt program to the memory under test.

[0034] In some embodiments, the controller further includes an interrupt recording module and a supplementary jump module.

[0035] The interruption recording module is used to record and accumulate the number of non-jumps corresponding to the target detection statement; based on the accumulated number of non-jumps when the detection program executes to the jump statement, determine the consecutive execution times of the interruption program;

[0036] The jump supplement module is used to accelerate the transmission of the interruption signal corresponding to the consecutive execution times to the memory under test.

[0037] In some of the embodiments, the controller further includes an interruption recording module, a jump acceleration module, and a jump supplement module,

[0038] When the target detection statement allows jumping, the jump acceleration module is used to accelerate the transmission of the interruption signal corresponding to the interruption program to the memory under test;

[0039] When the target detection statement does not allow jumping, the interruption recording module is used to record and accumulate the number of non-jumps corresponding to the target detection statement, and based on the accumulated number of non-jumps when the detection program executes to the jump statement, determine the consecutive execution times of the interruption program; the jump supplement module is used to sequentially transmit the interruption signal corresponding to the consecutive execution times to the jump acceleration module, and the jump acceleration module is used to accelerate the transmission of the interruption signal to the memory under test.

[0040] In some of the embodiments, the execution module includes a command sequence control sub-module, an algorithm generation sub-module, and a signal selection sub-module,

[0041] The command sequence control sub-module is used to sequentially execute the detection statements in the detection program, and when the determination module determines that at least one target detection signal meets the preset determination conditions, jump from the detection program to the interruption program and execute;

[0042] The algorithm generation sub-module is used to configure multiple detection signals based on the detection statement and input them into the signal selection sub-module, and generate the interruption signal input into the memory under test based on the interruption program;

[0043] The signal selection sub-module is used to select at least one target detection signal from the multiple detection signals and input it into the determination module for determination.

[0044] In some of the embodiments, the controller further includes a waveform replacement module and a buffer,

[0045] The algorithm generation sub-module is further used to generate a corresponding detection signal stream based on the detection program, and generate a corresponding interruption signal stream based on the interruption program;

[0046] The waveform replacement module is used to stop converting the detection signal stream into corresponding timing signals and store the detection signal stream in a buffer when the determination condition is met; convert the interrupt signal stream into corresponding timing signals and send them to the memory under test until the interrupt program is executed; read the detection signal stream from the buffer, convert it into corresponding timing signals, and send the timing signals to the memory under test.

[0047] In some of these embodiments, the memory detection system further includes a host computer.

[0048] The host computer is used to send a memory test program and corresponding configuration parameters to the controller before the controller executes the detection program.

[0049] Compared with the related art, in the method for executing an interrupt program for memory testing provided in this embodiment, by sequentially executing the detection statements in the detection program and configuring multiple detection signals based on the detection statements, the detection signals are used to input the memory under test for memory testing; when the preset target detection statement is executed and the multiple detection signals are configured correspondingly, whether the state of the target detection signal meets the determination condition is used as the basis for whether to jump to the interrupt program, providing a feasible method for entering the interrupt program; when the determination condition is met, jump from the detection program to the interrupt program and execute it, generating an interrupt signal input to the memory under test, meeting the refresh requirements for dynamically refreshing the memory; through the setting of the jump determination condition and jump statement, flexibly control the alternating operation of the memory detection task and the refresh task, reflecting the influence of different refresh intervals on the characteristic parameters of the dynamically refreshed memory, and expanding the test items of the memory.

[0050] The details of one or more embodiments of the present application are set forth in the following drawings and description, so that other features, objects, and advantages of the present application will become more clearly understood. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The drawings described herein are used to provide a further understanding of the present application and form a part of the present application. The illustrative embodiments and descriptions thereof of the present application are used to explain the present application and do not constitute an improper limitation of the present application. In the drawings:

[0052] Figure 1 is a hardware structure block diagram of a memory detection system according to some embodiments of the present application;

[0053] Figure 2 is a flowchart of a method for executing an interrupt program for memory testing according to some embodiments of the present application;

[0054] Figure 3 is a flowchart of jumping from a detection program to an interrupt program according to some embodiments of the present application;

[0055] Figure 4 is the flowchart of continuous execution after the interruption program jump in some embodiments of the present application;

[0056] Figure 5 is the flowchart of the interruption program jump based on the register in some embodiments of the present application;

[0057] Figure 6 is the flowchart of jumping from the detection program to the interruption program in some other embodiments of the present application;

[0058] Figure 7 is the hardware structure block diagram of the memory detection system in some embodiments of the present application;

[0059] Figure 8 is the hardware structure block diagram of the memory detection system in some other embodiments of the present application;

[0060] Figure 9 is the hardware structure block diagram of the memory detection system in some other embodiments of the present application;

[0061] Figure 10 is the hardware structure block diagram of the memory detection system in some other embodiments of the present application;

[0062] Figure 11 is the hardware structure block diagram of the memory detection system in some other embodiments of the present application;

[0063] Figure 12 is the hardware structure block diagram of the memory detection system in some other embodiments of the present application;

[0064] Figure 13 is the flowchart of the execution method of the interruption program for memory testing in some preferred embodiments of the present application. Detailed implementation manners

[0065] To understand the purpose, technical solution and advantages of the present application more clearly, the present application will be described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0066] Unless otherwise defined, technical terms or scientific terms involved in this application shall have the ordinary meanings understood by those with ordinary skills in the technical field to which this application belongs. In this application, words such as "a", "one", "a kind of", "the", "these", etc. do not indicate a limitation in quantity, and they can be singular or plural. The terms "including", "comprising", "having" and any variants thereof involved in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or device including a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent in these processes, methods, products or devices. The terms "connected", "coupled" and other similar words involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether directly or indirectly connected. The term "plurality" involved in this application means two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, and B exists alone. Usually, the character " / " indicates that the objects associated before and after are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific order for the objects.

[0067] The method for executing an interrupt program for memory testing provided by an embodiment of this application can be executed in Figure 1 the controller in Figure 1 FIG. is a system structure block diagram of the method for executing an interrupt program for memory testing according to some embodiments of this application. As Figure 1 shown, the system includes a host computer 30, a controller 10, and a memory under test 20 that are connected in sequence. Among them, the host computer 30 can be a computer, a server, a terminal device, etc. with data calculation, program processing, and communication functions, and this embodiment does not make any limitations. The controller 10 can be an integrated circuit with programmable logic functions, such as a field programmable gate array chip (Field Programmable Gate Array, FPGA), a complex programmable logic device (Complex Programmable Logic Device, CPLD), etc. The memory under test 20 can be a dynamic random access memory that needs to be dynamically refreshed, such as a synchronous dynamic random access memory (Synchronous Dynamic Random Access Memory, SDRAM), etc.

[0068] Those of ordinary skill in the art can understand that Figure 1The structure shown is only illustrative and does not limit the structure of the above-mentioned memory detection system. For example, the memory detection system may further include more or fewer components than those shown in Figure 1 or have a different configuration from that shown in Figure 1 .

[0069] The host computer 30 is used to send a configuration data packet to the controller 10, and the configuration data packet includes the configuration parameters of each register of the controller 10. The controller 10 parses the configuration data packet, obtains the configuration parameters, and configures the registers of each internal module according to the configuration parameters.

[0070] The host computer 30 is also used to send the compiled MPAT program to the first buffer inside the controller 10. The MPAT program includes register configuration parameters and a memory test program. The first buffer can be a volatile memory such as DDR. The controller 10 can execute the detection statements in the memory test program, convert the detection statements into corresponding detection signals and input them into the memory under test 20 to test the memory under test 20.

[0071] In this embodiment, a method for executing an interrupt program of memory testing is provided. Figure 2 is a flowchart of the method for executing an interrupt program of memory testing in some embodiments of the present application, as shown in Figure 2 . The process includes the following steps:

[0072] Step S201: Sequentially execute the detection statements in the detection program and configure multiple detection signals based on the detection statements. The detection signals are used to be input into the memory under test for memory testing.

[0073] After the host computer issues an instruction to load the memory test program to the controller, the controller loads the memory test program from the first buffer to the second buffer. The second buffer can be a volatile memory such as RAM or a non-volatile memory. The memory test program includes a detection program and an interrupt program. Among them, the detection program is the main program for executing the test task and includes multiple detection statements arranged in the execution order. The detection program may also include loop statements. The interrupt program only runs when the detection program makes an interrupt jump. In practical applications, the interrupt program can be used to execute intermittent tasks, such as the refresh task of the memory.

[0074] When the host computer sends a start instruction, the controller starts to sequentially execute the detection statements in the detection program. The controller configures the level value of the corresponding detection signal according to the detection statement and inputs the detection signal into the memory under test based on a specific timing to execute the test item of the memory. Among them, the detection signal can be a test vector PATTERN.

[0075] Step S202: When the preset target detection statement is executed and multiple detection signals are configured accordingly, determine whether at least one target detection signal, which is preselected from the multiple detection signals, meets the preset determination condition.

[0076] Before the detection program is executed, the host computer can specify a specific detection statement in the detection program as the target detection statement and specify one or more specific detection signals as the target detection signals. While each detection statement is being executed, the controller configures the corresponding detection signals according to the definition and assignment of the detection signals in the detection statement. It should be noted that the detection signals corresponding to the target detection statement are not necessarily the target detection signals. When the target detection statement is executed and the detection signals are configured accordingly, the controller detects the values of the target detection signals and determines whether the values of the target detection signals meet the preset determination condition. The determination condition can be sent by the host computer to the register of the controller in advance.

[0077] In some embodiments, the determination condition can be that within the same command cycle, the values of at least one target detection signal are all equal to the corresponding preset reference values. For example, the target detection signal and the corresponding reference values are signal0 = 1, signal1 = 0, signal2 = 1. The reference values can be sent by the host computer to a specific register of the controller. After the target detection statement is executed and the detection signals are configured accordingly, the controller compares the actual detected values of one or more target detection signals with the corresponding reference values. If the actual detected values are consistent with the reference values, it is determined that at least one target detection signal meets the determination condition. A command cycle refers to the time cycle for performing a test on the memory under test.

[0078] Step S203: When the determination condition is met, jump from the detection program to the interrupt program and execute it, and generate an interrupt signal input to the memory under test based on the interrupt program.

[0079] When one or more target detection signals all meet the corresponding determination conditions, the controller aborts the currently running detection program, jumps to the interrupt program and starts to execute. After jumping to the interrupt program, the interrupt statements in the interrupt program are executed in sequence, corresponding interrupt signals are generated according to the interrupt statements, and the interrupt signals are input to the memory under test based on a specific timing sequence to perform the interrupt task of the memory.

[0080] Through steps S201 to S203, by sequentially executing the detection statements in the detection program and configuring multiple detection signals based on the detection statements, the detection signals are used to input the memory under test for memory testing; when the preset target detection statement is executed and the multiple detection signals are configured correspondingly, whether the state of the target detection signal meets the determination condition is used as the basis for whether to jump to the interrupt program, providing a feasible method to enter the interrupt program; in the case of meeting the determination condition, jump from the detection program to the interrupt program and execute, generating an interrupt signal for inputting the memory under test, meeting the refresh requirement of dynamically refreshing the memory; through the setting of the jump determination condition and jump statement, flexibly control the alternating operation of the detection task and refresh task of the memory, reflecting the influence of different refresh intervals on the characteristic parameters of the dynamically refreshed memory, and expanding the test function of the memory.

[0081] In some embodiments, it relates to a specific method for interrupt program jump. Figure 3 It is a flowchart of jumping from the detection program to the interrupt program and executing in some embodiments of the present application, as Figure 3 shown, and this process includes the following steps:

[0082] Step S301, determine whether the target detection statement allows jumping.

[0083] The detection statements in the detection program may include a jump keyword, which is used to determine whether the corresponding detection statement allows jumping. For example, if the jump keyword is INT_EN, the detection statement containing INT_EN allows jumping.

[0084] Step S302, in the case where the target detection statement allows jumping, jump from the target detection statement to the interrupt program and execute.

[0085] In the case where the target detection statement allows jumping, after the target detection statement is executed, stop the execution of the detection program, jump to the interrupt program and start sequentially executing the interrupt statements in the interrupt program until the interrupt program is executed, and output the corresponding interrupt signal. And input the interrupt signal into the memory under test based on a specific timing to execute the interrupt task of the memory.

[0086] Step S303, in the case where the target detection statement does not allow jumping, based on the execution order of the detection program, determine the jump statement closest to the target detection statement; when the detection program executes to this jump statement, jump from this jump statement to the interrupt program and execute.

[0087] When the target detection statement does not allow jumping, based on the execution order of the detection program, continue to execute the detection statements after the target detection statement, and determine whether each detection statement allows jumping until the nearest jump statement to the target detection statement is found. When the detection program executes to this jump statement and finishes execution, it can jump from this jump statement to the interrupt program and execute the interrupt program.

[0088] Through steps S301 - S303, by determining whether the target detection statement allows jumping, when the target detection statement allows jumping, jump from the target detection statement to the interrupt program and execute. When it does not allow jumping, based on the execution order of the detection program, determine the nearest jump statement to the target detection statement, and jump from this jump statement to the interrupt program and execute. By setting the jump statement to control the execution timing of the interrupt program, the flexibility of the alternating execution of the interrupt program and the detection program is improved, providing a feasible way for the characteristic parameter test of the memory.

[0089] In some embodiments, it also involves the continuous execution of the interrupt program multiple times. Figure 4 It is the flowchart of the continuous execution after the jump of the interrupt program in some embodiments of the present application, as Figure 4 shown, and this process includes the following steps:

[0090] Step S401, when the target detection statement does not allow jumping, during the running of the detection program, accumulate the number of non - jumped times corresponding to the target detection statement.

[0091] In some embodiments, the detection program includes multiple detection statements that are executed in a loop, and the target detection statement can be set in the multiple detection statements that are executed in a loop. When all the multiple detection statements executed in a loop are set to prohibit jumping through the jump keyword, and only the detection statements outside the loop allow jumping, the number of non - jumped times corresponding to the target detection statement can be equal to the number of loops. In this way, the jump timing of the interrupt program can be set by setting the number of loops.

[0092] Step S402, based on the accumulated number of non - jumped times when the detection program executes to the jump statement, determine the continuous execution times of the interrupt program.

[0093] After the loop statement finishes execution, the detection program continues to execute and reaches the nearest jump statement to the target detection statement. According to the accumulated number of non - jumped times, determine the continuous execution times of the interrupt program. For example, the continuous execution times can be equal to the number of non - jumped times, or equal to the product of the number of non - jumped times and a preset coefficient. The value of the coefficient can be determined according to the test requirements.

[0094] Step S403, based on the continuous execution times, jump from the jump statement to the interrupt program and execute continuously.

[0095] After the detection program reaches the jump statement and executes, it jumps from the jump statement to the interrupt program and continuously executes the interrupt program multiple times, and the number of executions is equal to the number of consecutive executions.

[0096] Through steps S401 to S403, when the target detection statement does not allow jumping, during the running of the detection program, the number of non-jumped times corresponding to the target detection statement is accumulated, and the number of consecutive executions of the interrupt program is determined according to the accumulated number of non-jumped times, establishing a connection between the number of executions of the interrupt program and the number of executions of the loop statement in the detection program, providing a method for flexibly setting the number of executions of the interrupt program; through the continuous multiple executions of the interrupt program, the influence of the difference in the number of refresh times on the performance parameters of the memory under test can be tested, expanding the test function of the memory test.

[0097] In some embodiments, it also relates to a method for jumping an interrupt program based on a buffer. The controller includes a third buffer, which is used to store a detection signal stream composed of multiple detection signals. The third buffer can be a volatile memory such as RAM or a non-volatile memory. Figure 5 It is a flowchart of jumping an interrupt program based on a buffer in some embodiments of the present application, as Figure 5 shown, and this process includes the following steps:

[0098] Step S501, stop converting the detection signal stream into the corresponding timing signal, and store the detection signal stream in the buffer, and the detection signal stream is generated based on the detection program.

[0099] When the detection program is executed normally, the controller generates multiple detection signals according to the sequentially executed detection statements, and the multiple detection signals form a detection signal stream. Then, timing settings are performed on the detection signal stream, and after converting the detection signal stream into the corresponding timing signal, it is input into the memory under test for testing.

[0100] When the program jumps from the detection program to the interrupt program, the controller stops the process of converting the detection signal stream into the corresponding timing signal, and stores the already generated detection signal stream in the third buffer.

[0101] Step S502, based on the interrupt program, generate the corresponding interrupt signal stream and send the corresponding timing signal to the memory under test until the interrupt program finishes execution.

[0102] After the interrupt program starts to execute, the controller generates multiple interrupt signals according to the sequentially executed interrupt statements, and the multiple interrupt signals form an interrupt signal stream. Then, timing settings are performed on the interrupt signal stream, and after converting the interrupt signal stream into the corresponding timing signal, it is input into the memory under test until the interrupt program finishes execution.

[0103] Step S503: Read the detection signal stream from the buffer, convert it into the corresponding timing signal, and send the timing signal to the memory under test.

[0104] After the interruption program execution is completed, read out the previously cached detection signal stream from the third buffer, continue the process of converting the detection signal stream into the corresponding timing signal, and send the timing signal to the memory under test. After the cached detection signal stream is executed, return to the jump statement of the detection program and continue to execute.

[0105] Through steps S501 - S503, by stopping converting the detection signal stream into the corresponding timing signal, storing the detection signal stream in the third buffer, and caching the unexecuted detection signal stream; by generating the corresponding interruption signal stream based on the interruption program and sending the corresponding timing signal to the memory under test until the interruption program execution is completed, it ensures the timely execution of the interruption program; by reading the detection signal stream from the third buffer, converting it into the corresponding timing signal, and sending the timing signal to the memory under test, it ensures the smooth connection between the detection program and the interruption program, and avoids timing errors during program jumps.

[0106] In some embodiments, the memory under test is divided into multiple memory blocks. The specific method for executing the interruption program after jumping from the detection program to the interruption program further includes:

[0107] Based on the interruption program, determine the memory block to be refreshed in the memory under test; refresh this memory block.

[0108] When the interruption program is used to refresh and replenish the power of the memory under test, the refresh area of the memory can be specified in the interruption program. This refresh area can be a specific memory block of the memory under test. For example, if the memory under test is divided into multiple memory arrays (logical banks), a specific bank can be targeted for refreshing, which increases the flexibility of the memory to execute the refresh task, and can test the impact of specific memory block refreshing on the boundary parameters of the memory under test during memory testing, expanding the function of memory testing.

[0109] In some embodiments, Figure 6 is the flowchart of jumping from the detection program to the interruption program in other embodiments of the present application, as Figure 6 shown, this process includes the following steps:

[0110] Step S601: When the determination condition is met, increment the cumulative detection times of the memory under test by 1.

[0111] When the target detection statement meets the determination condition, cumulatively increment the detection times of the memory under test by 1. That is, each time the detection program runs to the target detection statement and the target detection statement meets the determination condition, it is determined that the memory under test has completed one detection.

[0112] Step S602, when the cumulative number of detection times reaches a preset test times threshold and the target detection statement allows jumping, jump from the target detection statement to the interrupt program and execute.

[0113] Set a test times threshold for the number of detection times of the memory under test in advance.

[0114] In this embodiment, when the cumulative number of detection times does not reach the test times threshold, it is not necessary to confirm whether the target detection statement allows jumping; when the cumulative number of detection times reaches the test times threshold, confirm whether the target detection statement allows jumping. If the target detection statement allows jumping, jump to the interrupt program and execute; if the target detection statement does not allow jumping, jump after the detection program runs to the nearest jump statement.

[0115] Through steps S601 - S602, by adding 1 to the cumulative number of detection times of the memory under test when the determination condition is met, and when the cumulative number of detection times reaches the preset test times threshold and the target detection statement allows jumping, jump from the target detection statement to the interrupt program and execute, a method of directly jumping to the interrupt program after the memory under test completes the preset number of detections is provided by setting the number of detection times of the memory under test, improving the execution efficiency of the interrupt program.

[0116] This embodiment also provides a memory detection system. Figure 7 It is a structural block diagram of the memory detection system of some embodiments of the present application, as Figure 7 shown. The memory detection system includes a memory under test 20 and a controller 10. The controller 10 includes an execution module 11 and a determination module 12. The execution module 11 is respectively connected to the memory under test 20 and the determination module 12. Of course, those skilled in the art know that the connection relationship is a physical connection or a signal connection.

[0117] The execution module 11 is used to sequentially execute the detection statements in the detection program, and configure multiple detection signals based on the detection statement. The detection signal is used to be input into the memory under test for memory testing; it is also used to jump from the detection program to the interrupt program and execute when the determination module 12 determines that at least one target detection signal meets the preset determination condition, and generate an interrupt signal input into the memory under test based on the interrupt program.

[0118] The determination module 12 is used to determine whether at least one target detection signal meets the determination condition when the preset target detection statement is executed and the multiple detection signals are configured correspondingly. The target detection signal is preselected from the multiple detection signals.

[0119] The memory detection system of this embodiment sequentially executes the detection statements in the detection program through an execution module, and configures a plurality of detection signals based on the detection statements. The detection signals are used to input the memory under test for memory testing; when the determination condition is met, it jumps from the detection program to the interrupt program and executes, generating an interrupt signal input to the memory under test, meeting the refresh requirements of the dynamic refresh memory; when the preset target detection statement is executed and the corresponding configurations of the plurality of detection signals are completed, the determination module uses whether the state of the target detection signal meets the determination condition as the basis for whether to jump to the interrupt program, providing a feasible method to enter the interrupt program; through the setting of the jump determination condition and the jump statement, it flexibly controls the alternating operation of the memory detection task and the refresh task, reflects the influence of different refresh intervals on the characteristic parameters of the dynamic refresh memory, and expands the test function of the memory.

[0120] In some embodiments, Figure 8 is the structural block diagram of the memory detection system of other embodiments of the present application, as Figure 8 shown, the controller 10 further includes a jump acceleration module 19. The jump acceleration module 19 is used to accelerate the transmission of the interrupt signal corresponding to the interrupt program to the memory under test when jumping from the detection program to the interrupt program. As Figure 8 shown, the execution module 11, the determination module 12, and the jump acceleration module 19 are connected in sequence. The jump acceleration module 19 is connected to the execution module 11, and the execution module 11 is connected to the memory under test 20. Of course, those skilled in the art know that the connection relationship is a physical connection or a signal connection.

[0121] Specifically, the jump acceleration module 19 may include a fourth buffer. The fourth buffer is used to store the interrupt signal corresponding to the interrupt program, as well as data such as relevant statistical information. The fourth buffer may be a volatile memory such as a FIFO or a non-volatile memory. When the execution module 11 jumps from the detection program to the interrupt program, the jump acceleration module 19 determines the transmission order of each interrupt signal according to the execution order of each interrupt statement in the interrupt program and the corresponding statistical information, and controls the interrupt signal to replace the detection signal sent before the jump, and accelerates the transmission to the memory under test 20 in sequence according to the transmission order.

[0122] The memory detection system of this embodiment replaces the detection signal with the interrupt signal corresponding to the interrupt program through the jump acceleration module and accelerates the transmission to the memory under test, realizing the timely jump from the detection program to the interrupt program and improving the execution efficiency of the interrupt program.

[0123] In some embodiments, Figure 9 is the structural block diagram of the memory detection system of still other embodiments of the present application, as Figure 9As shown, the controller 10 further includes an interrupt recording module 15 and a jump supplement module 16. The interrupt recording module 15 is used to record and accumulate the number of un-jumped times corresponding to the target detection statement; based on the accumulated number of un-jumped times when the detection program executes to the jump statement, determine the continuous execution times of the interrupt program; the jump supplement module 16 is used to accelerate the transmission of the interrupt signal corresponding to the continuous execution times to the memory under test.

[0124] As Figure 9 shown, the execution module 11, the determination module 12, the interrupt recording module 15, and the jump supplement module 16 are connected in sequence. The jump supplement module 16 is connected to the execution module 11, and the execution module 11 is connected to the memory under test 20. Of course, those skilled in the art know that the connection relationship is a physical connection or a signal connection.

[0125] Specifically, the jump supplement module 16 may include a fifth buffer. The fifth buffer is used to store the interrupt signals corresponding to multiple stored interrupt programs corresponding to the continuous execution times, as well as data such as relevant statistical information. The fifth buffer may be a volatile memory such as a RAM or a non-volatile memory. When the execution module 11 jumps from the detection program to the interrupt program, the jump supplement module 16 determines the transmission order of each interrupt signal according to the execution order of each interrupt statement in the interrupt program and the corresponding statistical information, and controls the interrupt signal to replace the detection signal sent before the jump and accelerate the transmission to the memory under test 20 in sequence according to the transmission order, so as to realize the continuous execution of the interrupt program multiple times.

[0126] In the memory detection system of this embodiment, the interrupt recording module accumulates the number of un-jumped times corresponding to the target detection statement during the operation of the detection program, and determines the continuous execution times of the interrupt program according to the accumulated number of un-jumped times, establishing a connection between the execution times of the interrupt program and the execution times of the loop statement in the detection program, providing a means for flexibly setting the execution times of the interrupt program; the jump supplement module accelerates the transmission of the interrupt signal corresponding to the continuous execution times to the memory under test, realizing the continuous execution of the interrupt program multiple times, and testing the influence of the difference in the number of refresh times on the performance parameters of the memory under test, expanding the test function of the memory test.

[0127] In some embodiments, Figure 10 is the structural block diagram of the memory detection system of some other embodiments of the present application. As Figure 10 shown, the controller further includes an interrupt recording module 15, a jump acceleration module 19, and a jump supplement module 16. The execution module 11, the determination module 12, the interrupt recording module 15, the jump supplement module 16, and the jump acceleration module 19 are connected in sequence. The interrupt recording module 15 is connected to the jump acceleration module 19, the jump acceleration module 19 is connected to the execution module 11, and the execution module 11 is connected to the memory under test 20. Of course, those skilled in the art know that the connection relationship is a physical connection or a signal connection.

[0128] When the target detection statement allows jumping, the interruption recording module 15 directly sends an instruction to the jump acceleration module 19, and the jump acceleration module 19 accelerates the transmission of the interruption signal corresponding to the interruption program to the memory under test 20.

[0129] When the target detection statement does not allow jumping, the interruption recording module 15 is used to record and accumulate the number of non-jumping times corresponding to the target detection statement, and determine the continuous execution times of the interruption program based on the accumulated number of non-jumping times when the detection program executes to the jump statement; the supplementary jump module 16 is used to sequentially transmit the interruption signals corresponding to the continuous execution times to the jump acceleration module 19, and the jump acceleration module 19 accelerates the transmission of the interruption signals to the memory under test 20.

[0130] The memory detection system of this embodiment obtains the execution times of the interruption program through the interruption recording module, stores the interruption signals and statistical information through the jump acceleration module and the supplementary jump module, and accelerates the transmission of the interruption signals corresponding to the interruption programs with different execution times to the memory under test, realizing the timely jump from the detection program to the interruption program and improving the execution efficiency of the interruption program.

[0131] In a further embodiment, Figure 11 is the structural block diagram of the memory detection system of some other embodiments of this application, as Figure 11 shown, the execution module 11 further includes a command sequence control sub-module 110, an algorithm generation sub-module 13, and a signal selection sub-module 14.

[0132] As Figure 11 shown, the command sequence control sub-module 110, the algorithm generation sub-module 13, the signal selection sub-module 14, the determination module 12, the interruption recording module 15, the supplementary jump module 16, and the jump acceleration module 19 are connected in sequence. The determination module 12 is connected to the command sequence control sub-unit 110. The interruption recording module 15 is connected to the jump acceleration module 19. The jump acceleration module 19 is connected to the command sequence control sub-unit 110. The algorithm generation sub-module 13 is connected to the memory under test 20.

[0133] The command sequence control sub-module 110 is used to sequentially execute the detection statements in the detection program, and when the determination module 12 determines that at least one target detection signal meets the preset determination conditions, jump from the detection program to the interruption program and execute; the algorithm generation sub-module 13 is used to generate multiple detection signals based on the detection statements and input them into the signal selection sub-module 14; the signal selection sub-module 14 is used to select at least one target detection signal from the multiple detection signals and input it into the determination module 12 for determination.

[0134] The memory detection system of this embodiment ensures that the detection program and the interrupt program are executed sequentially in order and the correct jump of the interrupt program through the command sequence control sub-module; the algorithm generation sub-module generates corresponding detection signals based on the detection statements, and the signal selection sub-module selects at least one target detection signal from multiple detection signals for determination, realizing the jump of the detection program and the interrupt program based on the determination conditions, and meeting the dynamic refresh requirements of the memory under test based on the interrupt program.

[0135] In a further embodiment, Figure 12 is the structural block diagram of the memory detection system of some other embodiments of this application, as Figure 12 shown, the controller further includes a waveform replacement module 17 and a third buffer 18. Specifically, on the basis of Figure 11 shown, the waveform replacement module 17 is respectively connected to the algorithm generation sub-module 13, the third buffer 18, and the memory under test 20.

[0136] The algorithm generation module 13 is further configured to generate a corresponding detection signal stream Normal based on the detection program, and generate a corresponding interrupt signal stream Replace based on the interrupt program; the waveform replacement module 17 is configured to stop converting the detection signal stream Normal into a corresponding timing signal and store the detection signal stream Normal in the third buffer 18 when the determination condition is met; convert the interrupt signal stream Replace into a corresponding timing signal and send it to the memory under test 20 until the interrupt program is executed; read the detection signal stream Normal from the third buffer 18, convert it into a corresponding timing signal, and send the timing signal to the memory under test 20.

[0137] The memory detection system of this embodiment stops converting the detection signal stream into a corresponding timing signal through the waveform replacement module, stores the detection signal stream in the third buffer, and caches the unexecuted detection signal stream; the algorithm generation module and the waveform replacement module generate a corresponding interrupt signal stream based on the interrupt program and send the corresponding timing signal to the memory under test until the interrupt program is executed, ensuring the timely execution of the interrupt program; the waveform replacement module reads the detection signal stream from the third buffer, converts it into a corresponding timing signal, and sends the timing signal to the memory under test, ensuring the smooth connection between the detection program and the interrupt program and avoiding timing errors during program jumps.

[0138] In some embodiments, the memory detection system further includes a host computer, which is configured to send a memory test program and corresponding configuration parameters to the controller before the controller executes the detection program.

[0139] Specifically, the configuration parameters may include the determination conditions in the determination module, the target detection signals in the signal selection module, etc.

[0140] In a further embodiment, the host computer is further configured to configure the registers of each module of the controller according to the configuration parameters.

[0141] In a further embodiment, the host computer is further configured to issue a loading instruction for the memory test program and a start instruction for the controller.

[0142] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation manners, and will not be elaborated herein.

[0143] The following describes the method for executing the interrupt program of the memory test of the present application through some preferred embodiments. This method is applied to the controller of the memory detection system, and the memory detection system includes a host computer, a controller, and a memory under test. The controller is an FPGA chip and includes an internal structure as Figure 12 shown (where the first buffer and the second buffer are not shown).

[0144] Figure 13 is a flowchart of the method for executing the interrupt program of the memory test in some preferred embodiments of the present application. As Figure 13 shown, the process includes the following steps:

[0145] Step S1101: Receive and parse the configuration data packet sent by the host computer, including register configuration of the signal selection sub-module, determination module, etc.;

[0146] Step S1102: Configure the signal selection sub-module and the determination module according to the content of the data packet; configure the reference value corresponding to the target detection signal and the test times threshold;

[0147] The signal selection sub-module is used to select the target detection signal (i.e., test vector PATTERN) to be detected and output it to the determination module. For example, the target detection signal is pattern0. The determination module is used to compare the reference value with the corresponding target detection signal.

[0148] Step S1103: Download the compiled MPAT program to the first buffer of the controller through the host computer. The values compiled by the MPAT include register configuration of the algorithm generation sub-module and the command sequence control sub-module, as well as the memory test program;

[0149] Step S1104: Receive the loading instruction issued by the host computer, load the MPAT program from the first buffer to the second buffer, and configure the registers of the algorithm generation sub-module and the command sequence control sub-module;

[0150] The command sequence control sub-module is responsible for sequentially executing the content in the second buffer, and the algorithm generation sub-module is used to generate the corresponding test signal.

[0151] In this embodiment, the test signal is a detection signal or an interruption signal.

[0152] Step S1105: Receive the start data packet sent by the host computer, and start the operation of the command sequence control sub-module and the algorithm generation sub-module;

[0153] Step S1106: When the command sequence control sub-module executes the test program, the algorithm generation sub-module outputs multiple detection signals;

[0154] Step S1107: The determination module detects the target detection signal and compares it in real time with the configured reference value to check for a match;

[0155] Step S1108: When the determination module determines that there is a match, the internal detection counter is incremented by 1;

[0156] Step S1109: When the value of the detection counter of the determination module reaches the test times threshold and the target detection statement allows a jump, a jump occurs, and the jump acceleration module accelerates the transmission of the interruption signal corresponding to the interruption program to the memory under test;

[0157] Step S1110: If the target detection statement does not allow a jump, the interruption record module records and accumulates the number of non-jump times corresponding to the target detection statement;

[0158] Step S1111: The jump supplement module continuously detects the interruption record module, and a jump request corresponding to the number of non-jump times is formed and stored in the jump supplement module;

[0159] Step S1112: The jump supplement module sequentially transmits the interruption signals corresponding to the number of consecutive executions to the jump acceleration module, and the jump acceleration module controls the command sequence control sub-module to repeatedly execute the interruption function, and the number of executions is the number of non-jump times recorded by the interruption record module;

[0160] Step S1113: During normal operation, the detection signal stream generated by the algorithm generation sub-module is output to the waveform replacement module. When a jump occurs, the waveform replacement module caches the detection signal stream being sent in the third buffer, and directly sends the data of the interruption signal stream to the memory under test; after the interruption program execution ends, the algorithm generation sub-module stops sending the interruption signal stream. At this time, the waveform replacement module reads out the detection signal stream in the third buffer and continues to send it. After sending, it continues to send the detection signal stream generated by the algorithm generation sub-module.

[0161] Through steps S1101 to S1113, by setting the jump determination conditions of the determination module and the jump statements of the detection program, the state of the target detection signal is used as the determination condition for whether to jump to the interrupt program, flexibly controlling the alternating operation of the test task and the refresh task of the memory, reflecting the influence of different refresh intervals on the characteristic parameters of the memory; determining the continuous execution times of the interrupt program according to the accumulated number of non-jumped times, establishing a connection between the execution times of the interrupt program and the execution times of the loop statements in the detection program, and providing a method for flexibly setting the execution times of the interrupt program; through the continuous execution of the interrupt program multiple times, the influence of the difference in the number of refresh times on the performance parameters of the memory under test can be tested, expanding the test function of the memory; by caching the detection signal flow, the connection between the detection program and the interrupt program is ensured to be smooth, avoiding timing errors during program jumps.

[0162] It should be understood that the specific embodiments described herein are only used to explain this application and not to limit it. According to the embodiments provided in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application.

[0163] Obviously, the drawings are only some examples or embodiments of this application. For those of ordinary skill in the art, this application can also be applied to other similar situations based on these drawings without creative efforts. Additionally, it can be understood that although the work done during the development process here may be complex and time-consuming, for those of ordinary skill in the art, certain design, manufacturing, or production changes based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient disclosure of this application.

[0164] The term "embodiment" in this application means that the specific features, structures, or characteristics described in connection with the embodiment may be included in at least one embodiment of this application. The phrase appears in various positions in the specification and does not necessarily mean the same embodiment, nor does it mean being independent or alternative to other embodiments and mutually exclusive. Those of ordinary skill in the art can clearly or implicitly understand that the embodiments described in this application can be combined with other embodiments without conflict.

[0165] The above-described embodiments only represent several implementation manners of this application, and their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of patent protection. It should be noted that for those of ordinary skill in the art, without departing from the concept of this application, several modifications and improvements can still be made, and these all belong to the protection scope of this application. Therefore, the protection scope of this application shall be subject to the appended claims.

Claims

1. An interrupt program execution method for memory testing, characterized in that, The memory test program includes a detection program and an interrupt program, and the method includes: Sequentially execute the detection statements in the detection program, and configure a plurality of detection signals based on the detection statements, where the detection signals are used to input the memory under test for memory testing; When the preset target detection statement is executed and the plurality of detection signals are correspondingly configured, determine whether at least one target detection signal satisfies a preset determination condition, where the target detection signal is preselected from the plurality of detection signals; In the case where the determination condition is satisfied, jump from the detection program to the interrupt program and execute, and generate an interrupt signal for inputting the memory under test based on the interrupt program.

2. The method according to claim 1, characterized in that, The jumping from the detection program to the interrupt program and executing includes: Determine whether the target detection statement allows jumping; In the case where the target detection statement allows jumping, jump from the target detection statement to the interrupt program and execute; In the case where the target detection statement does not allow jumping, determine the jump statement closest to the target detection statement based on the execution order of the detection program; when the detection program executes to the jump statement, jump from the jump statement to the interrupt program and execute.

3. The method according to claim 2, wherein The jumping from the detection program to the interrupt program and executing further includes: In the case where the target detection statement does not allow jumping, accumulate the number of non-jumped times corresponding to the target detection statement during the running of the detection program; Based on the accumulated number of non-jumped times when the detection program executes to the jump statement, determine the continuous execution times of the interrupt program; Based on the continuous execution times, jump from the jump statement to the interrupt program and continuously execute.

4. The method according to claim 1, wherein The determining whether at least one target detection signal satisfies a preset determination condition includes: Determine whether the values of the at least one target detection signal are all equal to the preset corresponding reference values within the same command cycle; In the case of equality, determine that the at least one target detection signal satisfies the determination condition.

5. The method according to claim 1, wherein The controller includes a buffer, and the jumping from the detection program to the interrupt program and executing includes: Stop converting the detection signal stream into corresponding timing signals, and store the detection signal stream in the buffer, where the detection signal stream is generated based on the detection program; Based on the interrupt program, generate a corresponding interrupt signal stream and send the corresponding timing signals to the memory under test until the interrupt program finishes execution; Read the detection signal stream from the buffer, convert it into corresponding timing signals, and send the timing signals to the memory under test.

6. The method according to claim 1, wherein The memory under test is divided into multiple memory blocks, and the interrupt program is used to refresh the memory under test. The jumping from the detection program to the interrupt program and executing includes: Based on the interrupt program, determine the memory blocks to be refreshed in the memory under test; refresh the memory blocks.

7. The method according to claim 1, wherein The jumping from the detection program to the interrupt program and executing further includes: In the case where the determination condition is satisfied, increment the cumulative detection times of the memory under test by 1; When the cumulative number of detections reaches a pre-set test number threshold and the target detection statement allows jumping, jump from the target detection statement to an interrupt program and execute it.

8. A memory detection system, the memory detection system comprising a controller, characterized in that, The controller includes an execution module and a determination module. The execution module is configured to sequentially execute the detection statements in the detection program and configure a plurality of detection signals based on the detection statements, where the detection signals are used to be input into the memory under test for memory testing. And it is further configured to, when the determination module determines that at least one target detection signal meets a pre-set determination condition, jump from the detection program to an interrupt program and execute it, and generate an interrupt signal input into the memory under test based on the interrupt program. The determination module is configured to determine whether at least one target detection signal meets the determination condition when a pre-set target detection statement is executed and the plurality of detection signals are correspondingly configured, where the target detection signal is pre-selected from the plurality of detection signals.

9. The system according to claim 8, wherein The controller further includes a jump acceleration module. The jump acceleration module is configured to, when jumping from the detection program to the interrupt program, accelerate the transmission of the interrupt signal corresponding to the interrupt program to the memory under test.

10. The system according to claim 8, characterized in that, The controller further includes an interrupt recording module and a supplementary jump module. The interrupt recording module is configured to record and accumulate the number of non-jumps corresponding to the target detection statement; and determine the continuous execution times of the interrupt program based on the accumulated number of non-jumps when the detection program executes to the jump statement. The supplementary jump module is configured to accelerate the transmission of the interrupt signal corresponding to the continuous execution times to the memory under test.

11. The system according to claim 8, characterized in that, The controller further includes an interrupt recording module, a jump acceleration module and a supplementary jump module. When the target detection statement allows jumping, the jump acceleration module is configured to accelerate the transmission of the interrupt signal corresponding to the interrupt program to the memory under test. When the target detection statement does not allow jumping, the interrupt recording module is configured to record and accumulate the number of non-jumps corresponding to the target detection statement, and determine the continuous execution times of the interrupt program based on the accumulated number of non-jumps when the detection program executes to the jump statement; the supplementary jump module is configured to sequentially transmit the interrupt signal corresponding to the continuous execution times to the jump acceleration module, and the jump acceleration module is configured to accelerate the transmission of the interrupt signal to the memory under test.

12. The system according to claim 8, characterized in that, The execution module includes a command sequence control sub-module, an algorithm generation sub-module and a signal selection sub-module. The command sequence control sub-module is configured to sequentially execute the detection statements in the detection program, and jump from the detection program to an interrupt program and execute it when the determination module determines that at least one target detection signal meets a pre-set determination condition. The algorithm generation sub-module is configured to configure a plurality of detection signals based on the detection statements and input them into the signal selection sub-module, and generate an interrupt signal input into the memory under test based on the interrupt program. The signal selection sub-module is configured to select at least one target detection signal from the plurality of detection signals and input it into the determination module for determination.

13. The system according to claim 12, wherein The controller further includes a waveform replacement module and a buffer. The algorithm generation sub-module is further configured to generate a corresponding detection signal stream based on the detection program, and generate a corresponding interrupt signal stream based on the interrupt program. The waveform replacement module is configured to, when the determination condition is satisfied, stop converting the detection signal stream into a corresponding timing signal, and store the detection signal stream in the buffer; convert the interrupt signal stream into a corresponding timing signal and send it to the memory under test until the interrupt program is executed; read the detection signal stream from the buffer, convert it into a corresponding timing signal, and send the timing signal to the memory under test.

14. The system according to claim 8, wherein The memory detection system further includes a host computer. The host computer is configured to send a memory test program and corresponding configuration parameters to the controller before the controller executes the detection program.

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