Array substrate and preparation method thereof, display panel and display equipment

Abstract

The embodiment of the invention relates to an array substrate and a preparation method thereof, a display panel and display equipment. The array substrate comprises a channel layer which is provided with a first channel region of a plurality of first driving transistors; the first metal layer is arranged on one side of the first channel layer, the first metal layer is provided with first grid electrodes of a plurality of first driving transistors, the first grid electrodes of the plurality of first driving transistors are arranged corresponding to the plurality of first channel regions respectively, and first grid electrode orthographic projections of the first grid electrodes on the channel layer are overlapped with the corresponding first channel regions; wherein the first channel region comprises a first sub-region and a second sub-region, and the first doping concentration of the first sub-region is higher than the second doping concentration of the second sub-region.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of display technologies, and in particular, to an array substrate, a method for manufacturing the same, a display panel, and a display device. Background Art

[0002] With the continuous development of display technologies, people's requirements for the display quality of display panels are also constantly increasing. Among them, transistors are used to directly determine the light emission brightness of sub-pixels. Therefore, the electrical performance of transistors is an important factor affecting the display ability of display panels. However, the existing electrical performance of transistors can no longer meet the needs of users. Summary of the Invention

[0003] Based on this, it is necessary to provide an array substrate, a method for manufacturing the same, a display panel, and a display device for the above technical problems.

[0004] In a first aspect, the present application provides an array substrate, including:

[0005] A channel layer provided with first channel regions of a plurality of first driving transistors;

[0006] A first metal layer disposed on one side of the first channel layer, the first metal layer being provided with first gates of a plurality of first driving transistors, the first gates of the plurality of first driving transistors being respectively disposed corresponding to the plurality of first channel regions, and the first gate orthographic projection on the channel layer overlapping with the corresponding first channel region;

[0007] Wherein, the first channel region includes a first sub-region and a second sub-region, and a first doping concentration of the first sub-region is higher than a second doping concentration of the second sub-region.

[0008] In a second aspect, the present application provides a method for manufacturing an array substrate, including:

[0009] Providing a substrate;

[0010] Forming a channel layer on one side of the substrate; the channel layer includes a plurality of first channel material regions;

[0011] Forming a first metal layer on a side of the channel layer away from the substrate; the first metal layer is provided with first gates of a plurality of first driving transistors, the first gates of the plurality of first driving transistors being respectively disposed corresponding to the plurality of first channel material regions, and the first gate orthographic projection on the channel layer overlapping with the corresponding first channel material region, the first gate orthographic projection having a first side and a second side facing away from each other in a first direction, and the first channel region being disposed close to a target side of the corresponding first side and the second side of the first gate orthographic projection;

[0012] Dope the first channel material region through the first gate to convert a portion of the first channel material region near the target edge into a first sub-region;

[0013] Wherein, the first sub-region is used together with a second sub-region as the first channel region of the first driving transistor, the second sub-region includes the first channel material region except the first sub-region, and the first doping concentration of the first sub-region is higher than the second doping concentration of the second sub-region.

[0014] In a third aspect, the present application provides a display panel, including:

[0015] The array substrate as described above, or an array substrate prepared by using the preparation method of the array substrate as described above;

[0016] A light-emitting layer, disposed on one side of the array substrate, the light-emitting layer is provided with a plurality of sub-pixels, and the plurality of sub-pixels are respectively arranged corresponding to the plurality of first driving transistors to emit light under the control of the corresponding first driving transistors.

[0017] In a fourth aspect, the present application provides a display device, including the display panel as described above.

[0018] For the above-mentioned array substrate and its preparation method, display panel and display device, by providing a channel region located in the channel layer and a first gate located in the first metal layer, and making the positive projection of the first gate on the channel layer overlap with the corresponding channel region, a first driving transistor of the sub-pixel can be formed to control the light-emitting brightness of the sub-pixel. Moreover, by providing a first sub-region with a higher first doping concentration in the first channel region, the resistance of the channel region of the first driving transistor can be reduced, so that the channel region produces an effect similar to increasing the channel width-to-length ratio compared with the setting method in the related art, thereby increasing the saturation current of the first driving transistor. By providing the second sub-region, when the first driving transistor is in the off state, the leakage current is small, thereby suppressing problems such as pixel voltage drift and brightness unevenness caused by the leakage current. Therefore, the embodiments of the present application can adjust the doping concentration of the first sub-region and the size relationship between the first sub-region and the second sub-region, so that the first driving transistor can not only meet the requirements of leakage current in the off state, but also have good conductivity and switching speed in the on state, output the required electrical signal in a shorter time, and improve the response speed and display quality of the display panel. Description of the Drawings

[0019] To more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for the description of the embodiments or related technologies. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0020] Figure 1 Partial cross-sectional schematic diagram of an array substrate according to an embodiment;

[0021] Figure 2 One of the top views of the first driving transistor according to an embodiment;

[0022] Figure 3 Cross-sectional schematic diagram of the first channel region according to an embodiment;

[0023] Figure 4 Schematic diagram of the middle part of the first channel region corresponding to the orthographic projection of the first gate;

[0024] Figure 5 Schematic diagram of the preparation of the first source contact region and the first drain contact region according to an embodiment;

[0025] Figure 6 Another top view of the first driving transistor according to an embodiment;

[0026] Figure 7 Another top view of the first driving transistor according to an embodiment;

[0027] Figure 8 Top view of the second driving transistor according to an embodiment;

[0028] Figure 9 Flow chart of the preparation method of the array substrate according to an embodiment;

[0029] Figure 10 Cross-sectional schematic diagram of the array substrate according to an embodiment.

[0030] Element number description:

[0031] Channel layer: 100; Channel region: 110; First channel region: 111; First sub-region: 1111; Second sub-region: 1112; Second channel region: 112; Source contact region: 120; First source contact region: 121; Drain contact region: 130; First drain contact region: 131; First channel extension region: 141; Second channel extension region: 142; First metal layer: 200; Gate: 210; First gate: 211; Second gate: 212; Storage capacitor plate: 310; Substrate: 400. Detailed implementation manners

[0032] In order to make the objectives, technical solutions, and advantages of this application clearer and more understandable, the following further elaborates on this application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely used to explain this application and are not used to limit this application.

[0033] It can be understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, the first metal layer may be referred to as the second metal layer, and similarly, the second metal layer may be referred to as the first metal layer.

[0034] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one of such features. The meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. The meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0035] In the array substrate of a display panel, there are usually multiple thin-film transistors (TFTs). However, in related technologies, the electrical performance of the transistors is not good, which affects the brightness of the sub-pixels. Taking two related technologies as examples, the reasons for the insufficient electrical performance of the transistors are briefly described below.

[0036] In one related technology, if the display device where the display panel is located has a heat generation problem, the characteristic curve of the thin-film transistors in the array substrate will shift, resulting in a shift in the threshold voltage Vth. Especially when displaying a low gray-scale image, since the driving current of the sub-pixels is small, a slight change in the threshold voltage Vth of the transistors will affect the driving current. In another related technology, under different bias voltages, the electric field corresponding to the bias voltage will drive charged defects such as oxygen vacancies to migrate inside the material, affecting the interface state density, or causing carriers to be injected into the semiconductor, resulting in a temporary decrease or increase in the defect concentration, thereby making the thin-film transistors exhibit different defect states. When the response of the defect state cannot keep up with the change speed of the external bias voltage, it will cause a voltage switching, resulting in a hysteresis phenomenon of the thin-film transistors.

[0037] To improve the electrical performance of transistors, researchers consider using materials with higher mobility to replace traditional silicon-based materials to form the channel region of transistors, thereby enhancing the conductivity of the channel region. Among them, materials with higher mobility include, but are not limited to, two-dimensional materials such as graphene and transition metal dichalcogenides, as well as oxide semiconductors such as zinc oxide and indium gallium zinc oxide. Taking indium gallium zinc oxide as an example, its electron mobility is relatively high, enabling electrons to move more efficiently in the channel region, thus enhancing conductivity. However, the above methods still cannot meet the requirements of users for the display quality of display panels.

[0038] Embodiments of the present application provide an array substrate. Figure 1 It is a partial cross-sectional schematic diagram of an array substrate of an embodiment. Refer to Figure 1 , the array substrate includes a channel layer 100 and a first metal layer 200.

[0039] Among them, the channel layer 100 is provided with channel regions 110 of multiple transistors. The first metal layer 200 is disposed on one side of the channel layer 100. The first metal layer 200 is provided with gates 210 of multiple transistors, and the gates 210 of the multiple transistors are respectively arranged corresponding to the channel regions 110 of the multiple transistors.

[0040] The orthographic projection of the gate 210 of the transistor on the channel layer 100 overlaps with the corresponding channel region 110. Through the overlapping arrangement of the gate 210 and the channel region 110, it can be ensured that the electric field of the gate 210 can cover the effective region of the channel region 110, avoiding electric field leakage or action blind spots, thereby realizing precise control of the on and off states of the channel region 110. When a suitable voltage is applied to the gate 210 of the transistor, a conductive channel is formed in the channel region 110, enabling current to flow between the source contact region 120 and the drain contact region 130. When the voltage of the gate 210 changes, the conductivity of the channel region 110 changes, thereby blocking the current. That is, based on the one-to-one correspondence between the gate 210 and the channel region 110, by controlling the voltage of the gate 210, the on and off states of the channel region 110 can be controlled to adjust the supply of a suitable driving current to the sub-pixel, thereby realizing precise control of the emission brightness of the sub-pixel.

[0041] Further, a source contact region 120 and a drain contact region 130 are also provided in the channel layer 100. The source contact region 120 and the drain contact region 130 are respectively disposed on both sides of the channel region 110. Exemplarily, two N regions can be formed in the P-type semiconductor as the source contact region 120 and the drain contact region 130 of the transistor. The source contact region 120 is used to connect to the source, and the drain contact region 130 is used to connect to the drain. After forming the source contact region 120, the drain contact region 130, and the channel region 110, a gate insulating layer can be covered on the side away from the substrate of the three, and a gate 210 can be formed on the side away from the substrate of the gate insulating layer to form a transistor structure. In the case where the array substrate includes a substrate, the first metal layer 200 is disposed on the side away from the substrate of the channel layer 100. When the gate 210 is located on the side away from the substrate of the channel layer 100, the distance between the gate 210 and the substrate is relatively far, thereby reducing the parasitic capacitance between the gate 210 and the substrate, enabling faster charging and discharging of the gate 210 voltage, realizing fast switching of the transistor, and reducing the dynamic power consumption.

[0042] Further, the plurality of transistors include a plurality of first driving transistors. Figure 2 FIG. 5 is one of the top view schematic diagrams of the first driving transistor according to an embodiment, Figure 2 showing a first channel region 111 and a first gate 211 corresponding to a first driving transistor. With reference to Figure 1 and Figure 2 , the channel layer 100 is provided with first channel regions 111 of a plurality of first driving transistors, the first metal layer 200 is provided with first gates 211 of a plurality of first driving transistors, the first gates 211 of the plurality of first driving transistors are respectively arranged corresponding to the plurality of first channel regions 111, and the first gate orthographic projection of the first gate 211 on the channel layer 100 overlaps with the corresponding first channel region 111.

[0043] Figure 3 FIG. 6 is a cross-sectional schematic diagram of the first channel region 111 according to an embodiment. With reference to Figure 3 , the first channel region 111 includes a first sub-region 1111 and a second sub-region 1112. Specifically, doping methods such as ion implantation or diffusion can be used to introduce an appropriate amount of doping atoms into the first channel region 111 for doping to form a first sub-region 1111 with a higher doping concentration. The free electron or hole concentration in the first sub-region 1111 is relatively high, thereby reducing the resistivity of the first sub-region 1111 and decreasing the overall resistance of the first channel region 111.

[0044] The first channel region 111 may further include a second sub-region 1112, and a first doping concentration of the first sub-region 1111 is higher than a second doping concentration of the second sub-region 1112. Optionally, the second sub-region 1112 may be set in a non-doped or lightly doped manner and has the same or similar doping concentration as the channel region 110 of a transistor in the related art. It should be noted that the doping concentration of the first sub-region 1111 may be gradient, and a doping concentration of a portion of the first sub-region 1111 far from the second sub-region 1112 is higher than a doping concentration of a portion of the first sub-region 1111 close to the second sub-region 1112. Similarly, the doping concentration of the second sub-region 1112 may also be gradient, and a doping concentration of a portion of the second sub-region 1112 far from the first sub-region 1111 is lower than a doping concentration of a portion of the second sub-region 1112 close to the first sub-region 1111. Therefore, the first doping concentration in this embodiment may be understood as an average doping concentration of the first sub-region 1111, and the second doping concentration may be understood as an average doping concentration of the second sub-region 1112.

[0045] In an embodiment of the application, by providing a channel region 110 located in a channel layer 100 and a first gate 211 located in a first metal layer 200, and enabling a positive projection of the first gate 211 on the channel layer 100 to overlap with a corresponding channel region 110, a first driving transistor of a sub-pixel may be formed to control a light-emitting brightness of the sub-pixel. Moreover, by providing a first sub-region 1111 with a relatively high first doping concentration in the first channel region 111, a resistance of the channel region 110 of the first driving transistor may be reduced, so that the channel region 110 produces an effect similar to increasing a channel width-to-length ratio compared with a setting manner in the related art, thereby improving a saturation current of the first driving transistor. By providing the second sub-region 1112, when the first driving transistor is in an off state, a leakage current may be small, thereby suppressing problems such as pixel voltage drift and brightness non-uniformity caused by the leakage current. Therefore, in the embodiment of the application, by regulating a doping concentration of the first sub-region 1111 and a size relationship between the first sub-region 1111 and the second sub-region 1112, the first driving transistor can not only meet requirements of the leakage current in the off state, but also have good conductivity and switching speed in the on state, output a required electrical signal in a shorter time, and improve a response speed and a display quality of a display panel.

[0046] With reference to Figure 2 and Figure 3, in one embodiment, the first gate orthographic projection has a first side 2111 and a second side 2112 that face away from each other in the first direction. Among them, the first channel region 111 can be understood as a strip-shaped structure extending along the second direction, and the first direction and the second direction are arranged crosswise. For example, the second direction is perpendicular to the first direction. The first channel region 111 is disposed close to the target side among the first side 2111 and the second side 2112 of the corresponding first gate orthographic projection. That is, the first distance between the first channel region 111 and the first side 2111 is different from the second distance between the first channel region 111 and the second side 2112.

[0047] Taking the outer contour of the first gate 211 as a rectangle as an example, the first gate orthographic projection is also a rectangle. Further, the extending directions of the sides of the first gate orthographic projection are correspondingly arranged with the extending direction of the first channel region 111, wherein the first side 2111 and the second side 2112 of the first gate orthographic projection are two sides parallel to the second direction. Correspondingly, the first distance between the first channel region 111 and the first side 2111 refers to the shortest distance between the first side 2111 and the outer contour of the first channel region 111 in the first direction. The second distance between the first channel region 111 and the second side 2112 refers to the shortest distance between the second side 2112 and the outer contour of the first channel region 111 in the first direction.

[0048] When doping is carried out in the same process, since the first gate 211 covers the surface of the channel layer 100 on the side away from the substrate, doping atoms cannot enter from the surface of the channel layer 100 on the side away from the substrate, but can only enter from the sidewalls of the channel layer 100. Therefore, based on the differences in different positions in the first channel region 111, the acting distances of the doping atoms are not exactly the same, so that different doping effects are produced at different positions in the first channel region 111, so as to form a first sub-region 1111 and a second sub-region 1112 with different doping concentrations in the first channel region 111, and the first sub-region 1111 and the second sub-region 1112 are arranged along the first direction, and the first sub-region 1111 is disposed close to the target side.

[0049] Figure 4 Schematic diagram of the middle part of the first gate orthographic projection corresponding to the first channel region 111, refer to Figure 4 , if the first channel region 111 is disposed corresponding to the middle part of the first gate orthographic projection, that is, the distances between the first channel region 111 and the first side 2111 and the second side 2112 of the corresponding first gate orthographic projection are the same or similar, then the shielding of the first gate 211 for the first channel layer 100 is better. During the doping process, since the acting distance of the doping ions along the sidewall direction is too long, it is easy to cause a situation where the doping effect of the first sub-region 1111 is not good.

[0050] In the embodiments of the application, the first channel region 111 is disposed deviating from the middle of the orthographic projection of the first gate, so that the first channel region 111 is closer to the target side among the first side 2111 and the second side 2112 of the orthographic projection of the first gate, which can ensure the doping effect on the first sub-region 1111, so that the first sub-region 1111 has a relatively high doping concentration. In addition, by forming the first sub-region 1111 and the second sub-region 1112 simultaneously through the same process, the number of process flows for manufacturing the first driving transistor can be reduced, and the manufacturing efficiency of the first driving transistor can be improved.

[0051] Figure 5 Schematic diagram for manufacturing the first source contact region 121 and the first drain contact region 131 in an embodiment. Refer to Figure 5 In one of the embodiments, the channel layer 100 is further provided with the first source contact regions 121 and the first drain contact regions 131 of a plurality of first driving transistors. The first source contact regions 121 and the first drain contact regions 131 are respectively disposed on both sides of the corresponding first channel region 111. In the process flow, the first source contact regions 121 and the first drain contact regions 131 can be formed by a heavy doping process. Specifically, doping can be performed from one side of the first gate 211. The doping concentrations of the first source contact regions 121 and the first drain contact regions 131 as the heavy doping regions are relatively high, and the doping concentration is generally between 10^18 and 10^20 cm^-3. The high doping concentration helps to reduce the contact resistance and improve the conductivity and switching speed of the first driving transistor.

[0052] Specifically, the following process flow can be adopted to form the first source contact regions 121 and the first drain contact regions 131: form the channel layer 100 on one side of the substrate. The channel layer 100 includes a plurality of first channel material regions, and the materials of the first channel material regions include but are not limited to amorphous silicon (a-Si), low-temperature polycrystalline silicon (LTPS), or indium gallium zinc oxide (IGZO). Then, form the first metal layer 200 on the side of the channel layer 100 away from the substrate. The first metal layer 200 is provided with the first gates 211 of a plurality of first driving transistors. The orthographic projection of the first gate covers a part of the corresponding first channel material region and exposes another part of the corresponding first channel material region. The exposed first channel material region includes two sub-parts, which are respectively located on both sides of the first channel material region covering the orthographic projection of the first gate.

[0053] Based on the above structure, the first gate 211 can be used as a hard mask layer, and the exposed first channel material region can be doped through the first gate 211 to convert the exposed first channel material region into a first source contact region 121 and a first drain contact region 131. When doping to form the first source contact region 121 and the first drain contact region 131, due to the diffusion effect, some doping atoms will diffuse into a part of the first channel material region that overlaps with the positive projection of the first gate, thereby converting a part of the first channel material region into a first sub-region 1111, specifically converting the part of the first channel material region close to the target edge into the first sub-region 1111 ( Figure 5 not shown). Therefore, the target doping process of this embodiment can simultaneously form the first source contact region 121 and the first drain contact region 131, and form the first sub-region 1111 and the second sub-region 1112. Among them, the doping concentrations of the first source contact region 121 and the first drain contact region 131 are similar and greater than the first doping concentration of the first sub-region 1111.

[0054] Correspondingly, the process parameters of the target doping process can be determined according to the requirements such as the doping concentration and doping depth of the first source contact region 121 and the first drain contact region 131 to ensure the doping effect of the first source contact region 121 and the first drain contact region 131. Among them, the process parameters of the target doping process include but are not limited to at least one of doping temperature, doping concentration, doping time, etc. Further, the effective action distance of the doping atoms acting on the first channel region 111 can be obtained according to the above process parameters, and the effective action distance can be used as a preset distance threshold, so as to determine the distance between the first channel region 111 and the target edge of the corresponding first gate positive projection, and make the above distance less than the preset distance threshold to ensure that the first sub-region 1111 can be doped well.

[0055] In one embodiment, the channel layer 100 further includes a lightly doped region, which is located between the first source contact region 121 and the first drain contact region 131 and is adjacent to the first channel region 111. The doping concentration of the lightly doped region is relatively low, usually between 10^15 and 10^17 cm^-3. Optionally, the lightly doped region can be formed synchronously with the first source contact region 121, the first drain contact region 131 and the first sub-region 1111 based on the diffusion effect in the foregoing target doping process, or the lightly doped region can also be formed by another doping process, which is not limited in this embodiment. In the embodiment of the application, by adding a lightly doped region between the first source contact region 121 and the first drain contact region 131, the series resistance can be effectively increased, thereby reducing the electric field strength of the first drain contact region 131, thereby reducing the hot carrier effect and the short channel effect.

[0056] Continue to refer to Figure 2, in one embodiment, the outer contours of the first channel region 111 and the first gate 211 are both axisymmetric figures. The first channel region 111 of the first driving transistor is a linear bar-shaped structure, and the extending direction of the first channel region 111 is the second direction. The first channel region 111 has a first axis of symmetry extending along the second direction, and the second direction is perpendicular to the first direction. The outer contour of the first gate 211 includes, but is not limited to, any axisymmetric figure such as a rectangle, a square, a rounded rectangle, etc. The first gate 211 has a second axis of symmetry extending along the second direction. Among them, the first axis of symmetry and the second axis of symmetry are staggered in the first direction, so that the distances between the first channel region 111 and the first side 2111 and the second side 2112 of the corresponding first gate's orthographic projection are different, and it is arranged close to the target side among the first side 2111 and the second side 2112 of the corresponding first gate's orthographic projection, thereby shortening the distance between the first channel region 111 and the target side, ensuring that the doping atoms can diffuse well, so as to form a first sub-region 1111 with a relatively high doping concentration in the first channel region 111.

[0057] Figure 6 is the second top view schematic diagram of the first driving transistor in an embodiment. Refer to Figure 6 , in one embodiment, one first driving transistor is correspondingly provided with two first channel regions 111, and the two first channel regions 111 are respectively arranged on both sides of the second axis of symmetry. Specifically, by arranging the two first channel regions 111, one first channel region 111 can be close to the first side 2111 of the corresponding first gate's orthographic projection, and the other first channel region 111 can be close to the second side 2112 of the corresponding first gate's orthographic projection. During doping, the corresponding first sub-regions 1111 can be respectively formed in each first channel region 111. Even if the diffusion distance of the doping atoms on one side of the first side 2111 and the second side 2112 is insufficient, the setting method of this embodiment can diffuse from both sides and respectively form the first sub-regions 1111 in each first channel region 111, so that the two first sub-regions 1111 can have a larger total width in the first direction, improving the overall conductivity of the first driving transistor.

[0058] In one embodiment, the two first channel regions 111 are symmetrically arranged with respect to the second axis of symmetry, which can make the electric field strengths near the first side 2111 and the second side 2112 in the channel region 110 of the first driving transistor similar, so that the electric field distribution in the channel region 110 of the first driving transistor is more uniform, reducing the situation of unilateral leakage current. In addition, due to the limitations of the lithography process, an overly wide channel may exceed the fine control ability of the lithography process, resulting in irregular edges or line width deviations, affecting the performance consistency of the transistor. Moreover, due to the limitations of the film forming process, a large-area channel may have uneven current distribution due to the uniformity defects of the thin film material. Therefore, the setting method of using two first channel regions 111 in this embodiment can further reduce the performance impact of the first driving transistor caused by process defects on the premise that the total area of the first channel regions 111 in the first driving transistor does not decrease, thereby improving the performance of the first driving transistor.

[0059] Exemplarily, the channel width of each first channel region 111 in the first driving transistor can be set to 2 um. Then, based on the two symmetrically arranged first channel regions 111, the total channel width of the two first channel regions 111 is 4 um. In the conventional single first channel region 111 scheme, when the upper limit of the channel width is 3 um and the channel length is also 10 um, the setting method of this embodiment can increase the channel width-to-length ratio of the first driving transistor from 3 / 10 to 4 / 10, thereby effectively improving the channel width-to-length ratio.

[0060] Continue to refer to Figure 6 , in one embodiment, the channel layer 100 is further provided with a first channel extension region 141 and a second channel extension region 142. The first channel extension region 141 is used to connect one end of the first channel region 111 to the first source contact region 121, and the second channel extension region 142 is used to connect the other end of the first channel region 111 to the first drain contact region 131. Among them, the number of the first channel extension region 141 and the second channel extension region 142 is two each, and one first channel region 111 is respectively connected to a corresponding first channel extension region 141 and a second channel extension region 142. The doping concentrations of the first channel extension region 141 and the second channel extension region 142 can be the same. The first channel extension region 141 is between the doping concentration of the first channel region 111 and the doping concentration of the first source contact region 121, and the second channel extension region 142 is between the doping concentration of the first channel region 111 and the doping concentration of the first drain contact region 131. In the embodiments of the application, by setting the first channel extension region 141 and the second channel extension region 142, effective conduction between the first source contact region 121, the first drain contact region 131 and the first channel region 111 can be achieved to provide a current transmission path.

[0061] Figure 7The third top view schematic diagram of the first driving transistor in an embodiment, reference Figure 7 , in one embodiment, the channel layer 100 further includes a first channel extension region 141 and a second channel extension region 142. The first channel extension region 141 is used to connect one end of the first channel region 111 to the first source contact region 121, and the second channel extension region 142 is used to connect the other end of the first channel region 111 to the first drain contact region 131. Wherein, the number of the first channel extension region 141 and the second channel extension region 142 is one each, and the two first channel regions 111 are connected to the same first channel extension region 141 and second channel extension region 142. The doping concentrations of the first channel extension region 141 and the second channel extension region 142 may be the same. The first channel extension region 141 is between the doping concentration of the first channel region 111 and the doping concentration of the first source contact region 121, and the second channel extension region 142 is between the doping concentration of the first channel region 111 and the doping concentration of the first drain contact region 131. In the embodiment of the application, by providing the first channel extension region 141 and the second channel extension region 142, effective conduction between the first source contact region 121, the first drain contact region 131 and the first channel region 111 can be achieved to provide a current transmission path. Moreover, compared with the previous embodiment, the areas of the first channel extension region 141 and the second channel extension region 142 in this embodiment are larger. On the premise that the doping concentrations of the first channel extension region 141 and the second channel extension region 142 are greater than the doping concentration of the first channel region 111, the conductivity of the first driving transistor can be further improved, thereby improving the display effect.

[0062] In the related art, if the influence degrees of the thin film transistors corresponding to sub-pixels of different colors are not exactly the same, the light emitting brightness of sub-pixels of different colors will be different, which is manifested as the color shift problem of the display panel. The following takes two related technologies as examples to briefly illustrate the occurrence reasons of the color shift problem of the display panel.

[0063] In a related technology, since the driving currents of sub-pixels of different colors are not exactly the same, the brightness of sub-pixels of different colors is also not affected by temperature in exactly the same way. Among them, the smaller the driving current of a sub-pixel, the greater the influence of its brightness by temperature. Taking an OLED display panel as an example, OLED materials of different colors may have different electroluminescence efficiencies, that is, different currents are required to generate the same brightness. For example, green light materials usually have higher efficiency, so a smaller driving current may be required to achieve the same brightness, while blue light materials have lower efficiency and may require a larger driving current. Correspondingly, under the same temperature influence, the brightness change of green sub-pixels will be greater, resulting in a green color shift in the display panel at high temperatures. In another related technology, since the driving currents of sub-pixels of different colors are not exactly the same, a larger driving current may make the change of the defect state more obvious, resulting in a longer hysteresis time, while a smaller driving current may make the change of the defect state smaller, resulting in a shorter hysteresis time. For example, green light materials usually have higher efficiency, so a smaller driving current may be required to achieve the same brightness, while blue light materials have lower efficiency and may require a larger driving current. Based on this, the long hysteresis time of blue sub-pixels will cause the display effect of blue sub-pixels to fail to meet the requirements, resulting in a color shift in the display panel.

[0064] In order to alleviate the color shift problem of the above display panel, in one embodiment, the channel layer 100 is further provided with second channel regions 112 of a plurality of second driving transistors, and the conductivity of the second channel regions 112 is weaker than that of the first channel region 111. Among them, the first driving transistor and the second driving transistor are used to drive sub-pixels with different emission colors. Further, the colors of the sub-pixels driven by different second driving transistors may not be exactly the same. For example, the first driving transistor is used to drive blue sub-pixels, some second driving transistors are used to drive red sub-pixels, and some other second driving transistors are used to drive green sub-pixels.

[0065] Specifically, since different transistors in the array substrate have different characteristic requirements, the conductivity of the first driving transistor and the second driving transistor can be made different by adjusting the doping concentration of the channel region 110. For example, a first sub-region 1111 with a first doping concentration and a second sub-region 1112 with a second doping concentration are provided in the first channel region 111 of the first driving transistor, and only the second sub-region 1112 with the second doping concentration is provided in the second channel region 112 of the second driving transistor, so that the conductivity of the second channel region 112 is weaker than that of the first channel region 111. Further, the first driving transistor and the second driving transistor can have different channel lengths. Figure 8 A top view schematic diagram of the second driving transistor in an embodiment, refer to Figure 8, the second driving transistor may include a plurality of channel segments with different extending directions, and the plurality of channel segments are connected to form a second channel region 112 of the second driving transistor. Exemplarily, as Figure 8 shown, the second channel region 112 includes two first channel segments extending in a first direction and three second channel segments extending in a second direction, and the first channel segments and the second channel segments are alternately arranged. Accordingly, the second driving transistor further includes a first gate 212 disposed on the first metal layer 200.

[0066] In one embodiment, the array substrate further includes a second metal layer. The second metal layer is disposed on a side of the first metal layer 200 away from the channel layer 100. With reference to Figure 2 , Figure 4 , Figure 6 and Figure 8 , the second metal layer is provided with a plurality of storage capacitor plates 310, and the plurality of storage capacitor plates 310 are respectively arranged corresponding to the gates 210 of the plurality of transistors. That is, the storage capacitor plates 310 corresponding to the gates 210 face each other, and the orthographic projection of the outer contour of the storage capacitor plates 310 on the first metal layer 200 at least partially overlaps to form a storage capacitor in the pixel driving circuit. The storage capacitor is used to store the electric charge corresponding to the data signal during the data writing stage and provide a corresponding voltage to the transistor during the light emitting stage to control the driving current output by the transistor. Wherein, the outer contour shape of the storage capacitor plate 310 is the same as the outer contour shape of the gate 210. By setting the storage capacitor plates 310 and the gates 210 with the same shape, the uniformity of the electric field distribution in the capacitor region can be improved.

[0067] At the same time, the size of the storage capacitor plate 310 is greater than or equal to the size of the corresponding gate 210, so that the orthographic projection of the outer contour of the storage capacitor plate 310 on the first metal layer 200 covers the corresponding gate 210. Further, the size of the storage capacitor plate 310 is greater than the size of the corresponding gate 210. The larger storage capacitor plate 310 can increase the capacitance value, while the smaller gate 210 is used to connect the transistor, so as to achieve a higher charge storage capacity within a limited pixel. Moreover, the storage capacitor plates 310 and the gates 210 with different sizes can reduce the process difficulty and reduce the influence of process fluctuations on the capacitance value of the storage capacitor, ensuring good performance consistency between different array substrates. It should be noted that the first driving transistor and the second driving transistor may have the gates 210 and the storage capacitor plates 310 with the same shape to reduce the design difficulty of the gates 210 and the storage capacitor plates 310.

[0068] The embodiment of the present application further provides a method for manufacturing an array substrate. Figure 9 is a flowchart of a method for manufacturing an array substrate according to an embodiment. Figure 10FIG. 1 is a cross-sectional schematic diagram of an array substrate of an embodiment. It should be noted that: Figure 10 The cross-sectional view of FIG. 1 does not show the first sub-area 1111 and the second sub-area 1112. Figure 9 and Figure 10 , the method for preparing the array substrate includes steps 902 to 908.

[0069] Step 902 , providing a substrate 400 .

[0070] The substrate 400 may be a hard substrate 400 made of glass or a flexible substrate 400 made of polyimide or the like. Specifically, the substrate 400 may be ultrasonically cleaned and rinsed with deionized water, organic solvents, and chemical reagents, and the surface of the substrate 400 may be dried by drying or nitrogen blowing to ensure the quality of subsequent thin film deposition.

[0071] Step 904 , forming a channel layer 100 on one side of the substrate 400 .

[0072] Among them, the channel layer 100 includes multiple first channel material areas. The materials of the first channel material area include but are not limited to amorphous silicon, low-temperature polycrystalline silicon or indium gallium zinc oxide. After forming the first channel material area of amorphous silicon or low-temperature polycrystalline silicon, the crystallinity and carrier mobility of silicon can be improved by laser annealing and other treatments. Furthermore, before forming the channel layer 100, a buffer layer (Buffer) can be deposited on the cleaned substrate 400 to inhibit the diffusion of impurities in the substrate 400 into the channel layer 100 and enhance the adhesion between the channel layer 100 and the substrate 400.

[0073] Step 906 , forming a first metal layer 200 on a side of the channel layer 100 away from the substrate 400 .

[0074] Among them, the first metal layer 200 is provided with a plurality of first driving transistors' first gates 211, and the plurality of first driving transistors' first gates 211 are respectively arranged corresponding to the plurality of first channel material regions, and the first gate orthographic projection of the first gate 211 on the channel layer 100 overlaps with the corresponding first channel material region, and the first gate orthographic projection has a first edge 2111 and a second edge 2112 opposite to each other in a first direction, and the first channel region 111 is arranged close to the target edge of the first edge 2111 and the second edge 2112 of the corresponding first gate orthographic projection.

[0075] Specifically, the material of the first metal layer 200 includes but is not limited to conductive metals such as molybdenum, aluminum, and copper. During the preparation process, a conductive metal thin film can be first formed on the front side, and a photoresist can be coated on the surface of the conductive metal thin film and exposed, so as to transfer the pattern of the first gate 211 onto the photoresist. Then, the metal thin film not protected by the photoresist can be removed by an etching process, thereby forming the first gate 211. Further, before forming the first metal layer 200, a gate insulating layer can be deposited on the channel layer 100 to ensure good insulation performance between the first gate 211 and the channel layer 100.

[0076] Step 908: Dope the first channel material region through the first gate 211 to convert the part of the first channel material region close to the target edge into the first sub-region 1111.

[0077] Among them, the first sub-region 1111 and the second sub-region 1112 are jointly used as the first channel region 111 of the first driving transistor. The second sub-region 1112 includes the first channel material region except the first sub-region 1111, and the first doping concentration of the first sub-region 1111 is higher than the second doping concentration of the second sub-region 1112. Specifically, boron ions can be implanted to dope the first channel material region to convert the part of the first channel material region close to the target edge into the first sub-region 1111. After ion implantation, an annealing process can be performed to activate the implanted doping atoms and make them enter the lattice positions, and at the same time repair the damage to the semiconductor lattice caused by ion implantation. The annealing methods include but are not limited to rapid thermal annealing and laser annealing.

[0078] In the embodiments of the application, through the above method for preparing the array substrate, by setting the channel region 110 located in the channel layer 100 and the first gate 211 located in the first metal layer 200, and making the orthographic projection of the first gate 211 on the channel layer 100 overlap with the corresponding channel region 110, the first driving transistor of the sub-pixel can be formed to control the light emission brightness of the sub-pixel. Moreover, by setting the first sub-region 1111 with a higher first doping concentration in the first channel region 111, the resistance of the channel region 110 of the first driving transistor can be reduced, so that the channel region 110 produces an effect similar to increasing the channel width-to-length ratio compared with the setting method in the related art, thereby increasing the saturation current of the first driving transistor. By setting the second sub-region 1112, when the first driving transistor is in the off state, the leakage current can be small, thereby suppressing problems such as pixel voltage drift and brightness non-uniformity caused by the leakage current. Therefore, in the embodiments of the application, by adjusting the doping concentration of the first sub-region 1111 and the size relationship between the first sub-region 1111 and the second sub-region 1112, the first driving transistor can not only meet the requirements of the leakage current in the off state, but also have good conductivity and switching speed in the on state, output the required electrical signal in a shorter time, and improve the response speed and display quality of the display panel.

[0079] In one embodiment, the positive projection of the first gate covers a part of the corresponding first channel material region and exposes another part of the corresponding first channel material region. The exposed first channel material region includes two sub-parts, which are respectively located on both sides of the first channel material region covering the positive projection of the first gate. The step of doping the first channel material region through the first gate 211 to convert the part of the first channel material region close to the target edge into the first sub-region 1111 includes: using the first gate 211 as a hard mask layer and doping the exposed first channel material region through the first gate 211 to convert the exposed first channel material region into the first source contact region 121 and the first drain contact region 131, and converting the part of the first channel material region close to the target edge into the first sub-region 1111. Specifically, when doping to form the first source contact region 121 and the first drain contact region 131, due to the diffusion effect, some doping atoms will diffuse into a part of the first channel material region that overlaps with the positive projection of the first gate, so as to convert a part of the first channel material region into the first sub-region 1111.

[0080] An embodiment of the present application further provides a display panel, including a light-emitting layer and the array substrate as described above. Among them, the light-emitting layer is disposed on one side of the array substrate. Among them, in the case where the display panel includes the substrate 400, the light-emitting layer may be disposed on the side of the array substrate away from the substrate 400. The light-emitting layer is provided with a plurality of sub-pixels, and the plurality of sub-pixels are respectively arranged corresponding to a plurality of transistors to emit light under the control of the corresponding transistors. The sub-pixel may include any one of a plasma display, an organic light emitting diode (OLED), an electro-wetting display (EWD), an electro-phoretic display (EPD), or an electro-chromic display (ECD), etc.

[0081] In one embodiment, the defect states of the first driving transistor and the second driving transistor are different at the same gray scale level, and the light-emitting color of the sub-pixel driven by the first driving transistor is different from the light-emitting color of the sub-pixel driven by the second driving transistor. Specifically, since the defect states of sub-pixels of different colors are not exactly the same at the same gray scale level, taking an OLED display panel as an example, OLED materials of different colors may have different electroluminescence efficiencies, that is, different currents are required to generate the same brightness. Correspondingly, the defect states of sub-pixels of different colors are also different at the same gray scale level, so that the hysteresis durations corresponding to sub-pixels of different colors in the display panel are different and color shift occurs.

[0082] In the embodiments of the application, based on the different emission colors of the sub-pixels corresponding to the first driving transistor and the second driving transistor, the first driving transistor is set for the sub-pixel with a longer hysteresis duration. The first sub-region 1111 in the first channel region 111 helps to reduce the resistance of the first driving transistor, accelerate the charging efficiency, and output the required electrical signal in a shorter time. Based on this, the sub-pixel corresponding to the first driving transistor can have a faster response speed, and thus can balance the brightness between sub-pixels of different colors to suppress the color shift problem of the display panel.

[0083] In one of the embodiments, the light-emitting layer includes blue sub-pixels and green sub-pixels. The emission color of the sub-pixel driven by the first driving transistor includes blue, and the emission color of the sub-pixel driven by the second driving transistor includes green. Further, the light-emitting layer further includes red sub-pixels. Exemplarily, the red sub-pixel may correspond to being driven by either the first driving transistor or the second driving transistor.

[0084] The embodiments of the present application further provide a display screen, which includes a cover plate and the display panel as described above. The cover plate is disposed on the light-emitting side of the display panel and covers the display panel. In this embodiment, by providing the cover plate, the display panel can be protected, and the damage to the display panel caused by external forces can be reduced, thereby improving the reliability of the display panel.

[0085] The embodiments of the present application further provide a display device. In this embodiment, based on the aforementioned display panel and display screen, a display device with a smaller color shift at high temperatures is provided. Specifically, the display device can be, but is not limited to, various personal computers, laptop computers, smart phones, tablet computers, Internet of Things devices, and portable wearable devices. The Internet of Things devices can be smart speakers, smart TVs, smart air conditioners, smart vehicle-mounted devices, etc. The portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc.

[0086] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0087] The above embodiments only represent several implementation manners of the embodiments of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the embodiments of the present application, several deformations and improvements can still be made, and these all belong to the protection scope of the embodiments of the present application. Therefore, the protection scope of the patent of the embodiments of the present application should be subject to the appended claims.

Claims

1. An array substrate, characterized in that, Comprising: A channel layer having a first channel region of a plurality of first driving transistors; A first metal layer disposed on one side of the first channel layer, the first metal layer having first gates of the plurality of first driving transistors, the first gates of the plurality of first driving transistors being respectively disposed corresponding to the plurality of first channel regions, and the first gate orthogonally projected onto the channel layer overlapping the corresponding first channel region; Wherein, the first channel region includes a first sub-region and a second sub-region, and a first doping concentration of the first sub-region is higher than a second doping concentration of the second sub-region.

2. The array substrate according to claim 1, wherein The first gate orthogonally projected has a first side and a second side opposite to each other in a first direction, and the first channel region is disposed close to a target side of the corresponding first gate orthogonally projected among the first side and the second side to form the first sub-region and the second sub-region in the same process; Wherein, the first sub-region and the second sub-region are arranged along the first direction, and the first sub-region is disposed close to the target side.

3. The array substrate according to claim 1, wherein Outer contours of both the first channel region and the first gate are axisymmetric figures, an extending direction of the first channel region is a second direction, and the second direction is perpendicular to the first direction; Wherein, the first channel region has a first symmetry axis extending along the second direction, the first gate has a second symmetry axis extending along the second direction, and the first symmetry axis and the second symmetry axis are offset in the first direction.

4. The array substrate according to claim 2 or 3, characterized in that, The channel layer further has first source contact regions and first drain contact regions of the plurality of first driving transistors, and the first source contact regions and the first drain contact regions are respectively disposed on two sides of the corresponding first channel region; Wherein, a distance between the first channel region and the target side of the corresponding first gate orthogonally projected is less than a preset distance threshold, and the preset distance threshold is determined according to process parameters of a target doping process, and the target doping process is used to form the first source contact regions and the first drain contact regions and to form the first sub-region and the second sub-region.

5. The array substrate according to claim 3, wherein One of the first driving transistors is correspondingly provided with two of the first channel regions, the two first channel regions are respectively disposed on two sides of the second symmetry axis, and the two first channel regions are symmetrically disposed with respect to the second symmetry axis.

6. The array substrate according to claim 5, wherein The channel layer further has: A first channel extension region for connecting one end of the first channel region to the first source contact region; A second channel extension region for connecting the other end of the first channel region to the first drain contact region; Wherein, numbers of both the first channel extension region and the second channel extension region are two, and one of the first channel regions is respectively connected to a corresponding one of the first channel extension region and a corresponding one of the second channel extension region; or Numbers of both the first channel extension region and the second channel extension region are one, and the two first channel regions are connected to the same first channel extension region and the same second channel extension region.

7. The array substrate according to claim 1, characterized in that The channel layer further has second channel regions of a plurality of second driving transistors, and conductivity of the second channel regions is weaker than conductivity of the first channel regions; Among them, the first driving transistor and the second driving transistor are used to drive sub-pixels with different emission colors.

8. A method for preparing an array substrate, characterized in that, Comprising: Providing a substrate; Forming a channel layer on one side of the substrate; the channel layer includes a plurality of first channel material regions; Forming a first metal layer on the side of the channel layer away from the substrate; the first metal layer is provided with first gates of a plurality of first driving transistors, the first gates of the plurality of first driving transistors are respectively arranged corresponding to the plurality of first channel material regions, and the first gate orthographic projection on the channel layer overlaps with the corresponding first channel material region, the first gate orthographic projection has a first side and a second side facing away from each other in a first direction, and the first channel region is arranged close to a target side among the first side and the second side of the corresponding first gate orthographic projection; Doping the first channel material region through the first gate to convert a portion of the first channel material region close to the target side into a first sub-region; Among them, the first sub-region is used to jointly serve as the first channel region of the first driving transistor with a second sub-region, the second sub-region includes the first channel material region other than the first sub-region, and the first doping concentration of the first sub-region is higher than the second doping concentration of the second sub-region.

9. A display panel, characterized in that, Comprising: The array substrate according to any one of claims 1 to 7, or the array substrate prepared by the preparation method of the array substrate according to claim 8; An emission layer, provided on one side of the array substrate, the emission layer is provided with a plurality of sub-pixels, and the plurality of sub-pixels are respectively arranged corresponding to the plurality of first driving transistors to emit light under the control of the corresponding first driving transistors.

10. A display device, characterized in that, Including the display panel according to claim 9.

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