Server

Abstract

The invention discloses a server, which relates to the technical field of servers, and is characterized in that a management control board is vertically fixed on a mainboard instead of arranging the management control board and the mainboard side by side on the same horizontal plane, so that the size of a server main board card in the length direction is only the size of the mainboard in the length direction; the overall size of the main board and the management control board after the main board and the management control board are overlapped in the length direction is not the overall size of the main board and the management control board after the main board and the management control board are overlapped in the length direction, due to the fact that pluggable packaging is larger than the packaging size of ball grid array packaging, one first flash memory and one second flash memory are arranged to be in pluggable packaging, and the other first flash memories and the other second flash memories are in ball grid array packaging. Therefore, the size of the management control board can be reduced as much as possible while the debugging requirement of the board card in the initial stage and the online burning requirement after complete later function development can be met, so that the purpose of integrally reducing the sizes of the server main body board card in multiple directions is achieved.

Description

Technical Field

[0001] This application relates to the technical field of servers, and particularly to a server. Background Art

[0002] With the rapid development of artificial intelligence technology, especially the increasingly wide application of large-scale deep learning models (such as speech recognition, image processing, and natural language processing, etc.), the demand for computing resources has also increased sharply. Modern servers provide powerful parallel computing capabilities by integrating high-performance CPUs and GPUs, and can efficiently process massive data and complex algorithms.

[0003] In the related art, the server circuit board consists of a main board and a management controller board. Refer to Figure 1 , and the two are in the same horizontal space. The management control board is connected to the main board through a gold finger interface. With this design scheme, the server main board card (main board + management control board) extends significantly in the length direction, exceeding the size range that can be accommodated by a standard chassis, resulting in the machine being unable to be placed normally in the standard chassis, which limits the physical deployment compatibility of the server. In addition, the excessive length of the server main board card increases the limiting conditions for the internal wiring layout of the PCB (printed circuit board), and it is easy to have over-long wiring. In a server, over-long wiring will cause problems such as signal attenuation and crosstalk, increasing the risk of abnormal signal quality and affecting the overall stable operation of the server. Summary of the Invention

[0004] This application provides a server to at least solve the problem that the server main board card has an excessive size in the length direction in the related art.

[0005] This application provides a server, including a main board and a management control board; The main board includes a first processor and first accessory devices; the management control board includes a second processor and second accessory devices; the second accessory devices include at least two first flash memories and at least two second flash memories. The first flash memories are used to provide storage services for the first processor, and the second flash memories are used to provide storage services for the second processor; The management control board is vertically fixed on the main board, and the management control board is communicatively connected to the main board; One of the first flash memories and one of the second flash memories are encapsulated in a pluggable manner and installed on the management control board through a socket; the remaining first flash memories and second flash memories are encapsulated by ball grid array and directly mounted on the management control board.

[0006] With this application, since the management control board is vertically fixed to the main board instead of being arranged side by side with the main board on the same horizontal plane, the length dimension of the server main board card can be only the length dimension of the main board itself, rather than the total dimension after the superposition of the main board and the management control board in the length direction. Therefore, the technical solution of this application can effectively achieve the purpose of reducing the dimension of the server main board card in the length direction. In addition, since the pluggable package is larger than the ball grid array package in terms of package size, by arranging a first flash memory and a second flash memory to be packaged in a pluggable manner and installed on the management control board through a socket; the remaining first flash memories and second flash memories are packaged by ball grid array and directly mounted on the management control board, the purpose is to reduce the size of the management control board as much as possible while ensuring that the initial debugging requirements of the board card during the backplane return and the on-line programming requirements after the completion of the later function development can be met.

[0007] The reduction in the dimension of the server main board card in the length direction and the reduction in the size of the management control board itself mean that it is easier to adapt to the internal space dimension requirements of the standard chassis, improving the physical deployment compatibility of the server. In addition, the shortening of the length of the main board card also means that the space limitation on the internal wire routing layout of the printed circuit board (PCB) used to make the board card is correspondingly reduced, thereby reducing the possibility of ultra-long wire routing, further reducing the risks of signal quality anomalies such as signal attenuation and crosstalk caused by too long signal transmission paths, and enhancing the stability and reliability of the overall operation of the server.

[0008] The server provided by the technical solution of this application is particularly suitable for the field of artificial intelligence (AI) servers, and AI servers can be used to support the operation of large-scale deep learning models. In the current mainstream AI server architecture, the design method of directly connecting multiple GPU nodes to the CPU through PCIe at high speed is usually adopted. To ensure the stability and efficiency of signal transmission, the system puts forward strict requirements for the signal transmission path between the CPU and the GPU, that is, the wire routing distance should be shortened as much as possible to reduce signal delay and attenuation. Since the dimension of the server main board card in the length direction is shortened in the technical solution provided by this application, greater flexibility is provided in the PCB wiring design, which is conducive to planning a wire routing layout that meets the requirement of a shorter signal path from the CPU to the GPU in the AI server. Therefore, the technical solution of this application can not only improve the hardware management efficiency of the AI server, but also better meet its requirements for high-performance computing and high-speed interconnection. Brief Description of the Drawings

[0009] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0010] Figure 1 It is a schematic structural diagram of a server main board card in the related art; Figure 2 It is a schematic structural diagram of a server provided by an embodiment of the present application; Figure 3 It is a schematic structural diagram of a server main board card provided by an embodiment of the present application; Figure 4 It is a schematic connection diagram of a management control board and a main board provided by an embodiment of the present application; Figure 5 It is a schematic diagram of the first surface of a management control board provided by an embodiment of the present application; Figure 6 It is a schematic diagram of the second surface of a management control board provided by an embodiment of the present application; Figure 7 It is a schematic partial structure diagram of a management control board provided by an embodiment of the present application; Figure 8 It is a schematic three-dimensional structure diagram of a management control board provided by an embodiment of the present application; Figure 9 It is a schematic connection relationship diagram of a management control board and a first connector provided by an embodiment of the present application; Figure 10 It is a schematic connection relationship diagram of a first connector and a main board provided by an embodiment of the present application; Figure 11 It is a schematic SPI topology structure diagram of a management control board provided by an embodiment of the present application; Figure 12 It is a schematic JTAG topology structure diagram of a management control board provided by an embodiment of the present application; Figure 13 It is a schematic UART and LTPI topology structure diagram of a management control board provided by an embodiment of the present application; Figure 14 It is a schematic network topology structure diagram of a management control board provided by an embodiment of the present application; Figure 15 It is a schematic VGA and USB topology structure diagram of a management control board provided by an embodiment of the present application. Detailed implementation manners

[0011] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0012] It should be noted that in the description of the present application, the terms "including", "comprising" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0013] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0014] The present application provides a server, which includes a main board and a management control board; the main board includes a first processor and first accessories; the management control board includes a second processor and second accessories; the second accessories include at least two first flash memories and at least two second flash memories, the first flash memory is used to provide storage services for the first processor, and the second flash memory is used to provide storage services for the second processor; the management control board is vertically fixed on the main board, and the management control board is communicatively connected to the main board. One first flash memory and one second flash memory are encapsulated in a pluggable manner and installed on the management control board through a socket; the remaining first flash memories and second flash memories are encapsulated by ball grid array and directly mounted on the management control board.

[0015] Exemplarily, Figure 2 is a schematic structural diagram of a server provided by an embodiment of the present application; Figure 3 is a schematic structural diagram of a main board card of a server provided by an embodiment of the present application; Figure 4 is a schematic connection diagram of a management control board and a main board provided by an embodiment of the present application. Refer to Figure 2 , the server is of 8U or 10U specification. Among them: In the 8U server, 6U layout space is reserved for the GPU (Graphics Processing Unit); in the 10U server, 8U layout space is reserved for the GPU to achieve a higher computing power density. The PSU (Power Supply Unit) occupies 1U layout space, and the actual available layout space of the server main board card is 1U, and the overall space resources are extremely compact.

[0016] See Figure 3 and Figure 4 , the server includes a main board 1 and a management control board 2; the main board 1 includes a first processor and first accessory devices; the management control board 2 includes a second processor and second accessory devices; the management control board 2 is vertically fixed on the main board 1, and the management control board 2 is communicatively connected to the main board 1.

[0017] This application does not limit what specific devices the first processor and the first accessory devices refer to. Exemplarily, the first processor may be a CPU (Central Processing Unit). The first accessory devices may include one or more of the following: PDB (Power Distribution Board), PWR-CON (Power Connector), OCP (Open Compute Project) network card, radiator, solid state drive, PHY (Physical Layer) device, etc.

[0018] Similarly, this application does not limit what specific devices the second processor and the second accessory devices refer to. Exemplarily, the second processor may be a BMC (Baseboard Management Controller). The second accessory devices may include one or more of the following: CPLD (Complex Programmable Logic Device), JTAG (Joint Test Action Group) connector, TPM (Trusted Platform Module), EEPROM (Electrically Erasable Programmable Read-Only Memory), voltage regulator, EMMC (Embedded Multi-Media Card), BIOS (Basic Input / Output System) flash memory, BMC flash memory, DRAM (Dynamic Random-Access Memory), PHY device.

[0019] Among them, the voltage regulator, also known as VR, is used to convert the P12V_STBY input from the main board through the gold fingers into other voltage values to supply power to other devices. The BMC is the core device for server system management. The BMC flash memory, also known as BMCFLASH, is the medium for storing the BMC's image file, and the program that the BMC runs is determined by this. The BIOS flash memory, also known as BIOSFLASH, is the medium for storing the BIOS's image file, and the program that the CPU runs is determined by this. The EMMC is a storage medium with a large storage scale, where the running LOG of the BMC can be stored or the BMC's OS system can be installed in the EMMC to run some top-level applications. The CPLD is mainly used to implement the power-on management and control function on the board card and interact with the BMC, and the interaction method is mainly achieved through GPIO signals. The core role of the CPLD is to communicate with the main board, specifically including encoding and converting the parallel bus signals transmitted from the main board side into a serial bus form for transmission, decoding and restoring the serial signals inside itself, and then forwarding the relevant status information to the BMC for system monitoring and management use. The PHY is used to convert the BMC's gigabit network signal RGMII into SGMII, so that the network signal transmission rate becomes higher and the wiring length can be extended. The DRAM is the medium for the BMC to obtain memory and is used for acceleration during task processing. The TPM is used for security verification during the BMC startup.

[0020] Optionally, when the first processor is the CPU, the first flash memory is the BIOS flash memory. When the second processor is the BMC, the second flash memory is the BMC flash memory.

[0021] Set the number of the first flash memory and the second flash memory on the management control board to at least two, and the purpose is to achieve redundant design of the storage function. By setting multiple flash memories, in the case that one of the flash memories fails or the data is damaged, the other normal flash memories can continue to undertake the data storage and reading functions, so as to ensure the continuous operation of the system and data integrity. This redundant configuration method effectively improves the reliability and fault tolerance of the management control board during operation.

[0022] "A first flash memory and a second flash memory are encapsulated in a pluggable manner and installed on the management control board through a socket." For example, the first flash memory and the second flash memory may adopt the Small Outline Package (SOP) form. SOP is a surface mount plastic dual in-line small outline package with a standard pin pitch and a mechanical structure suitable for plugging and unplugging the socket, which is convenient for manual plugging and unplugging replacement and is suitable for use in the system debugging stage. Correspondingly, the socket for installing the first flash memory and the second flash memory is fixed on the management control board by the Ball Grid Array (BGA) package method to ensure good electrical connection and mechanical stability between the socket and the management control board. Thus, the first flash memory and the second flash memory using the SOP package can be installed in the socket by plugging, thereby realizing the pluggable connection of the flash memory module. This package method has a relatively large package size and is suitable for the initial debugging stage of the board card when it is returned to the board. The first flash memory and the second flash memory can be manually programmed for hardware verification and firmware debugging, or they can be programmed online after the later function development is complete. The remaining flash memories (including the first flash memory and the second flash memory) that do not adopt the SOP package are directly soldered to the management control board in the BGA form, which is suitable for batch online programming after the system runs stably.

[0023] In the technical solution of this application, by setting the management control board vertically fixed to the main board instead of arranging the management control board and the main board side by side on the same horizontal plane, the length dimension of the server main board card can be only the length dimension of the main board itself, rather than the total dimension after the superposition of the main board and the management control board in the length direction. Therefore, the technical solution of this application can effectively achieve the purpose of reducing the size of the server main board card in the length direction. In addition, since the pluggable package is larger than the Ball Grid Array package in terms of package size, by setting a first flash memory and a second flash memory to be encapsulated in a pluggable manner and installed on the management control board through a socket, and the remaining first flash memory and second flash memory are encapsulated by the Ball Grid Array and directly mounted on the management control board, the purpose is to reduce the size of the management control board as much as possible while ensuring that the requirements for the initial debugging of the board card when it is returned to the board and the online programming requirements after the later function development is complete can be met.

[0024] The reduction in the size of the server main board card in the length direction and the reduction in the size of the management control board itself mean that it is easier to adapt to the internal space size requirements of the standard chassis, improving the physical deployment compatibility of the server. In addition, the shortening of the length of the main board card also means that the space limitation for the internal wiring layout of the printed circuit board (PCB) used to make the board card is correspondingly reduced, thereby reducing the possibility of ultra-long wiring, further reducing the risks of signal attenuation, crosstalk and other signal quality abnormalities caused by too long signal transmission paths, and enhancing the stability and reliability of the overall operation of the server.

[0025] The server provided by the technical solution of the present application is particularly applicable to the field of artificial intelligence (AI) servers, and the AI server can be used to support the operation of large-scale deep learning models. In the current mainstream AI server architecture, a design method is usually adopted in which the CPU is directly connected to multiple GPU nodes through PCIe at high speed. To ensure the stability and efficiency of signal transmission, the system puts forward strict requirements for the signal transmission path between the CPU and the GPU, that is, the wiring distance should be shortened as much as possible to reduce signal delay and attenuation. Since the size of the server main board in the length direction is shortened by the technical solution provided by the present application, greater flexibility is provided in the PCB wiring design, which is beneficial to planning a wiring layout that meets the requirement of a short signal path from the CPU to the GPU in the AI server. Therefore, the technical solution of the present application can not only improve the hardware management efficiency of the AI server, but also better meet its requirements for high-performance computing and high-speed interconnection.

[0026] It should be noted that in actual setting, the distance between the position on the main board for fixing the management control board and the position of the first processor can be set to be less than the set distance threshold, so as to shorten the distance between the second processor and the first processor, and the distance between the second processor and other devices on the main board, thereby reducing the probability of the occurrence of abnormal signal quality caused by the excessive length of the signal line related to the second processor.

[0027] Furthermore, it can be set that the second accessory device includes an EEPROM. The EEPROM is packaged in UDFN (Ultra-Thin Dual Flat No-Lead) to reduce the size of the EEPROM, and thus achieve the purpose of reducing the size of the management control board.

[0028] Furthermore, it can be set that the second accessory device further includes a resistor and / or a capacitor, and the resistor and / or the capacitor are packaged in 0201 to reduce the size of the management control board.

[0029] Based on the above technical solutions, optionally, the number of the second accessory devices is multiple; the multiple second accessory devices are respectively arranged on both sides of the management control board.

[0030] Exemplarily, Figure 5 is a schematic diagram of the first surface of a management control board, Figure 6 is a schematic diagram of the second surface of a management control board. Refer to Figure 5, two voltage regulators, namely VR1 and VR2, a physical layer device (PHY), an electrically erasable programmable read-only memory (EEPROM), a baseboard management controller (BMC), a complex programmable logic device (CPLD), a Joint Test Action Group connector (JTAG CON), and a Trusted Platform Module (TPM) are provided on the first surface of the management control board. See Figure 6 , two voltage regulators, namely VR3 and VR4, an embedded multimedia card (EMMC), a temperature sensor (SENSOR), two first flash memories (BIOS flash0 and BIOS flash1), and two second flash memories (BMC flash0 and BMC flash1) are provided on the second surface of the management control board.

[0031] A plurality of second accessory devices are respectively arranged on both sides of the management control board, that is, some second accessory devices are arranged on the first surface of the management control board, and the remaining second accessory devices are arranged on the second surface of the management control board. By distributing the second accessory devices in a bilateral layout on the management control board, the space resources of the circuit board can be effectively utilized, and the problems of wiring congestion and increased board area caused by all devices being concentrated on one side can be avoided. Thus, this setting method helps to reduce the overall size of the management control board, improve the space utilization rate, and further enhance its adaptability and integration degree inside the server on the premise of meeting the functional requirements.

[0032] Furthermore, it can also be set that the second accessory device includes a plurality of circuit layers stacked on top of each other. Solder pads are provided on the surface of the management control board, and the solder pads are used to solder the second processor and / or the second accessory device; vias penetrating the management control board are provided on the solder pads; the second processor and / or the second accessory device are electrically connected to the circuit layer in the management control board through the vias on the solder pads corresponding to their welding positions.

[0033] Figure 7 This is a schematic diagram of a partial structure of a management control board provided by this application. See Figure 7 , a plurality of solder pads 21 are provided on the surface of the management control board 2, and these solder pads 21 are used to solder a second processor (such as a baseboard management controller) and / or a second accessory device (such as Figure 5 or Figure 6 other devices except the baseboard management controller in Figure 7 , in this management control board, vias 22 penetrating the management control board are provided on some of the solder pads 21, and the vias 22 can specifically be blind vias or buried vias, thus forming a via-on-pad structure.

[0034] By providing vias on the pads that penetrate the management control board, the second processor and / or the second accessory device can be electrically connected to one or more circuit layers in the management control board through the vias on the pads corresponding to their welding positions. In essence, the vias are directly provided on the pads and penetrate multiple dielectric layers (provided between adjacent circuit layers) of the management control board, thereby establishing a reliable electrical path between the pads and the internal circuit layers. Adopting this design method changes the traditional wiring method that requires reserving space around the welded devices to arrange vias and perform wire-wrapping connections, and it can effectively utilize the space resources under the pads. Without increasing the overall area of the management control board and the number of circuit layers, it realizes the interconnection of more signal paths between layers, significantly improving the wiring density and flexibility of the management control board. In addition, by using this method, the signal transmission path can be shortened, the signal transmission quality can be further improved, the possibility of signal delay and interference can be reduced, and the electrical performance and stability of the management control board wiring can be improved.

[0035] The solution of "providing vias on the pads that penetrate the management control board, enabling the second processor and / or the second accessory device to be electrically connected to the circuit layers in the management control board through the vias on the pads corresponding to their welding positions" is particularly applicable to the application scenarios of pads formed in the ball grid array package form. This is because devices using the ball grid array package usually have a very dense pin arrangement, and the spacing between adjacent pins is extremely small, resulting in extremely limited space around them for wiring and drilling holes. In such high-density packaging structures, the traditional peripheral wiring method often fails to meet the signal interconnection requirements. By providing vias on the pads, the pad body can be directly used as a signal extraction channel, avoiding additional occupation of peripheral wiring space, thereby effectively alleviating the wiring congestion problem.

[0036] Optionally, in practice, the vias on the pads can be used to transmit low-speed GPIO signals or GND signals.

[0037] Based on the above technical solution, the server can also include a heat sink; the heat sink is fixed to at least one side of the management control board. That is, the heat sink is located at a position close to the first surface of the management control board, or the heat sink is located at a position close to the second surface of the management control board.

[0038] The function of the heat sink is to quickly conduct heat from the heat-generating components to the external environment. By providing a heat sink for the management control board, it is beneficial to improve the heat dissipation efficiency of the management control board in the high-load operating state, thereby effectively reducing the operating temperature of key devices (such as the second processor and the second accessory device), and avoiding problems such as performance degradation, system instability, or shortened device life caused by excessive local temperature.

[0039] Furthermore, the server further includes a fixing member and a housing; the housing includes side plates; fixing holes penetrating through the management control board are provided on the management control board; the fixing member passes through the fixing holes of the management control board and the heat sink, and is connected to the side plate of the server housing, fixing the management control board, the heat sink and the side plate of the server housing into one body.

[0040] The side plates of the server housing are flat plate members on the left and right sides of the server chassis, and are fixedly connected to the main chassis frame (such as the front plate, the rear plate, the bottom plate, the top plate) through screws or buckles to form a closed box structure for covering and protecting the internal hardware. The fixing member can be, for example, a screw or a buckle, etc.

[0041] Exemplarily, in Figure 5 and Figure 6 A1 and A2 represent fixing holes for passing through the fixing member.

[0042] Furthermore, the server may further include a limiting plate; the limiting plate is located on the side of the management control board away from the side plate of the housing, and the limiting plate is fixedly integrated with the main board and the management control board.

[0043] Exemplarily, referring to Figure 8 , the management control board 2 is located between the limiting plate 4 and the heat sink 3. Three fixing holes, namely fixing hole S1, fixing hole S2 and fixing hole S3, are provided on the limiting plate 4. During installation, three fixing members are selected for fixing. Specifically, the first fixing member passes through the fixing hole S1 on the limiting plate 4, the fixing hole A1 of the management control board 2 and the heat sink, and is fixedly integrated with the side plate of the server housing. The second fixing member passes through the fixing hole S2 on the limiting plate 4, the fixing hole A2 of the management control board 2 and the heat sink, and is fixedly integrated with the side plate of the server housing. The third fixing member passes through the fixing hole S3 on the limiting plate 4 and is fixedly integrated with the main board.

[0044] By arranging the limiting plate on the side of the management control board away from the side plate of the housing, and the limiting plate is fixedly integrated with the main board and the management control board, its essence is to limit the position of the management control board in the server by means of the limiting plate, preventing the management control board from shaking during the movement of the server, and avoiding the occurrence of bad phenomena such as damage to the management control board.

[0045] On the basis of the above technical solution, optionally, referring to Figure 4 , the server may further include a first connector 9, and the first connector is connected between the main board 1 and the management control board 2 for realizing signal transmission between the main board 1 and the management control board 2.

[0046] To achieve functional decoupling and structural independence between the management control board and the main board, the technical solution of this application introduces a first connector. The role of the first connector is to establish an electrical connection and a signal transmission path between the management control board and the main board. The first connector has a standardized pin definition, enabling the management control board to be docked with the main board as an independent functional module without depending on the specific design layout of the main board.

[0047] By adopting this connection method, the management control board can be completely separated from the main board and developed, tested, maintained, and replaced as an independent module. Especially when the management control board fails or needs to be upgraded, the overall rapid replacement of the management control board can be achieved by disassembling the first connector, without the need to perform overall maintenance or replacement of the main board, thus significantly improving the maintainability and scalability of the server.

[0048] In addition, due to the standardized interface design of the first connector, the same management control board can be reused between different projects, reducing the repetitive cost of hardware development and improving the product iteration efficiency.

[0049] Optionally, the first connector is a 4C+ connector.

[0050] Figure 9 This is a schematic diagram of the port connection between a first connector and a management control board provided by an embodiment of this application. Figure 10 This is a schematic diagram of the port connection between a first connector and a main board provided by an embodiment of this application. In Figure 9 and Figure 10 the first connector is a 4C+ connector.

[0051] See Figure 9 and Figure 10 Set the baseboard management controller (BMC) on the management control board to establish communication connections with the main board and external devices through multiple interfaces to complete functions such as status collection, remote control, and security management. Specifically, the BMC accesses the I2C devices on the main board through the I2C (Inter-Integrated Circuit) interface and feeds back relevant data to the BMC to achieve real-time monitoring of the operating status of the I2C devices on the main board; it communicates with the DIMM (Dual In-line Memory Module) on the main board through the I3C (Improved Inter-Integrated Circuit) interface to obtain and monitor the memory status information of the system. In terms of the graphics display function, the BMC receives the video signal from the main board through the PCIe EP interface and converts it into a VGA (Video Graphics Array) signal for output to support local or remote display.

[0052] Furthermore, the BMC also communicates with high-speed peripherals such as the PCIe switch in the server through the PCIe RC interface to achieve efficient management of its operating status; it obtains system startup status information through the ESPI / LPC (Enhanced Serial Peripheral Interface / Low-Pin Count) bus, which is a key communication channel during the system power-on process to ensure that the BMC can respond to system initialization events in a timely manner. In addition, the BMC accesses the BIOS image located on the management control board through SPI (Serial Peripheral Interface) and combines it with the TPM (Trusted Platform Module) to perform security verification on the image content to ensure the security of system startup.

[0053] In terms of interaction with network devices, the BMC establishes a 100M network connection with the OCP network card through the NCSI (Network Controller Sideband Interface) to achieve out-of-band network management functions; and transmits system monitoring information to the network through the SGMII (Serial Gigabit Media Independent Interface), enabling users to remotely view the server operating status through the WEB interface. The LTPI (Low-Pin Translator Interface) is used for GPIO signal interaction between the BMC and the motherboard, and signal conversion and routing are achieved through the CPLD (Complex Programmable Logic Device), thus effectively reducing the occupancy of pin resources. In some scenarios, I2C signals and UART (Universal Asynchronous Receiver-Transmitter) signals can also be multiplexed for transmission, further reducing the occupancy of pin resources.

[0054] In addition, the BMC also includes several dedicated GPIO signals, such as HPM_EN (Power-on Enable), HPM_RDY (Power-on Ready), HPM_RST (Reset), etc., which are used to achieve power control logic interaction with the motherboard to ensure consistent power management of the system in different operating modes; at the same time, the system serial port and the BMC serial port signals are transmitted through the UART interface, and the CPLD is used to select and switch the serial port channels to improve communication flexibility and system compatibility.

[0055] The following further explains from five aspects: the SPI topology of the management control board, the JTAG topology of the management control board, the UART and LTPI topology of the management control board, the network topology of the management control board, and the VGA and USB topology of the management control board.

[0056] I. Management Control Panel and SPI Topology Optionally, in the server, the second accessory device may include a first multiplexer and a first flash memory. The first multiplexer includes a first port, a second port, and a third port. The first port of the first multiplexer is connected to the second processor, the second port of the first multiplexer is connected to the first flash memory, and the third port of the first multiplexer is connected to the first connector. In the first multiplexer, the link states between the first port and the third port, and between the second port and the third port are adjustable.

[0057] The first flash memory is used to provide storage services for the first processor (such as a central processing unit). The function of the first multiplexer is to control the on / off of signal transmission between the first flash memory and the second processor, or between the first flash memory and the first processor.

[0058] Specifically, the link state may be a through state or an open state. Taking the link state between the first port and the third port in the first multiplexer as an example, if the link state between the first port and the third port in the first multiplexer is a through state, it means that signals can be transmitted from the first port of the first multiplexer to the third port of the first multiplexer, and can also be transmitted from the third port of the first multiplexer to the first port of the first multiplexer.

[0059] Optionally, when the first accessory device includes a third flash memory for providing storage services for the first processor, the link state between the second port and the third port in the first multiplexer is an open state; when the first accessory device does not include a third flash memory for providing storage services for the first processor, the link state between the second port and the third port in the first multiplexer is a through state.

[0060] Furthermore, the first accessory device includes a second multiplexer and a third flash memory. The third flash memory is used to provide storage services for the first processor. The second multiplexer includes a first port, a second port, and a third port. The first port of the second multiplexer is connected to the first processor, the second port of the first multiplexer is connected to the third flash memory, and the third port of the first multiplexer is connected to the first connector. In the second multiplexer, the link states between the first port and the second port, and between the second port and the third port are adjustable. The function of the second multiplexer is to control the on / off of signal transmission between the third flash memory and the second processor, or between the third flash memory and the first processor.

[0061] Optionally, when the server is in the boot-up process, the link state between the first port and the second port is a through state; when the firmware of the third flash memory is being updated, the link state between the second port and the third port is a through state.

[0062] Exemplarily, refer to Figure 11 , the second accessory device includes a first multiplexer MUX1 and a first flash memory. In Figure 11 , there are two first flash memories in total, namely BIOS0 and BIOS1. The purpose of setting two first flash memories here is to implement a redundant design for the storage function. Through the redundant design, in the case of a failure or data corruption of one of the first flash memories, the normal first flash memory can continue to undertake the data storage and reading functions, thus ensuring the continuous operation of the system and data integrity.

[0063] Continue to refer to Figure 11 , the first multiplexer MUX1 includes a first port a, a second port b, and a third port c; the first port a of the first multiplexer MUX1 is connected to the second processor (BMC), the second port b of the first multiplexer MUX1 is connected to the first flash memory (i.e., BIOS0 and BIOS1), and the third port c of the first multiplexer MUX1 is connected to the first connector (i.e., 4C+CON); in the first multiplexer MUX1, the link state between the first port a and the third port c, and the link state between the second port b and the third port c are adjustable.

[0064] The first accessory device includes a second multiplexer MUX2 and a third flash memory. In Figure 11 , there are two third flash memories in total, namely BIOS2 and BIOS3. The purpose of setting two third flash memories here is to implement a redundant design for the storage function. Through the redundant design, in the case of a failure or data corruption of one of the third flash memories, the normal third flash memory can continue to undertake the data storage and reading functions, thus ensuring the continuous operation of the system and data integrity.

[0065] The second multiplexer MUX2 includes a first port d, a second port e, and a third port f; the first port d of the second multiplexer MUX2 is connected to the first processor (such as the central processor on the motherboard), the second port e of the second multiplexer MUX2 is connected to the third flash memory (i.e., BIOS2 and BIOS3), and the third port f of the second multiplexer MUX2 is connected to the first connector (i.e., 4C+CON). In the second multiplexer MUX2, the link state between the first port d and the second port e and the link state between the second port e and the third port f are adjustable. Figure 11 , the first flash memory (i.e., BIOS0 and BIOS1) and the third flash memory (i.e., BIOS2 and BIOS3) are both used to provide storage services for the first processor (such as the central processor on the motherboard).

[0066] Continue to refer to Figure 11, since a third flash memory (i.e., BIOS2 and BIOS3) is provided on the motherboard, the link state between the second port b and the third port c in the first multiplexer MUX1 is set to an open state. When the server is in the boot-up process, the link state between the first port d and the second port f of the second multiplexer MUX2 is in a conducting state, so that the first processor (such as the central processing unit on the motherboard) can access the third flash memory (i.e., BIOS2 and BIOS3). When performing a firmware upgrade on the third flash memory (i.e., BIOS2 and / or BIOS3), the link state between the second port e and the third port f of the second multiplexer MUX2 is in a conducting state, so that the second processor (BMC) can access the third flash memory (i.e., BIOS2 and BIOS3) through the first connector to update information.

[0067] If the third flash memory is not provided on the motherboard, that is, there is no BIOS2 and BIOS3 on the motherboard, the first processor (such as the central processing unit CPU on the motherboard) must read the firmware information from the first flash memory (i.e., BIOS0 and BIOS1). Therefore, when the server is in the boot-up process, the link state between the third port c and the second port b of the first multiplexer MUX1 is set to a conducting state, so that the first processor (such as the central processing unit on the motherboard) can access the first flash memory (i.e., BIOS0 and BIOS1). When performing a firmware upgrade on the first flash memory (i.e., BIOS0 and BIOS1), the link state between the second port b and the first port a of the first multiplexer MUX1 is in a conducting state, so that the second processor (BMC) can access the first flash memory (i.e., BIOS0 and BIOS1) to update information.

[0068] It should be noted that the buses connecting the first processor to the first flash memory (i.e., BIOS0 and BIOS1) and the third flash memory (i.e., BIOS2 and / or BIOS3) can be SPI buses.

[0069] Continue to refer to Figure 11 , the control and management board further includes a second flash memory. In Figure 11 , there are 2 second flash memories in total, namely BMC FLASH0 and BMC FLASH1. The second flash memory is used to provide storage services for the second processor (such as the baseboard management controller BMC). The purpose of setting two second flash memories here is to implement a redundant design for the storage function. Through the redundant design, in the case where one of the second flash memories fails or data is damaged, the normal second flash memory can continue to undertake the data storage and reading functions, thereby ensuring the continuous operation of the system and data integrity.

[0070] II. Management Control Board and JTAG Topology The JTAG bus can be used to capture log information related to faults and program the CPLD (Complex Programmable Logic Device) when the server fails.

[0071] Based on this, for the case where the JTAG bus is used to capture log information related to faults, in some embodiments, the first accessory device may be set to include a third multiplexer and a hardware detection tool; the third multiplexer includes a first port, a second port, and a third port; the second processor is connected to the first connector through a first log acquisition line, the first connector is connected to the second end of the third multiplexer through a second log acquisition line, the first end of the third multiplexer is connected to the first processor, and the third end of the third multiplexer is connected to the hardware detection tool; in the third multiplexer, the link state between the first port and the third port, and the link state between the second port and the first port are adjustable.

[0072] Further, when it is detected that the server fails, the link state between the second port and the first port is in a conducting state, so that the second processor obtains log information related to the fault from the first processor; or, the link state between the first port and the third port is in a conducting state, and the hardware detection tool obtains log information related to the fault from the first processor.

[0073] Figure 12 Schematic diagram of a management control board and JTAG topology provided by this application. Refer to Figure 12 , the first accessory device includes a third multiplexer MUX3 and a hardware detection tool HDT; the third multiplexer MUX3 includes a first port g, a second port i, and a third port h. The second processor (such as a baseboard management controller BMC) is connected to the first connector (such as a 4C+CON) through a first log acquisition line (which can be a JTAG bus), the first connector (such as a 4C+CON) is connected to the second end i of the third multiplexer MUX3 through a second log acquisition line (which can be a JTAG bus), the first end g of the third multiplexer MUX3 is connected to the first processor (such as a central processing unit CPU), and the third end h of the third multiplexer MUX is connected to the hardware detection tool HDT. In the third multiplexer MUX3, the link state between the first port g and the third port h, and the link state between the second port i and the first port g are adjustable.

[0074] When a server failure is detected, a first enable signal is sent to the third multiplexer MUX3 through a second processor (such as a baseboard management controller BMC) to cause the third multiplexer MUX3 to switch its operating state. After the operating state of the third multiplexer MUX3 is switched, the link state between the second port i and the first port g of the third multiplexer MUX3 is in a connected state. In this way, the second processor (such as a baseboard management controller BMC) can remotely capture various information (i.e., logs) during the process of the system running from normal operation to downtime from the first processor (such as a central processing unit CPU).

[0075] Alternatively, when a server failure is detected, a second enable signal is sent to the third multiplexer MUX3 through a second processor (such as a baseboard management controller BMC) to cause the third multiplexer MUX3 to switch its operating state. After the operating state of the third multiplexer MUX3 is switched, the link state between the first port g and the third port h of the third multiplexer MUX3 is in a connected state. In this way, the hardware detection tool HDT can capture various information (i.e., logs) during the process of the system running from normal operation to downtime from the first processor (such as a central processing unit CPU).

[0076] For the case where the JTAG bus can be used to program a CPLD (Complex Programmable Logic Device), in some embodiments, optionally, the second accessory device includes a fourth multiplexer, a fifth multiplexer, a first programming connector, and a first logic processing unit; the first logic processing unit is used to assist the second processor in hardware coordination and control; the first port of the fourth multiplexer is connected to the second processor, the second port of the fourth multiplexer is connected to the first port of the fifth multiplexer; the third port of the fourth multiplexer is connected to the first connector; the second port of the fifth multiplexer is connected to the first programming connector; the third port of the fifth multiplexer is connected to the first logic processing unit; in the fourth multiplexer, the link state between the first port and the second port, and the link state between the first port and the third port are adjustable; in the fifth multiplexer, the link state between the first port and the third port, and the link state between the second port and the third port are adjustable.

[0077] Further, the first accessory device includes a sixth multiplexer, a second programming connector, and a second logic processing unit; the second logic processing unit is used to assist the first processor in hardware coordination and control; the first connector is connected to the first end of the sixth multiplexer, the second end of the sixth multiplexer is connected to the second programming connector, and the third end of the sixth multiplexer is connected to the second logic processing unit; in the sixth multiplexer, the link state between the first port and the third port, and the link state between the second port and the third port are adjustable.

[0078] Continue to refer toFigure 12 The second accessory device includes a fourth multiplexer MUX4, a fifth multiplexer MUX5, a first programming connector JTAG HDR0, and a first logic processing unit SCM CPLD; the first logic processing unit SCM CPLD is used to assist the second processor (such as a baseboard management controller BMC) in performing hardware coordination and control; the first port j of the fourth multiplexer MUX4 is connected to the second processor (such as a baseboard management controller BMC), and the second port m of the fourth multiplexer MUX4 is connected to the first port n of the fifth multiplexer MUX5; the third port k of the fourth multiplexer MUX4 is connected to the first connector (i.e., 4C+CON); the second port p of the fifth multiplexer MUX5 is connected to the first programming connector JTAG HDR0; the third port q of the fifth multiplexer MUX5 is connected to the first logic processing unit SCM CPLD; in the fourth multiplexer MUX4, the link state between the first port j and the second port m, and the link state between the first port j and the third port k are adjustable; in the fifth multiplexer MUX5, the link state between the first port n and the third port q, and the link state between the second port p and the third port q are adjustable.

[0079] Continue to refer to Figure 12 The first accessory device includes a sixth multiplexer MUX6, a second programming connector JTAG HDR1, and a second logic processing unit MB CPLD; the second logic processing unit MB CPLD is used to assist the first processor (such as a central processing unit CPU) in performing hardware coordination and control; the first connector (such as 4C+CON) is connected to the first end u of the sixth multiplexer MUX6, the second end v of the sixth multiplexer MUX6 is connected to the second programming connector JTAG HDR1, and the third end w of the sixth multiplexer MUX6 is connected to the second logic processing unit MB CPLD; in the sixth multiplexer MUX6, the link state between the first port u and the third port w, and the link state between the second port v and the third port w are adjustable.

[0080] In the technical solution of this application, the first logic processing unit SCM CPLD is specifically used to implement the control of the power-on logic of the management control board, and complete cross-module collaborative control through the communication interface with the second logic processing unit MB CPLD. Similarly, the second logic processing unit MB CPLD is responsible for the power-on management of the main board and related logic control functions, and exchanges information with the first logic processing unit SCM CPLD. The first logic processing unit SCM CPLD and the second logic processing unit MB CPLD together constitute the core control unit for power management, status synchronization, and remote control in the server system.

[0081] For the firmware burning method of the CPLD (including the first logic processing unit SCM CPLD and the second logic processing unit MB CPLD), for example, it can include the following two types: one is offline burning, that is, connecting to the burning connector through a CPLD burner and completing the program writing without accessing the server main system; the other is online burning, that is, realizing remote burning operation through the BMC (Baseboard Management Controller), and the firmware can be updated or repaired without physically contacting the device (such as a CPLD burner), improving the maintainability and deployment efficiency of the system.

[0082] Regarding Figure 12 For the given technical solution, when performing CPLD program writing for the first logic processing unit SCM CPLD in the offline burning mode, the CPLD burner is connected to the burning connector JTAG HDR0, and the operating state of the fifth multiplexer MUX5 is adjusted so that the link state between the second port p and the third port q of the fifth multiplexer MUX5 is in a through state; ensure that the burning signal passes through the first burning connector JTAG HDR0 and the fifth multiplexer MUX5 and is transmitted to the first logic processing unit SCM CPLD.

[0083] When performing CPLD program writing for the second logic processing unit MB CPLD in the offline burning mode, the CPLD burner is connected to the burning connector JTAG HDR1, and the operating state of the sixth multiplexer MUX6 is adjusted so that the link state between the second port v and the third port w of the sixth multiplexer MUX6 is in a through state; ensure that the burning signal passes through the second burning connector JTAG HDR1 and the sixth multiplexer MUX6 and is transmitted to the second logic processing unit MB CPLD.

[0084] When the server is in a normal running state and online burning for the first logic processing unit SCM CPLD and / or the second logic processing unit MB CPLD is required, the user can initiate a burning request by logging in to the BMC Web interface, and the second processor (i.e., the baseboard management controller BMC) controls the selection logic of the relevant multiplexers through its GPIO (General-Purpose Input / Output) interface.

[0085] Specifically, when performing online burning for the first logic processing unit SCM CPLD, the operating states of the fifth multiplexer MUX5 and the fourth multiplexer MUX4 are adjusted so that the link state between the first port n and the third port q of the fifth multiplexer MUX5 is in a through state, and the link state between the first port j and the second port m of the fourth multiplexer MUX4 is in a through state, ensuring that the burning signal passes through the second processor (i.e., the baseboard management controller BMC), the fourth multiplexer MUX4, and the fifth multiplexer MUX5 and is transmitted to the first logic processing unit SCM CPLD.

[0086] When performing online programming on the second logic processing unit MB CPLD, adjust the operating states of the sixth multiplexer MUX6 and the fourth multiplexer MUX4 so that the link state between the first port u and the third port w of the sixth multiplexer MUX6 is in a connected state, and the link state between the first port j and the third port k of the fourth multiplexer MUX4 is in a connected state, ensuring that the programming signal is transmitted to the second logic processing unit MB CPLD through the second processor (i.e., the baseboard management controller BMC), the fourth multiplexer MUX4, and the sixth multiplexer MUX5.

[0087] This design method supports the free switching between two programming modes, providing the possibility for the function upgrade of the first logic processing unit SCM CPLD and the second logic processing unit MB CPLD, and can improve the maintainability, security, and deployment flexibility of the server system.

[0088] It should be noted that in the above technical solutions, it can be set that the second processor (i.e., the baseboard management controller BMC) controls the selection logic of the relevant multiplexers through the GPIO (General-Purpose Input / Output) interface, so as to complete capturing the log information related to faults, or programming the CPLD (Complex Programmable Logic Device), or assisting the CPU to access the flash memory that can provide storage services for it, or performing firmware upgrade on the flash memory that can provide storage services for the CPU.

[0089] III. UART and LTPI Topology of the Management Control Board In some embodiments, optionally, the second accessory device includes a first signal exchanger; the first signal exchanger is connected to the second processor through multiple first functional buses, and different first functional buses are used to transmit signals with different functions; the first signal exchanger is also connected to the first connector through a first serial bus.

[0090] Optionally, the first accessory device includes a second signal exchanger, a third connector, and a third signal exchanger; the second signal exchanger is connected to the first connector through a second serial bus; the second signal exchanger is also connected to the third signal exchanger and the third connector; the third signal exchanger is used to receive signals from the third processor.

[0091] Optionally, the first logic processing unit can be multiplexed as the first signal exchanger. Such a setting can reduce the number of devices set in the management control board, which is beneficial to reducing the area of the management control board. Similarly, the second logic processing unit can be multiplexed as the second signal exchanger, and such a setting can reduce the number of devices set in the main board, which is beneficial to reducing the area of the main board.

[0092] Exemplarily, refer to Figure 13, the second accessory device includes a first signal exchanger (such as a first logic processing unit SCM CPLD); the first signal exchanger (i.e., SCM CPLD) and the second processor (i.e., the baseboard management controller BMC) are connected through multiple first functional buses (in Figure 13 it is BMC UART, CPU UART, and SMART NIC URAT), and different first functional buses are used to transmit signals of different functions; the first signal exchanger (i.e., the first logic processing unit SCM CPLD) is also connected to the first connector (such as 4C+CON) through a first serial (such as SGPIO or LTPI) bus.

[0093] Optionally, the first accessory device includes a second signal exchanger (such as a second logic processing unit MB CPLD), a third connector (such as UART CON), and a third signal exchanger (such as PCIE SW); the second signal exchanger (such as the second logic processing unit MB CPLD) is connected to the first connector (such as 4C+CON) through a second serial (such as SGPIO or LTPI) bus; the second signal exchanger (such as the second logic processing unit MB CPLD) is also connected to the third signal exchanger (such as PCIE SW) and the third connector (such as UART CON); the third signal exchanger (such as PCIE SW) is used to receive signals from a third processor (such as a graphics processing unit GPU, not shown in Figure 13 it).

[0094] To achieve comprehensive monitoring of the operating status of the server motherboard, the BMC (baseboard management controller) needs to obtain and analyze the key logic control signals and serial port information from the motherboard. However, due to the limited number of interconnection interfaces between the motherboard and the SCM (system management module) board, directly transmitting all status signals through multiple independent GPIO pins has problems such as high wiring complexity and tight pin resources. The essence of the above technical solution is a signal aggregation mechanism based on a serial bus (such as SGPIO or LTPI). Multiple GPIO signals to be monitored are uniformly connected to the serial bus, and the motherboard transmits the relevant status information to the SCM CPLD. Then, the SCM CPLD converts it into standard GPIO signals and outputs them to the BMC for acquisition and analysis, so as to achieve remote monitoring of the key operating status of the motherboard.

[0095] In addition, in terms of serial communication, the serial port information of the CPU needs to be transmitted to the BMC through the LPC or eSPI bus for parsing, and all serial port logs generated during the system operation should be output externally through the serial port connector (i.e., URATCON) on the IO panel. At the same time, to meet the requirements of remote operation and maintenance, the three key serial port information, such as BMC UART, CPU UART, and SMART NIC UART, should also be remotely accessible and viewable through the network interface. Therefore, the above three serial port signals need to be finally connected to the BMC.

[0096] It should be noted again that considering the docking between the management control board and the motherboard through the 4C+ high-speed connector, and the available pin resources of this connector are limited, it is impossible to directly transmit all serial port signals one by one to the motherboard side. For this reason, the present application further provides a multiplex serial port multiplexing and switching mechanism based on CPLD: First, all serial port signals on the management control board are aggregated and connected to the SCM CPLD, and a virtual UART Switch (serial port selection switch) is constructed inside the CPLD to achieve selective output of the three signals of BMC UART, CPU UART, and Smart NIC UART. Subsequently, the selected serial port signal is transmitted to the MB CPLD on the motherboard side through the 4C+ connector.

[0097] In the MB CPLD, the processing logic for the signals related to the GPU node PCIe switch (PCIE SW) is further integrated, and the multiplex serial port signals are integrated and switched through the internal logic design. Finally, the selected serial port signal will be output to the serial port connector on the front panel, enabling users to obtain the serial port information during the system operation through the physical interface on the front panel, or remotely access the required serial port data through the network interface of the BMC.

[0098] The above technical solution effectively solves the serial port signal transmission problem caused by the limited pin resources of the 4C+ connector by introducing the serial port signal aggregation and multiplex selection mechanism based on CPLD. At the same time, it realizes the synchronous output ability of the key serial port information at the network end and the front panel end, improves the observability, maintainability, and remote management efficiency of the system, and is especially suitable for application scenarios with high requirements for space layout and signal integrity, such as high-density AI servers.

[0099] IV. Network Topology of the Management Control Board In some examples, optionally, the second accessory device includes a first physical layer device, the first accessory device includes a second physical layer device and a first network card; the second processor is connected to the first connector through a network card management bus; the second processor is connected to the first physical layer device through a parallel network data transmission bus, and the first physical layer device is connected to the first connector through a first serial network data transmission bus; the first connector is connected to the second physical layer device through a second serial network data transmission bus, and the second physical layer device is connected to a network interface; the second processor is also connected to the first physical layer device and the second physical layer device through a first control signal line.

[0100] Figure 14 This is a schematic diagram of the network topology of a management control board provided by this application. Refer to Figure 14 , exemplarily, the second accessory device includes a first physical layer device (PHY1), the first accessory device includes a second physical layer device (PHY2) and a first network card (in Figure 14 , exemplarily, the first network card is an OCP network card); the second processor (i.e., the baseboard management controller BMC) is connected to the first connector (such as Figure 14 4C+CON in) through a network card management bus; the second processor (i.e., the baseboard management controller BMC) is connected to the first physical layer device (i.e., PHY1) through a parallel network data transmission bus, and the first physical layer device (i.e., PHY1) is connected to the first connector (such as Figure 14 4C+CON in) through a first serial network data transmission bus; the first connector (such as Figure 14 4C+CON in) is connected to the second physical layer device (i.e., PHY2) through a second serial network data transmission bus, and the second physical layer device (i.e., PHY2) is connected to a network interface (exemplarily, Figure 14 RJ45 interface in); the second processor (i.e., the baseboard management controller BMC) is also connected to the first physical layer device (i.e., PHY1) and the second physical layer device (i.e., PHY2) through a first control signal line.

[0101] Here, the first physical layer device (i.e., PHY1) and the second physical layer device (i.e., PHY2) can be, for example, Ethernet PHY devices, high-speed SerDes PHY devices, and retiming Retimer PHY devices, etc.

[0102] Optionally, refer to Figure 14 , it can also be set that the network card management bus connected between the second processor (i.e., the baseboard management controller BMC) and the first connector (such as 4C+CON), and the network card management bus connected between the first connector (such as 4C+CON) and the OCP network card are both NCSI buses. The NCSI bus can implement the remote management function of the BMC for network devices.

[0103] Optionally, the parallel network data transmission bus connected between the second processor (i.e., the baseboard management controller BMC) and the first physical layer device (i.e., PHY1) is a GRMII bus, and the first serial network data transmission bus connected between the first physical layer device (i.e., PHY1) and the first connector (such as Figure 14 4C+CON in the figure) is an SGMII bus. The first control signal line output from the second processor (i.e., the baseboard management controller BMC) for controlling the first physical layer device (i.e., PHY1) and the second physical layer device (i.e., PHY2) is an MDIO / MDC bus.

[0104] The core idea of the technical solution of this application is that the control management board is physically isolated from the main board and is not on the same circuit board. If cross-board transmission is carried out according to the RGMII protocol, it is difficult to meet the control requirements in terms of timing matching and wiring length. If the RGMII protocol is directly used for cross-board transmission, it may lead to a decline in signal integrity and cannot guarantee the stability of communication.

[0105] In addition, limited by the space layout of the management control board, it is difficult to arrange the RJ45 physical interface on this miniaturized management control board. Therefore, it is also impossible to perform long-distance transmission after converting the RGMII signal into the MDI (Media Dependent Interface) form. In view of this, the essence of the above technical solution is to convert the original network signal based on the RGMII protocol into an SGMII protocol signal for transmission based on the signal conversion mechanism of the PHY device.

[0106] As a serialized network interface protocol, SGMII has higher anti-interference ability and more flexible wiring characteristics, and is especially suitable for long-distance and high-density PCB routing scenarios. Through this conversion method, not only the timing matching problem existing in RGMII cross-board transmission is solved, but also the stability and reliability of network signal transmission are effectively improved.

[0107] Furthermore, the BMC is connected to PHY1 on the management control board through a group of MDC and MDIO signal lines, and establishes a communication connection with other PHY2 on the main board in a daisy chain manner. This structure facilitates the implementation of network status monitoring and remote configuration management of the entire server system.

[0108] V. VGA and USB Topology of the Management Control Board In some embodiments, a first external interface is provided on the housing of the server; the first processor is connected to the first connector through a first display signal transmission bus, the first connector is connected to the second processor through a second display signal transmission bus, the second processor is connected to the first connector through a first video transmission bus and a third serial bus; the first connector is connected to the first external interface on the server housing through a second video transmission bus and a fourth serial bus.

[0109] Further, a signal converter is provided on the motherboard; the first connector is connected to the signal converter through a second video transmission bus and a fourth serial bus, and the signal converter is connected to the first external interface on the server housing through a cable.

[0110] Figure 15 It is a schematic diagram of the VGA and USB topology of a management control board provided by this application.

[0111] See Figure 15 , a first external interface is provided on the housing of the server; the first processor (such as a central processing unit CPU) is connected to the first connector (such as 4C+CON) through a first display signal transmission bus, and the first connector (such as 4C+CON) is connected to the second processor (such as a baseboard management controller BMC) through a second display signal transmission bus (such as a PCIE bus). The second processor (such as a baseboard management controller BMC) is connected to the first connector (such as 4C+CON) through a first video transmission bus (such as VGA) and a third serial bus (such as USB); the first connector (such as 4C+CON) is connected to the first external interface on the server housing ( Figure 15 not shown in) through a second video transmission bus (such as VGA) and a fourth serial bus (such as USB).

[0112] Further, see Figure 10 , a signal converter 6 is provided on the motherboard 1 (the signal converter is marked as MCIO in Figure 15 ); the first connector (such as 4C+CON) is connected to the signal converter 6 through a second video transmission bus and a fourth serial bus, and the signal converter 6 is connected to the first external interface on the server housing through a cable. The first external interface is provided on the front panel of the server housing. In Figure 15 , the front panel of the server housing is referred to as FRONT PANEL, and in Figure 10 , the front panel of the server housing is referred to as FP.

[0113] With the technical solution of the present application, the VGA (Video Graphics Array) or DP (DisplayPort) display signal required by the BMC (Baseboard Management Controller) is generated by the CPU through PCIe resources and transmitted to the BMC side. To implement the local or remote display control function of the server system, this video signal needs to be converted and routed before being output to the first external interface on the front window panel of the server. At the same time, the USB access function supported by the BMC also needs to be connected to the first external interface to facilitate operations such as peripheral access, system debugging, and firmware update.

[0114] Those skilled in the art can understand that by setting the first connector to be connected to the signal converter through the second video transmission bus and the fourth serial bus, the signals transmitted in the second video transmission bus and the fourth serial bus can be combined into one for conversion, so as to reduce the number of the first external interfaces to be set on the server housing, and the intensive design of the server hardware architecture can be realized.

[0115] In addition, the signal converter is connected to the first external interface on the server housing through a cable, rather than using motherboard routing to achieve the electrical connection between the signal converter and the first external interface component. This design can reduce the complexity of the motherboard design, avoid too long signal lines, simplify the internal circuit layout of the motherboard, and thus improve the signal integrity.

[0116] Based on the above technical solutions, optionally, the operation process of the server may include a power-on process, a kernel loading process, a function enabling process, a display function activation process, an operation supervision process, and a regulation process.

[0117] Power-on process: When the management control board is inserted into the first connector on the motherboard, the power supply unit (PSU) outputs the P12V_PSU voltage, which is transmitted to the electronic fuse (EFUSE) as the power input of the management control board. The enabling state of the EFUSE is controlled by the "presence detection signal (PRSNT_N)" - if PRSNT_N is at a high level, it is determined that the management control board is not inserted properly (not in place), the EFUSE enabling signal is low, and the board cannot be powered on; if PRSNT_N is at a low level, it is determined that the board is in place, the EFUSE enabling signal is set high, and the power-on process is started. After passing through the EFUSE, the P12V_PSU is converted into the P12V_STBY_SCM power network to supply power to the voltage regulator (VR) on the management control board; the voltage regulator (VR) then generates different voltage signals in sequence according to the BMC standard power-on requirements to provide adapted power for the BMC and other accessory devices on the management control board.

[0118] Kernel loading process: After the management control board is powered on, it sends the voltage signal (PWRGD) output by the last voltage regulator (VR) as the HPM enable signal (HPM_EN) to the motherboard's EFUSE module, triggering the motherboard power-on process. Simultaneously, the BMC loads firmware from its own flash memory (BMC FLASH) and starts the kernel program. Once the kernel is loaded, basic BMC functions (such as network communication and its own serial port) are enabled, preparing for subsequent interactions.

[0119] Function Enabling Process: When the kernel is loaded, the motherboard is usually powered on. After the motherboard powers on, the HPM Ready signal (HPM_RDY) signals the logic processing unit (MB CPLD) in the management control board that power-on is complete. The BMC then resets itself and then resets the motherboard via the HPM Reset signal (HPM_RST). After the motherboard reset is complete, the BMC loads the bootloader (uboot) information. At this point, most bus functions on the management control board become active and accessible. After the motherboard loads the Basic Input / Output System (BIOS), the BMC establishes communication (handshake) with the motherboard CPU via the Enhanced Serial Peripheral Interface (ESPI) or Low Pin Count (LPC) bus. It accesses slave devices via the I2C bus and memory resources via the I3C bus, while also monitoring system temperature. The SCM CPLD in the management control board and the MB CPLD in the motherboard also continuously exchange hardware status information.

[0120] Display function activation process: When the user presses the system power-on button, the system completes the power-on process according to the preset timing. After the CPU sends PCIe resources to the BMC and the PCIe reset signal (PERST) completes the reset, the BMC's display function is officially enabled, supporting external display devices. At this point, the management control board is fully functional.

[0121] Operational Monitoring and Control: From the moment the display function is activated until the system is powered off, the management control board continuously monitors the system. This monitoring includes real-time monitoring of system temperature, graphics processing unit (GPU) temperature, the operating status of key components (such as PCIe switches), and overall system power consumption. The management control board also provides control capabilities: users can access the web management interface through the BMC to view system operating parameters; support manual / automatic fan speed adjustment; and online updates and upgrades of the BIOS, BMC program, CPLD firmware, and the firmware of the PCIe switch connected to the GPU, ensuring long-term system stability and maintainability.

[0122] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0123] The above has introduced in detail a server provided by this application. Specific examples are used herein to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can still be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A server, characterized in that, It includes a main board and a management control board; The main board includes a first processor and first accessory devices; the management control board includes a second processor and second accessory devices; the second accessory devices include at least two first flash memories and at least two second flash memories, the first flash memories are used to provide storage services for the first processor, and the second flash memories are used to provide storage services for the second processor; The management control board is vertically fixed on the main board, and the management control board is communicatively connected to the main board; One of the first flash memories and one of the second flash memories are packaged in a pluggable manner and installed on the management control board through a socket; the remaining first flash memories and second flash memories are packaged through ball grid array and directly mounted on the management control board.

2. The server according to claim 1, wherein The number of the second accessory devices is multiple; The multiple second accessory devices are respectively arranged on both sides of the management control board.

3. The server according to claim 1, wherein The management control board includes multiple stacked circuit layers, and pads are arranged on the surface of the management control board, and the pads are used for soldering the second processor and / or the second accessory devices; vias penetrating the management control board are arranged on the pads; the second processor and / or the second accessory devices are electrically connected to the circuit layers in the management control board through the vias on the pads corresponding to their soldering positions.

4. The server according to claim 1, characterized in that The server further includes a heat sink; The heat sink is fixed on at least one side of the management control board.

5. The server according to claim 4, characterized in that, The server further includes a fixing member and a housing; the housing includes side plates; Fixing holes penetrating the management control board are arranged on the management control board, The fixing member passes through the fixing holes of the management control board and the heat sink and is connected to the side plate of the housing of the server, fixing the management control board, the heat sink and the side plate of the housing of the server as a whole.

6. The server according to claim 5, wherein The server further includes a limiting plate; The limiting plate is located on the side of the management control board away from the side plate of the housing, and the limiting plate is fixed as a whole with the main board and the management control board.

7. The server according to claim 1, characterized in that The server further includes a first connector, and the first connector is connected between the main board and the management control board and is used to realize signal transmission between the main board and the management control board.

8. The server according to claim 7, wherein The second accessory device includes a first multiplexer, and the first multiplexer includes a first port, a second port and a third port; The first port of the first multiplexer is connected to the second processor, the second port of the first multiplexer is connected to the first flash memory, and the third port of the first multiplexer is connected to the first connector; In the first multiplexer, the link state between the first port and the third port, and the link state between the second port and the third port are adjustable.

9. The server according to claim 8, wherein When the first auxiliary device includes a third flash memory for providing storage services for the first processor, in the first multiplexer, the link state between the second port and the third port is a disconnected state; When the first accessory device does not include a third flash memory for providing storage services for the first processor, in the first multiplexer, the link status between the second port and the third port is a connection status.

10. The server according to claim 8, wherein The first auxiliary device includes a second multiplexer and a third flash memory, and the third flash memory is used to provide storage services for the first processor. The second multiplexer includes a first port, a second port, and a third port; The first port of the second multiplexer is connected to the first processor, the second port of the second multiplexer is connected to the third flash memory, and the third port of the second multiplexer is connected to the first connector; In the second multiplexer, a link state between the first port and the second port and a link state between the second port and the third port are adjustable.

11. The server according to claim 10, wherein: When the server is in the boot process, the link state between the first port and the second port of the second multiplexer is a connection state; When the third flash memory is in the process of firmware upgrade, the link state between the second port and the third port of the second multiplexer is a connection state.

12. The server according to claim 7, wherein: The first auxiliary device includes a third multiplexer and a hardware detection tool; the third multiplexer includes a first port, a second port and a third port; The second processor is connected to the first connector via a first log collection line, the first connector is connected to the second end of the third multiplexer via a second log collection line, the first end of the third multiplexer is connected to the first processor, and the third end of the third multiplexer is connected to the hardware detection tool; In the third multiplexer, the link status between the first port and the third port, and the link status between the second port and the first port are adjustable.

13. The server according to claim 12, wherein: When a fault is detected in the server, the link status between the second port and the first port of the third multiplexer is a connected state, so that the second processor obtains log information related to the fault from the first processor; or the link status between the first port and the third port of the third multiplexer is a connected state, and the hardware detection tool obtains log information related to the fault from the first processor.

14. The server according to claim 7, wherein The second auxiliary device includes a fourth multiplexer, a fifth multiplexer, a first burning connector and a first logic processing unit; The first logic processing unit is used to assist the second processor in hardware coordination and control; The first port of the fourth multiplexer is connected to the second processor, and the second port of the fourth multiplexer is connected to the first port of the fifth multiplexer; The third port of the fourth multiplexer is connected to the first connector; The second port of the fifth multiplexer is connected to the first burning connector; The third port of the fifth multiplexer is connected to the first logic processing unit; In the fourth multiplexer, the link status between the first port and the second port, and the link status between the first port and the third port are adjustable; In the fifth multiplexer, the link status between the first port and the third port, and the link status between the second port and the third port are adjustable.

15. The server according to claim 14, characterized in that, The first auxiliary device includes a sixth multiplexer, a second programming connector, and a second logic processing unit; the second logic processing unit is used to assist the first processor in hardware coordination and control; The first connector is connected to a first terminal of the sixth multiplexer, a second terminal of the sixth multiplexer is connected to the second burning connector, and a third terminal of the sixth multiplexer is connected to the second logic processing unit; In the sixth multiplexer, the link status between the first port and the third port, and the link status between the second port and the third port are adjustable.

16. The server according to claim 7, wherein The second accessory device includes a first signal switch; The first signal exchanger is connected to the second processor via a plurality of first functional buses, where different first functional buses are used to transmit signals of different functions; The first signal switch is also connected to the first connector via a first serial bus.

17. The server according to claim 16, wherein The first accessory device includes a second signal switch, a third connector, and a third signal switch; The second signal switch is connected to the first connector via a second serial bus; the second signal switch is also connected to the third signal switch and the third connector; The third signal switch is used to receive a signal from a third processor.

18. The server according to claim 7, wherein: The second auxiliary device includes a first physical layer device, and the first auxiliary device includes a second physical layer device and a first network card; The second processor is connected to the first connector via a network card management bus; The second processor is connected to the first physical layer device via a parallel network data transmission bus, and the first physical layer device is connected to the first connector via a first serial network data transmission bus; the first connector is connected to the second physical layer device via a second serial network data transmission bus, and the second physical layer device is connected to the network interface; The second processor is further connected to the first physical layer device and the second physical layer device via a first control signal line.

19. The server according to claim 7, wherein: The shell of the server is provided with a first external interface; The first processor is connected to the first connector via a first display signal transmission bus, the first connector is connected to the second processor via a second display signal transmission bus, and the second processor is connected to the first connector via a first video transmission bus and a third serial bus; The first connector is connected to the first external interface on the server housing through a second video transmission bus and a fourth serial bus.

20. The server according to claim 19, wherein A signal converter is provided on the main board; The first connector is connected to the signal converter via a second video transmission bus and a fourth serial bus, and the signal converter is connected to the first external interface on the server housing via a cable.

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