Controller configured to control memory device, method of operating controller, and method of operating memory device including memory device and controller

Abstract

A controller configured to control a memory device, an operating method of the controller, and an operating method of a memory device including the memory device and the controller are disclosed. An operating method of a controller for controlling a memory device includes: sequentially receiving first hard decision data and first data from a first memory block of the memory device; starting initial soft decision decoding based on the first hard decision data and the first coarse data based on completion of the reception of the first hard decision data; replacing the first coarse data with the first soft decision data based on the first data received from the memory device while the initial soft decision decoding is performed; and after the initial soft decision decoding is completed, performing the first soft decision decoding based on the first hard decision data and the first soft decision data.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0013267, filed with the Korean Intellectual Property Office on January 29, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a semiconductor memory, and more particularly, to a controller configured to control a memory device, an operation method of the controller, and an operation method of a storage device including the memory device and the controller. Background Art

[0003] Semiconductor memories can be classified into volatile memories (such as static random access memory (SRAM) or dynamic random access memory (DRAM)) or non-volatile memories (such as flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM)). Volatile memories can lose the data stored therein when power is turned off, and non-volatile memories can retain the data stored therein even when power is turned off. [[ID=?]]

[0004] Flash memory devices can be used as high-capacity storage media. Due to the physical characteristics of flash memory devices or various environmental factors, errors may occur in the data stored in flash memory devices. Separate error correction processing can be used to correct the error. For example, an error correction code (ECC) engine can use iterative decoding for data read from a flash memory device to correct data errors. However, iterative decoding may cause latency. Due to the latency, performance may be reduced. Summary of the Invention

[0005] Provided are a controller configured to control a memory device with improved performance and improved reliability, an operation method of the controller, and an operation method of a storage device including the memory device and the controller.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0007] According to an aspect of the disclosure, an operation method of a controller for controlling a memory device includes: sequentially receiving first hard decision data and first data from a first memory block of the memory device; based on completion of the reception of the first hard decision data, starting initial soft decision decoding based on the first hard decision data and first rough data; while the initial soft decision decoding is being performed, replacing the first rough data with first soft decision data based on the first data received from the memory device; and after completion of the initial soft decision decoding, performing first soft decision decoding based on the first hard decision data and the first soft decision data.

[0008] According to one aspect of the disclosure, a controller for controlling a memory device includes: a NAND interface circuit configured to receive first hard decision data and first compressed soft decision data from the memory device; a decompression engine configured to decompress the first compressed soft decision data to generate first soft decision data; a random access memory (RAM) configured to store the first hard decision data and the first soft decision data; and an error correction code (ECC) engine configured to: based on the first hard decision data being stored in the RAM, start an initial soft decision decoding based on the first hard decision data and first rough data, and after the first soft decision data is stored in the RAM, perform a first soft decision decoding based on the first hard decision data and the first soft decision data.

[0009] According to one aspect of the disclosure, an operation method of a storage device including a memory device and a controller includes: sending, by the controller, a read command to the memory device; generating, by the memory device, first hard decision data and first soft decision data by performing a read operation on selected word lines based on the read command; generating, by the memory device, first compressed soft decision data by compressing the first soft decision data; sending, by the memory device, the first hard decision data and the first compressed soft decision data to the controller; starting, by the controller, an initial soft decision decoding based on the first hard decision data and first rough data based on the controller completing the reception of the first hard decision data; generating, by the controller, first decompressed soft decision data by decompressing the first compressed soft decision data; and performing a first soft decision decoding based on the first hard decision data and the first decompressed soft decision data.

[0010] According to one aspect of the disclosure, an operation method of a storage device including a memory device and a controller includes: sequentially reading hard decision data and soft decision data from the memory device; starting an initial soft decision decoding based on the hard decision data and rough data before completing the reading of the soft decision data; and starting a first soft decision decoding based on the hard decision data and the soft decision data after completing the reading of the soft decision data. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become more apparent from the following description in conjunction with the drawings.

[0012] Figure 1 is a block diagram showing a storage device according to an embodiment of the present disclosure.

[0013] Figure 2 is a block diagram showing a Figure 1 controller according to an embodiment of the present disclosure.

[0014] Figure 3 is a block diagram showing aFigure 1 Block diagram of a memory device.

[0015] Figure 4 It shows, according to an embodiment of the present disclosure, Figure 3 Diagram showing the threshold voltage distribution of memory cells in a memory cell array.

[0016] Figures 5A to 5C It is a diagram for describing the operations of reading hard decision data and soft decision data from memory cells according to an embodiment of the present disclosure.

[0017] Figure 6 It shows, according to an embodiment of the present disclosure, Figure 1 Flowchart of the operations of a storage device.

[0018] Figures 7A to 7E It is for describing, according to an embodiment of the present disclosure, Figure 6 Diagram of the operations of a storage device according to the flowchart.

[0019] Figure 8 It shows, according to an embodiment of the present disclosure, Figure 1 Flowchart of the operations of a storage device.

[0020] Figure 9A and Figure 9B It is for describing, according to an embodiment of the present disclosure, Figure 8 Diagram of the operations of a storage device according to the flowchart.

[0021] Figure 10 It shows, according to an embodiment of the present disclosure, Figure 1 Flowchart of the operations of a storage device.

[0022] Figure 11 It is for describing, according to an embodiment of the present disclosure, Figure 10 Diagram of the operations according to the flowchart.

[0023] Figure 12 It shows, according to an embodiment of the present disclosure, Figure 1 Flowchart of the operations of a controller.

[0024] Figure 13 It is for describing, according to an embodiment of the present disclosure, Figure 12 Diagram of the operations according to the flowchart.

[0025] Figure 14 It is for describing, according to an embodiment of the present disclosure, Figure 1 Flowchart of the operations of a controller.

[0026] Figure 15 It is for describing, according to an embodiment of the present disclosure, Figure 14Diagram of the operation of the flowchart.

[0027] Figure 16 Is a block diagram showing a storage device according to an embodiment of the present disclosure.

[0028] Figure 17 Is for describing according to an embodiment of the present disclosure Figure 16 Diagram of the variable compression engine.

[0029] Figure 18 Is for describing according to an embodiment of the present disclosure Figure 16 Diagram of the variable decompression engine.

[0030] Figure 19 Is a flowchart showing the operation of a storage device according to an embodiment of the present disclosure Figure 16 Of the storage device.

[0031] Figure 20 Is a flowchart showing the operation of a storage device according to an embodiment of the present disclosure Figure 16 Of the storage device.

[0032] Figure 21 Is a block diagram showing a storage device according to an embodiment of the present disclosure.

[0033] Figure 22 Is a block diagram showing a host-storage system according to an embodiment of the present disclosure. Detailed Description

[0034] The embodiments of the present disclosure are described in detail and clearly below to the extent that those of ordinary skill in the art can more easily implement the present disclosure.

[0035] In the detailed description or drawings, functional blocks represented by terms such as "unit", "module", etc. can be implemented in the form of hardware, software, or a combination thereof configured to perform specific functions. As an example, a "computing module" may refer to a hardware circuit configured to perform the related functions or operations disclosed in the detailed description.

[0036] Figure 1 Is a block diagram showing a storage device according to an embodiment of the present disclosure. Refer to Figure 1, the storage device 100 may include a controller 110 and a memory device 120. The memory device 120 may be, for example, a non-volatile memory device. In one embodiment, the storage device 100 may be a high-capacity storage device that can be configured to store data in a computing system (such as a solid-state drive (SSD) or a universal flash storage (UFS) card), but the embodiments are not limited thereto. In some embodiments, the storage device 100 may be included in a mobile system (such as a mobile phone, a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device). In some embodiments, the storage device 100 may be included in a personal computer, a laptop computer, a server, a media player, or an automotive device (such as a navigation system).

[0037] The controller 110 may be configured to control the memory device 120. For example, the controller 110 may store data in the memory device 120 or may read data stored in the memory device 120. For example, the controller 110 may send a command CMD and an address ADDR to the memory device 120 through a first signal line SIGL1, and may exchange data DATA with the memory device 120 through the first signal line SIGL1. In one embodiment, the first signal line SIGL1 may be a data signal line (e.g., a DQ line). The controller 110 may send a control signal CTRL to the memory device 120 through a second signal line SIGL2. In one embodiment, the control signal CTRL may be used to classify the signals exchanged through the first signal line SIGL1 into a command CMD, an address ADDR, and data DATA. However, the embodiments are not limited thereto.

[0038] The memory device 120 may operate under the control of the controller 110. For example, in response to or based on a signal received from the controller 110, the memory device 120 may store data or may output stored data. In one embodiment, the memory device 120 may include a flash memory device, but the embodiments are not limited thereto.

[0039] The controller 110 may include an error correction code (ECC) engine 111. The ECC engine 111 of the controller 110 may be configured to detect or correct errors in the data stored in the memory device 120. For example, due to the physical characteristics of the memory device 120 or various external factors, errors may occur in the data stored in the memory device 120. The ECC engine 111 may generate ECC data by performing ECC encoding on the user data to be stored in the memory device 120. The ECC data may be stored in the memory device 120 together with the user data. The ECC engine 111 may detect and correct the errors included in the read data by performing an ECC decoding operation based on the data read from the memory device 120 and the related ECC data.

[0040] In one embodiment, the ECC engine 111 may detect and correct errors in data based on a soft decision decoding scheme. For example, under the control of the controller 110, the memory device 120 may perform a read operation on the memory cells to generate hard decision data and soft decision data. Refer to Figures 5A to 5C Examples of hard decision data and soft decision data are described in detail. The controller 110 may receive the hard decision data and the soft decision data from the memory device 120, and may correct errors in the data by performing iterative soft decision decoding based on the received hard decision data and the received soft decision data.

[0041] In one embodiment, soft decision decoding may be performed using both hard decision data and soft decision data. For example, the controller 110 may receive both the hard decision data and the soft decision data, and then may start soft decision decoding. In this case, the time point at which soft decision decoding starts may be delayed.

[0042] According to an embodiment of the present disclosure, the memory device 120 may include a compression engine 121. In some embodiments, the compression engine 121 may be or may include a compression circuit. The compression engine 121 may compress the soft decision data to be sent to the controller 110, and may send the compressed soft decision data to the controller 110. In one embodiment, the compression engine 121 may perform a compression operation based on lossy compression, but the embodiment is not limited thereto. In this case, since the compressed soft decision data of a relatively small size may be provided to the controller 110, the time taken to send the soft decision data may be shortened. Therefore, the time point at which the ECC engine 111 of the controller 110 may start soft decision decoding may be advanced.

[0043] According to an embodiment of the present disclosure, before the soft decision data or the compressed soft decision data can be received from the memory device 120, the ECC engine 111 of the controller 110 may start soft decision decoding based on the hard decision data and coarse data. In this case, since soft decision decoding may start at the time point when the hard decision data can be completely received from the memory device 120, the time to start soft decision decoding may be advanced. Therefore, the performance of the storage device 100 may be improved.

[0044] In one embodiment, the rough data may indicate a data pattern or a data set determined based on the state of the memory device 120 (e.g., at least one of the degradation state of the memory device 120 and the number of program / erase (P / E) cycles). When the ECC engine 111 performs soft decision decoding using the hard decision data and the rough data, the accuracy of the result of the soft decision decoding may be relatively low. However, the ECC engine 111 may perform the soft decision decoding iteratively, and may perform subsequent soft decision decoding based on the soft decision data or the compressed soft decision data received from the memory device 120. Therefore, the accuracy of the soft decision decoding may be generally maintained.

[0045] In one embodiment, the ECC engine 111 may perform soft decision decoding iteratively based on a low density parity check (LDPC) code. However, the embodiment is not limited thereto. For example, in one embodiment, the ECC engine 111 may use at least one of an LDPC code, a Bose - Chaudhuri - Hocquenghem (BCH) code, a turbo code, a Reed - Solomon code, coded modulation (such as trellis - coded modulation (TCM) or block - coded modulation (BCM)), and various other codes or schemes to perform various encoding operations or decoding operations for error correction.

[0046] Figure 2 is a block diagram of Figure 1 the controller. Referring to Figure 1 and Figure 2 the controller 110 may include an ECC engine 111, a decompression engine 112, a host interface circuit 113, a NAND interface circuit 114, a central processing unit (CPU) 115, a random access memory (RAM) 116, and a flash translation layer (FTL) 117.

[0047] The ECC engine 111 may detect and correct errors in the data read from the memory device 120. An example of the operation of the ECC engine 111 is as described above, and is also described in detail with reference to the following drawings.

[0048] The decompression engine 112 may perform decompression on the data received from the memory device 120. For example, as described with reference to Figure 1 the memory device 120 may compress the soft decision data and may send the compressed soft decision data to the controller 110. The decompression engine 112 of the controller 110 may perform decompression on the compressed soft decision data to generate soft decision data. In one embodiment, the soft decision data generated by decompression may be used for the soft decision decoding of the ECC engine 111.

[0049] The host interface circuit 113 can communicate with an external host through or by using a host interface. The host interface can include at least one of various host interfaces (such as, a Peripheral Component Interconnect Express (PCI-express) interface, a PCI-express based Non-Volatile Memory Express (NVMe) interface, a Serial Advanced Technology Attachment (SATA) interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS) interface, a Universal Flash Storage (UFS) interface, and a Compute Express Link (CXL) interface).

[0050] The NAND interface circuit 114 can communicate with the memory device 120. In one embodiment, the NAND interface circuit 114 can be implemented to conform to a protocol such as Toggle or Open NAND Flash Interface (ONFI).

[0051] The CPU 115 can be configured to control the overall operation of the controller 110. For example, the CPU 115 can run various applications on the controller 110. The RAM 116 can be configured to store various information used by the controller 110 for operation. In one embodiment, the RAM 116 can be used as at least one of a working memory, a cache memory, and a buffer memory of the controller 110. In one embodiment, the RAM 116 can be an ECC buffer configured to store data (such as, hard decision data, soft decision data, and decoding results) to be used by the ECC engine 111.

[0052] The FTL 117 can perform various maintenance operations for efficiently managing or using the memory device 120. The maintenance operations can include operations such as address mapping operations, wear leveling operations, and garbage collection operations.

[0053] The address mapping operation of the FTL 117 may refer to an operation of converting a logical address received from an external host into a physical address to be used for actually storing data in the memory device 120. In one embodiment, the FTL 117 may use the L2P mapping data to perform the address mapping operation. The wear leveling operation of the FTL 117 may refer to an operation of preventing excessive degradation of a specific memory block among the memory blocks included in the memory device 120. For example, the FTL 117 may allocate the memory blocks included in the memory device 120 so as to be evenly used, thereby preventing excessive degradation of a specific memory block. In one embodiment, the wear leveling operation of the FTL 117 may be implemented by a firmware technique for balancing the erase counts of the memory blocks of the memory device 120. The garbage collection operation of the FTL 117 may refer to an operation of ensuring available memory blocks or capacity in the memory device 120 by copying valid data of a source memory block to a target memory block and erasing the source memory block or switching the source memory block to an idle block. In addition to the above operations, the FTL 117 may also perform various management operations (such as, bad block management operations). In one embodiment, some or all of the functions of the FTL 117 may be implemented by software, hardware, or a combination thereof.

[0054] Figure 3 is a block diagram of a memory device showing Figure 1 Refer to Figure 1 and Figure 3 FIGs. , the memory device 120 may include a compression engine 121, a memory cell array 122, a row address decoding circuit 123, a page buffer circuit 124, a data input / output (I / O) circuit 125, a buffer circuit 126, a control logic circuit 127, and a voltage generation circuit 128. In some embodiments, the compression engine 121 may be or may include a compression circuit.

[0055] The compression engine 121 may be configured to compress data read from the memory device 120 or the memory cell array 122. In one embodiment, the compression engine 121 may be configured to compress soft decision data. In one embodiment, the soft decision data may have a low-density data pattern including a relatively large number of specific bit values (e.g., the value one (“1”)). Thus, the soft decision data may be compressed to have a relatively small size. In one embodiment, the compression engine 121 may compress the soft decision data based on a lossy compression method.

[0056] The memory cell array 122 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of cell strings. Each of the plurality of cell strings may include a plurality of cell transistors stacked in a direction perpendicular to the substrate. The plurality of cell transistors may be connected in series between the bit line BL and the common source line. The plurality of cell transistors may be connected to the string select line SSL, the word line WL, and the ground select line GSL.

[0057] The row address decoding circuit 123 may be connected to the memory cell array 122 through the string select line SSL, the word line WL, and the ground select line GSL. The row address decoding circuit 123 may operate under the control of the control logic circuit 127. For example, under the control of the control logic circuit 127, the row address decoding circuit 123 may decode the row address RA received from the buffer circuit 126; based on the decoding result, the row address decoding circuit 123 may control or drive the string select line SSL, the word line WL, and the ground select line GSL, or may control the voltage applied to the string select line SSL, the word line WL, and the ground select line GSL.

[0058] The page buffer circuit 124 may be connected to the memory cell array 122 through the bit line BL. The page buffer circuit 124 may be connected to the data I / O circuit 125 through a plurality of data lines DL. The page buffer circuit 124 may operate under the control of the control logic circuit 127. For example, in the programming operation of the memory device 120, the page buffer circuit 124 may store the data to be programmed in the memory cell array 122 under the control of the control logic circuit 127. In the read operation of the memory device 120, the page buffer circuit 124 may sense the voltage of the bit line BL and may store the sensed result as read data.

[0059] In one embodiment, hard decision data and soft decision data may be generated by or during one read operation of the memory device 120. For example, the page buffer circuit 124 may include a plurality of latches for sensing voltage changes of a plurality of bit lines BL. The page buffer circuit 124 may store the hard decision data in a first latch (e.g., an S latch) by sensing the voltage of the sense node connected to each of the plurality of bit lines BL at a first time point. The page buffer circuit 124 may store the soft decision data in a second latch (e.g., an F latch) by sensing the voltage of the sense node connected to each of the plurality of bit lines BL at each of a second time point and a third time point. In one embodiment, the first time point to the third time point may be different from each other. The above method of reading hard decision data and soft decision data is provided as an example, and the embodiment is not limited thereto.

[0060] The data I / O circuit 125 can be connected to the page buffer circuit 124 through multiple data lines DL. The data I / O circuit 125 can receive the column address CA from the buffer circuit 126. The data I / O circuit 125 can send the read data read by the page buffer circuit 124 to the buffer circuit 126 according to the column address CA. The data I / O circuit 125 can send the data received from the buffer circuit 126 to the page buffer circuit 124 based on the column address CA.

[0061] In one embodiment, the data I / O circuit 125 can send the soft decision data received from the page buffer circuit 124 to the compression engine 121. The compression engine 121 can generate compressed soft decision data by compressing the soft decision data received from the data I / O circuit 125. The compressed soft decision data can be provided to the buffer circuit 126.

[0062] The buffer circuit 126 can receive the command CMD and the address ADDR from the controller 110 through the first signal line SIGL1, and can exchange data DATA with the controller 110 through the first signal line SIGL1. In one embodiment, the first signal line SIGL1 can be a data signal line (e.g., DQ line).

[0063] The buffer circuit 126 can operate under the control of the control logic circuit 127. For example, the control logic circuit 127 can exchange control signals CTRL with the controller 110 through the second signal line SIGL2. The control logic circuit 127 can control the buffer circuit 126 based on the control signal CTRL so that the buffer circuit 126 routes the command CMD, the address ADDR, and the data DATA. Under the control of the control logic circuit 127, the buffer circuit 126 can identify the signal received through the first signal line SIGL1 as the command CMD or the address ADDR. The buffer circuit 126 can send the command CMD to the control logic circuit 127. The buffer circuit 126 can send the row address RA of the address ADDR to the row address decoding circuit 123 and can send the column address CA of the address ADDR to the data I / O circuit 125. The buffer circuit 126 can exchange data DATA with the data I / O circuit 125.

[0064] The control logic circuit 127 can decode the command CMD received from the buffer circuit 126, and can control the memory device 120 or various components of the memory device 120 based on the decoding result.

[0065] Under the control of the control logic circuit 127, the voltage generation circuit 128 can generate various operating voltages VOP used in the memory device 120. In one embodiment, the operating voltages VOP can include a programming voltage, a pass voltage, a selected read voltage, a non-selected read voltage, an erase voltage, and a verify voltage.

[0066] Figure 4 is a diagram showing Figure 3 the threshold voltage distribution of the memory cells of a memory cell array. In one embodiment, each of the memory cells in the memory cell array 122 may be a triple-level cell (TLC) configured to store 3 bits. However, the embodiments are not limited thereto. For example, each of the memory cells may be a single-level cell (SLC) configured to store one bit, or may be a cell configured to store more than one bit (e.g., a multi-level cell (MLC), a triple-level cell (TLC), a quad-level cell (QLC), or a penta-level cell (PLC)).

[0067] Referring to Figure 3 and Figure 4 , the memory cells included in the memory cell array 122 can be programmed to have an erase state E and one of a plurality of programming states P1 to P7. The threshold voltage (Vth) or state of each memory cell may correspond to the data or bits stored in each memory cell. The memory device 120 can determine the threshold voltage or programming state of the memory cells by applying a plurality of read voltages VRD1 to VRD7 to the word lines connected to the memory cells, and can read the data stored in the memory cells based on the determination result.

[0068] In one embodiment, the threshold voltage of the memory cells can change due to various factors. In this case, errors may occur in the data read from the memory cells. Various error correction schemes can be used to detect and correct the errors.

[0069] Figures 5A to 5C is a diagram for describing the operations of reading hard decision data and soft decision data from memory cells. For ease of description, referring to Figures 5A to 5C an example of the operations of reading hard decision data and soft decision data from a memory cell having a third programming state P3 and a fourth programming state P4 is described. However, the embodiments are not limited thereto. For example, the operations of reading hard decision data and soft decision data from a memory cell having any other programming state can be similarly performed.

[0070] Referring to Figure 3 , Figure 4 , Figure 5A , Figure 5B and Figure 5C, the memory cell can be programmed to have one of a third programming state P3 and a fourth programming state P4. In this case, the memory device 120 can apply a fourth read voltage VRD4 to the selected word line to determine whether the memory cell has the third programming state P3 or the fourth programming state P4. In one embodiment, the data corresponding to "the memory cell whose threshold voltage is lower than the fourth read voltage VRD4" can be determined to have a value of one ("1"), and the data corresponding to "the memory cell whose threshold voltage is higher than the fourth read voltage VRD4" can be determined to have a value of zero ("0").

[0071] In one embodiment, the data of the memory cell determined by the fourth read voltage VRD4 can be hard decision data HD. For example, the hard decision data HD can be data generated by distinguishing two adjacent programming states (e.g., P3 and P4) using one read voltage (e.g., VRD4). In this case, the hard decision data HD may not reflect the errors occurring in the memory cell. For example, the first memory cell can be programmed to the third programming state P3. After that, due to various factors, the threshold voltage of the first memory cell can be higher than the fourth read voltage VRD4. In this case, the data corresponding to the first memory cell programmed to the third programming state P3 can have a value of one ("1"), but the hard decision data HD can have a value of zero ("0"). In contrast, the second memory cell can be programmed to the fourth programming state P4. After that, due to various factors, the threshold voltage of the second memory cell can be lower than the fourth read voltage VRD4. In this case, the data corresponding to the second memory cell programmed to the fourth programming state P4 should have a value of zero ("0"), but the hard decision data HD can have a value of one ("1"). For example, due to various factors, the hard decision data HD read from the memory cell may include errors; in this case, the errors may not be corrected by the ECC engine 111.

[0072] To supplement the hard decision data HD, the memory device 120 can read soft decision data SD from the memory cell. For example, the memory device 120 can detect the memory cells among the memory cells having a threshold voltage included in the range from (VRD4 - a) to (VRD4 + a). The bit value of the soft decision data SD corresponding to "the memory cell having a threshold voltage included in the range from (VRD4 - a) to (VRD4 + a)" can be determined to have a value of zero ("0"), and the bit value of the soft decision data SD corresponding to "the memory cell having a threshold voltage outside the range from (VRD4 - a) to (VRD4 + a)" can be determined to have a value of one ("1").

[0073] In one embodiment, the soft decision data SD may be determined such that a memory cell having a value of one ("1") may be a strong error type, and a memory cell having a value of zero ("0") may be a weak error type.

[0074] For example, among the memory cells programmed to the third programming state P3, a memory cell with "soft decision data SD determined to have a value of one ("1") and hard decision data HD determined to have a value of one ("1")" may have no error (e.g., the memory cells in the first region R1 may have no error). Among the memory cells programmed to the third programming state P3, a memory cell with "soft decision data SD determined to have a value of zero ("0") and hard decision data HD determined to have a value of one ("1")" may have no error (e.g., the memory cells in the second region R2 may have no error). Among the memory cells programmed to the third programming state P3, an error may occur in a memory cell with "soft decision data SD determined to have a value of zero ("0") and hard decision data HD determined to have a value of zero ("0")" (e.g., an error may exist in the memory cells in the third region R3).

[0075] Similarly, among the memory cells programmed to the fourth programming state P4, a memory cell with "soft decision data SD determined to have a value of one ("1") and hard decision data HD determined to have a value of zero ("0")" may have no error (e.g., the memory cells in the fourth region R4 may have no error). Among the memory cells programmed to the fourth programming state P4, a memory cell with "soft decision data SD determined to have a value of zero ("0") and hard decision data HD determined to have a value of zero ("0")" may have no error (e.g., the memory cells in the third region R3 may have no error). Among the memory cells programmed to the fourth programming state P4, an error may occur in a memory cell with "soft decision data SD determined to have a value of zero ("0") and hard decision data HD determined to have a value of one ("1")" (e.g., an error may occur in the memory cells in the second region R2).

[0076] Based on the above description, the probability of an error occurring in the memory cells of the first region R1 and the fourth region R4 may be low, which may be referred to as a "strong error type". In contrast, the probability of an error occurring in the memory cells of the second region R2 and the third region R3 may exist, which may be referred to as a "weak error type".

[0077] As described above, the soft decision data SD can be used to determine whether the hard decision data HD read from the memory cell is error-free or has a relatively high probability of error occurrence. Thus, since data with a relatively high error probability can be identified, the ECC engine 111 of the controller 110 can improve the error correction ability by performing decoding (e.g., soft decision decoding) using the hard decision data HD and the soft decision data SD.

[0078] In one embodiment, the memory device 120 can read the soft decision data SD based on various schemes. For example, the memory device 120 can distinguish the memory cells in the first region R1 from the memory cells in the second region R2 to the fourth region R4 by applying a voltage (VRD4-a) to the selected word line. Thereafter, the memory device 120 can distinguish the memory cells in the first region R1 to the third region R3 from the memory cells in the fourth region R4 by applying a voltage (VRD4+a) to the selected word line. As Figure 5A shown, the memory device 120 can combine the results of the above two read operations and can generate the soft decision data SD.

[0079] In some embodiments, the memory device 120 can generate the hard decision data HD and the soft decision data SD through one read operation (e.g., using one read operation, or during one read operation). For example, the page buffer circuit 124 can include a plurality of page buffers respectively connected to a plurality of bit lines. Figure 5B An example of one of the plurality of page buffers is shown.

[0080] The page buffer PB of the page buffer circuit 124 can include a precharge circuit CHC and a plurality of latches S-LAT, F-LAT, D-LAT, and C-LAT. The precharge circuit CHC can be connected between the bit line BL and the sense node SO, and can be configured to precharge the bit line BL and the sense node SO according to the operation of the memory device 120. The plurality of latches S-LAT, F-LAT, D-LAT, and C-LAT can be configured to sense and store the voltage change of the sense node SO, or control the voltage of the sense node SO based on the data stored therein.

[0081] For example, as Figure 5C shown, the page buffer circuit 124 can perform a first sense node precharge operation SO PCH1, a first sense node development operation SO DEV1, a second sense node precharge operation SO PCH2, and a second sense node development operation SO DEV2. In one embodiment, before the first sense node precharge operation SO PCH1, at least one of the memory device 120 and the page buffer circuit 124 can perform a bit line precharge operation.

[0082] In the first sense node precharge operation SO_PCH1, the precharge circuit CHC of the page buffer PB can precharge the sense node SO. In the first sense node develop operation SO_DEV1, the precharge circuit CHC of the page buffer PB can electrically connect the bit line BL and the sense node SO. The voltage of the sense node SO can decrease according to the voltage level of the bit line BL. The slope of the decrease in the voltage level of the sense node SO can vary according to the threshold voltage of the associated memory cell and the voltage applied to the associated word line. For example, based on the fourth read voltage VRD4 being applied to the selected word line, when the threshold voltage of the memory cell is included in the first region R1, the voltage level of the sense node SO can decrease along the Figure 5C solid line shown in. In this example, when the threshold voltage of the memory cell is included in the second region R2, the voltage level of the sense node SO can decrease along the Figure 5C dotted line shown in. Additionally, in this example, when the threshold voltage of the memory cell is included in the third region R3, the voltage level of the sense node SO can decrease along the Figure 5C double-dotted line shown in. Further, in this example, when the threshold voltage of the memory cell is included in the fourth region R4, the voltage level of the sense node SO can decrease along the Figure 5C dashed line shown in.

[0083] According to an embodiment, at a first time point t1, the page buffer PB can set the value of the S-latch S-LAT based on the level of the sense node SO. For example, at the first time point t1, when the level of the sense node SO is lower than the reference voltage REF, the value of the S-latch S-LAT can be set to one ("1"). In the Figure 5A and Figure 5C embodiments, the value of the S-latch S-LAT corresponding to each of the memory cells included in the first region R1 and the second region R2 can be set to one ("1"). In one embodiment, the value stored in the S-latch S-LAT can be used as hard decision data HD.

[0084] After that, in the second sense node precharge operation SO_PCH2, the precharge circuit CHC of the page buffer PB can precharge the sense node SO. In the second sense node develop operation SO_DEV2, the precharge circuit CHC of the page buffer PB can electrically connect the bit line BL and the sense node SO. In this case, as described above, the voltage of the sense node SO can decrease.

[0085] According to an embodiment, at a second time point t2, the page buffer PB may set the value of the F-latch F-LAT based on the level of the sense node SO. For example, at the second time point t2, when the level of the sense node SO is lower than the reference voltage REF, the value of the F-latch F-LAT may be set to one ("1"). In Figure 5A and Figure 5C 's embodiment, the value of the F-latch F-LAT corresponding to each of the memory cells included in the first region R1 may be set to one ("1").

[0086] After that, at a third time point t3, the page buffer PB may set the value of the F-latch F-LAT based on the level of the sense node SO. For example, at the third time point t3, when the level of the sense node SO is higher than the reference voltage REF, the value of the F-latch F-LAT may be set to one ("1"). In the example shown in Figure 5A and Figure 5C , the value of the F-latch F-LAT corresponding to each of the memory cells included in the fourth region R4 may be set to one ("1"). The value stored in the F-latch F-LAT may be used as soft decision data SD.

[0087] As described above, according to an embodiment of the present disclosure, during one read operation, hard decision data HD and soft decision data SD may be read from the memory cells. The thus read hard decision data HD and soft decision data SD may be provided to the controller 110.

[0088] The above method of reading the hard decision data HD and the soft decision data SD is provided as an example, and the embodiment is not limited thereto.

[0089] Figure 6 is a flowchart showing the operation of the Figure 1 storage device. For ease of description, additional descriptions associated with the above components may be omitted to avoid redundancy. Referring to Figure 1 and Figure 6 , in operation S110, the controller 110 may send a read command to the memory device 120. For example, the controller 110 may provide a read command for reading data from the memory device 120 to the memory device 120.

[0090] In operation S120, the memory device 120 may perform a read operation in response to the read command. For example, the memory device 120 may perform a read operation on the memory cells connected to the selected word line in response to the read command and may generate hard decision data HD and soft decision data SD. Examples of the operations of generating the hard decision data HD and the soft decision data SD using the read operation have been described above, and thus, additional descriptions may be omitted to avoid redundancy.

[0091] In operation S130, the memory device 120 may send the hard decision data HD and the soft decision data SD to the controller 110. For example, under the control of the controller 110, the memory device 120 may sequentially send the hard decision data HD and the soft decision data SD to the controller 110.

[0092] In operation S140, the controller 110 may determine whether the reception of the hard decision data HD is completed. In some embodiments, the controller 110 may determine whether all of the hard decision data HD has been received. When the reception of the hard decision data HD is not completed (the "No" of operation S140), the controller 110 may continue to perform operation S130 (e.g., continue to receive the hard decision data HD and the soft decision data SD).

[0093] When it is determined that all of the hard decision data HD has been received (the "Yes" of operation S140), in operation S150, the controller 110 may start an initial soft decision decoding based on the hard decision data HD and the rough data CRS. For example, as described above, the controller 110 may sequentially receive the hard decision data HD and the soft decision data SD from the memory device 120. For example, even if the reception of the hard decision data HD may be completed, the reception of the soft decision data SD may not have been completed yet. In this case, the ECC engine 111 of the controller 110 may first start the initial soft decision decoding using the rough data CRS instead of the not yet fully received soft decision data SD. In one embodiment, the rough data CRS may be a data pattern preset based on the state of the memory device 120. In one embodiment, the initial soft decision decoding may refer to a soft decision decoding that may be performed before the "first soft decision decoding included in the iterative soft decision decoding performed by the ECC engine 111". In some embodiments, the initial soft decision decoding may be referred to as, for example, a preliminary soft decision decoding, a zero-th soft decision decoding, and a 0-th soft decision decoding, but the embodiments are not limited thereto.

[0094] At operation S160, while performing initial soft decision decoding, the controller 110 may update the rough data CRS based on the soft decision data SD received from the memory device 120. In one embodiment, operation S160 may be performed simultaneously, in parallel, or independently of operations S130 and S150. For example, during the initial soft decision decoding SD_DEC0, the controller 110 may replace the rough data CRS with the received soft decision data SD or may update the rough data CRS based on a specific unit (e.g., a codeword unit, a sector unit, or a page unit) such that the rough data CRS is changed to the received soft decision data SD while receiving the soft decision data SD from the memory device 120. In some embodiments, during the initial soft decision decoding SD_DEC0, the controller 110 may replace the rough data CRS with the received soft decision data SD in real time or may update the rough data CRS such that the rough data CRS is changed to the received soft decision data SD in real time while receiving the soft decision data SD from the memory device 120.

[0095] At operation S170, the controller 110 may perform subsequent soft decision decoding or iterative soft decision decoding based on the hard decision data HD and the updated soft decision data SD.

[0096] Generally, since soft decision decoding may use both the hard decision data HD and the soft decision data SD, soft decision decoding may start after both the hard decision data HD and the soft decision data SD are received. In contrast, according to an embodiment of the present disclosure, at the time point when the reception of the hard decision data HD is completed (e.g., before all the soft decision data SD are received), the ECC engine 111 of the controller 110 may start the initial soft decision decoding using the rough data CRS. Accordingly, since the time point at which the initial soft decision decoding starts is advanced, the time point at which the ECC engine 111 completes decoding may be advanced. Therefore, the overall performance of the storage device 100 is improved.

[0097] Figures 7A to 7E is a diagram for describing the operation of a storage device of a flowchart according to Figure 6 As an example, referring to Figure 1 and Figure 7A , during the time period from t0 to ta, the controller 110 may receive the hard decision data HD from the memory device 120. The received hard decision data HD may be stored in the ECC buffer. In one embodiment, the ECC buffer may be or may correspond to the RAM 116 included in the Figure 2 controller 110. In some embodiments, the ECC buffer may be a separate storage device for temporarily storing data received from the memory device 120 and may be located inside or outside the controller 110.

[0098] After the hard decision data HD is stored in the ECC buffer, during the time period from ta to tb, the ECC engine 111 may perform iterative hard decision decoding HD_DEC0 to HD_DECk using the hard decision data HD, where k may be a positive integer. In one embodiment, the ECC engine 111 may iteratively perform the hard decision decoding a predetermined number of times.

[0099] The iterative hard decision decoding may fail (or the result of the iterative hard decision decoding may indicate a decoding failure). In this case, during the time period from tb to tc, the controller 110 may receive soft decision data SD from the memory device 120. The received soft decision data SD may be stored in the ECC buffer. In one embodiment, when the memory device 120 performs a separate operation for reading the soft decision data SD, the time for reading the soft decision data SD may be added between the time point when the hard decision decoding is completed and the time point when the reception of the soft decision data SD starts.

[0100] At the c-th time point tc when all the soft decision data SD is received and stored in the ECC buffer, the ECC engine 111 may start the initial soft decision decoding SD_DEC0 using the hard decision data HD and the soft decision data SD. After that, the ECC engine 111 may continue with subsequent soft decision decoding SD_DEC1 to SD_DECn, where n may be a positive integer. In one embodiment, the ECC engine 111 may iteratively perform the soft decision decoding a predetermined number of times.

[0101] Hereinafter, for ease of description, the configuration of changing or modifying the hard decision data or the soft decision data by iterative decoding is omitted. However, the embodiment is not limited thereto. For example, the data stored in the ECC buffer may be changed by the iteration of decoding. For example, when the hard decision decoding is iteratively performed, the result of the previous hard decision decoding may be applied to the hard decision data HD. In some embodiments, when the soft decision decoding is iteratively performed, the result of the previous soft decision decoding may be applied to the soft decision data SD.

[0102] As another example, referring to Figure 1 and Figure 7B, the controller 110 may receive hard decision data HD from the memory device 120 and may perform iterative hard decision decoding HD_DEC0 to HD_DECk. When the iterative hard decision decoding HD_DEC0 to HD_DECk fails (or when the results of the iterative hard decision decoding HD_DEC0 to HD_DECk indicate a decoding failure), at the b-th time point tb, the controller 110 may receive soft decision data SD from the memory device 120. In this case, the controller 110 may start initial soft decision decoding SD_DEC0 using the coarse data CRS while receiving the soft decision data SD from the memory device 120. For example, before completing the reception of the soft decision data SD, at the b-th time point tb, the controller 110 may start initial soft decision decoding SD_DEC0 using the coarse data CRS. After completing the reception of the soft decision data SD, the coarse data CRS may be replaced with the soft decision data SD, and the ECC engine 111 may perform subsequent soft decision decoding SD_DEC1 to SD_DECn using the hard decision data HD and the soft decision data SD. In this case, compared with the example shown in Figure 7A , since the ECC engine 111 starts the initial soft decision decoding SD_DEC0 before completing the reception of the soft decision data SD, the decoding start time point may be advanced.

[0103] As another example, referring to Figure 1 and Figure 7C , the controller 110 may sequentially receive hard decision data HD and soft decision data SD from the memory device 120. For example, under the control of the controller 110, the memory device 120 may read the hard decision data HD and the soft decision data SD during one read operation. During the time period from t0 to t1, the controller 110 may receive the hard decision data HD from the memory device 120. The received hard decision data HD may be stored in the ECC buffer. Thereafter, during the time period from t1 to t2, the controller 110 may receive the soft decision data SD from the memory device 120. The received soft decision data SD may be stored in the ECC buffer.

[0104] After both the hard decision data HD and the soft decision data SD are stored in the ECC buffer, the ECC engine 111 of the controller 110 may start initial soft decision decoding SD_DEC0. For example, at the second time point t2, both the hard decision data HD and the soft decision data SD may be received and stored in the ECC buffer. In this case, the ECC engine 111 may perform iterative soft decision decoding SD_DEC0 to SD_DECn using the hard decision data HD and the soft decision data SD.

[0105] As described above, in Figure 7CIn the example shown, the controller 110 may sequentially receive hard decision data HD and soft decision data SD from the memory device 120. Thus, compared with Figure 7A the example shown in Figure 7C the soft decision decoding start time point in the example shown in

[0106] may be advanced. Figure 7D Hereinafter, an example of an operation method of the storage device 100 according to the Figure 6 flowchart will be described in detail. Referring to Figure 1 and Figure 7D the controller 110 may sequentially receive hard decision data HD and soft decision data SD from the memory device 120. For example, under the control of the controller 110, the memory device 120 may read the hard decision data HD and the soft decision data SD through one read operation. During the time period from t0 to t1a, the controller 110 may receive the hard decision data HD from the memory device 120. The received hard decision data HD may be stored in the ECC buffer.

[0107] At the first time point t1a when the hard decision data HD is completely received, the ECC engine 111 of the controller 110 may start initial soft decision decoding SD_DEC0 using the hard decision data HD and the rough data CRS. For example, based on the hard decision data HD being stored in the ECC buffer, the ECC engine 111 may start initial soft decision decoding SD_DEC0 using the hard decision data HD and the rough data CRS.

[0108] For example, during the time period from t1a to t2a, the controller 110 may receive the soft decision data SD from the memory device 120. For example, even if all the soft decision data SD has not been received, the ECC engine 111 may start initial soft decision decoding SD_DEC0 using the rough data CRS instead of the soft decision data SD. In this case, since the soft decision decoding is performed at the time point when the hard decision data HD is completely received, compared with Figure 7C the embodiment shown in

[0109] In one embodiment, during a time period from t1a to t2a (e.g., while the initial soft decision decoding SD_DEC0 is being performed), the controller 110 may receive soft decision data SD from the memory device 120. In this case, the controller 110 may update the rough data CRS based on the received soft decision data SD. For example, at the second time point t2a when the reception of the soft decision data SD is completed, the rough data CRS may be replaced with the soft decision data SD, or may be updated to be changed to the soft decision data SD. Thus, the subsequent soft decision decoding (e.g., SD_DEC1 to SD_DECn) may be performed using the hard decision data HD and the soft decision data SD.

[0110] In one embodiment, the operation of changing the rough data CRS to the soft decision data SD may be performed during the initial soft decision decoding SD_DEC0. For example, referring to Figure 7E , at the first time point t1a, the ECC engine 111 may start the initial soft decision decoding SD_DEC0 using the rough data CRS. At the same time, the controller 110 may start receiving the soft decision data SD from the memory device 120 or may continue to receive the soft decision data SD from the memory device 120. While the soft decision decoding is being performed, the rough data CRS may be replaced with the received soft decision data SD in a given unit or in real time. For example, when the initial soft decision decoding SD_DEC0 is being performed and the soft decision data SD is received, the rough data CRS may be replaced with the soft decision data SD, or may converge to the soft decision data SD.

[0111] In one embodiment, at the initial time point (e.g., T1) of the initial soft decision decoding SD_DEC0, since the ratio of the rough data CRS to the soft decision data SD may be relatively high, the result SD_DEC0 of the initial soft decision decoding may be relatively inaccurate. In contrast, when the rough data CRS is updated, at a later time point (e.g., T2) of the initial soft decision decoding SD_DEC0, since the ratio of the soft decision data SD to the rough data CRS may be relatively high, the result of the initial soft decision decoding SD_DEC0 may be relatively accurate. In addition, in the subsequent iteratively performed soft decision decoding SD_DEC1 to SD_DECn, since the soft decision data SD received from the memory device 120 may be used, the soft decision decoding may be generally performed normally.

[0112] As described above, according to an embodiment of the present disclosure, the controller 110 may sequentially receive hard decision data HD and soft decision data SD from the memory device 120. In this case, at the time point when the reception of the hard decision data HD is completed, the ECC engine 111 of the controller 110 may start initial soft decision decoding SD_DEC0 (or, preliminary soft decision decoding or initial soft decision decoding) using the hard decision data HD and the rough data CRS. Therefore, before the soft decision data SD is received, since the ECC engine 111 is capable of starting the initial soft decision decoding SD_DEC0, the time point when the decoding of the ECC engine 111 is completed may be advanced. Accordingly, the overall performance of the storage device 100 may be improved.

[0113] Figure 8 is a flowchart showing Figure 1 the operation of the storage device. For ease of description, additional descriptions associated with the above components may be omitted to avoid redundancy. Referring to Figure 1 and Figure 8 , in operation S210, the controller 110 may send a read command to the memory device 120. In operation S220, the memory device 120 may perform a read operation in response to the read command. The memory device 120 may perform the read operation to generate hard decision data HD and soft decision data SD.

[0114] In operation S230, the memory device 120 may compress the soft decision data SD to generate compressed soft decision data CSD. For example, as described with reference to Figure 1 and Figure 3 , the memory device 120 may include a compression engine 121. The compression engine 121 may compress the soft decision data SD to generate compressed soft decision data CSD. In one embodiment, the soft decision data SD may include a specific pattern. For example, when a relatively large number of memory cells have a strong error type, there may be a relatively large number of bits corresponding to the value one ("1") among the bits included in the soft decision data SD. In contrast, when a relatively large number of memory cells have a weak error type, there may be a relatively large number of bits corresponding to the value zero ("0") among the bits included in the soft decision data SD. Generally, memory cells having a strong error type may be relatively common. Therefore, the compression engine 121 may generate the compressed soft decision data CSD based on the characteristics of the soft decision data SD. In one embodiment, the compression engine 121 may perform the compression operation based on a lossy compression method.

[0115] In operation S240, the memory device 120 may sequentially send the hard decision data HD and the compressed soft decision data CSD to the controller 110.

[0116] At operation S250, the controller 110 may determine whether the reception of the hard decision data HD is complete. In some embodiments, the controller 110 may determine whether all of the hard decision data HD has been received. When the reception of the hard decision data HD is not complete (the "No" of operation S250), the controller 110 may continue to perform operation S240 (e.g., continue to receive the hard decision data HD and the compressed soft decision data CSD).

[0117] When it is determined that all of the hard decision data HD has been received (the "Yes" of operation S250), at operation S260, the controller 110 may start initial soft decision decoding using the hard decision data HD and the rough data CRS. Operation S260 may be similar to operation S150, and thus, additional description may be omitted to avoid redundancy.

[0118] At operation S270, the controller 110 may decompress the compressed soft decision data CSD received from the memory device 120 to generate the soft decision data SD, and may update the rough data CRS based on the soft decision data SD. In one embodiment, operation S270 may be performed simultaneously, in parallel, or independently of operation S240 and operation S260. Except for the operation of decompressing the compressed soft decision data CSD, operation S270 may be similar to Figure 6 operation S160, and thus, additional description may be omitted to avoid redundancy.

[0119] At operation S280, the controller 110 may perform iterative soft decision decoding (or subsequent soft decision decoding) based on the hard decision data HD and the updated soft decision data SD. Operation S280 may be similar to Figure 6 operation S170, and thus, additional description may be omitted to avoid redundancy.

[0120] Figure 9A and Figure 9B are diagrams for describing the operations of a memory device according to the flowchart of Figure 8 . For example, referring to Figure 1 and Figure 9A , the controller 110 may sequentially receive the hard decision data HD and the compressed soft decision data CSD from the memory device 120. For example, under the control of the controller 110, the memory device 120 may read the hard decision data HD and the soft decision data SD during one read operation. The memory device 120 may generate the compressed soft decision data CSD by compressing the soft decision data SD using the compression engine 121. The memory device 120 may sequentially send the hard decision data HD and the compressed soft decision data CSD to the controller 110.

[0121] During the time period from t0 to t1b, the controller 110 may receive hard decision data HD from the memory device 120, and the received hard decision data HD may be stored in the ECC buffer. During the time period from t1b to t2b, the controller 110 may receive compressed soft decision data CSD from the memory device 120. The controller 110 may decompress the compressed soft decision data CSD to generate soft decision data SD, and the generated soft decision data SD may be stored in the ECC buffer. In one embodiment, since the compressed soft decision data CSD having a relatively small size may be sent from the memory device 120 to the controller 110, the time for sending data may be shortened.

[0122] At the second time point t2b when both the hard decision data HD and the soft decision data SD are stored in the ECC buffer, the ECC engine 111 of the controller 110 may start an initial soft decision decoding SD_DEC0 using the hard decision data HD and the soft decision data SD. Thereafter, the ECC engine 111 may perform subsequent soft decision decodings SD_DEC1 to SD_DECn.

[0123] As another example, referring to Figure 1 and Figure 9B , the controller 110 may sequentially receive the hard decision data HD and the compressed soft decision data CSD from the memory device 120. The configuration for sequentially receiving the hard decision data HD and the compressed soft decision data CSD may be similar to the configuration described with reference to Figure 9A , and thus, additional description may be omitted to avoid redundancy.

[0124] At the time point t1c when the hard decision data HD is completely received (or at the time point when the hard decision data HD is completely stored in the ECC buffer), the controller 110 may start the initial soft decision decoding SD_DEC0. For example, at the first time point t1c, the ECC engine 111 of the controller 110 may start the initial soft decision decoding SD_DEC0 based on the hard decision data HD and the rough data CRS. Accordingly, since the ECC engine 111 starts the initial soft decision decoding SD_DEC0 before the compressed soft decision data CSD is received, the time point at which the soft decision decoding starts may be advanced.

[0125] In one embodiment, during the time period from t1c to t2c, the controller 110 may receive the compressed soft decision data CSD from the memory device 120. The controller 110 may decompress the compressed soft decision data CSD to generate the soft decision data SD. While the initial soft decision decoding SD_DEC0 is being executed, the controller 110 may update the coarse data CRS based on the soft decision data SD. The ECC engine 111 may use the updated soft decision data SD to perform subsequent soft decision decodings SD_DEC1 to SD_DECn. In one embodiment, in addition to the controller 110 decompressing the compressed soft decision data CSD, the configuration for updating the coarse data CRS may be similar to that Figure 7D and Figure 7E described, and thus, additional description may be omitted to avoid redundancy.

[0126] As described above, the controller 110 may sequentially receive the hard decision data HD and the compressed soft decision data CSD from the memory device 120. At the time point when the reception of the hard decision data HD is completed, the ECC engine 111 of the controller 110 may start the initial soft decision decoding SD_DEC0 based on the hard decision data HD and the coarse data CRS. While the initial soft decision decoding SD_DEC0 is being executed, the controller 110 may decompress the compressed soft decision data CSD received from the memory device 120 to generate the soft decision data SD, and may update or replace the coarse data CRS based on the soft decision data SD. Thus, while the overall decoding performance may be maintained, the decoding start time point may be advanced.

[0127] Figure 10 is a flowchart showing Figure 1 the operation of the storage device. For ease of description, additional description associated with the above components may be omitted to avoid redundancy. Referring to Figure 1 and Figure 10 , the controller 110 and the memory device 120 may perform operations S310 to operation S330. Operations S310 to S330 may be similar to Figure 8 operations S210 to S230, and thus, additional description may be omitted to avoid redundancy.

[0128] At operation S340, the memory device 120 may send hard decision data HD to the controller 110. At operation S350, the controller 110 may perform an initial soft decision decoding SD_DEC0 based on the hard decision data HD and the rough data CRS. At operation S360, the memory device 120 may send the compressed soft decision data CSD to the controller 110. At operation S370, the controller 110 may generate soft decision data SD by decompressing the compressed soft decision data CSD while the initial soft decision decoding SD_DEC0 is being performed, and may replace the rough data CRS with the soft decision data SD. At operation S380, the controller 110 may perform subsequent soft decision decoding based on the hard decision data HD and the soft decision data SD.

[0129] In one embodiment, operations S340 and S360 may be performed sequentially. In one embodiment, operations S360 and S370 may be performed sequentially. For example, in Figure 8 the example shown, the controller 110 may receive the compressed soft decision data CSD from the memory device 120 while the initial soft decision decoding SD_DEC0 is being performed; while the compressed soft decision data CSD is being received, the controller 110 may decompress the compressed soft decision data CSD to update the rough data CRS. In contrast, in Figure 10 the example shown, the controller 110 may receive the compressed soft decision data CSD from the memory device 120 while the initial soft decision decoding SD_DEC0 is being performed; after all of the compressed soft decision data CSD has been received, the controller 110 may decompress the compressed soft decision data CSD to replace the rough data CRS with the soft decision data SD.

[0130] Figure 11 is a diagram for describing operations of a flowchart according to Figure 10 . Referring to Figure 1 , Figure 10 and Figure 11 , the controller 110 may receive the hard decision data HD and the compressed soft decision data CSD from the memory device 120. The configuration for receiving the hard decision data HD and the compressed soft decision data CSD may be similar to the configuration described with reference to Figure 9B , and thus, additional description may be omitted to avoid redundancy.

[0131] As in the above description given with reference to Figure 9B , at the first decision time point t1d when the reception of the hard decision data HD is completed, the ECC engine 111 of the controller 110 may start the initial soft decision decoding SD_DEC0 using the hard decision data HD and the rough data CRS.

[0132] WithFigure 9B Compared with the illustrated example, in Figure 11 In the example illustrated in, after all the compressed soft decision data CSD is received, the controller 110 may decompress the compressed soft decision data CSD, and may replace the rough data CRS with the soft decision data SD. For example, the reception of the compressed soft decision data CSD may be completed at the 2d time point t2d. At the 2d time point t2d, the controller 110 may decompress the compressed soft decision data CSD, and may replace the rough data CRS with the soft decision data SD. In this case, in the time period from t1d to t2d, the ECC engine 111 performs the initial soft decision decoding SD_DEC0 using the hard decision data HD and the rough data CRS. After the 2d time point t2d, the ECC engine 111 of the controller 110 may continue to perform the remaining part of the initial soft decision decoding SD_DEC0 using the hard decision data HD and the soft decision data SD.

[0133] As described above, according to an embodiment of the present disclosure, before the soft decision data SD or the compressed soft decision data CSD is received from the memory device 120, the ECC engine 111 of the controller 110 may start the initial soft decision decoding SD_DEC0 (or the initial soft decision decoding) using the rough data CRS. Therefore, the time point at which the ECC engine 111 starts decoding may be advanced. This may mean that the time point at which all decoding operations are completed may be advanced. Therefore, the performance of the storage device 100 may be improved.

[0134] Figure 12 is a flowchart showing the operation of Figure 1 the controller. Referring to Figure 1 and Figure 12 , in operation S410, the controller 110 may monitor the state of the memory device 120. For example, the state of the memory device 120 may include information such as the degradation level, the lifespan, and the number of P / E cycles. The controller 110 may monitor or manage the degradation level of the memory device 120 based on the decoding result of the ECC engine 111. In some embodiments, the controller 110 may monitor or manage the degradation level of the memory device 120 based on the soft decision data SD received from the memory device 120. In some embodiments, the controller 110 may monitor or manage the information about the lifespan of the memory device 120 based on the number of P / E cycles of the memory device 120. The above configurations for monitoring the state of the memory device 120 are provided only as examples, and the embodiments are not limited thereto. For example, in an embodiment, the controller 110 may monitor or manage the state of the memory device 120 in units of memory cells, word lines, sub-blocks, memory blocks, super-blocks, or planes.

[0135] In operation S420, the controller 110 may determine the coarse data CRS based on the state of the memory device 120. For example, the soft decision data SD may have values corresponding to the error states of the memory cells. In this case, the state of the memory cells may be affected by factors such as the degradation level, lifespan, and number of P / E cycles. As described above, the coarse data CRS may refer to a data pattern or data set that can be used in the initial soft decision decoding SD_DEC0 (e.g., initial soft decision decoding) instead of the soft decision data SD. For example, the pattern of the coarse data CRS may change according to the state of the memory device 120. Therefore, the accuracy of the initial soft decision decoding SD_DEC0 may be improved. In one embodiment, multiple patterns associated with the coarse data CRS may be managed in the form of a lookup table, and the controller 110 may select the best pattern as the coarse data CRS based on the state of the memory device 120.

[0136] In operation S430, the controller 110 may perform the initial soft decision decoding SD_DEC0 based on the determined coarse data CRS.

[0137] Figure 13 is a diagram for describing the operations of a flowchart according to Figure 12 Referring to Figure 1 、 Figure 12 and Figure 13 , the memory device 120 may include first to third memory blocks BLK1 to BLK3.

[0138] When performing a read operation on the first memory block BLK1, the controller 110 may receive first hard decision data HD1 and first soft decision data SD1 from the first memory block BLK1 of the memory device 120. Before the first soft decision data SD1 is received, the ECC engine 111 of the controller 110 may perform the initial soft decision decoding SD_DEC0 using the first hard decision data HD1 and the first coarse data CRS1. After the first soft decision data SD1 is received, the controller 110 may replace the first coarse data CRS1 with the first soft decision data SD1 or may update the first coarse data CRS1 such that the first coarse data CRS1 is changed to the first soft decision data SD1, and the controller 110 may use the first hard decision data HD1 and the first soft decision data SD1 to perform subsequent soft decision decodings SD_DEC1 to SD_DECn.

[0139] The read operation on the second memory block BLK2 may be similar to the read operation on the first memory block BLK1, except that the controller 110 may receive second hard decision data HD2 and second soft decision data SD2 and may perform the initial soft decision decoding SD_DEC0 using the second coarse data CRS2. Therefore, additional descriptions may be omitted to avoid redundancy.

[0140] In addition to receiving the third hard decision data HD3 and the third soft decision data SD3 and performing an initial soft decision decoding SD_DEC0 using the third coarse data CRS3, the read operation of the third memory block BLK3 may be similar to the read operation of the first memory block BLK1, and thus, additional description may be omitted to avoid redundancy.

[0141] In one embodiment, examples of configurations for updating or replacing the coarse data CRS1, CRS2, and CRS3 with the soft decision data SD1, SD2, and SD3 have been described above, and thus, additional description may be omitted to avoid redundancy.

[0142] The controller 110 may use different coarse data associated with the first memory block BLK1 to the third memory block BLK3 of the memory device 120. For example, the states of the first memory block BLK1 to the third memory block BLK3 may be different from each other. As an example, the degradation level (e.g., the degree of error occurrence or the error occurrence ratio) of the first memory block BLK1 may be greater than that of the second memory block BLK2, and the degradation level of the second memory block BLK2 may be greater than that of the third memory block BLK3. In this case, compared with the second coarse data CRS2, the first coarse data CRS1 may include more values corresponding to zero ("0") (e.g., values corresponding to weak errors), and compared with the third coarse data CRS3, the second coarse data CRS2 may include more values corresponding to zero ("0") (e.g., values corresponding to weak errors).

[0143] For example, the ECC engine 111 of the controller 110 may perform the initial soft decision decoding SD_DEC0 using the coarse data set differently according to the state of the memory device 120 (or the state of the memory block). Accordingly, the time point at which the ECC engine 111 starts the soft decision decoding may be advanced, and the initial accuracy of the soft decision decoding may be improved.

[0144] Figure 14 is a flowchart for describing Figure 1 the operations of the controller. Figure 15 is a diagram for describing the operations of the flowchart according to Figure 14 Referring to Figure 1 and Figure 14 , at operation S510, the controller 110 may monitor the state of the memory device 120. Operation S510 may be similar to Figure 12 operation S410, and thus, additional description may be omitted to avoid redundancy.

[0145] At operation S520, the controller 110 may update the coarse data CRS based on the state of the memory device 120. For example, as the memory device 120 is used, the number of P / E cycles of the memory device 120 may increase, and the degradation level of the memory device 120 may increase. In this case, the controller 110 may update the coarse data CRS.

[0146] For example, as shown in Figure 15 , in an initial state (e.g., in a state where the memory device 120 is not degraded), the controller 110 may perform initial soft decision decoding using the initial coarse data CRS0. In an embodiment, the initial coarse data CRS0 may be referred to as, for example, the zero-th coarse data and the 0-th coarse data, but the embodiment is not limited thereto.

[0147] After that, as the memory device 120 operates, the degradation level of the memory device 120 may increase. In this case, the controller 110 may update the initial coarse data CRS0 based on the degradation level of the memory device 120 (e.g., may change the initial coarse data CRS0 to the first coarse data CRS1). Compared with the initial coarse data CRS0, the first coarse data CRS1 may include more values corresponding to zero ("0") (e.g., more values corresponding to weak errors). In an embodiment, the values corresponding to zero ("0") may be shown as shaded squares in Figure 15 .

[0148] After that, as the memory device 120 operates, the degradation level of the memory device 120 may further increase. In this case, the controller 110 may update the first coarse data CRS1 based on the degradation level of the memory device 120 (e.g., may change the first coarse data CRS1 to the second coarse data CRS2). Compared with the first coarse data CRS1, the second coarse data CRS2 may include more values corresponding to zero ("0") (e.g., more values corresponding to weak errors).

[0149] In one embodiment, the position of the bit of the coarse data that is changed to have the value zero ("0") may be determined based on the decoding result of the ECC engine 111 (or the physical location where errors may frequently occur) or the soft decision data SD.

[0150] As described above, the controller 110 may update the coarse data CRS based on the state of the memory device 120. Accordingly, the accuracy of the initial soft decision decoding SD_DEC0 performed using the coarse data CRS may be improved. In one embodiment, the controller 110 may perform the initial soft decision decoding based on the initial coarse data CRS0 and the hard decision data received from the first memory block of the memory device 120. In one embodiment, the controller 110 may perform the initial soft decision decoding based on the updated coarse data CRS (e.g., the first coarse data CRS1 or the second coarse data CRS2) and the hard decision data received from the first memory block of the memory device 120.

[0151] Figure 16 is a block diagram of a storage device according to an embodiment of the present disclosure. For ease of description, additional descriptions associated with the above components will be omitted to avoid redundancy. Referring to Figure 16 , the storage device 200 may include a controller 210 and a memory device 220. The controller 210 and the memory device 220 may operate as described with reference to Figures 1 to 15 description.

[0152] In one embodiment, the memory device 220 may include a variable compression engine 221 (shown as "vCOMP.Engine"). The variable compression engine 221 may be configured to compress the soft decision data SD based on a variable compression ratio. For example, as described above, the soft decision data SD may have a high ratio of specific bit values (e.g., the value one ("1") (e.g., a value corresponding to a strong error)). In this case, the soft decision data SD may be compressed at a relatively high compression ratio. In contrast, in the soft decision data SD, the ratio of the specific bit values (e.g., the value one ("1") (e.g., a value corresponding to a strong error)) may decrease according to the state of the memory cells. In this case, the soft decision data SD may be compressed at a relatively low compression ratio. The variable compression engine 221 may perform variable compression based on the state of the soft decision data SD or the bit value ratio of the soft decision data SD, and may generate the compressed soft decision data CSD. The size of the compressed soft decision data CSD may vary according to the compression ratio or the state of the memory cells.

[0153] The controller 210 may include an ECC engine 211 and a variable decompression engine 212 (shown as "vDECOMP.Engine"). The ECC engine 211 may operate based on the method described with reference to Figures 1 to 15 description. Accordingly, additional descriptions will be omitted to avoid redundancy.

[0154] The variable decompression engine 212 can decompress the compressed soft decision data CSD received from the memory device 220. For example, the compressed soft decision data CSD received from the memory device 220 can be in a state compressed based on a variable compression ratio. The variable decompression engine 212 can decompress the compressed soft decision data CSD based on the variable compression ratio and can generate soft decision data SD.

[0155] In one embodiment, the variable compression ratio can be managed by the controller 210 or the memory device 220. For example, the controller 210 can set the variable compression ratio based on the state of the memory device 220. In some embodiments, the memory device 220 can set the variable compression ratio based on the read soft decision data SD.

[0156] Figure 17 is a diagram for describing Figure 16 the variable compression engine. Figure 18 is a diagram for describing Figure 16 the variable decompression engine. Referring to Figures 16 to 18 , the variable compression engine 221 can compress the read soft decision data based on the variable compression ratio. For example, the variable compression engine 221 can generate the first compressed soft decision data CSD1 by compressing the first soft decision data SD1 based on the variable compression ratio. The variable compression engine 221 can generate the second compressed soft decision data CSD2 by compressing the second soft decision data SD2 based on the variable compression ratio. In one embodiment, even if the size of the first soft decision data SD1 can be similar to the size of the second soft decision data SD2, the size of the first compressed soft decision data CSD1 can be greater than the size of the second compressed soft decision data CSD2.

[0157] The variable decompression engine 212 can generate soft decision data SD by decompressing the compressed soft decision data CSD based on the variable compression ratio. For example, the variable decompression engine 212 can generate the first soft decision data SD1 by decompressing the first compressed soft decision data CSD1 based on the variable compression ratio. The variable decompression engine 212 can generate the second soft decision data SD2 by decompressing the second compressed soft decision data CSD2 based on the variable compression ratio.

[0158] In one embodiment, the variable compression ratio can be set by the controller 210, can be set by the memory device 220, or can be set based on the pattern of the soft decision data SD (e.g., the ratio of bit values).

[0159] Figure 19 is a flowchart showing Figure 16 the operation of the storage device. Referring to Figure 16 and Figure 19, in operation S610, the controller 210 may monitor the status of the memory device 220. In one embodiment, the configuration for monitoring the status of the memory device 220 may be similar to the configuration described in Figure 12 operation S410, and thus, additional description may be omitted to avoid redundancy.

[0160] In operation S620, the controller 210 may determine a compression ratio based on the status of the memory device 220. For example, when the degradation level of the memory device 220 is relatively low, a first compression ratio may be selected; when the degradation level of the memory device 220 is relatively high, a second compression ratio may be selected. In this case, the first compression ratio may be higher than the second compression ratio. For example, when the degradation level of the memory device 220 is relatively low, the ratio of a specific value (e.g., value one ("1") (e.g., the value corresponding to a strong error)) in the soft decision data read from the memory device 220 may be high. In this case, the soft decision data may be compressed at a relatively high compression ratio. In contrast, when the degradation level of the memory device 220 is relatively high, the ratio of a specific value (e.g., value one ("1") (e.g., the value corresponding to a strong error)) in the soft decision data read from the memory device 220 may be relatively low. In this case, the soft decision data may be compressed at a relatively low compression ratio.

[0161] In operation S630, the controller 210 may set the determined compression ratio to the memory device 220. In one embodiment, operation S630 may be performed by a "SET FEATURE" command, a reserved command, or a vendor command, or a combination thereof.

[0162] In operation S640, the controller 210 may send a read command to the memory device 220. In operation S650, the memory device 220 may perform a read operation to generate hard decision data HD and soft decision data SD. In operation S660, the memory device 220 may compress the soft decision data SD to generate compressed soft decision data CSD.

[0163] In operation S670, the memory device 220 may sequentially send the hard decision data HD and the compressed soft decision data CSD to the controller 210. In operation S680, the controller 210 may decompress the compressed soft decision data CSD based on the determined compression ratio and may perform soft decision decoding. In one embodiment, except that a variable compression ratio may be used, operations S670 and S680 may correspond to Figure 8 operations S240 to S280 of Figure 10 or operations S340 to S380 ofFigure 8 Operations S240 to S280 or Figure 10 Operations S340 to S380 to perform soft decision decoding.

[0164] Figure 20 is a flowchart showing Figure 16 the operations of the storage device. Referring to Figure 16 and Figure 20 , at operation S710, the memory device 220 may monitor the state of the memory device 220. At operation S720, the memory device 220 may determine a compression ratio based on the state of the memory device 220. Subsequently, the controller 210 and the memory device 220 may perform operations S730 to S770. Operations S730 to S770 may be similar to Figure 19 operations S640 to S680, and thus, additional description may be omitted to avoid redundancy.

[0165] In one embodiment, when the variable compression ratio is set by the memory device 220 or set based on the pattern of the soft decision data SD (e.g., the ratio of bit values), the controller 210 may not know the exact variable compression ratio. In this case, the variable decompression engine 212 of the controller 210 may decompress the compressed soft decision data CSD at a predetermined compression ratio. Thereafter, the ECC engine 211 of the controller 210 may perform soft decision decoding based on the decompressed data. The variable decompression engine 212 may adjust the compression ratio based on the result of the soft decision decoding, and may decompress the compressed soft decision data CSD again based on the adjusted compression ratio. As an example, when the soft decision decoding result indicates the presence of a relatively large number of weak errors, the compression ratio may be decreased; when the soft decision decoding result indicates the presence of a relatively large number of strong errors, the compression ratio may be increased. The variable decompression engine 212 may decompress the compressed soft decision data CSD again based on the adjusted compression ratio. The soft decision data SD after decompression again may be used in subsequent soft decision decoding.

[0166] Figure 21 is a block diagram showing a storage device according to an embodiment of the present disclosure. Referring to Figure 21 , the storage device 300 may include a controller 310 and a memory device 320. The controller 310 and the memory device 320 may operate as described above with reference to Figures 1 to 20 .

[0167] In one embodiment, the memory device 320 may include an ECC engine 321. The ECC engine 321 may be as described above with reference to Figures 1 to 20Perform iterative soft decision decoding as described. For example, the ECC engine 321 may perform iterative soft decision decoding based on the hard decision data HD and the soft decision data SD read from the memory device 320. In this case, before all the soft decision data SD is read, the ECC engine 321 may start the initial soft decision decoding SD_DEC0 (e.g., the initial soft decision decoding) using the rough data CRS and the hard decision data HD. When the soft decision data SD is read, the rough data CRS may be updated or replaced with the soft decision data SD; thereafter, the ECC engine 321 may perform subsequent soft decision decoding based on the hard decision data HD and the soft decision data SD.

[0168] Figure 22 is a block diagram of a host storage system according to an example embodiment.

[0169] The host storage system 1000 may include a host 1100 and a storage device 1200. In addition, the storage device 1200 may include a storage controller 1210 and a non-volatile memory (NVM) 1220. According to an example embodiment, the host 1100 may include a host controller 1110 and a host memory 1120. The host memory 1120 may be used as a buffer memory configured to temporarily store data to be sent to the storage device 1200 or data received from the storage device 1200.

[0170] The storage device 1200 may include a storage medium configured to store data in response to a request from the host 1100. As an example, the storage device 1200 may include at least one of an SSD, an embedded memory, and a removable external memory. When the storage device 1200 is an SSD, the storage device 1200 may be a device compliant with the NVMe standard. When the storage device 1200 is an embedded memory or an external memory, the storage device 1200 may be a device compliant with the UFS standard or the eMMC standard. Each of the host 1100 and the storage device 1200 may generate a packet according to an adopted standard protocol and send the packet.

[0171] When the NVM 1220 of the storage device 1200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 1200 may include various other types of NVM. For example, the storage device 1200 may include a magnetic RAM (MRAM), a spin transfer torque STT RAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FRAM), a PRAM, an RRAM, and various other types of memories.

[0172] According to an embodiment, the host controller 1110 and the host memory 1120 may be implemented as separate semiconductor chips. In some embodiments, the host controller 1110 and the host memory 1120 may be integrated in the same semiconductor chip. As an example, the host controller 1110 may be any one of a plurality of modules included in an application processor (AP). The AP may be implemented as a system on a chip (SoC). In addition, the host memory 1120 may be an embedded memory included in the AP or a non-volatile memory (NVM) or a memory module located outside the AP.

[0173] The host controller 1110 may manage an operation of storing data (e.g., write data) in a buffer area of the host memory 1120 in the NVM 1220 or an operation of storing data (e.g., read data) in the NVM 1220 in the buffer area.

[0174] The storage controller 1210 may include a host interface (e.g., a host interface circuit) 1211, a memory interface (e.g., a memory interface circuit) 1212, and a CPU 1213. In addition, the storage controller 1210 may further include a flash translation layer (FTL) 1214, a packet manager 1215, a buffer memory 1216, an error correction code (ECC) engine 1217, and an advanced encryption standard (AES) engine 1218. The storage controller 1210 may further include a working memory (not shown) in which the FTL 1214 is loaded. The CPU 1213 may run the FTL 1214 to control data write and read operations on the NVM 1220.

[0175] The host interface 1211 may send packets to the host 1100 and receive packets from the host 1100. Packets sent from the host 1100 to the host interface 1211 may include commands or data to be written to the NVM 1220. Packets sent from the host interface 1211 to the host 1100 may include responses to commands or data read from the NVM 1220. The memory interface 1212 may send data to be written to the NVM 1220 to the NVM 1220 or receive data read from the NVM 1220. The memory interface 1212 may be configured to comply with a standard protocol such as Toggle or Open NAND Flash Interface (ONFI).

[0176] The FTL 1214 can perform various functions (such as address mapping operations, wear leveling operations, and garbage collection operations). The address mapping operation can be an operation of converting a logical address received from the host 1100 into a physical address for actually storing data in the NVM 1220. The wear leveling operation can be a technique for preventing excessive degradation of a specific block by uniformly using the blocks of the NVM 1220. As an example, a firmware technique for balancing the erase counts of physical blocks can be used to implement the wear leveling operation. The garbage collection operation can be a technique for ensuring the available capacity in the NVM 1220 by erasing an existing block after copying the valid data of the existing block to a new block.

[0177] The packet manager 1215 can generate a packet according to the protocol of an interface permitted by the host 1100, or parse various types of information from a packet received from the host 1100. In addition, the buffer memory 1216 can temporarily store data to be written to the NVM 1220 or data to be read from the NVM 1220. Although the buffer memory 1216 can be a component included in the storage controller 1210, the buffer memory 1216 can be external to the storage controller 1210.

[0178] The ECC engine 1217 can perform error detection and correction operations on the read data read from the NVM 1220. More specifically, the ECC engine 1217 can generate parity bits for the write data to be written to the NVM 1220, and the generated parity bits can be stored in the NVM 1220 together with the write data. During the reading of data from the NVM 1220, the ECC engine 1217 can use the parity bits read from the NVM 1220 together with the read data to correct the errors in the read data, and output the error-corrected read data.

[0179] The AES engine 1218 can perform at least one of an encryption operation and a decryption operation on the data input to the storage controller 1210 using a symmetric key algorithm.

[0180] In one embodiment, the ECC engine 1217 can perform soft decision decoding as described above with reference to Figures 1 to 21 the description.

[0181] According to the present disclosure, a controller configured to control a memory device may sequentially receive hard decision data and soft decision data from the memory device. In this case, before the time point when the reception of the soft decision data is completed (or before the soft decision data is received), the controller may start initial soft decision decoding based on the hard decision data and rough data. For example, since the time point at which the controller starts decoding is advanced, the time point at which the decoding is completed may also be advanced. Accordingly, provided are a controller configured to control a memory with improved performance, an operation method of the controller, and an operation method of a storage device including the memory device and the controller.

[0182] Although some embodiments of the present disclosure have been described above, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made without departing from the spirit and scope of the present disclosure as set forth in the appended claims.

Claims

1. A method for operating a controller for controlling a memory device, the operating method comprising: Sequentially receiving first hard decision data and first data from a first memory block of the memory device; Based on completion of receiving the first hard decision data, starting initial soft decision decoding based on the first hard decision data and first rough data; While the initial soft decision decoding is being performed, replacing the first rough data with first soft decision data based on the first data received from the memory device; And After completion of the initial soft decision decoding, performing first soft decision decoding based on the first hard decision data and the first soft decision data.

2. The operating method according to claim 1, wherein, The first rough data includes a predetermined data pattern corresponding to the state of the memory device.

3. The operating method according to claim 1, further comprising: Iteratively performing soft decision decoding a predetermined number of times based on the first hard decision data and the first soft decision data.

4. The operating method according to claim 1, wherein, The first data includes the first soft decision data, and Wherein, the first soft decision data is read from a memory cell corresponding to the first hard decision data.

5. The operating method according to claim 1, wherein, The first data is obtained by compressing the first soft decision data, and Wherein, the first soft decision data is read from a memory cell corresponding to the first hard decision data.

6. The operating method according to claim 5, wherein, The replacing step includes: Decompressing the first data to generate the first soft decision data; and Updating the first rough data based on the first soft decision data.

7. The operating method according to claim 1, wherein, The first hard decision data and the first data are received from the memory device based on a first read command sent to the memory device.

8. The operating method according to any one of claims 1 to 7, further comprising: Sequentially receiving second hard decision data and second data from a second memory block of the memory device; Based on completion of receiving the second hard decision data, starting second soft decision decoding based on the second hard decision data and second rough data; While the second soft decision decoding is being performed, replacing the second rough data with second soft decision data based on the second data received from the memory device; And After completion of the second soft decision decoding, performing third soft decision decoding based on the second hard decision data and the second soft decision data.

9. The operating method according to claim 8, wherein The first rough data is different from the second rough data.

10. The operating method according to any one of claims 1 to 7, further comprising: Monitoring the state of the memory device; And Updating the first rough data with third rough data based on the state of the memory device.

11. The operating method according to claim 10, further comprising: Sequentially receiving third hard decision data and third data from the first memory block of the memory device; And Based on completion of receiving the third hard decision data, starting fourth soft decision decoding based on the third hard decision data and the third rough data.

12. A controller for controlling a memory device, the controller comprising: A NAND interface circuit configured to receive first hard decision data and first compressed soft decision data from the memory device; A decompression engine configured to decompress the first compressed soft decision data to generate the first soft decision data; A random access memory configured to store the first hard decision data and the first soft decision data; And An error correction code engine configured to: After the first hard decision data is stored in the random access memory, initial soft decision decoding is started based on the first hard decision data and the first rough data, and after the first soft decision data is stored in the random access memory, first soft decision decoding is performed based on the first hard decision data and the first soft decision data.

13. The controller according to claim 12, wherein, The error correction code engine is further configured to start initial soft decision decoding before all of the first compressed soft decision data is received through the NAND interface circuit.

14. The controller according to claim 12 or 13, wherein, The decompression engine is further configured to: decompress the first compressed soft decision data based on the first compression ratio; and generate the first soft decision data.

15. The controller according to claim 14, wherein, The decompression engine is further configured to: adjust the first compression ratio to a second compression ratio based on the result of the first soft decision decoding; and decompress the first compressed soft decision data using the second compression ratio to generate second soft decision data.

16. An operation method of a storage device including a memory device and a controller, the operation method comprising: sending, by the controller, a read command to the memory device; generating, by the memory device, first hard decision data and first soft decision data by performing a read operation on a selected word line based on the read command; generating, by the memory device, first compressed soft decision data by compressing the first soft decision data; sending, by the memory device, the first hard decision data and the first compressed soft decision data to the controller; starting, by the controller, initial soft decision decoding based on the first hard decision data and the first rough data upon completion of the reception of the first hard decision data by the controller; generating, by the controller, first decompressed soft decision data by decompressing the first compressed soft decision data; and performing, by the controller, first soft decision decoding based on the first hard decision data and the first decompressed soft decision data.

17. The operating method according to claim 16, wherein, The first hard decision data and the first compressed soft decision data are sequentially sent to the controller.

18. The operating method according to claim 16, wherein, The controller is further configured to: receive the first compressed soft decision data from the memory device while the initial soft decision decoding is being performed; and decompress the first compressed soft decision data to generate the first soft decision data.

19. The operating method according to claim 16, wherein, The memory device is further configured to generate first compressed soft decision data by compressing the first soft decision data based on a variable compression ratio.

20. The operating method according to claim 19, wherein The controller is further configured to: decompress the first compressed soft decision data based on the first compression ratio to generate first decompressed soft decision data; adjust the first compression ratio to a second compression ratio based on the result of the first soft decision decoding; and decompress the first compressed soft decision data based on the second compression ratio to generate second decompressed soft decision data.

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