Nitride semiconductor light-emitting element

Abstract

The present invention improves damage resistance of a nitride semiconductor light-emitting element during external connection. A nitride semiconductor light-emitting element is provided with: a nitride semiconductor laminated part having a light-emitting mesa structure part disposed on a first conductive semiconductor layer formed on a substrate, and a non-light-emitting protective mesa structure part disposed on a second conductive semiconductor layer formed on the substrate; a non-light-emitting protective mesa structure portion disposed on the first conductive semiconductor layer, spatially separated from the light-emitting mesa structure portion, and surrounding the light-emitting mesa structure portion; a first electrode disposed on the other portion of the first conductivity type semiconductor layer and having at least two or more electrode regions including a first electrode region disposed at a first interval from the protective mesa structure portion and a second electrode region disposed at a second interval from the first electrode region; a passivation layer directly covering an edge portion of the protective mesa structure portion, an outer edge portion of each of the plurality of electrode regions, and a surface of the first conductivity type semiconductor layer; and a first pad electrode disposed so as to cover a part of the surface of the passivation layer and at least a part of the surface of each of the plurality of electrode regions that is not covered by the passivation layer.

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor light-emitting element. Background Art

[0002] Conventionally, in a nitride semiconductor element, for example, an n-type nitride semiconductor layer, a nitride semiconductor light-emitting layer, and a p-type nitride semiconductor light-emitting layer are stacked on a substrate, and the nitride semiconductor element includes an n-type electrode disposed on the n-type nitride semiconductor layer, a p-type electrode disposed on the p-type nitride semiconductor layer, and external connection pad electrodes electrically connected to the n-type electrode and the p-type electrode, respectively (for example, Patent Documents 1 and 2).

[0003] Prior Art Documents

[0004] Patent Documents

[0005] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2016-096193

[0006] Patent Document 2: International Publication No. 2016 / 163083 Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] In such a nitride semiconductor element, when the nitride semiconductor element is externally connected to a package substrate, a wiring substrate, etc., a physical load is applied to the element, and sometimes the nitride semiconductor element is damaged. In the above-described conventional nitride semiconductor elements, for example, external connection electrodes, contact electrodes, and lead wirings that electrically connect the external connection electrodes and the contact electrodes are also formed separately, so that the overall thickness of the electrodes in the external connection portion becomes thick (Citation Document 1), or the n-type electrode immediately below the external connection electrode is spatially separated so that the corrosion of the n-type electrode does not spread (Citation Document 2), thereby suppressing damage to the nitride semiconductor element. However, from the viewpoint of damage resistance, it is necessary to further improve the suppression of damage to the nitride semiconductor element.

[0009] An object of the present disclosure is to provide a nitride semiconductor element with improved damage resistance during external connection.

[0010] Means for Solving the Problems

[0011] In order to solve the above problems, a nitride semiconductor light-emitting element according to one aspect of the present disclosure includes: a substrate; a nitride semiconductor stack portion having: a first conductivity type semiconductor layer disposed on the substrate, a light-emitting mesa structure portion disposed on a part of the first conductivity type semiconductor layer, and a non-light-emitting protective mesa structure portion disposed on the first conductivity type semiconductor layer and spatially separated from the light-emitting mesa structure portion and configured to surround the light-emitting mesa structure portion; a first electrode disposed on another part of the first conductivity type semiconductor layer and having at least two electrode regions including a first electrode region disposed with a first interval from the protective mesa structure portion in a plan view and a second electrode region disposed with a second interval from the first electrode region; a passivation layer directly covering an edge portion of the protective mesa structure portion, an outer edge portion of each of the plurality of electrode regions, and a surface of the first conductivity type semiconductor layer; and a first pad electrode disposed so as to cover a part of the surface of the passivation layer and at least a part of the surface of the region of each of the plurality of electrode regions not covered by the passivation layer, and electrically connecting the plurality of electrode regions to each other.

[0012] It should be noted that the above-described summary of the invention does not enumerate all the features of the invention related to the present disclosure.

[0013] Advantages of the Invention

[0014] According to the present disclosure, a nitride semiconductor element with improved damage resistance during external connection can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. is a plan view schematically showing a structural example of a nitride semiconductor light-emitting element according to a first embodiment of the present disclosure.

[0016] Figure 2A FIG. is a cross-sectional view schematically showing a structural example of a nitride semiconductor light-emitting element according to a first embodiment of the present disclosure.

[0017] Figure 2B FIG. is a cross-sectional view schematically showing a structural example of a nitride semiconductor light-emitting element according to a first embodiment of the present disclosure.

[0018] Figure 3 FIG. is a plan view schematically showing a structural example of a nitride semiconductor light-emitting element according to a first embodiment of the present disclosure.

[0019] Figure 4 FIG. is an enlarged view magnifying a part of a structural example of a nitride semiconductor light-emitting element according to a first embodiment of the present disclosure.

[0020] Figure 5It is a top view schematic diagram showing a structural example of a nitride semiconductor light-emitting element of a comparative example of the present disclosure.

[0021] Figure 6 It is a cross-sectional schematic diagram showing a structural example of a nitride semiconductor light-emitting element of a comparative example of the present disclosure.

[0022] Figure 7 It is a top view schematic diagram showing a structural example of a nitride semiconductor light-emitting element of a comparative example of the present disclosure.

[0023] Figure 8 It is a cross-sectional schematic diagram showing a structural example of a nitride semiconductor light-emitting element of a comparative example of the present disclosure. Detailed Description of the Invention

[0024] Hereinafter, the nitride semiconductor light-emitting element of the present disclosure will be described by way of embodiments. However, the following embodiments do not limit the invention of the claims. In addition, the combinations of the features described in the embodiments are not necessarily all essential for the solution means of the invention.

[0025] In addition, the drawings described below are schematic drawings, and the ratios of the size and thickness do not necessarily reflect the actual size ratios. In addition, "up" and "down" in the following description do not necessarily indicate the vertical direction with respect to the ground. That is, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for determining the relative positional relationship of surfaces, layers, substrates, etc., and do not limit the technical concept of the present disclosure. For example, if the paper surface is rotated 180 degrees, "up" becomes "down" and "down" becomes "up", which goes without saying.

[0026] The nitride semiconductor light-emitting element according to an embodiment of the present disclosure will be described.

[0027] [Structure of Nitride Semiconductor Light-Emitting Element]

[0028] Hereinafter, with reference to Figures 1 to 4 A specific structural example of the nitride semiconductor light-emitting element 1 will be described. Figures 1 to 4 It is a schematic diagram for explaining the nitride semiconductor light-emitting element 1 of the present embodiment. Figure 1 It is a top view schematic diagram showing the planar structure of the nitride semiconductor light-emitting element 1. Figure 2A It shows Figure 1 A cross-sectional schematic diagram of the cross-sectional structure at the A-A section of the nitride semiconductor light-emitting element 1 shown, Figure 2B It shows Figure 1 A cross-sectional schematic diagram of the cross-sectional structure at the B-B section of the nitride semiconductor light-emitting element 1 shown.

[0029] As shown in Figure 1 AndFigures 2A to 2B As shown, a nitride semiconductor light-emitting element 1 according to an embodiment of the present disclosure (hereinafter referred to as the present embodiment) includes a substrate 10, a nitride semiconductor laminate 20 disposed on the substrate 10, a first electrode 30 and a second electrode 40, and a passivation layer 50 and a pad electrode 70. Here, in Figure 1 , an opening provided in the passivation layer 50 is indicated by a dotted line, and a formation region of the pad electrode 70 is indicated by a dashed line. In addition, in Figure 2B , an example of a position where a conductive bump is provided when the nitride semiconductor light-emitting element 1 is externally connected is indicated by a dashed line.

[0030] As Figure 1 and Figure 2A shown, the nitride semiconductor laminate 20 has: a first n-type semiconductor layer (an example of a first conductivity type semiconductor layer) 21, a light-emitting mesa structure portion 22 disposed on a part of the first n-type semiconductor layer 21, and a protective mesa structure portion 23 disposed on the first n-type semiconductor layer 21 and spatially separated from the light-emitting mesa structure portion 22. The light-emitting mesa structure portion 22 includes a light-emitting layer. In addition, the protective mesa structure portion 23 has a function of protecting a region inside the protective mesa structure portion 23 that includes the light-emitting mesa structure portion 22. The protective mesa structure portion 23 is preferably disposed at an outer edge portion of the substrate.

[0031] The first electrode 30 is disposed on another part of the first n-type semiconductor layer 21 (a region where the light-emitting mesa structure portion 22 is not provided). As Figure 2A and Figure 2B shown, the first electrode 30 has a first electrode region 31 serving as a base of an external connection portion and a second electrode region 32 disposed spatially separated from the first electrode region 31. The first electrode region 31 is disposed with a first narrow space portion 61 therebetween and the protective mesa structure portion 23. In addition, the second electrode region 32 is disposed with a second narrow space portion 62 therebetween and the first electrode region 31. That is, the first narrow space portion 61 is formed by the spatial arrangement of the protective mesa structure portion 23 and the first electrode region 31, and the second narrow space portion 62 is formed by the spatial arrangement of the first electrode region 31 and the second electrode region 32. Hereinafter, without distinguishing between the first narrow space portion 61 and the second narrow space portion 62, it is sometimes referred to as the narrow space portion 60.

[0032] In addition, the first electrode 30 has a third electrode region 33 disposed between the light-emitting mesa structure portions 22. A part of the third electrode region 33 is disposed at a position facing the second electrode region 32 with the light-emitting mesa structure portion 22 therebetween.

[0033] The second electrode 40 is disposed on the light-emitting mesa structure portion 22.

[0034] The pad electrode 70 has a first pad electrode portion 71 and a second pad electrode portion 72.

[0035] The first pad electrode portion 71 is arranged so as to cover a part of the surface of the passivation layer 50 and the surfaces of the first electrodes 30 (the first electrode region 31, the second electrode region 32, and the third electrode region 33) not covered by the passivation layer 50. Specifically, the first pad electrode portion 71 is arranged so as to cover a part of the second passivation covering region 52 and the third passivation covering region 53 (details will be described later). In addition, the first pad electrode portion 71 electrically connects the first electrode region 31, the second electrode region 32, and the third electrode region 33.

[0036] The second pad electrode portion 72 is arranged on a part of the passivation layer 50 and the second electrode 40 not covered by the passivation layer 50.

[0037] More preferably, the pad electrode 70 includes a third pad electrode portion 73, and the third pad electrode portion 73 covers a part of the surface of the passivation layer 50 and a part of the protection mesa structure portion 23 not covered by the passivation layer 50. Specifically, the third pad electrode portion 73 is arranged so as to cover at least a part of the first passivation covering region 51.

[0038] The narrow space portion 60 has a first narrow space portion 61 formed by the spatial arrangement of the protection mesa structure portion 23 and the first electrode region 31, and a second narrow space portion 62 formed by the spatial arrangement of the first electrode region 31 and the second electrode region 32.

[0039] The passivation layer 50 is arranged on the entire surface except for the outer peripheral portion of the protection mesa structure portion 23 (the outer peripheral portion of the nitride semiconductor light-emitting element 1), and the central portions of the first electrode 30 (the first electrode region 31, the second electrode region 32, and the third electrode region 33) and the second electrode 40, and is formed across the first narrow space portion 61 and the second narrow space portion 62. The passivation layer 50 has a first passivation covering region 51 covering the outer edge portion on the first electrode region 31 side of the protection mesa structure portion 23, a second passivation covering region 52 covering the outer edge portion of the first electrode region 31, and a third passivation covering region 53 covering the outer edge portion of the second electrode region 32. That is, the first passivation covering region 51 covers the end portion and the side surface of the upper surface of the protection mesa structure portion 23, the second passivation covering region 52 covers the end portion and the side surface of the upper surface of the first electrode region 31, and the third passivation covering region 53 covers the end portion and the side surface of the upper surface of the second electrode region 32.

[0040] The nitride semiconductor light-emitting element 1 of the present embodiment has the above-mentioned structure, thereby achieving improved damage resistance during external connection. Damage during external connection refers to, for example, peeling or cracking of the pad electrode 70 or the first electrode 30 in the area where the conductive bump is provided from the underlying layer, peeling or cracking (including microcracks) of the passivation layer 50. When the nitride semiconductor light-emitting element 1 is damaged, degradation of the nitride semiconductor light-emitting element 1 occurs, especially during power-on in a high-humidity environment. The degradation of the nitride semiconductor light-emitting element 1 during power-on mainly refers to corrosion of the electrode or an increase in the driving voltage or disconnection caused by corrosion of the semiconductor layer. In the case of an AlGaN-based nitride semiconductor light-emitting element, the higher the Al composition ratio, the more likely the semiconductor layer is to be corroded. In addition, when peeling of the pad electrode 70 or the first electrode 30 occurs, the risk of the nitride semiconductor light-emitting element 1 detaching from the externally connected packaging substrate, wiring substrate, etc. (not shown) increases.

[0041] In nitride semiconductor light-emitting element 1, the passivation layer 50 formed across narrow space 60 improves the adhesion of passivation layer 50 due to the anchoring effect, thereby enhancing the effect of suppressing first electrode region 31 and improving adhesion to the underlying layer (first n-type semiconductor layer 21) of first electrode region 31. Therefore, nitride semiconductor light-emitting element 1 having a passivation covering region and narrow space 60 does not experience peeling of pad electrode 70 or first electrode 30 during external connection, and exhibits particularly excellent damage resistance.

[0042] Furthermore, the first pad electrode portion 71 of this embodiment also functions as an extraction electrode that electrically connects the first electrode region 31 and the second electrode region 32. Furthermore, the first pad electrode portion 71 also functions as an extraction electrode that electrically connects the first electrode region 31 and the second electrode region 32 to the third electrode region 33. Therefore, there is no need to separately form the external connection portion and the extraction electrode, which is also preferable from the perspective of simplifying the manufacturing process.

[0043] Furthermore, the narrow space 60 can be formed by protecting the spatial arrangement of the mesa structure 23 and the first electrode region 31, and the spatial arrangement of the first electrode region 31 and the second electrode region 32. Therefore, it is preferable from the viewpoint of being able to obtain a nitride semiconductor light-emitting element 1 with high damage resistance without changing the manufacturing process.

[0044] Furthermore, in this embodiment, since damage resistance can be improved, it is no longer necessary to design the nitride semiconductor light-emitting element 1 with a large margin for deviations in the size and position of the external connection portion. Consequently, the area within the nitride semiconductor light-emitting element 1 that does not contribute to light emission can be reduced, which is also advantageous from the perspective of increasing the light emission output per unit area of the chip.

[0045] In addition, the second narrow space portion 62 has an effect of preventing corrosion from spreading to the second electrode region 32 even if the first electrode region 31 is corroded during energization in a high-humidity environment. In this case, the corrosion does not spread to the second electrode region 32, and the carrier supply to the light-emitting mesa structure portion 22 is not hindered. Therefore, a decrease in device performance such as an increase in the driving voltage during energization, disconnection, and deterioration of the light-emitting performance does not occur. Therefore, from the viewpoint of further suppressing a decrease in device performance during energization in a high-humidity environment, the nitride semiconductor light-emitting device 1 having the second narrow space portion 62 is sometimes preferable.

[0046] Next, each component of the nitride semiconductor light-emitting device 1 of the present embodiment will be described in detail.

[0047] <Substrate>

[0048] The substrate 10 is not particularly limited as long as the first n-type semiconductor layer 21 can be formed on the substrate 10. Specifically, examples of the substrate 10 include sapphire, Si, SiC, MgO, Ga2O3, ZnO, GaN, InN, AlN, or a mixed crystal substrate thereof.

[0049] From the viewpoints of a small lattice constant difference from the first n-type semiconductor layer 21 formed on the substrate 10, reduction of threading dislocations by growth in a lattice-matching system, and an increase in lattice distortion for generating a hole gas, the substrate 10 is preferably a single crystal substrate mainly composed of a nitride semiconductor such as GaN, AlN, or AlGaN, or a nitride semiconductor layer (also referred to as a template) such as GaN, AlN, or AlGaN grown on a certain material. In addition, impurities may be mixed in the substrate 10.

[0050] In addition, from the viewpoint of improving light extraction, the surface of the substrate 10 opposite to the surface on which the first n-type semiconductor layer 21 is formed may be processed.

[0051] <Nitride Semiconductor Stack>

[0052] The nitride semiconductor stack 20 includes a first n-type semiconductor layer 21, a light-emitting mesa structure portion 22 disposed on the first n-type semiconductor layer 21, and a protective mesa structure portion 23.

[0053] The light-emitting mesa structure portion 22 and the protective mesa structure portion 23 have a mesa structure protruding from a part of the first n-type semiconductor layer 21. The method for forming the mesa structure is not particularly limited and can be formed by the following method: Stacking each layer on the substrate 10 using a known film-forming apparatus using methods such as molecular beam epitaxy (MBE: Molecular Beam Epitaxy), metal organic chemical vapor deposition (MOCVD: Metal Organic Chemical Vapor Deposition), forming a mask pattern using photolithography, and etching a desired region by dry etching or wet etching.

[0054] The light-emitting mesa structure portion 22 and the protective mesa structure portion 23 are spatially separated. Here, "spatially separated" means that there are sides of the light-emitting mesa structure portion 22 and sides of the protective mesa structure portion 23 and they do not contact each other.

[0055] In order to realize the nitride semiconductor light-emitting element 1 with a longer lifespan, in a plan view, the protective mesa structure portion 23 is preferably arranged so as to surround the light-emitting mesa structure portion 22. Here, "arranged so as to surround" means that in a plan view, more than 50% of the sides of the smallest convex polygon surrounding the entire light-emitting mesa structure portion 22 face the sides of the protective mesa structure portion 23.

[0056] The light-emitting mesa structure portion 22 has a second n-type semiconductor layer (an example of a first conductive type semiconductor layer) 221, a first quantum well layer 222 disposed on the second n-type semiconductor layer, and a first p-type semiconductor layer 223 disposed on the first quantum well layer 222.

[0057] The protective mesa structure portion 23 has a third n-type semiconductor layer 231, a second quantum well layer 232 disposed on the third n-type semiconductor layer, and a second p-type semiconductor layer 233 disposed on the second quantum well layer 232.

[0058] Preferably, the end portion of a part of the protective mesa structure portion 23 overlaps with the end portion of a part of the substrate 10 when viewed from above, that is, the side surface of the protective mesa structure portion 23 is disposed substantially in the same plane as the side surface of the substrate 10. Thus, for example, the protective mesa structure portion 23 can cover the first n-type semiconductor layer 21 up to the outer peripheral portion of the chip, and can protect a wide area on the first n-type semiconductor layer 21. For example, when the Al composition ratio of the first n-type semiconductor layer 21 is high, the first n-type semiconductor layer 21 has a tendency to deteriorate easily. However, by providing the protective mesa structure portion 23 on the first n-type semiconductor layer 21, the exposed area of the first n-type semiconductor layer 21 can be reduced. Thus, deterioration of the first n-type semiconductor layer 21 can be suppressed, and a nitride semiconductor light-emitting element 1 with a longer lifespan can be realized. Note that "overlap" means that the deviation between a part of the end portion of the protective mesa structure portion 23 and the end portion of the substrate 10 is 2 μm or less when viewed from above.

[0059] <n-type semiconductor layer>

[0060] The n-type semiconductor layer (an example of the first conductive type semiconductor layer) includes a first n-type semiconductor layer 21, a second n-type semiconductor layer 221 that is a part of the light-emitting mesa structure portion 22, and a third n-type semiconductor layer 231 that is a part of the protective mesa structure portion 23.

[0061] As Figure 2A etc. show, the first n-type semiconductor layer 21 is directly formed on the substrate 10. Alternatively, a layer other than the first n-type semiconductor layer 21 may be provided on the substrate 10, and the first n-type semiconductor layer 21 may be provided on the layer other than the first n-type semiconductor layer 21. Specifically, for example, a buffer layer (not shown) may be provided on the substrate 10, and the first n-type semiconductor layer 21 may be provided on the buffer layer.

[0062] The first n-type semiconductor layer 21, the second n-type semiconductor layer 221, and the third n-type semiconductor layer 231 are preferably formed of Al x Ga 1- x N (x > 0.3), and more preferably formed of n-type Al x Ga 1-x N (x > 0.3). Thereby, the luminous efficiency of the nitride semiconductor light-emitting element 1 is improved.

[0063] In the first n-type semiconductor layer 21, the second n-type semiconductor layer 221, and the third n-type semiconductor layer 231, in addition to being doped with an n-type dopant, other group V elements such as P, As, and Sb; impurities such as C, H, F, O, Mg, and Si may also be mixed in.

[0064] <Quantum well layer>

[0065] The quantum well layer includes a first quantum well layer 222 that is part of the light-emitting mesa structure portion 22 and a second quantum well layer 232 that is part of the protective mesa structure portion 23.

[0066] As Figure 2A shown, the first quantum well layer 222 is directly disposed on the second n-type semiconductor layer 221, and the second quantum well layer 232 is directly disposed on the third n-type semiconductor layer 231. Additionally, the first quantum well layer 222 may also be disposed on a layer other than the quantum well layer disposed on the second n-type semiconductor layer 221. Specifically, an undoped AlGaN layer (not shown) may be disposed on the second n-type semiconductor layer 221, and the first quantum well layer 222 may be disposed on the AlGaN layer. Similarly, the second quantum well layer 232 may also be disposed on an undoped AlGaN layer or the like formed on the third n-type semiconductor layer 231.

[0067] There are no particular limitations on the first quantum well layer 222 and the second quantum well layer 232 as long as they are nitride semiconductor layers, but from the perspective of achieving high luminous efficiency, a mixed crystal of AlN, GaN, and InN is preferred. In the first quantum well layer 222 and the second quantum well layer 232, in addition to N being incorporated, other Group V elements such as P, As, and Sb; impurities such as C, H, F, O, Mg, and Si may also be incorporated. Additionally, the first quantum well layer 222 and the second quantum well layer 232 may be a multi-quantum well structure or a single-layer quantum well structure, but from the perspective of achieving high luminous efficiency, a well structure having at least two or more is preferred.

[0068] <p-type semiconductor layer>

[0069] The p-type semiconductor layer includes a first p-type semiconductor layer 223 that is part of the light-emitting mesa structure portion 22 and a second p-type semiconductor layer 233 that is part of the protective mesa structure portion 23. The p-type semiconductor layer corresponds to the second conductive type semiconductor layer.

[0070] As Figure 2A shown, the first p-type semiconductor layer 223 is directly formed on the first quantum well layer 222, and the second p-type semiconductor layer 233 is directly formed on the second quantum well layer 232. Additionally, the first p-type semiconductor layer 223 may also be disposed on a layer other than the p-type semiconductor layer disposed on the third n-type semiconductor layer 231. Specifically, a graded composition layer (not shown) in which the ratio of constituent elements changes continuously or discretely may be disposed on the first quantum well layer 222, and the first p-type semiconductor layer 223 may be disposed on the graded composition layer. Similarly, the second p-type semiconductor layer 233 may also be disposed on a composition graded layer or the like disposed on the second quantum well layer 232.

[0071] Alternatively, a barrier layer having a relatively large bandgap may also be provided between the graded composition layer and the first p-type semiconductor layer 223 or the second p-type semiconductor layer 233.

[0072] When the proportion of Al element in the constituent elements on the uppermost surface of the first p-type semiconductor layer 223 and the second p-type semiconductor layer 233 is large, light with a wavelength in the deep ultraviolet region is likely to pass through, and high luminous efficiency can be achieved. Therefore, it is preferred. However, when there is too much Al element, the chemical reaction with oxygen and water vapor in the air is likely to be promoted, so deterioration is likely to occur. Therefore, in order to realize the nitride semiconductor light-emitting element 1, it is preferred that the first p-type semiconductor layer 223 and the second p-type semiconductor layer 233 are composed of Al y Ga 1-y N (0 ≤ y ≤ 0.6).

[0073] From the viewpoint of efficiently generating the two-dimensional hole gas in the composition graded layer and the p-type semiconductor layer, it is preferred to deform the p-type semiconductor layer, that is, to reduce the relaxation rate. In order to reduce the relaxation rate of the p-type semiconductor layer, the thickness of the p-type semiconductor layer is preferably 1 nm to 10 nm, and more preferably 4 nm to 8 nm.

[0074] The electrode may be in direct contact with the upper layer of the p-type semiconductor layer, or the electrode may be in contact with the uppermost surface of the p-type semiconductor layer stacked in multiple layers. From the viewpoint of generating holes inside the thin film, the p-type semiconductor layer may contain a p-type dopant, or in order to inject holes directly from the electrode into the two-dimensional hole gas at the interface, it may also not contain a dopant. As the p-type dopant, Mg is generally used, but as long as it is an impurity that generates holes, Be, Zn, etc. may also be used.

[0075] As a method for confirming the compositional difference between the outermost surfaces of the p-type semiconductor layer and the graded composition layer, it can be identified by various analytical methods such as XRD (X-ray diffraction), EDX (energy dispersive X-ray spectroscopy), XRF (fluorescent X-ray analysis), AES (Auger electron spectroscopy), SIMS (secondary ion mass spectrometry), and EELS (electron energy loss spectroscopy).

[0076] <First Electrode>

[0077] The first electrode 30 has a first electrode region 31 formed on the upper surface of the first n-type semiconductor layer 21 and serving as a base of an external connection portion, and a second electrode region 32 formed on the upper surface of the first n-type semiconductor layer 21 and spatially separated from the first electrode region 31. In addition, the first electrode 30 has a third electrode region 33 disposed on the first n-type semiconductor layer 21 and facing the second electrode region 32 across the light-emitting mesa structure portion 22. Herein, "spatially separated" means that there are sides of the first electrode region 31 and sides of the second electrode region 32 and they do not contact each other. The first electrode region 31 is provided to improve the adhesion of the base of the external connection portion, and the second electrode region 32 and the third electrode region 33 are provided to supply electrons to the light-emitting mesa structure portion 22.

[0078] In addition, from the viewpoint of reliability such as detachment of the external connection portion, it is preferable that the number of the first electrode regions 31 is large. However, when the number of the first electrode regions 31 is too large, the area ratio of the light-emitting mesa structure portion 22 becomes small and the relative light-emitting output power per unit area decreases, so it is not preferable. Therefore, it is preferable to form the first electrode regions 31 at two or more corners of the substrate 10, and more preferably to form the first electrode regions 31 at four corners of the substrate 10. Thereby, the reliability of the external connection portion can be improved, and the adhesion can be effectively improved without reducing the area ratio of the light-emitting mesa structure portion 22.

[0079] The first electrode 30 is formed of a material having effects such as improving the adhesion of the electrode, preventing oxidation of the electrode material, and having a low contact resistance with the first n-type semiconductor layer 21. As such a material, for example, metals such as Ti, Al, Ni, Mo, V, Au, W, Pt, Pd, Si, Zr, Cr, Hf, Nb, Ta, Co, Rh, Ir, Cu, Ag, and alloys containing these metals, or conductive oxides such as ITO or Ga2O3 can be used. More preferably, it is formed of a material containing titanium, aluminum, nickel, and gold, but is not limited to these materials.

[0080] When the first electrode 30 is composed of titanium, aluminum, nickel, and gold, it preferably has both an alloy layer containing aluminum and nickel formed on or near the contact surface with the first n-type semiconductor layer 21 and an aluminum-containing layer other than the alloy layer. Herein, near the contact surface means a portion of the first electrode 30 close to the first n-type semiconductor layer 21 but not in contact with the first n-type semiconductor layer 21. For example, it means a region between the contact surface in the layer of the first electrode 30 and a position 3 nm away from the contact surface.

[0081] In order to reduce the resistance of the interface with the first n-type semiconductor layer 21, at least a part of the above-mentioned contact surface of the first electrode 30 may contain, for example, Ti, Mo, V, Au, W, Pt, Pd, Si, Zr, etc. It is more preferable to contain Ti or Au, and it is further preferable to contain Ti.

[0082] In addition, in the first electrode 30, the alloy layer containing aluminum and nickel and the aluminum-containing layer may exist in multiple regions. In this case, in the first electrode 30, the total existence rate of the alloy layer containing aluminum and nickel and the aluminum-containing layer is preferably 60% or more, and more preferably 70% or more. However, it is not limited to these structures.

[0083] Such a first electrode 30 can be obtained, for example, by forming a metal laminate on the first n-type semiconductor layer 21 by sputtering or evaporation and performing a heat treatment such as RTA (Rapid Thermal Annealing). In addition, the first electrode region 31, the second electrode region 32, and the third electrode region 33 of the first electrode 30 can be formed simultaneously by one lithography, film formation, and heat treatment, which is preferable from the viewpoint of simplifying the manufacturing process.

[0084] <Second Electrode>

[0085] The second electrode 40 is provided to supply holes (holes) to the nitride semiconductor light-emitting element 1. The second electrode 40 is formed on the upper surface of the first p-type semiconductor layer 223 of the light-emitting mesa structure portion 22.

[0086] The second electrode 40 may be formed of a conductive material. As such materials, for example, Ni, Al, Ti, Au, Pt, Ag, Rh, Pd, Pt, Cu, and their alloys or ITO, etc. can be cited. It is more preferable to use Ni, Au, or their alloy layer with a small contact resistance with the nitride semiconductor layer. Such an electrode can be obtained, for example, by forming a metal laminate by sputtering or evaporation and performing a heat treatment such as RTA (Rapid Thermal Annealing).

[0087] Each electrode may further include a UV (ultraviolet) reflector. The UV reflector is a structure for preventing photons from escaping from the semiconductor layer structure by re-directing the direction of photons emitted toward the electrode. In addition, the UV reflector is designed to improve the extraction efficiency of photons generated in the active region of the device by re-directing the direction of photons toward a desired light-emitting surface, such as the bottom surface.

[0088] <Configuration of the Protective Mesa Structure Portion and the First and Second Electrode Regions>

[0089] Refer to Figure 3 AndFigure 4 A narrow space portion 60 formed between the protective mesa structure portion 23 and the first electrode region 31 and between the first electrode region 31 and the second electrode region 32 will be described. Figure 3 It is a top view schematic diagram showing an example of the schematic structure of the nitride semiconductor light-emitting element 1, and shows a light-emitting mesa structure portion 22, a protective mesa structure portion 23, a first electrode 30 (a first electrode region 31, a second electrode region 32, a third electrode region 33), and a first n-type semiconductor layer 21. In addition, Figure 4 It is an enlarged view showing Figure 3 the region indicated by the dashed line in

[0090] In a state before the formation of the passivation layer 50, a narrow space portion 60 with a predetermined interval is formed between the protective mesa structure portion 23 and the first electrode region 31. In a state before the formation of the passivation layer 50, the narrow space portion 60 has a first narrow space portion 61 formed by the spatial arrangement of the protective mesa structure portion 23 and the first electrode region 31 provided with a first interval W1 therebetween. In addition, the narrow space portion 60 has a second narrow space portion 62 formed by the spatial arrangement of the first electrode region 31 and the second electrode region 32 provided with a second interval W2 therebetween. The protective mesa structure portion 23 is preferably disposed at the outer edge portion of the substrate 10. Therefore, the first electrode region 31 is preferably disposed at two or more corners of the substrate 10 in a top view, more preferably disposed at four corners, and is disposed with a first interval W1 between it and the protective mesa structure portion 23. As Figure 4 shown, the light-emitting mesa structure portion 22 and the protective mesa structure portion 23 are disposed in regions other than the first narrow space portion 61 and the second narrow space portion 62.

[0091] By forming the passivation layer 50 (details will be described later) across the first narrow space portion 61 and the second narrow space portion 62 respectively, the adhesion of the passivation layer 50 around the first electrode region 31 is improved by the anchoring effect.

[0092] The first narrow space portion 61 is formed by a region surrounded by the side surface of the protective mesa structure portion 23 and the side surface of the first electrode region 31. As Figure 4 shown, the first narrow space portion 61 is preferably formed so as to surround at least two sides of each first electrode region 31, and preferably there are the same number of first narrow space portions 61 as the number of first electrode regions 31. In addition, the first narrow space portion 61 is preferably formed at two or more corners of the nitride semiconductor light-emitting element 1, more preferably formed at four corners. However, it is not limited to these structures.

[0093] The first interval W1 as the width of the first narrow space portion 61 (refer to Figure 4)It is determined by the distance between the protective mesa structure portion 23 and the first electrode region 31. When the first interval W1 is too narrow, sometimes the passivation layer 50 cannot fully cover, or the first narrow space portion 61 cannot be formed due to misalignment during the manufacturing process. In addition, when the first interval W1 is too wide, the ratio of the chip area to the area of the light-emitting portion becomes larger, and the area that does not contribute to light emission increases. Therefore, the first interval W1 is preferably 0.5 μm or more and 25 μm or less, more preferably 1 μm or more and 20 μm or less.

[0094] The second narrow space portion 62 is formed by the region surrounded by the side surfaces of the first electrode region 31 and the second electrode region 32. As Figure 4 shown, the second narrow space portion 62 is preferably formed between each first electrode region 31 and the closest second electrode region 32, and preferably the number of second narrow space portions 62 is the same as the number of first electrode regions 31. However, it is not limited to these structures.

[0095] As the second interval W2 (refer to Figure 4 ) of the width of the second narrow space portion 62 is determined by the distance between the first electrode region 31 and the second electrode region 32. When the second interval W2 is too narrow, the passivation layer 50 cannot fully cover. In addition, when the second interval W2 is too wide, the balance of the light emission distribution of the light-emitting mesa structure portion 22 becomes uneven. Therefore, the second interval W2 is preferably 0.5 μm or more and 140 μm or less, more preferably 1 μm or more and 120 μm or less.

[0096] Compared with the second electrode region 32, the first electrode region 31 is directly subjected to physical loads when externally connected, so it is easily damaged and is prone to corrosion in a high-humidity environment. However, by forming the first electrode region 31 and the second electrode region 32 with a second interval W2 therebetween, it is possible to suppress the spread of corrosion from the first electrode region 31 to the second electrode region 32 during energization in a high-humidity environment. Since the electrode regions that supply electrons (carriers) to the light-emitting mesa structure portion 22 are the second electrode region 32 and the third electrode region 33, by suppressing the spread of corrosion to the second electrode region 32, it is possible to suppress an increase in the drive voltage and disconnection in the nitride semiconductor light-emitting element 1 during energization in a high-humidity environment.

[0097] <Passivation layer>

[0098] The passivation layer 50 has a first passivation coverage region 51 that covers an edge portion (an outer edge portion on the first electrode region 31 side of the protective mesa structure portion 23) that is a part of the upper surface covering the protective mesa structure portion 23, a second passivation coverage region 52 that covers the outer edge portion of the first electrode region 31, and a third passivation coverage region 53 that covers the outer edge portion of the second electrode region 32. That is, the passivation layer 50 is disposed on the entire surface except for the outer peripheral portion of the protective mesa structure portion 23 (the outer peripheral portion of the nitride semiconductor light-emitting element 1), and the central portions of the first electrode 30 (the first electrode region 31, the second electrode region 32, and the third electrode region 33) and the second electrode 40, and is formed across the first narrow space portion 61 and the second narrow space portion 62.

[0099] By covering the protective mesa structure portion 23 with the first passivation coverage region 51, the adhesion of the passivation layer 50 to the protective mesa structure portion 23 is improved, and the region where the first n-type semiconductor layer 21 contacts air and water vapor can be reduced. In addition, the wider the region where the first passivation coverage region 51 covers the protective mesa structure portion 23, the higher the adhesion of the passivation layer 50 to the protective mesa structure portion 23. Therefore, by covering the protective mesa structure portion 23 with the first passivation coverage region 51, a nitride semiconductor light-emitting element 1 with a longer lifespan can be realized. On the other hand, when the first passivation coverage region 51 covers the entire protective mesa structure portion 23, cracks sometimes occur in the passivation layer 50 when the nitride semiconductor light-emitting elements 1 on the wafer are made into monolithic devices. Therefore, it is preferable to dispose the passivation layer 50 in the manner of covering the outer edge portion on the first electrode region side of the protective mesa structure portion 23 as described above.

[0100] The passivation layer 50 has a second passivation coverage region 52 that covers the outer edge portion of the first electrode region 31. That is, a structure is formed in which the end portion of the first electrode region 31 is pressed by the second passivation coverage region 52, whereby the first electrode region 31 can obtain high adhesion to the first n-type semiconductor layer 21. When the region where the second passivation coverage region 52 covers the first electrode region 31 becomes wider, the force pressing the first electrode region 31 generated by the second passivation coverage region 52 becomes stronger. However, when the region where the second passivation coverage region 52 covers the first electrode region 31 is too wide, the opening portion on the first electrode region 31 becomes too small, so it is not preferable. It is also possible to change the size of the first electrode region 31 to widen the second passivation coverage region 52 while maintaining the size of the opening portion. However, when the second passivation coverage region 52 is too wide, the area of the entire chip becomes larger, so the light emission output power per unit area of the chip decreases, which is not preferable. In addition, when the region where the second passivation coverage region 52 covers the first electrode region 31 is too narrow, the end portion of the first electrode region 31 cannot be covered due to alignment during manufacturing, so it is not preferable. Therefore, the width of the end portion of the upper surface of the passivation layer 50 that covers the first electrode region 31, that is, the width of the region where the upper surface of the first electrode region 31 is covered by the second passivation coverage region 52 (hereinafter sometimes referred to as the width of the second passivation coverage region 52) is preferably 0.5 μm or more and 15 μm or less, more preferably 1 μm or more and 10 μm or less.

[0101] The passivation layer 50 has a third passivation coverage region 53 that covers the outer edge portion of the second electrode region 32. That is, a structure is formed in which the end portion of the second electrode region 32 is pressed by the third passivation coverage region 53, whereby the second electrode region 32 can obtain high adhesion to the first n-type semiconductor layer 21. When the region where the third passivation coverage region 53 covers the second electrode region 32 becomes wider, the force pressing the second electrode region 32 generated by the third passivation coverage region 53 becomes stronger. However, when the region where the third passivation coverage region 53 covers the second electrode region 32 is too wide, the opening portion on the second electrode region 32 becomes too small, so it is not preferable. It is also possible to change the size of the second electrode region to widen the third passivation coverage region while maintaining the size of the opening portion. However, when the third passivation coverage region is too wide, the area of the entire chip becomes larger, so the light emission output power per unit area of the chip decreases, which is not preferable. In addition, when the region where the third passivation coverage region 53 covers the second electrode region 32 is too narrow, the end portion of the second electrode region 32 cannot be covered due to alignment during manufacturing, so it is not preferable. Therefore, the width of the end portion of the upper surface of the passivation layer 50 that covers the second electrode region 32, that is, the width of the region where the upper surface of the second electrode region 32 is covered by the third passivation coverage region 53 (hereinafter sometimes referred to as the width of the third passivation coverage region 53) is preferably 0.5 μm or more and 15 μm or less, more preferably 1 μm or more and 10 μm or less.

[0102] The passivation layer 50 is formed so as to overlap, in a plan view, a first narrow space portion 61 in the first n-type semiconductor layer 21 between the protective mesa structure portion 23 and the first electrode region 31. Thereby, the adhesion of the passivation layer 50 can be improved by the anchoring effect. In this case, in particular, the effect of adhesion between the first passivation covering region 51 and the protective mesa structure portion 23 and the effect of suppressing the first electrode region 31 by the second passivation covering region 52 become stronger. In addition, the passivation layer 50 is formed so as to overlap, in a plan view, a second narrow space portion 62 in the first n-type semiconductor layer 21 between the first electrode region 31 and the second electrode region 32. Thereby, the adhesion of the passivation layer 50 can be improved by the anchoring effect. In this case, in particular, the effect of suppressing the first electrode region 31 by the second passivation covering region 52 and the effect of suppressing the second electrode region 32 by the third passivation covering region 53 become stronger. Therefore, by forming the passivation layer 50 so as to straddle the first narrow space portion 61 and the second narrow space portion 62 respectively, even when a physical load is applied during external connection of the nitride semiconductor light-emitting element 1, peeling and crack (including microcrack) generation of the passivation layer 50 can be suppressed. In addition, the adhesion of the passivation layer 50 to the protective mesa structure portion 23 is improved, and the first n-type semiconductor layer 21 is less likely to come into contact with air and water vapor, thereby enabling extension of the life of the nitride semiconductor light-emitting element 1.

[0103] In such a nitride semiconductor light-emitting element 1, the damage resistance to the first electrode region 31 and the passivation layer 50 during external connection of the nitride semiconductor light-emitting element 1 is improved. Therefore, it is not necessary to set the area of the first electrode region 31 and the opening portion provided on the first electrode region 31 to a size with a large margin considering the sizes of the conductive wire and the conductive bump adhered during external connection. Thereby, it is not necessary to increase the area of the first electrode region 31 in the nitride semiconductor light-emitting element 1 to more than the necessary value, and thus the acquisition number of the nitride semiconductor light-emitting elements 1 in the wafer plane can be increased. In addition, the area (occupancy ratio with respect to the chip area) of the light-emitting mesa structure portion 22 in the nitride semiconductor light-emitting element 1 can also be increased. Therefore, an effect of increasing the light emission output power per unit area in the nitride semiconductor light-emitting element 1 can also be expected.

[0104] The passivation layer 50 can be formed of oxides or nitrides such as SiN, SiO2, SiON, Al2O3, and ZrO layers, for example. From the viewpoints of waterproofness and stress on the device, silicon oxide or silicon nitride or both are preferably used in the passivation layer 50.

[0105] The method for forming the passivation layer 50 is not particularly limited. For example, it can be formed using a plasma CVD (Chemical Vapor Deposition) apparatus, a sputtering apparatus, a vacuum evaporation apparatus, etc. When using a plasma CVD apparatus to fabricate a silicon nitride film as the passivation layer 50, a method of using silane (SiH4) as the supply gas for the constituent element silicon and ammonia (NH3) as the supply gas for nitrogen is well-known. Additionally, when using a plasma CVD apparatus to fabricate a silicon oxide film as the passivation layer 50, a method of using silane (SiH4) as the supply gas for the constituent element silicon and nitrous oxide (N2O) as the supply gas for oxygen is well-known.

[0106] Furthermore, from the viewpoints of productivity and stress on the device, the film thickness of the passivation layer 50 is preferably 10 nm or more and 1000 nm or less, more preferably 50 nm or more and 500 nm or less.

[0107] Moreover, from the viewpoints of further improving the waterproof property and suppressing peeling of the passivation layer 50, other passivation layers, metal layers, etc. can be disposed on the passivation layer 50.

[0108] <Pad electrode>

[0109] The pad electrode 70 is disposed on a part of the passivation layer 50, on the first electrode region 31, the second electrode region 32, and the third electrode region 33 not covered by the passivation layer 50, and on the second electrode 40 not covered by the passivation layer 50. The pad electrode 70 has: a first pad electrode portion 71 that electrically connects the first electrode region 31, the second electrode region 32, and the third electrode region 33; a second pad electrode portion 72 disposed on a part of the passivation layer 50 and the second electrode 40 not covered by the passivation layer 50; and a third pad electrode portion 73 formed on a part of the passivation layer 50 and a part of the protection mesa structure portion 23.

[0110] The first pad electrode portion 71 covers a part of the second passivation coverage region 52 and a part of the third passivation coverage region 53. Therefore, the first pad electrode portion 71 has the effect of improving the adhesion of the second passivation coverage region 52 to the first electrode region 31 and the adhesion of the third passivation coverage region 53 to the second electrode region 32. Additionally, by forming the first pad electrode portion 71, an external connection region with the first electrode region 31 as the base and a lead electrode region that electrically connects the first electrode region 31, the second electrode region 32, and the third electrode region 33 can be formed at once, so it is preferable from the viewpoint of simplifying the manufacturing process.

[0111] The second pad electrode portion 72 covers a part of an unillustrated passivation covering region where the passivation layer 50 covers the outer edge portion of the light-emitting mesa structure portion 22 (see Figure 2A ). Therefore, the second pad electrode portion 72 has the effect of improving the adhesion of the passivation layer 50 to the light-emitting mesa structure portion 22.

[0112] The third pad electrode portion 73 covers a part of the first passivation covering region 51 that covers the protective mesa structure portion 23. More specifically, as Figure 3 shown, the third pad electrode portion 73 is arranged so as to cover at least a part of the first passivation covering region 51 which is a region in the passivation layer 50 covering the outer edge portion of the protective mesa structure portion 23 and the region of the protective mesa structure portion 23 not covered by the passivation layer 50. Therefore, the third pad electrode portion 73 has the effect of improving the adhesion of the first passivation covering region 51 to the protective mesa structure portion 23.

[0113] In addition, by forming a structure in which the pad electrode 70 covers the outer edge portion of the passivation layer 50, there is an effect of suppressing moisture from entering the semiconductor layer and the electrode portion from the end portion of the passivation layer 50 and suppressing reactions with oxygen and water vapor in the air. Therefore, it is also preferable from the viewpoint of reliability.

[0114] Examples

[0115] Hereinafter, the invention of the present disclosure will be described more specifically by way of examples and comparative examples. It should be noted that the nitride semiconductor light-emitting element of the present disclosure is not limited to the examples shown below.

[0116] [Example 1]

[0117] <Example 1-1>

[0118] The nitride semiconductor light-emitting element of Example 1-1 is a nitride semiconductor light-emitting element having the structure described in the embodiment Figure 1 and shown in FIG. 2. Each layer of the nitride semiconductor light-emitting element has the following configuration.

[0119] The substrate is an AlN substrate.

[0120] The first n-type semiconductor layer is an n-type Al 20 cm -3 containing 2.0×10 0.7 Ga 0.3 N (n-Al 0.7 Ga 0.3 N) layer doped with Si as an impurity, and the thickness of the first n-type semiconductor layer is 400 nm.

[0121] The light-emitting mesa structure portion is composed of a second n-type semiconductor layer with a thickness of 150 nm, a first quantum well layer with a thickness of 70 nm, and a first p-type semiconductor layer with a thickness of 10 nm. Additionally, the protective mesa structure portion is composed of a third n-type semiconductor layer with a thickness of 150 nm, a second quantum well layer with a thickness of 70 nm, and a second p-type semiconductor layer with a thickness of 10 nm.

[0122] The second n-type semiconductor layer and the third n-type semiconductor layer are formed of an n-Al 20 cm -3 GaN layer containing Si as an impurity at a concentration of 2.0×10 0.7 Ga 0.3 The first quantum well layer and the second quantum well layer are formed by alternately stacking 5 layers each of an Al 0.51 Ga 0.49 N layer (well layer) with a thickness of 3 nm and an Al 0.78 Ga 0.22 N layer (barrier layer) with a thickness of 11 nm containing Si as an impurity. The first p-type semiconductor layer of the light-emitting mesa structure portion and the second p-type semiconductor layer of the protective mesa structure portion are formed of a p-type GaN (p-GaN) layer containing Mg as an impurity at a concentration of 2.0×10 20 cm -3

[0123] The first electrode formed on the first n-type semiconductor layer is composed of Ti, Al, Ni, and Au.

[0124] The second electrode formed on the first p-type semiconductor layer of the light-emitting mesa structure portion is composed of Ni and Au.

[0125] The passivation layer is a silicon nitride layer with a film thickness of 240 nm.

[0126] The nitride semiconductor light-emitting element of Example 1-1 is fabricated by the following method.

[0127] First, an n-Al 20 cmy -3 GaN layer containing Si as an impurity at a concentration of 2.0×10 0.7 Ga 0.3 was formed on an AlN substrate made of AlN single crystal with a thickness of 550 nm.

[0128] Next, 5 layers each of an Al 0.7 Ga 0.3 N layer with a thickness of 3 nm and an Al 0.51 Ga 0.49 N layer with a thickness of 11 nm containing Si as an impurity were alternately stacked on the n-Al 0.78 Ga 0.22 N layer to a total thickness of 70 nm.

[0129] Next, a p-GaN layer containing Mg as an impurity at a concentration of 2.0×10 20 cm -3 was formed with a thickness of 10 nm. These layers were formed by metalorganic chemical vapor deposition (MOCVD).

[0130] Thereby, a stack formed of nitride semiconductor layers was formed on the AlN substrate.

[0131] Next, dry etching was performed on the stack on the AlN substrate to remove the regions of the stack other than the regions that become the light-emitting mesa structure portion and the protective mesa structure portion to a specified depth, exposing a part of the n-Al 0.7 Ga 0.3 N layer. Thereby, the stack was formed into a shape in which the light-emitting mesa structure portion and the protective mesa structure portion protruded from the first n-type semiconductor layer having a thickness of 400 nm. A resist pattern was formed on the stack using photolithography, and then this dry etching was performed using a chlorine-containing gas. The chip of Example 1 was square, the chip size was 860 μm on each side, and a protective mesa structure portion was formed in a region 20 μm from the outer periphery to the inside of the chip.

[0132] Next, a metal stack film was formed by sequentially depositing a Ti layer, an Al layer, a Ni layer, and an Au layer on a part of the exposed first n-type semiconductor layer using electron beam evaporation, and heat treatment was performed using the RTA method, thereby forming a first electrode. At this time, the first electrode (the first electrode region, the second electrode region, and the third electrode region) was formed such that the first gap, which is the distance between the protective mesa structure portion and the first electrode region, was 2 μm and the second gap, which is the distance between the first electrode region and the second electrode region, was 9 μm.

[0133] In addition, a metal stack film was formed by sequentially depositing a Ni layer and an Au layer on a part of the first p-type semiconductor layer of the light-emitting mesa structure portion using electron beam evaporation, and heat treatment was performed using the RTA method, thereby forming a second electrode.

[0134] Next, a silicon nitride film with a thickness of 240 nm was formed by plasma CVD so as to cover the entire AlN substrate (the entire upper surface and the entire side surface) on which the light-emitting mesa structure portion, the protective mesa structure portion, the first electrode, and the second electrode were formed.

[0135] Next, using a resist pattern formed by photolithography, an opening was formed at a predetermined position of the silicon nitride film by etching using CF4. In Example 1-1, openings were formed on the upper surface of the first electrode and a part of the upper surface of the second electrode. At this time, the opening was formed such that the width of the first passivation covering region covering a part of the upper surface of the mesa structure portion was 7 μm, the width of the second passivation covering region covering the outer edge portion of the first electrode region was 4 μm, and the width of the third passivation covering region covering the outer edge portion of the second electrode was 4 μm. Next, Ti was deposited on the first electrode in the formed opening with a thickness of 20 nm, and Au was deposited with a thickness of 1000 nm in sequence, thereby forming a first pad electrode. In addition, Ti was deposited on the second electrode in the formed opening with a thickness of 20 nm, and Au was deposited with a thickness of 1000 nm in sequence, thereby forming a second pad electrode.

[0136] Next, the back side of the AlN substrate was ground and polished until the AlN substrate reached a thickness of 100 μm. It should be noted that the processes up to this point were carried out in a wafer state.

[0137] Finally, the wafer was singulated by laser scribing and dicing, and flip-chip mounting of the submount was performed by the GGI (Gold to Gold Interconnection) method, thereby performing packaging.

[0138] [Evaluation]

[0139] For the obtained nitride semiconductor light-emitting element of Example 1-1, in order to confirm the effect of damage resistance during external connection, the peeling state of the first pad electrode and the first electrode (first electrode region) was observed. As a result, it was confirmed that peeling did not occur in the nitride semiconductor light-emitting element of Example 1-1. It should be noted that since the nitride semiconductor light-emitting element after grinding and polishing has sufficient transparency, the peeling state of the pad electrode and the first electrode in the external connection region can be visually observed from the back side.

[0140] In addition, in order to evaluate the peeling, cracking, and microcracks of the first pad electrode and the first electrode that are not visually observable, a continuous power-on test (250 mA) was performed on the nitride semiconductor light-emitting element for 1000 hours in an environment of 55°C and 85% RH. Generally, when the nitride semiconductor containing Al, the first electrode (electrode for n-type semiconductor), reacts with oxygen and water vapor in the air and deteriorates during the power-on test, blackening occurs. When the deterioration progresses further, the resistance of the semiconductor increases, and an increase in the driving voltage of the element is observed. Therefore, the appearance around the external connection region after the continuous power-on test was evaluated, and as a result, it was confirmed that no blackening occurred around the external connection region. That is, it was confirmed that in the nitride semiconductor light-emitting element of Example 1-1, peeling or cracking of the pad electrode and the first electrode, and peeling or cracking (including microcracks) of the passivation layer caused by the physical load during external connection were suppressed. That is, it was confirmed that a nitride semiconductor light-emitting element with improved damage resistance during external connection was obtained in Example 1-1.

[0141] <Comparative Example 1-1>

[0142] The nitride semiconductor light-emitting element of Comparative Example 1-1 is Figure 5 and Figure 6 the nitride semiconductor light-emitting element having the structure shown. Here, Figure 5 is a top view schematic diagram showing the schematic structure of the nitride semiconductor light-emitting element of Comparative Example 1-1, Figure 6 is a cross-sectional schematic diagram showing the schematic structure of the nitride semiconductor light-emitting element, showing the Figure 5 C-C cross-section in Figure 5 and Figure 6 For ease of explanation, in Figure 1 and the parts corresponding to the respective parts of the nitride semiconductor light-emitting element shown in Fig. 2 are labeled with the same reference numerals.

[0143] In Comparative Example 1, except that when forming the metal laminated film that becomes the first electrode, only the second electrode region and the third electrode region were formed and the first electrode region was not formed, and when opening the silicon nitride by CF4 etching, no opening was formed in the region where the first electrode region was not formed, the nitride semiconductor light-emitting element was formed in the same manner as in Example 1-1.

[0144] [Evaluation]

[0145] Regarding the obtained nitride semiconductor light-emitting element of Comparative Example 1-1, the peeling state of the first pad electrode in the same region as that of Example 1-1 (the region where the first electrode region was not formed) was confirmed by the same method as that of Example 1-1. As a result, peeling was clearly confirmed in the first pad electrode portion. In this Comparative Example 1-1, since the first electrode region was not formed, the first narrow space portion between the protective mesa structure portion and the first electrode region and the second narrow space portion between the first electrode region and the second electrode region could not be formed. That is, it is considered that in the region where the first electrode region was not formed, physical damage had to be tolerated only by the adhesion force between the first pad electrode and the passivation layer, and the adhesion between the first pad electrode and the passivation layer was insufficient.

[0146] <Comparative Example 1-2>

[0147] The nitride semiconductor light-emitting element of Comparative Example 1-2 was Figure 7 and Figure 8 the nitride semiconductor light-emitting element having the structure shown. Here, Figure 7 is a top view schematic diagram showing the schematic structure of the nitride semiconductor light-emitting element of Comparative Example 1-2, Figure 8 is a cross-sectional schematic diagram showing the schematic structure of the nitride semiconductor light-emitting element, showing the Figure 7 D-D cross section in Figure 7 and Figure 8 For ease of explanation, in Figure 1 and the parts corresponding to the respective parts of the nitride semiconductor light-emitting element shown in Fig. 2 are labeled with the same reference numerals.

[0148] In Comparative Example 2, except that when forming the metal laminated film of the first electrode, only the second electrode region and the third electrode region were formed and the first electrode region was not formed, and an opening was formed in the region where the first electrode region was not formed when opening the silicon nitride by CF4 etching, the nitride semiconductor light-emitting element was formed in the same manner as in Example 1-1.

[0149] [Evaluation]

[0150] Regarding the obtained nitride semiconductor light-emitting elements of Comparative Examples 1-2, the peeling state of the first pad electrode in the same region (the region where the first electrode region is not formed) as in Example 1-1 was confirmed by the same method as in Example 1-1. As a result, although it was improved compared with Comparative Example 1-1, peeling was clearly confirmed in the first pad electrode portion. In this Comparative Example 1-2, as in Comparative Example 1-1, since the first electrode region was not formed, the first narrow space portion and the second narrow space portion could not be formed. That is, it is considered that in the region where the first electrode region is not formed in Comparative Example 1-2, although the adhesion force between the first pad electrode and the first n-type semiconductor layer is higher than the adhesion force between the first pad electrode and the passivation layer in the region where the first electrode region is not formed in Comparative Example 1-1, the adhesion is insufficient.

[0151] The evaluation results of Example 1 are shown in Table 1 below.

[0152] [Table 1]

[0153]

[0154] As can be seen from the above, by forming the structure of Example 1-1, a nitride semiconductor light-emitting element with improved damage resistance during external connection can be obtained.

[0155] [Example 2]

[0156] In Example 2, nitride semiconductor light-emitting elements of Examples 2-1 to 2-9, which were fabricated by changing the width of the second passivation coverage region, were evaluated. Specifically, in order to change the length of the second passivation coverage portion, the size of the first electrode region was changed in the photomask for forming the first electrode to form the first electrode. Here, since the opening size of the passivation layer was maintained, the alignment margin with the conductive bumps for external connection (refer to Figure 2B ) was maintained, and the same physical load was applied, and the evaluation was performed with such a structure. In addition, since it was necessary to increase the chip size by the amount by which the size of the first electrode region increased, the other photomasks were also corrected in accordance with the first electrode (including the pitch of one chip) and fabricated. When the size of the first electrode region was reduced, the chip size was not changed. Except for changing the photomasks used, nitride semiconductor light-emitting elements of each example and comparative example were obtained in the same manner as in Example 1-1.

[0157] <Example 2-1>

[0158] A nitride semiconductor light-emitting element of Example 2-1 was formed in the same manner as in Example 1-1, except that the width of the second passivation coverage region was changed to 0.1 μm.

[0159] <Example 2-2>

[0160] A nitride semiconductor light-emitting element of Example 2-2 was formed in the same manner as in Example 1-1, except that the width of the second passivation covering region was changed to 0.5 μm.

[0161] <Example 2-3>

[0162] A nitride semiconductor light-emitting element of Example 2-3 was formed in the same manner as in Example 1-1, except that the width of the second passivation covering region was changed to 1.0 μm.

[0163] <Example 2-4>

[0164] A nitride semiconductor light-emitting element of Example 2-4 was formed in the same manner as in Example 1-1, except that the width of the second passivation covering region was changed to 2.0 μm.

[0165] <Example 2-5>

[0166] A nitride semiconductor light-emitting element of Example 2-5 was formed in the same manner as in Example 1-1, except that the width of the second passivation covering region was changed to 8.0 μm.

[0167] <Example 2-6>

[0168] A nitride semiconductor light-emitting element of Example 2-6 was formed in the same manner as in Example 1-1, except that the width of the second passivation covering region was changed to 10 μm.

[0169] <Example 2-7>

[0170] A nitride semiconductor light-emitting element of Example 2-7 was formed in the same manner as in Example 1-1, except that the width of the second passivation covering region was changed to 15 μm.

[0171] <Example 2-8>

[0172] A nitride semiconductor light-emitting element of Example 2-8 was formed in the same manner as in Example 1-1, except that the width of the second passivation covering region was changed to 17 μm.

[0173] <Example 2-9>

[0174] A nitride semiconductor light-emitting element of Example 2-9 was formed in the same manner as in Example 1-1, except that the width of the second passivation covering region was changed to 20 μm.

[0175] [Evaluation]

[0176] For the nitride semiconductor light-emitting elements of the respective embodiments, the peeling state of the first pad electrode and the first electrode (particularly the first electrode region) was confirmed and the discoloration after the continuous power-on test was confirmed by the same method as in Embodiment 1-1.

[0177] In addition, for the nitride semiconductor light-emitting elements of the respective embodiments, the output power at 500 mA was measured, and the relative output power per unit area of the chip based on the nitride semiconductor light-emitting element of Embodiment 1-1 (1.00) was calculated for evaluation.

[0178] The evaluation results of Embodiment 2 are shown in Table 2 below.

[0179] [Table 2]

[0180]

[0181] As shown in Table 2, in the nitride semiconductor light-emitting elements of the respective embodiments, regardless of the width of the second passivation covering region, peeling of the first pad electrode and the first electrode region does not occur. In addition, in the nitride semiconductor light-emitting elements of Embodiments 2-2 to 2-9 in which the width of the second passivation covering region is 0.5 μm or more, in addition to no peeling of the first pad electrode and the first electrode region, the following further effects were confirmed: suppression of blackening of the nitride semiconductor and the first electrode, that is, suppression of peeling, cracking, and microcracks of the first pad electrode and the first electrode that are not visually observable. It is considered that this is because when the width of the second passivation covering region is 0.5 μm or more, the coverage of the first electrode region by the passivation layer is sufficient, suppressing peeling, cracking, and microcracks of the first pad electrode and the first electrode that are not visually observable. When considering the margin for alignment based on the photomask, the width of the second passivation covering region is more preferably 1 μm or more.

[0182] In addition, as shown in Table 2, the narrower the width of the second passivation covering region, the more gradually the relative output power per unit area of the chip tends to increase. It is considered that this is because the narrower the width of the second passivation covering region, the smaller the chip size, and thus the output power per unit area of the chip increases. Therefore, the width of the second passivation covering region is preferably set to 15 μm or less, and more preferably set to 10 μm or less.

[0183] From the above, it was confirmed that the width of the second passivation covering region is preferably set to 0.5 μm or more and 15 μm or less, and more preferably set to 1 μm or more and 10 μm or less.

[0184] [Embodiment 3]

[0185] In Example 3, nitride semiconductor light-emitting elements of Examples 3-1 to 3-8 fabricated by changing the first interval which is the distance between the protective mesa structure portion and the first electrode region were evaluated. Specifically, in the photomask for forming the mesa structure portion, in order to change the distance between the protective mesa structure portion and the first electrode region, the position of the protective mesa structure portion was changed. Since changing the design of the photomask causes a change in the chip size, other photomasks were also fabricated with corrections in accordance with the protective mesa structure portion (including the pitch of one chip). Except for changing the used photomasks, nitride semiconductor light-emitting elements of each example and comparative example were obtained in the same manner as in Example 1-1.

[0186] <Example 3-1>

[0187] Except for changing the first interval to 0.1 μm, a nitride semiconductor light-emitting element of Example 3-1 was formed in the same manner as in Example 1-1.

[0188] <Example 3-2>

[0189] Except for changing the first interval to 0.5 μm, a nitride semiconductor light-emitting element of Example 3-2 was formed in the same manner as in Example 1-1.

[0190] <Example 3-3>

[0191] Except for changing the first interval to 1 μm, a nitride semiconductor light-emitting element of Example 3-3 was formed in the same manner as in Example 1-1.

[0192] <Example 3-4>

[0193] Except for changing the first interval to 10 μm, a nitride semiconductor light-emitting element of Example 3-4 was formed in the same manner as in Example 1-1.

[0194] <Example 3-5>

[0195] Except for changing the first interval to 15 μm, a nitride semiconductor light-emitting element of Example 3-5 was formed in the same manner as in Example 1-1.

[0196] <Example 3-6>

[0197] Except for changing the first interval to 20 μm, a nitride semiconductor light-emitting element of Comparative Example 3-2 was formed in the same manner as in Example 1-1.

[0198] <Example 3-7>

[0199] Except for changing the first interval to 25 μm, a nitride semiconductor light-emitting element of Example 3-7 was formed in the same manner as in Example 1-1.

[0200] <Example 3-8>

[0201] A nitride semiconductor light-emitting element of Example 3-8 was formed in the same manner as in Example 1-1, except that the first interval was changed to 30 μm.

[0202] [Evaluation]

[0203] For the nitride semiconductor light-emitting elements of each example, the peeling state of the first pad electrode and the first electrode (particularly the first electrode region) was confirmed and the discoloration after the continuous power-on test was confirmed by the same method as in Example 1-1.

[0204] In addition, for the nitride semiconductor light-emitting elements of each example, the output power at 500 mA was measured, and the relative output power per unit area of the chip was calculated based on the nitride semiconductor light-emitting element of Example 1-1 (1.00) for evaluation.

[0205] The evaluation results of Example 3 are shown in Table 3 below.

[0206] [Table 3]

[0207]

[0208] As shown in Table 3, in the nitride semiconductor light-emitting elements of each example, regardless of the first interval between the protective mesa structure portion and the first electrode region, peeling of the first pad electrode and the first electrode region does not occur. In addition, in the nitride semiconductor light-emitting elements of Examples 3-2 to 3-6 where the first interval is 0.5 μm or more, in addition to no peeling of the first pad electrode and the first electrode region, the following further effects were confirmed: suppression of blackening of the nitride semiconductor and the first electrode, that is, suppression of peeling, cracking, and microcracks of the first pad electrode and the first electrode that are not visually observable. When the first interval is 0.5 μm or more, no interference color is observed in the first space portion, and good coverage of the passivation layer is confirmed. Therefore, the first interval is preferably 0.5 μm or more, more preferably 1 μm or more.

[0209] In addition, as shown in Table 3, the shorter the first interval, the more gradually the relative output power per unit area of the chip tends to increase. It is considered that this is because the narrower the first interval, the smaller the overall size of the chip, that is, the larger the area ratio of the light-emitting mesa structure portion, and thus the output power per unit area of the chip increases. Therefore, the first interval is preferably set to 25 μm or less, more preferably set to 20 μm or less.

[0210] From the above, it was confirmed that the distance of the first narrow space portion is preferably set to 0.5 μm or more and 25 μm or less, more preferably set to 1 μm or more and 20 μm or less.

[0211] [Embodiment 4]

[0212] In Embodiment 4, nitride semiconductor light-emitting elements of Embodiments 4-1 to 4-7 fabricated by changing the second interval that is the distance between the first electrode region and the second electrode region were evaluated. Specifically, in the photomask for forming the first electrode region, in order to change the distance between the first electrode region and the second electrode region, the length of the second electrode region was changed. Except for changing the photomask for the second electrode region and the accompanying passivation opening mask, nitride semiconductor light-emitting elements of each embodiment and comparative example were obtained in the same manner as in Embodiment 1-1.

[0213] <Embodiment 4-1>

[0214] A nitride semiconductor light-emitting element of Embodiment 4-1 was formed in the same manner as in Embodiment 1-1, except that the second interval was changed to 0.1 μm.

[0215] <Embodiment 4-2>

[0216] A nitride semiconductor light-emitting element of Embodiment 4-2 was formed in the same manner as in Embodiment 1-1, except that the second interval was changed to 0.5 μm.

[0217] <Embodiment 4-3>

[0218] A nitride semiconductor light-emitting element of Embodiment 4-3 was formed in the same manner as in Embodiment 1-1, except that the second interval was changed to 1 μm.

[0219] <Embodiment 4-4>

[0220] A nitride semiconductor light-emitting element of Embodiment 4-4 was formed in the same manner as in Embodiment 1-1, except that the second interval was changed to 100 μm.

[0221] <Embodiment 4-5>

[0222] A nitride semiconductor light-emitting element of Embodiment 4-5 was formed in the same manner as in Embodiment 1-1, except that the second interval was changed to 120 μm.

[0223] <Comparative Example 4-6>

[0224] A nitride semiconductor light-emitting element of Comparative Example 4-6 was formed in the same manner as in Embodiment 1-1, except that the second interval was changed to 140 μm.

[0225] <Embodiment 4-7>

[0226] The nitride semiconductor light-emitting element of Example 4-7 was formed in the same manner as in Example 1-1, except that the second interval was changed to 160 μm.

[0227] [Evaluation]

[0228] For the nitride semiconductor light-emitting element of each example, the peeling state of the first pad electrode and the first electrode (especially the first electrode region) was confirmed and the discoloration after the continuous power-on test was confirmed by the same method as in Example 1-1.

[0229] In addition, for the nitride semiconductor light-emitting element of each example, the area of the light-emitting region (region where the light emission is 85% or more of the maximum light emission intensity) in the chip plane when 500 mA was applied was measured, and the area of the light-emitting region based on the area of the light-emitting region in the nitride semiconductor light-emitting element of Example 1-1 (1.00) was calculated as the relative output power per unit area of the chip for evaluation.

[0230] The evaluation results of Example 4 are shown in Table 4 below.

[0231] [Table 4]

[0232]

[0233] As shown in Table 4, in the nitride semiconductor light-emitting element of each example, regardless of the second interval between the first electrode region and the second electrode region, peeling of the first pad electrode and the first electrode region does not occur. In addition, in the nitride semiconductor light-emitting elements of Examples 4-2 to 4-6 where the second interval is 0.5 μm or more, in addition to no peeling of the first pad electrode and the first electrode region, the following further effects were confirmed: suppression of blackening of the nitride semiconductor and the first electrode, that is, suppression of peeling, cracking, and microcracks of the first pad electrode and the first electrode that are not visually observable. When the second interval is 0.5 μm or more, no interference color is observed in the second space portion, and good coverage of the passivation layer is confirmed. Therefore, the second interval is preferably 0.5 μm or more, more preferably 1 μm or more.

[0234] In addition, as shown in Table 4, when the second interval becomes short, the relative output power per unit area of the chip tends to increase. When the second interval becomes short, the length of the electrode becomes long, and it is easy to supply electrons to the front end of the light-emitting mesa structure portion, so non-uniformity of the light-emitting region is less likely to occur. Therefore, the shorter the second interval, the longer the length of the second electrode portion can be maintained, and non-uniformity of the light-emitting region is less likely to occur. Less likelihood of non-uniformity of the light-emitting region means less likelihood of local reduction in light-emitting output power, and the light-emitting output power per unit area of the chip increases. Therefore, the second interval is preferably set to 140 μm or less, more preferably set to 120 μm or less.

[0235] It has been confirmed above that the second interval is preferably set to 0.5 μm or more and 140 μm or less, and more preferably set to 1 μm or more and 120 μm or less.

[0236] The embodiments of the present disclosure have been described above, but the technical scope of the present disclosure is not limited to the technical scope described in the above embodiments. Various changes or improvements can also be made to the above embodiments, and as can be seen from the description of the claims, the embodiments to which such changes or improvements are made can also be included in the technical scope of the present disclosure.

[0237] Reference Numeral Explanation

[0238] 1 Nitride semiconductor light-emitting element

[0239] 10 Substrate

[0240] 20 Nitride semiconductor laminate

[0241] 21 First n-type semiconductor layer

[0242] 22 Light-emitting mesa structure portion

[0243] 221 Second n-type semiconductor layer

[0244] 222 First quantum well layer

[0245] 223 First p-type semiconductor layer

[0246] 23 Protection mesa structure portion

[0247] 231 Third n-type semiconductor layer

[0248] 232 Second quantum well layer

[0249] 233 Second p-type semiconductor layer

[0250] 30 First electrode

[0251] 31 First electrode region

[0252] 32 Second electrode region

[0253] 33 Third electrode region

[0254] 40 Second electrode

[0255] 50 Passivation layer

[0256] 51 First passivation coverage region

[0257] 52 Second passivation coverage region

[0258] 53 Third passivation coverage region

[0259] 60 Narrow space part

[0260] 61 First narrow space part

[0261] 62 Second narrow space part

[0262] 70 Pad electrode

[0263] 71 First pad electrode part

[0264] 72 Second pad electrode part

[0265] 73 Third pad electrode part

Claims

1. A nitride semiconductor light-emitting element, wherein, The nitride semiconductor light-emitting device includes: a substrate; a nitride semiconductor stacked portion having a first conductivity type semiconductor layer disposed on the substrate, a light-emitting mesa structure portion disposed on a part of the first conductivity type semiconductor layer, and a non-light-emitting protective mesa structure portion disposed on the first conductivity type semiconductor layer and spatially separated from the light-emitting mesa structure portion and configured to surround the light-emitting mesa structure portion; a first electrode disposed on another part of the first conductivity type semiconductor layer and having at least two electrode regions including a first electrode region disposed with a first interval from the protective mesa structure portion in a plan view and a second electrode region disposed with a second interval from the first electrode region; a passivation layer directly covering an edge portion of the protective mesa structure portion, outer edge portions of the plurality of electrode regions, and a surface of the first conductivity type semiconductor layer; and a first pad electrode disposed to cover at least a part of a surface of the passivation layer and at least a part of a surface of the plurality of electrode regions not covered by the passivation layer, and electrically connecting the plurality of electrode regions to each other.

2. The nitride semiconductor light-emitting device according to claim 1, wherein, The protective mesa structure portion is disposed at an outer edge portion of the substrate.

3. The nitride semiconductor light-emitting device according to claim 2, wherein, In a plan view, the first electrode region is disposed at two or more corners of the substrate with the first interval from the protective mesa structure portion.

4. The nitride semiconductor light-emitting device according to claim 2, wherein, In a plan view, the first electrode region is disposed at four corners of the substrate with the first interval from the protective mesa structure portion.

5. The nitride semiconductor light-emitting device according to claim 1, wherein, The light-emitting mesa structure portion and the protective mesa structure portion are disposed in a region other than a first narrow space portion formed with the first interval between the protective mesa structure portion and the first electrode region and a second narrow space portion formed with the second interval between the first electrode region and the second electrode region.

6. The nitride semiconductor light-emitting device according to claim 1, wherein, The passivation layer has a first passivation covering region covering the edge portion on the first electrode region side of the protective mesa structure portion.

7. The nitride semiconductor light-emitting device according to claim 6, wherein, The passivation layer is formed to overlap at least a part of a region in the first conductivity type semiconductor layer located between the protective mesa structure portion and the first electrode region and at least a part of a region in the first conductivity type semiconductor layer located between the first electrode region and the second electrode region in a plan view.

8. The nitride semiconductor light-emitting device according to claim 1, wherein, The passivation layer has a second passivation covering region covering an edge portion of the first electrode region, and a width of a region where an upper surface of the first electrode region is covered by the second passivation covering region is 0.5 μm or more and 15 μm or less.

9. The nitride semiconductor light-emitting device according to claim 8, wherein, The first pad electrode is disposed to cover a part of the second passivation covering region.

10. The nitride semiconductor light-emitting device according to any one of claims 1 to 9, wherein, The nitride semiconductor light-emitting device further includes a third pad electrode portion disposed to cover a region in the passivation layer covering the edge portion of the protective mesa structure portion and at least a part of a region of the protective mesa structure portion not covered by the passivation layer.

11. The nitride semiconductor light-emitting device according to claim 1, wherein, The first interval is 0.5 μm or more and 25 μm or less.

12. The nitride semiconductor light-emitting element according to claim 1, wherein, The second interval, which is the distance between the first electrode region and the second electrode region, is 0.5 μm or more and 140 μm or less.

13. The nitride semiconductor light-emitting device according to claim 1, wherein, In a plan view, the protective mesa structure portion is arranged so as to surround the light-emitting mesa structure portion.

14. The nitride semiconductor light-emitting device according to claim 1, wherein the substrate is rectangular in a plan view, the protective mesa structure portion is provided along the outer periphery of the substrate, a plurality of the light-emitting mesa structure portions are provided along the same direction as the direction in which one side of the protective mesa structure portion extends, the first electrode region is provided on the inner peripheral side of the corner portion of the protective mesa structure portion, the second electrode region is adjacent to the first electrode region and is provided so as to extend in one direction along the protective mesa structure portion and the light-emitting mesa structure portion.

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