Three-dimensional storage and calculation integrated circuit
By adopting the stacking design of the logic computing layer and the storage circuit layer in the three-dimensional memory and computing integrated circuit, combining the storage optimization and performance optimization storage layer, the challenges of the three-dimensional stacking chip in terms of storage capacity and energy consumption are solved, and efficient data storage and computing integration is achieved.
Patent Information
- Application Number
- CN202510503156.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-21
- Publication Date
- 2025-08-01
AI Technical Summary
How to improve the storage capacity of three-dimensional stacking chips and reduce system energy consumption while reducing system area, solves the difficulty of designing and manufacturing of 3D stacking technology in high-performance computing and mobile devices.
The logical computing layer and storage circuit layer with stacked settings include storage optimization and performance optimization storage layers, realizing integrated storage and computing design, and optimizing data transmission and energy consumption through the logical computing unit interaction with different types of storage layers.
It increases storage capacity, improves data storage operation speed, reduces communication costs and energy consumption, and improves system energy efficiency ratio.
Smart Images
Figure CN120407465A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of integrated circuit technology, and more particularly, to a three-dimensional memory and computing integrated circuit. Background Art
[0002] Three-dimensional (3D) stacked chips are a technology that vertically stacks multiple chip layers and interconnects them through Through-Silicon Vias (TSVs). Compared with traditional two-dimensional planar designs, 3D stacking can significantly improve chip performance, reduce power consumption, and shrink the size, offering the advantages of high-density integration, short interconnects, and heterogeneous integration.
[0003] However, due to process limitations, how to optimize issues such as the system area, storage capacity, and system power consumption of 3D stacked chips has been an ongoing pursuit in the industry. Summary of the Invention
[0004] Embodiments of the present disclosure at least provide a three-dimensional memory and computing integrated circuit, which can increase the storage capacity while improving the storage operation speed of data. In addition, it can also reduce communication costs and improve the system energy efficiency ratio.
[0005] Embodiments of the present disclosure provide a three-dimensional memory and computing integrated circuit, including:
[0006] A logic computing layer and a storage circuit layer stacked;
[0007] The storage circuit layer includes a first type of storage layer and a second type of storage layer; the first type of storage layer is provided with a first input / output interface, and the second type of storage layer is provided with a second input / output interface; the first type of storage layer refers to a storage-optimized storage layer, and the second type of storage layer refers to a performance-optimized storage layer;
[0008] The logic computing layer includes a logic computing unit and a control interface connected to the logic computing unit; the control interface is respectively connected to the first input / output interface and the second input / output interface;
[0009] The logic computing unit obtains stored data from the first type of storage layer and the second type of storage layer respectively through the control interface for calculation, and outputs corresponding calculation results.
[0010] In an optional implementation manner, the first type of storage layer and the second type of storage layer are stacked and at least partially overlapped.
[0011] In an optional implementation manner, the first type of storage layer and the second type of storage layer are arranged side by side in the same plane.
[0012] In an alternative embodiment, the number of layers of the first type of storage layer is at least one and includes a dynamic random access storage layer, and the number of layers of the second type of storage layer is at least one and includes a static random access storage layer.
[0013] In an alternative embodiment, the number of control interfaces is two, where the position of one control interface in the stacking direction corresponds to that of the first input / output interface, and the position of the other control interface in the stacking direction corresponds to that of the second input / output interface.
[0014] In an alternative embodiment, the two control interfaces are respectively located on opposite sides of the logic computing unit.
[0015] In an alternative embodiment, the logic computing unit is further configured to directly output the stored data obtained from the storage circuit layer.
[0016] In an alternative embodiment, the logic computing layer is fabricated using a first manufacturing process, and the storage circuit layer is fabricated using a second manufacturing process, and the first manufacturing process is superior to the second manufacturing process.
[0017] In an alternative embodiment, the three-dimensional memory-computation integrated circuit is used for model training, the first type of storage layer is used to store training initial data, and the second type of storage layer is used to store intermediate data generated during the intermediate process of training.
[0018] In an alternative embodiment, the logic computing layer, the first type of storage layer, and the second type of storage layer are chips; or, the logic computing layer, the first type of storage layer, and the second type of storage layer are bare die.
[0019] The three-dimensional memory-computation integrated circuit provided by the embodiments of the present disclosure, which adopts a stacked logic computing layer and a storage circuit layer, can realize an integrated design of storage and computing, thereby reducing the overall area. Further, since the storage circuit layer includes two types of storage layers, namely a storage-optimized type and a performance-optimized type, in this way, both the storage capacity can be increased and the storage operation speed of data can be improved, which is beneficial to improving the circuit performance. In addition, the communication cost can be reduced, and further the energy consumption caused by transmission can be reduced, thereby being beneficial to improving the energy efficiency ratio of the circuit.
[0020] To make the above objects, features, and advantages of the present disclosure more obvious and understandable, the following specific embodiments are given, and in conjunction with the accompanying drawings, the detailed description is as follows. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the accompanying drawings required for the embodiments will be briefly introduced below. The accompanying drawings herein are incorporated into the specification and form a part of this specification. These accompanying drawings show the embodiments that conform to the present disclosure and are used together with the specification to illustrate the technical solutions of the present disclosure. It should be understood that the following accompanying drawings only show some embodiments of the present disclosure and should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related accompanying drawings can also be obtained based on these accompanying drawings.
[0022] Figure 1 Fig. 4 shows a three-dimensional memory-computation integrated circuit three-dimensional schematic diagram provided by an embodiment of the present disclosure;
[0023] Figure 2 Fig. 8 shows a cross-sectional view of a three-dimensional memory-computation integrated circuit provided by an embodiment of the present disclosure;
[0024] Figure 3 Fig. 12 shows a cross-sectional view of another three-dimensional memory-computation integrated circuit provided by an embodiment of the present disclosure;
[0025] Figure 4 Fig. 16 shows a cross-sectional view of another three-dimensional memory-computation integrated circuit provided by an embodiment of the present disclosure. Detailed implementation manners
[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some embodiments of the present disclosure, rather than all the embodiments. Usually, the components of the embodiments of the present disclosure described and shown in the accompanying drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed present disclosure, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present disclosure.
[0027] It should be noted that: similar reference numerals and letters denote similar items in the following accompanying drawings. Therefore, once an item is defined in one accompanying drawing, it does not need to be further defined and explained in subsequent accompanying drawings.
[0028] As used herein, the term "and / or" is merely used to describe an associated relationship, indicating that there can be three relationships. For example, A and / or B can represent three cases: A exists alone, both A and B exist simultaneously, and B exists alone. In addition, the term "at least one" as used herein means any one of a plurality or any combination of at least two of a plurality. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set composed of A, B, and C.
[0029] In addition, the terms "first", "second", etc. in the description, claims, and the above-mentioned drawings of the embodiments of the present disclosure are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein.
[0030] Due to advantages such as high-density integration, short interconnections, and heterogeneous integration, 3D stacked chips have been applied in the fields of high-performance computing, mobile devices, and the Internet of Things. However, through research, it has been found that although 3D stacking technology can reduce the system area and improve performance, it is restricted by process limitations, resulting in increased design and manufacturing difficulties. Therefore, how to improve the storage capacity of the system and reduce the system power consumption on the premise of reducing the system area is an urgent problem to be solved in the industry.
[0031] Based on the above research, the embodiments of the present disclosure provide a three-dimensional memory and computing integrated circuit, which includes a logic computing layer and a storage circuit layer stacked. By adopting the stacked logic computing layer and storage circuit layer, an integrated design of storage and computing can be realized, thereby reducing the overall area. Further, the storage circuit layer includes two types of storage layers, namely, a storage optimization type and a performance optimization type. In this way, both the storage capacity can be increased and the storage operation speed of data can be improved, which is beneficial to improving the circuit performance. In addition, the communication cost can also be reduced, thereby reducing the power consumption caused by transmission, which is beneficial to improving the energy efficiency ratio of the circuit.
[0032] All the defects existing in the above solutions are the results obtained by the inventors through practice and careful research. Therefore, the process of discovering the above problems and the solutions proposed by the present disclosure for the above problems in the following text should be the contributions made by the inventors to the present disclosure during the process of the present disclosure.
[0033] The three-dimensional memory and computing integrated circuit provided by the present disclosure will be introduced in detail below with reference to the accompanying drawings.
[0034] See Figure 1 As shown, it is a three-dimensional structure schematic diagram of a three-dimensional memory and computing integrated circuit provided by the embodiments of the present disclosure. As Figure 1As shown, the three-dimensional computing-in-memory circuit 100 includes a logic computing layer 10 and a memory circuit layer 20 arranged in a stacked manner. The memory circuit layer 20 includes a first-type memory layer 21 and a second-type memory layer 22. Among them, the first-type memory layer 21 is provided with a first input / output interface 201, and the second-type memory layer 22 is provided with a second input / output interface 202. The first-type memory layer 21 refers to a memory-optimized memory layer, and the second-type memory layer 22 refers to a performance-optimized memory layer.
[0035] The logic computing layer 10 includes a logic computing unit 11 and a control interface 12 connected to the logic computing unit 11; the control interface 12 is respectively connected to the first input / output interface 201 and the second input / output interface 202. The logic computing unit 11 obtains stored data from the first-type memory layer 21 and the second-type memory layer 22 respectively through the control interface 12 for calculation, and outputs corresponding calculation results.
[0036] Here, the first input / output interface 201, the second input / output interface 202 and the control interface 12 can be communicatively connected through contact vias, and the contact vias are, for example, through-silicon vias (TSV). Since the logic computing unit 11 and the control interface 12 are in the same layer, the specific connection manner is not limited as long as data transmission can be achieved.
[0037] It can be understood that the number of layers of the first-type memory layer 21 and the second-type memory layer 22 can also be one layer or multiple layers, which can be specifically set according to actual needs, and the present disclosure does not make specific limitations.
[0038] It should be noted that when the number of layers of the first-type memory layer 21 is multiple layers, these multiple layers can share a first input / output interface 201. In specific implementation, the "layer selection signal" can be used to select which memory layer to connect to according to specific needs, so as to realize data transmission. Similarly, the processing method when the number of layers of the second-type memory layer 22 is multiple layers is similar and will not be elaborated here.
[0039] Specifically, the first-type memory layer 21 represents a memory-optimized memory layer, and this memory-optimized memory layer refers to a memory layer with a relatively high storage density (such as greater than a preset threshold), which can store a large amount of massive data and commands required at the initial stage of calculation.
[0040] Exemplarily, the first type of storage layer 21 includes, but is not limited to, DRAM (Dynamic Random Access Memory), Flash (Flash memory), RRAM (Resistive Random Access Memory), etc., as long as it is a storage-intensive memory.
[0041] The second type of storage layer 22 represents a performance-optimized storage layer, which refers to a storage layer with a running speed greater than a preset speed, and / or a throughput greater than a preset throughput, and / or a storage layer that can be repeatedly erased. For example, this performance-optimized storage layer has characteristics such as fast running speed, high throughput, and can be repeatedly erased and written, and can be used to store intermediate data that needs to change in real time and has a relatively high computational load.
[0042] Exemplarily, the second type of storage layer 22 includes, but is not limited to, SRAM (Static Random-Access Memory), MRAM (Magnetoresistive Random Access Memory), etc.
[0043] Therefore, in an optional embodiment, the number of layers of the first type of storage layer 21 is at least one layer and at least includes a dynamic random storage layer, and the number of layers of the second type of storage layer 22 is at least one layer and at least includes a static random storage layer.
[0044] Of course, in other embodiments, when the number of layers of the first type of storage layer 21 is multiple, the first type of storage layer 21 may include one or more storage-optimized storage layers. For example, the first type of storage layer 21 may include DRAM and RRAM at the same time. Similarly, when the number of layers of the second type of storage layer 22 is multiple, the second type of storage layer 22 may include one or more performance-optimized storage layers.
[0045] When the number of layers of the first type of storage layer 21 is multiple and they are of the same type of storage layer, for example, when each layer in the first type of storage layer 21 is DRAM or RRAM, it can ensure the consistency of the first type of storage layer, which helps to improve the reliability and stability of the three-dimensional computing-in-memory integrated circuit 100 and reduce failures caused by compatibility issues between different types of storage layers. In addition, the same type of storage layer can adopt the same manufacturing process and production equipment, reducing the additional cost caused by producing different types of storage layers. Similarly, the second type of storage layer 22 is similar.
[0046] Exemplarily, the three-dimensional memory-computation integrated circuit 100 can be applied to the field of artificial intelligence. For example, the three-dimensional memory-computation integrated circuit 100 can be used for model training. Specifically, the first type of storage layer 21 can be used to store training initial data (such as weights, eigenvalues, commands, etc.), and the second type of storage layer 22 can be used to store intermediate data generated during the intermediate process of model training.
[0047] As a specific implementation, the content targeted by the second type of storage layer 22 can be convolution multiplication. This convolution multiplication requires performing matrix multiplication on the input and stored data to obtain an operation result. The operation result is processed and then matrix multiplication is performed again with the stored data, and this process is repeated. The intermediate operation result, as well as the processing before performing multiplication on the operation result again, can both be intermediate data.
[0048] The logic computing layer 10 can be used to execute computing functions based on algorithm instructions. The weights and eigenvalues obtained from its preliminary calculation come from the first type of storage layer 21, and the data for subsequent calculations can be completed through the second type of storage layer 22.
[0049] It should be understood that, as the storage layer for intermediate data, the first type of storage layer 21 sends the initial data to the logic computing layer 10, and then through the computing process of the logic computing layer 10. In this way, a large amount of data transfer only occurs during the interaction process between the first type of storage layer 21 and the logic computing layer 10. The amount of data transmitted from the logic computing layer 10 will be much less than the initial data of the first type of storage layer 21. In addition, adding the second type of storage layer 22 can solve the problem of intermediate data in computing, enabling the logic computing layer 10 to implement a complete algorithm function and output the most concise data result.
[0050] See Figure 2 and Figure 3 As shown, in an alternative embodiment, the first type of storage layer 21 and the second type of storage layer 22 are stacked and at least partially overlapped. Among them, when stacking, the first type of storage layer 21 can be closer to the logic computing layer 10 (as shown in Figure 3 ), or the second type of storage layer 22 can be closer to the logic computing layer 10 (as shown in Figure 2 ).
[0051] Optionally, the first type of storage layer 21 and the second type of storage layer 22 can also be located on opposite sides of the logic computing layer 10, that is, the first type of storage layer 21 and the second type of storage layer 22 are located on different sides of the logic computing layer 10.
[0052] In addition, as shown in Figure 2As shown, the first - type storage layer 21 and the second - type storage layer 22 can mostly overlap or completely overlap, such as Figure 3 As shown, the first - type storage layer 21 and the second - type storage layer 22 can also overlap partially, which can be specifically set according to actual requirements.
[0053] In the above - mentioned implementation, since the first - type storage layer 21 is a storage - optimized storage layer, it can thus increase the on - chip storage capacity at most. Moreover, the first - type storage layer 21 and the second - type storage layer 22 are arranged in layers, and will not be affected by the processes of the second - type storage layer 22 and the logic - calculation layer 10. Therefore, it is beneficial to reduce the manufacturing difficulty and improve the manufacturing efficiency.
[0054] Exemplarily, the logic - calculation layer 10 is fabricated using a first manufacturing process, and the storage - circuit layer 20 can be fabricated using a second manufacturing process, and the first manufacturing process (such as 7nm, 5nm processes) is superior to the second manufacturing process. In this way, the logic - calculation layer 10 will not be restricted by the process of the storage - circuit layer 20 and can use advanced process technologies (such as 7nm, 5nm processes), while the storage - circuit layer 20 uses a relatively lower process to ensure its reliability.
[0055] See Figure 4 As shown, in some other embodiments, the first - type storage layer 21 and the second - type storage layer 22 can be arranged side - by - side in the same plane. In this way, while ensuring the performance of the storage - circuit layer 20 (storage optimization and performance optimization), the thickness of the storage - circuit layer 20 can be reduced.
[0056] Please refer to again Figure 1 , in an alternative embodiment, the number of the control interfaces 12 is two. One of the control interfaces 12 corresponds to the first input - output interface 201 in the stacking direction, and the other control interface 12 corresponds to the second input - output interface 202 in the stacking direction. In this way, not only can the circuit routing be simplified, but also the data transmission speed can be improved.
[0057] Optionally, the two control interfaces 12 are respectively located on opposite sides of the logic - calculation unit 11, which is thus beneficial to simplify the circuit layout and routing and reduce the circuit complexity.
[0058] In an alternative embodiment, the logic computing unit 11 is further configured to directly output the stored data obtained from the memory circuit layer 20. That is to say, after the control interface 12 obtains the data, it can also directly output the storage result through the bypass computing logic of the logic computing unit 11. At this time, the 3D memory-computation integrated circuit 100 can be used as an independent memory chip, which is conducive to improving the applicability of the 3D memory-computation integrated circuit 100.
[0059] It should be noted that in the embodiments of the present disclosure, the logic computing layer 10, the first type of memory layer 21, and the second type of memory layer 22 are dies. Of course, in other embodiments, the logic computing layer 10, the first type of memory layer 21, and the second type of memory layer 22 may also be chips, which are not specifically limited.
[0060] For the 3D memory-computation integrated circuit 100 provided by the present disclosure, by simultaneously using the first type of memory layer 21 optimized for storage and the second type of memory layer 22 optimized for performance, the communication requirements between systems can be reduced. The originally largest data transfer from off-chip DRAM to the on-chip system is restricted between the first type of memory layer 21 and the logic computing layer 10, and converted into an internal data transfer process within the system. The second type of memory layer 22 is used to provide secondary data processing services for the logic computing layer 10, so that the data finally transmitted from the system is also the final result of the entire algorithm, thereby reducing the energy consumption caused by data transfer between systems.
[0061] In addition, in the embodiments of the present disclosure, by simultaneously using the first type of memory layer 21 optimized for storage and the second type of memory layer 22 optimized for performance, the advantages of the high capacity of the first type of memory layer 21 and the fast operation speed of the second type of memory layer 22 can be utilized at the same time. Further, the logic computing layer 10 and the memory circuit layer 20 are stacked in layers. This not only effectively avoids the limitation of the logic computing layer 10 by the process of the memory circuit layer 20, but also ensures the reliability of the circuit and realizes an optimized solution for reducing the system area. On the other hand, it also greatly reduces the communication cost between systems, thereby reducing the energy consumption caused by data transfer and comprehensively improving the energy efficiency ratio and area efficiency ratio of the system.
[0062] In the description of the present disclosure, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation on the present disclosure.
[0063] In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of the present disclosure, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined.
[0064] In the present disclosure, unless otherwise clearly specified and defined, terms such as "mounted", "connected", "coupled", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal communication of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For those of ordinary skill in the art, the specific meanings of the above terms in the present disclosure may be understood according to specific circumstances.
[0065] In the present disclosure, unless otherwise clearly specified and defined, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature has a higher horizontal height than the second feature. The first feature being "under", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature has a lower horizontal height than the second feature.
[0066] It should be noted that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used herein are for illustrative purposes only and do not represent the only implementation.
[0067] The embodiments described above are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts shall fall within the scope of protection of the embodiments of the present disclosure.
[0068] In addition, the technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0069] Finally, it should be noted that the above-described embodiments are only specific implementations of the present disclosure, used to illustrate the technical solutions of the present disclosure, rather than limiting them. The scope of protection of the present disclosure is not limited thereto. Although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that any person skilled in the art within the technical scope disclosed by the present disclosure can still modify the technical solutions described in the foregoing embodiments or easily conceive of changes, or make equivalent replacements for some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should all be covered by the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope of protection of the claims described.
Claims
1. A three-dimensional memory and computing integrated circuit, characterized in that, Including: A logic computing layer and a storage circuit layer arranged in a stack; The storage circuit layer includes a first type of storage layer and a second type of storage layer; the first type of storage layer is provided with a first input / output interface, and the second type of storage layer is provided with a second input / output interface; the first type of storage layer refers to a storage-optimized storage layer, and the second type of storage layer refers to a performance-optimized storage layer; The logic computing layer includes a logic computing unit and a control interface connected to the logic computing unit; the control interface is respectively connected to the first input / output interface and the second input / output interface; The logic computing unit obtains storage data from the first type of storage layer and the second type of storage layer respectively through the control interface for calculation, and outputs corresponding calculation results.
2. The three-dimensional memory and computing integrated circuit according to claim 1, wherein The first type of storage layer and the second type of storage layer are arranged in a stack and at least partially overlap.
3. The three-dimensional memory and computing integrated circuit according to claim 1, wherein The first type of storage layer and the second type of storage layer are arranged side by side in the same plane.
4. The three-dimensional memory and computing integrated circuit according to claim 1, wherein The number of layers of the first type of storage layer is at least one and includes a dynamic random access storage layer, and the number of layers of the second type of storage layer is at least one and includes a static random access storage layer.
5. The three-dimensional memory and computing integrated circuit according to claim 1, wherein The number of control interfaces is two, one of the control interfaces corresponds to the first input / output interface in the stacking direction, and the other control interface corresponds to the second input / output interface in the stacking direction.
6. The three-dimensional memory and computing integrated circuit according to claim 5, wherein The two control interfaces are respectively located on opposite sides of the logic computing unit.
7. The three-dimensional memory and computing integrated circuit according to claim 1, wherein The logic computing unit is also used to directly output the storage data obtained from the storage circuit layer.
8. The three-dimensional memory and computing integrated circuit according to claim 1, characterized in that The logic computing layer is fabricated using a first manufacturing process, the storage circuit layer is fabricated using a second manufacturing process, and the first manufacturing process is superior to the second manufacturing process.
9. The three-dimensional memory and computing integrated circuit according to claim 1, wherein The three-dimensional memory-computation integrated circuit is used for model training, the first type of storage layer is used to store training initial data, and the second type of storage layer is used to store intermediate data generated during the training intermediate process.
10. The three-dimensional memory and computing integrated circuit according to any one of claims 1-9, characterized in that, The logic computing layer, the first type of storage layer, and the second type of storage layer are chips; or, the logic computing layer, the first type of storage layer, and the second type of storage layer are bare dies.