A single-ended to differential amplifier with high power supply rejection ratio

Abstract

The present invention belongs to the field of analog integrated circuit technology, and particularly relates to a single-ended to differential amplifier with a high power supply rejection ratio. The amplifier comprises a first-stage inverting amplifier, a second-stage inverting amplifier, and a bandgap reference (BG); a current mirror circuit, the input of which is connected to the output of the bandgap reference (BG); a buffer (BUF1), the input of which is connected to the output of the bandgap reference (BG), and the output of which is connected to the source of a PMOS transistor (PM1); and a delay unit (delay), the input of which is connected to the input of the bandgap reference (BG) and connected to an enable signal (EN), and the output of which is connected to the gate of the PMOS transistor (PM1). The present invention improves the ability to suppress power supply ripple or interference, resulting in a single-ended to differential amplifier circuit with a high power supply rejection ratio.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to a single-ended to differential amplifier with a high power supply rejection ratio. Background Art

[0002] In the field of audio power amplifier chips, in order to ensure the quality of the output audio signal, the audio amplifier is usually required to have a high power supply rejection ratio and anti-interference ability. Taking Class D amplifier as an example, Figure 1 In the fully differential audio power amplifier circuit shown, the input stage A1 is used for the first-stage amplification of the differential signal. The amplified differential signal is subjected to noise shaping and PWM modulation by the intermediate stage A2, and then passes through the driver stage A3 to drive the speaker. Figure 2 In the single-ended input audio power amplifier circuit shown, the input stage A1 converts the single-ended signal into a differential signal and performs a first-stage amplification. The amplified differential signal undergoes noise shaping and PWM modulation by the intermediate stage A2, and then is output by the driver stage A3 to drive the speaker.

[0003] Fully differential audio power amplifiers offer high power supply rejection ratios and interference immunity, making them popular in professional amplifiers. However, their interfaces are relatively complex and their cost is high. Most consumer audio equipment outputs signals in a single-ended format, making single-ended input power amplifiers directly compatible, reducing circuit complexity and cost.

[0004] In the single-ended input audio power amplifier circuit, the traditional single-ended to differential amplifier has a low PSRR. When used as the audio power amplifier input stage, it seriously reduces the single-ended input audio power amplifier's ability to suppress power supply ripple and interference. Figure 3 The figure shows a conventional single-ended-to-differential amplifier circuit, comprising a first-stage inverting amplifier 100, a second-stage inverting amplifier 101, and a bandgap reference BG. The first-stage inverting amplifier 100 includes an operational amplifier OP1, feedback resistors R1 and R2, a signal input terminal IN, a reference voltage terminal VREF, and a signal output terminal OUTN. The second-stage inverting amplifier 101 includes an operational amplifier OP2, feedback resistors R3 and R4, a signal input terminal OUTN, a reference voltage terminal VREF, and a signal output terminal OUTP. The bandgap reference BG receives an enable signal EN and outputs a reference voltage signal VREF. Figure 3 The amplification factor of the first stage inverting amplifier 100 is -R2 / R1, and the amplification factor of the second stage inverting amplifier 101 is -R4 / R3. Ideally, the bandgap reference BG provides a stable reference voltage VREF.

[0005] When the input signal of the single-ended to differential amplifier circuit is VIN, after being amplified by the first-stage inverting amplifier 100, the output signal OUTN is: After OUTN is amplified by the second-stage inverting amplifier 101, the output signal OUTP is: Usually, the feedback resistor R3=R4, so the differential output signal OUT of the single-ended to differential amplifier circuit is: In the above traditional circuit, once an interference signal appears on VREF, the interference signal will be amplified and superimposed on the output signal. The analysis is as follows:

[0006] When there is ripple or interference on the power line, interference signals appear on the output reference voltage VREF of the bandgap reference. This introduces a ripple signal vripple into the positive input VREF of the first-stage inverting amplifier 100 and the second-stage inverting amplifier 101. The ripple signal vripple is amplified by the first-stage inverting amplifier 100 and superimposed on the output OUTN, resulting in a ripple signal vripple_outn: After being amplified by the second-stage inverting amplifier 101, the ripple signal vripple_outp superimposed on the output OUTP is: ; Let the feedback resistor R3 = R4, so the differential output ripple signal vripple_vout of the above traditional single-ended to differential amplifier circuit is: In the differential output signal of the above-mentioned traditional single-ended to differential amplifier circuit, in addition to the amplified signal of the input signal VIN, the amplified signal of the interference ripple signal vripple on the reference voltage is also superimposed. Figure 3 The traditional single-ended to differential amplifier circuit described above has no suppression effect on the interference on the reference voltage and has weak suppression capability for circuit power supply ripple and interference.

[0007] Therefore, in traditional single-ended-to-differential amplifiers, the positive input reference voltage is provided by a bandgap reference. If the bandgap reference voltage fluctuates due to power supply ripple or other interference, the fluctuation will be directly amplified by the amplifier and superimposed on the output signal. If a traditional single-ended-to-differential amplifier is used in the input stage of a single-ended audio amplifier, it will seriously affect the performance of the audio amplifier. Summary of the Invention

[0008] The purpose of the present invention is to provide a single-ended to differential amplifier with a high power supply rejection ratio. The present invention is used in the input stage of a single-ended input audio power amplifier chip, in order to solve the problem that traditional single-ended input audio power amplifiers have weak power supply ripple and interference suppression capabilities.

[0009] To solve the above technical problems, the present invention provides a single-ended to differential amplifier with a high power supply rejection ratio, comprising a first-stage inverting amplifier, a second-stage inverting amplifier, and a bandgap reference BG; and further comprising:

[0010] A current mirror circuit, wherein the input end of the current mirror circuit is connected to the output end of the bandgap reference BG, and the output end of the current mirror circuit is connected to the drain of the PMOS transistor PM1 and the non-inverting input ends of the first-stage inverting amplifier and the second-stage inverting amplifier. The current mirror circuit includes: PMOS transistors PM2-PM3, NMOS transistors NM1-NM2, and a current source IB. One end of the current source IB is connected to the power supply VCC, and the other end is connected to the drain of the NMOS transistor NM1 and the gates of the NMOS transistors NM1-NM2. The sources of the NMOS transistors NM1-NM2 are grounded GND. The drain of the NMOS transistor NM2 is connected to the drain of the PMOS transistor PM2 and the gates of the PMOS transistors PM2-PM3. The sources of the PMOS transistors PM2-PM3 serve as the input end of the current mirror circuit. The drain of the PMOS transistor PM3 serves as the output end of the current mirror circuit.

[0011] a buffer BUF1, wherein the input end of the buffer BUF1 is connected to the output end of the bandgap reference BG, and the output end of the buffer BUF1 is connected to the source of the PMOS transistor PM1;

[0012] The delay unit delay has an input end connected to the input end of the bandgap reference BG and connected to the enable signal EN, and an output end of the delay unit delay is connected to the gate of the PMOS transistor PM1.

[0013] Preferably, an RC filter circuit is further included, wherein the RC filter circuit is connected between the output end of the bandgap reference BG and the input end of the current mirror circuit, and the output end of the bandgap reference BG outputs a reference voltage VREF.

[0014] Preferably, the RC filter circuit includes: a resistor R5 and a capacitor C2; one end of the resistor R5 is connected to the output end of the bandgap reference BG, the other end of the resistor R5 is connected to one end of the capacitor C2 and the source of the PMOS tubes PM2~PM3, and the other end of the capacitor C2 is grounded GND.

[0015] Preferably, a capacitor C1 is further included, one end of the capacitor C1 is connected to the drains of the PMOS transistor PM1 and the PMOS transistor PM3 to generate a reference voltage VREF1, and the other end of the capacitor C1 is grounded GND.

[0016] Preferably, the first-stage inverting amplifier includes: an operational amplifier OP1 and feedback resistors R1~R2; the signal input terminal IN is connected to one end of the feedback resistor R1, the inverting input terminal of the operational amplifier OP1 is connected to the other end of the feedback resistor R1 and one end of the feedback resistor R2, the non-inverting input terminal of the operational amplifier OP1 is connected to the reference voltage VREF1, and the output terminal of the operational amplifier OP1 is connected to the other end of the feedback resistor R2 and serves as the signal output terminal OUTN.

[0017] Preferably, the second-stage inverting amplifier includes: an operational amplifier OP2 and feedback resistors R3~R4; the signal output terminal OUTN is connected to one end of the feedback resistor R3, the inverting input terminal of the operational amplifier OP2 is connected to the other end of the feedback resistor R3 and one end of the feedback resistor R4, the non-inverting input terminal of the operational amplifier OP2 is connected to the reference voltage VREF1, and the output terminal of the operational amplifier OP2 is connected to the other end of the feedback resistor R4 and serves as the signal output terminal OUTP.

[0018] Preferably, the buffer BUF1 includes: PMOS transistors PM4 to PM6, NMOS transistors NM3 to NM6, a resistor R6, and a capacitor C3; wherein the sources of the PMOS transistors PM4 to PM6 are connected to the power supply VCC, the gate and drain of the PMOS transistor PM4 are connected to the gate of the PMOS transistor PM5 and the drain of the NMOS transistor NM3; the drain of the PMOS transistor PM5 is connected to the gate of the PMOS transistor PM6, the drain of the NMOS transistor NM4, and one end of the resistor R6, and the other end of the resistor R6 is connected to the gate of the PMOS transistor PM6. One end of the capacitor C3 is connected, and the other end of the capacitor C3 is connected to the drain of the PMOS transistor PM6, the drain of the NMOS transistor NM6, and the gate of the NMOS transistor NM3, and serves as the output end BUF1_OUT; the input end BUF1_IN is connected to the gate of the NMOS transistor NM4, the sources of the NMOS transistors NM3 and NM4 are connected to the drain of the NMOS transistor NM5, the bias voltage VB0 is connected to the gates of the NMOS transistors NM5 and NM6, and the sources of the NMOS transistors NM5 and NM6 are connected to the ground GND.

[0019] Preferably, the delay unit delay comprises: D flip-flops DFF1 to DFF3 and an AND gate AND1; wherein the enable input terminal EN is connected to the reset port Reset of the D flip-flops DFF1 to DFF3, and the input terminal D1 of the D flip-flop DFF1 is connected to the inverting output terminal The input terminal D2 of the D flip-flop DFF2 is connected to the inverting output terminal The input terminal D3 of the D flip-flop DFF3 is connected to the inverting output terminal The AND gate AND1 is connected to one of its input terminals, the other input terminal of the AND gate AND1 is connected to the clock signal CLK, the output terminal of the AND gate AND1 is connected to the clock signal input terminal Clk1 of the D flip-flop DFF1, the non-inverting output terminal Q1 of the D flip-flop DFF1 is connected to the clock signal input terminal Clk2 of the D flip-flop DFF2, the non-inverting output terminal Q2 of the D flip-flop DFF2 is connected to the clock signal input terminal Clk3 of the D flip-flop DFF3, and the delay output terminal delay_out is connected to the non-inverting output terminal Q3 of the D flip-flop DFF3.

[0020] Preferably, the NMOS transistors NM1 - NM2 form a group of current mirrors, and the PMOS transistors PM2 - PM3 form another group of current mirrors.

[0021] Preferably, the resistor R5 and the capacitor C2, as well as the PMOS transistor PM3 and the capacitor C1 form a second-order low-pass filter.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] The high-PSRR single-ended-to-differential amplifier circuit of the present invention utilizes a current mirror circuit and controls a delay switch to maintain the reference voltage even after the positive input of the operational amplifier is disconnected from the reference voltage source. This circuit provides a stable reference voltage for the positive input of the operational amplifier while isolating the positive input from the reference voltage source, thereby isolating the impact of interference from the reference voltage source on the operational amplifier. This improves the ability to suppress power supply ripple or interference, resulting in a high power supply rejection ratio (PSRR) for the single-ended-to-differential amplifier circuit. Furthermore, the present invention is applicable not only to the single-ended input audio power amplifier illustrated in the example, but also to all single-ended-to-differential amplifier circuits that meet the requirements of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is a circuit diagram of a fully differential audio power amplifier in the prior art.

[0025] Figure 2 This is a circuit diagram of a single-ended input audio power amplifier in the prior art.

[0026] Figure 3 It is a traditional single-ended to differential amplifier circuit in the prior art.

[0027] Figure 4 This is a schematic diagram of a single-ended to differential amplifier circuit provided by the present invention.

[0028] Figure 5 It is a specific circuit principle diagram of a buffer BUF1 according to one embodiment of the present invention.

[0029] Figure 6 This is a schematic diagram of a delay circuit of a delay unit according to one embodiment of the present invention.

[0030] Figure 7 This is a delay signal timing diagram of a delay unit according to one embodiment of the present invention.

[0031] Figure 8 This is a diagram of the internal signals and circuit operating states of the single-ended to differential amplifier provided by the present invention. DETAILED DESCRIPTION

[0032] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are only used to facilitate and clearly illustrate the embodiments of the present invention.

[0033] like Figure 4 The figure shows a schematic diagram of a single-ended to differential amplifier circuit of the present invention, which includes a first-stage inverting amplifier 200, a second-stage inverting amplifier 201, a current mirror circuit 202, a bandgap reference BG, a buffer BUF1, a PMOS transistor PM1, a delay unit delay, a resistor R5, and capacitors C1 and C2.

[0034] The first-stage inverting amplifier 200 includes an operational amplifier OP1, feedback resistors R1 and R2, a signal input terminal IN, a reference voltage terminal VREF1, and a signal output terminal OUTN. In the first-stage inverting amplifier 200, the signal input terminal IN is connected to one end of the feedback resistor R1, the negative input terminal of the operational amplifier OP1 is connected to the other end of the feedback resistor R1 and one end of the feedback resistor R2, the positive input terminal VREF1 of the operational amplifier OP1 is connected to one end of the capacitor C1, the drain of the PMOS transistor PM1, the drain of PM3, and the positive input terminal of the operational amplifier OP2, and the output terminal OUTN of the operational amplifier OP1 is connected to the other end of the feedback resistor R2.

[0035] The second-stage inverting amplifier 201 includes an operational amplifier OP2, feedback resistors R3 and R4, a signal output terminal OUTN, and a signal output terminal OUPN. In the second-stage inverting amplifier 201, the signal output terminal OUTN is connected to one end of the feedback resistor R3, the negative input terminal of the operational amplifier OP2 is connected to the other end of the feedback resistor R3 and one end of the feedback resistor R4, the positive input terminal VREF1 of the operational amplifier OP2 is connected to one end of the capacitor C1, the drain of the PMOS transistor PM1, the drain of PM3, and the positive input terminal of the operational amplifier OP1, and the output terminal OUTP of the operational amplifier OP2 is connected to the other end of the feedback resistor R4.

[0036] The current mirror circuit 202 includes PMOS transistors PM2 and PM3, NMOS transistors NM1 and NM2, and a current source IB. In the current mirror circuit 202, one end of the current source IB is connected to the power supply VCC, and the other end is connected to the drain of the NMOS transistor NM1 and the gates of NM1 and NM2. The sources of the NMOS transistors NM1 and NM2 are connected to ground GND. The drain of the NMOS transistor NM2 is connected to the drain of the PMOS transistor PM2 and the gates of PM2 and PM3. The sources of the PMOS transistors PM2 and PM3 are connected to resistor R5 and one end of capacitor C2. The drain of the PMOS transistor PM3 is connected to one end of capacitor C1, the positive input terminals of operational amplifiers OP1 and OP2, and the drain of the PMOS transistor PM1. The NMOS transistors NM1 and NM2 form one current mirror group, and the PMOS transistors PM2 and PM3 form another current mirror group.

[0037] In the single-ended-to-differential amplifier circuit, an enable signal EN is connected to the input of a bandgap reference BG and the input of a delay unit (delay). The output of the bandgap reference BG, VREF, is connected to one end of a resistor R5 and the input of a buffer BUF1. The output of the buffer BUF1 is connected to the source of PM1, and the output of the delay unit (delay) is connected to the gate of PM1. The other ends of capacitors C1 and C2 are grounded.

[0038] like Figure 5 The embodiment of the present invention is shown as above Figure 4 The schematic diagram of the specific circuit structure of buffer BUF1 in FIG. Buffer BUF1 includes PMOS transistors PM4, PM5, and PM6; NMOS transistors NM3, NM4, NM5, and NM6; resistor R6; capacitor C3; bias voltage VB0; buffer input terminal BUF1_IN; and buffer output terminal BUF1_OUT. In buffer BUF1, the sources of PMOS transistors PM4, PM5, and PM6 are connected to the positive power supply VCC. The gate and drain of PMOS transistor PM4 are connected to the gate of PM5 and the drain of NMOS transistor NM3. The drain of PMOS transistor PM5 is connected to the gate of PM6, the drain of NMOS transistor NM4, and one end of resistor R6. The other end of resistor R6 is connected to one end of capacitor C3. Buffer output terminal BUF1_OUT is connected to the other end of capacitor C3, the drain of PM6, the drain of NM6, and the gate of NM3. Buffer input terminal BUF1_IN is connected to the gate of NM4. The sources of the NMOS transistors NM3 and NM4 are connected to the drain of NM5. The bias voltage VB0 is connected to the gates of the NMOS transistors NM5 and NM6. The sources of the NMOS transistors NM5 and NM6 are connected to the negative power supply GND.

[0039] like Figure 6 The embodiment of the present invention is shown as above Figure 4The specific circuit structure principle diagram of the delay unit delay, the delay unit delay includes D flip-flops DFF1, DFF2, DFF3, AND gate AND1, enable input terminal EN, clock signal CLK, and delay output terminal delay_out. In the delay unit delay, the enable input terminal EN is connected to the reset port Reset of the D flip-flops DFF1, DFF2, and DFF3. The delay output terminal delay_out is connected to the in-phase output terminal Q3 of the D flip-flop DFF3. The input terminal D1 of the D flip-flop DFF1 is connected to the inverting output terminal Q3 of the D flip-flop DFF3. The input terminal D2 of the D flip-flop DFF2 is connected to the inverting output terminal The input terminal D3 of the D flip-flop DFF3 is connected to the inverting output terminal , connected to one input of AND gate AND1. Clock signal CLK is connected to the other input of AND gate AND1. The output of AND gate AND1 is connected to clock signal input Clk1 of D flip-flop DFF1. The non-inverting output Q1 of D flip-flop DFF1 is connected to clock signal input Clk2 of D flip-flop DFF2. The non-inverting output Q2 of D flip-flop DFF2 is connected to clock signal input Clk3 of D flip-flop DFF3.

[0040] like Figure 7 The figure shows the signal timing diagram of the delay unit after the enable signal EN is powered on. The D flip-flops DFF1, DFF2, and DFF3 are triggered by the falling edge. When the enable signal EN is at a low level, the in-phase output terminals Q1, Q2, and Q3 of the D flip-flops DFF1, DFF2, and DFF3 are set to 0, and the in-phase output terminals Q1, Q2, and Q3 are set to 0. 、 、 Set to 1. When the enable signal EN is at a high level, the delay unit delay starts timing, and after the timing is completed, the delay unit delay output terminal delay_out outputs a high level.

[0041] above Figure 4 In the single-ended to differential amplifier of the embodiment of the present invention, the specific circuit structure of the buffer BUF1 and the delay unit delay is not limited to Figure 6 、 Figure 7 The circuit structure shown in the figure can also be replaced by other common buffer and delay unit circuit structures without affecting Figure 4 The function and use of the single-ended to differential amplifier of the present invention.

[0042] The present invention also includes the following working principle:

[0043] like Figure 8Figure 1 shows the internal signals and circuit operating states of the single-ended-to-differential amplifier of the present invention. In the high-PSRR single-ended-to-differential amplifier circuit, the enable signal EN is active when it is high. When the enable signal EN is low, the single-ended-to-differential amplifier circuit is inoperative; when the enable signal EN is high, the single-ended-to-differential amplifier circuit is operational.

[0044] After the enable signal EN passes through the delay unit delay, a delay signal EN_delay is generated to control the on and off of the PMOS tube PM1; when EN_delay is low, PM1 is turned on, and when EN_delay is high, PM1 is turned off. Therefore, after the circuit is powered on, the PM1 enable signal EN jumps from low to high, and PM1 is turned on first and then turned off. The on time is determined by the delay unit.

[0045] When the enable signal EN jumps from low to high, the bandgap reference BG begins operating and outputs the reference voltage VREF. At this point, PM1 is in the on state. The reference voltage VREF charges capacitor C1 through buffer BUF1, making the voltage VREF1 on capacitor C1 equal to the reference voltage VREF. Subsequently, after the high level of the enable signal EN is delayed by the delay unit, the EN_delay signal jumps from low to high, turning PM1 off. The voltage VREF1 maintains the same VREF value. The single-ended-to-differential amplifier circuit can then perform normal signal amplification.

[0046] The output reference voltage VERF of the bandgap reference BG, after passing through an RC filter circuit consisting of resistor R5 and capacitor C2, serves as the power supply for current mirror circuit 202. The drain of PMOS transistor PM3 in current mirror circuit 202 is connected to capacitor C1. When PMOS transistor PM1 is turned off, the weak current provided by current mirror circuit 202 maintains the voltage of capacitor C1 at reference voltage VREF.

[0047] Figure 4 The amplification factor of the first stage inverting amplifier 200 is -R2 / R1, and the amplification factor of the second stage inverting amplifier 201 is -R4 / R3. When the input signal of the single-ended to differential amplifier circuit is VIN, after amplification by the first stage inverting amplifier 200, the output signal OUTN is: ;

[0048] After OUTN is amplified by the second-stage inverting amplifier 201, the output signal OUTP is: ;

[0049] Usually, the feedback resistor R3=R4, so the differential output signal VOUT of the single-ended to differential amplifier circuit is: .

[0050] When ripple or interference on the power line causes interference signals to appear on the output reference voltage VREF of the bandgap reference, while the op amp is operating normally and amplifying the signal, PMOS transistor PM1 is turned off, and the voltage VREF1 on capacitor C1 maintains the reference voltage VREF. Therefore, the ripple and interference signals cannot be transmitted through buffer BUF1 to the positive input terminals of first-stage inverting amplifier 200 and second-stage inverting amplifier 201. On the other hand, the second-order low-pass filter formed by resistor R5 and capacitor C2, as well as PMOS transistor PM3 and capacitor C1, has a low cutoff frequency due to the large output impedance of PMOS transistor PM3. Therefore, the ripple and interference on reference voltage VREF, after passing through the second-order low-pass filter, cannot be transmitted to the positive input terminals of first-stage inverting amplifier 200 and second-stage inverting amplifier 201.

[0051] The single-ended to differential amplifier does not amplify the ripple and interference signal on the positive input reference voltage VREF1, and has a strong inhibitory effect on the power supply ripple and interference of the entire operational amplifier. The PSRR of the single-ended to differential amplifier is much higher than that of the traditional single-ended to differential amplifier.

[0052] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention. Any changes and modifications made by ordinary technicians in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A single-ended to differential amplifier with high power supply rejection ratio, comprising a first-stage inverting amplifier, a second-stage inverting amplifier and a bandgap reference BG; characterized in that: Also includes: A current mirror circuit, wherein the input end of the current mirror circuit is connected to the output end of the bandgap reference BG, and the output end of the current mirror circuit is connected to the drain of the PMOS transistor PM1 and the non-inverting input ends of the first-stage inverting amplifier and the second-stage inverting amplifier. The current mirror circuit includes: PMOS transistors PM2-PM3, NMOS transistors NM1-NM2, and a current source IB. One end of the current source IB is connected to the power supply VCC, and the other end is connected to the drain of the NMOS transistor NM1 and the gates of the NMOS transistors NM1-NM2. The sources of the NMOS transistors NM1-NM2 are grounded GND. The drain of the NMOS transistor NM2 is connected to the drain of the PMOS transistor PM2 and the gates of the PMOS transistors PM2-PM3. The sources of the PMOS transistors PM2-PM3 serve as the input end of the current mirror circuit. The drain of the PMOS transistor PM3 serves as the output end of the current mirror circuit. a buffer BUF1, wherein the input end of the buffer BUF1 is connected to the output end of the bandgap reference BG, and the output end of the buffer BUF1 is connected to the source of the PMOS transistor PM1; The delay unit delay has an input end connected to the input end of the bandgap reference BG and connected to the enable signal EN, and an output end of the delay unit delay is connected to the gate of the PMOS transistor PM1.

2. The single-ended to differential amplifier with high power supply rejection ratio according to claim 1, wherein: It also includes an RC filter circuit, which is connected between the output end of the bandgap reference BG and the input end of the current mirror circuit, and the output end of the bandgap reference BG outputs a reference voltage VREF.

3. The single-ended to differential amplifier with high power supply rejection ratio according to claim 2, wherein: The RC filter circuit includes: a resistor R5 and a capacitor C2; one end of the resistor R5 is connected to the output end of the bandgap reference BG, the other end of the resistor R5 is connected to one end of the capacitor C2 and the source of the PMOS transistors PM2~PM3, and the other end of the capacitor C2 is grounded GND.

4. The single-ended to differential amplifier with high power supply rejection ratio according to claim 1, wherein: The device further includes a capacitor C1 , one end of which is connected to the drains of the PMOS transistor PM1 and the PMOS transistor PM3 to generate a reference voltage VREF1 , and the other end of the capacitor C1 is grounded GND.

5. The single-ended to differential amplifier with high power supply rejection ratio according to claim 1, wherein: The first-stage inverting amplifier includes: an operational amplifier OP1 and feedback resistors R1~R2; the signal input terminal IN is connected to one end of the feedback resistor R1, the inverting input terminal of the operational amplifier OP1 is connected to the other end of the feedback resistor R1 and one end of the feedback resistor R2, the non-inverting input terminal of the operational amplifier OP1 is connected to the reference voltage VREF1, and the output terminal of the operational amplifier OP1 is connected to the other end of the feedback resistor R2 and serves as the signal output terminal OUTN.

6. The single-ended to differential amplifier with high power supply rejection ratio according to claim 5, wherein: The second-stage inverting amplifier includes: an operational amplifier OP2 and feedback resistors R3~R4; the signal output terminal OUTN is connected to one end of the feedback resistor R3, the inverting input terminal of the operational amplifier OP2 is connected to the other end of the feedback resistor R3 and one end of the feedback resistor R4, the non-inverting input terminal of the operational amplifier OP2 is connected to the reference voltage VREF1, and the output terminal of the operational amplifier OP2 is connected to the other end of the feedback resistor R4 and serves as the signal output terminal OUTP.

7. The single-ended to differential amplifier with high power supply rejection ratio according to claim 1, wherein: The buffer BUF1 includes: PMOS transistors PM4 to PM6, NMOS transistors NM3 to NM6, a resistor R6 and a capacitor C3; wherein the sources of the PMOS transistors PM4 to PM6 are connected to the power supply VCC, the gate and drain of the PMOS transistor PM4 are connected to the gate of the PMOS transistor PM5 and the drain of the NMOS transistor NM3; the drain of the PMOS transistor PM5 is connected to the gate of the PMOS transistor PM6, the drain of the NMOS transistor NM4 and one end of the resistor R6, and the other end of the resistor R6 is connected to the capacitor C 3, the other end of the capacitor C3 is connected to the drain of the PMOS transistor PM6, the drain of the NMOS transistor NM6 and the gate of the NMOS transistor NM3, and serves as the output terminal BUF1_OUT; the input terminal BUF1_IN is connected to the gate of the NMOS transistor NM4, the sources of the NMOS transistors NM3 and NM4 are connected to the drain of the NMOS transistor NM5, the bias voltage VB0 is connected to the gates of the NMOS transistors NM5 and NM6, and the sources of the NMOS transistors NM5 and NM6 are connected to the ground GND.

8. The single-ended to differential amplifier with high power supply rejection ratio according to claim 1, wherein: The delay unit delay includes: D flip-flops DFF1~DFF3 and AND gate AND1; wherein the enable input terminal EN is connected to the reset port Reset of the D flip-flops DFF1~DFF3, and the input terminal D1 of the D flip-flop DFF1 is connected to the inverting output terminal The input terminal D2 of the D flip-flop DFF2 is connected to the inverting output terminal The input terminal D3 of the D flip-flop DFF3 is connected to the inverting output terminal The AND gate AND1 is connected to one of its input terminals, the other input terminal of the AND gate AND1 is connected to the clock signal CLK, the output terminal of the AND gate AND1 is connected to the clock signal input terminal Clk1 of the D flip-flop DFF1, the non-inverting output terminal Q1 of the D flip-flop DFF1 is connected to the clock signal input terminal Clk2 of the D flip-flop DFF2, the non-inverting output terminal Q2 of the D flip-flop DFF2 is connected to the clock signal input terminal Clk3 of the D flip-flop DFF3, and the delay output terminal delay_out is connected to the non-inverting output terminal Q3 of the D flip-flop DFF3.

9. The single-ended to differential amplifier with high power supply rejection ratio according to claim 1, wherein: The NMOS transistors NM1 and NM2 form a group of current mirrors, and the PMOS transistors PM2 and PM3 form another group of current mirrors.

10. The single-ended to differential amplifier with high power supply rejection ratio according to claim 3, wherein: The resistor R5 and the capacitor C2, as well as the PMOS transistor PM3 and the capacitor C1 form a second-order low-pass filter.

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