PID (Proportion Integration Differentiation)-based low-frequency time code Costas ring and carrier synchronization method

Abstract

The invention discloses a PID-based low-frequency time code Costas ring and a carrier synchronization method, and relates to the technical field of signal processing of low-frequency time codes, the PID-based low-frequency time code Costas ring mainly comprises a Costas ring and at least one PID controller, and the carrier synchronization method mainly comprises the following steps: setting initial values of a proportional term, an integral term and a differential term of the PID controller; dynamically adjusting the proportional term according to the signal-to-noise ratio and the initial value of the proportional term; dynamically adjusting the integral item according to the integral item initial value; and dynamically adjusting the differential item according to the signal-to-noise ratio and the differential item initial value. By implementing the PID-based low-frequency time code Costas ring and the carrier synchronization method provided by the invention, the carrier synchronization speed, precision and robustness of the LFTC system can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processing of low-frequency time code, and more specifically, to a PID-based low-frequency time code Costas loop and carrier synchronization method. Background Art

[0002] The low-frequency time code time service system is one of the successful applications of the ground-based radio time service system. The user terminals of this system have the characteristics of being convenient to use, simple, and low in price, and are widely used among medium- and low-precision users, but it also limits the application among high-end users. To solve this problem, appropriate modulation and demodulation technologies or interference suppression methods must be adopted to improve the timing accuracy of low-frequency time code reception, and this technology is undoubtedly the direct sequence spread spectrum technology that has now been widely used in the GPS satellite navigation system.

[0003] The combined modulation scheme of low-frequency time code is as Figure 1 shown. Within each second, there is 600 ms of pure carrier. Using this period of time, we can add spread spectrum modulation. At the beginning of each second, first, amplitude shift keying modulation (ASK) of the time code data is performed. After the modulation is completed, the carrier amplitude will drop to 10% of the original amplitude. After 400 ms, pseudo-random code sequence phase shift keying modulation (PSK) is performed, and finally, the combined modulation signal is sent out by the transmitter. This modulation structure has the following advantages: maintaining the original pulse width amplitude modulation signal structure, avoiding the impact on the original transmission system and receiving terminal, meeting the requirements of the conditions, and making full use of the low-frequency carrier resources.

[0004] For the receiver of the low-frequency time code signal, when the receiver performs coherent demodulation on the modulated time code, it is necessary to recover the local carrier with the same frequency and phase as the modulation carrier at the sending end, and a phase-locked loop is commonly used to complete this task. In the low-frequency time code spread spectrum communication system, although suppressing carrier modulation (such as DSB-SC) can improve the power efficiency, since the carrier is deeply suppressed, it is necessary to recover the carrier component through nonlinear processing. In the prior art, the square loop introduces chip rate harmonic interference due to the self-multiplication of the spread spectrum code, and the narrowband filtering performance is insufficient under low signal-to-noise ratio, resulting in the deterioration of synchronization stability; although the traditional Costas loop avoids chip interference, its fixed bandwidth loop filter converges slowly in narrowband and low signal-to-noise ratio scenarios, has insufficient suppression of phase jitter caused by multipath effects and ionospheric disturbances, and there is a problem of phase error accumulation when the high-frequency VCO is frequency-divided to adapt to the low-frequency carrier. In view of the narrowband, low signal-to-noise ratio, and dynamic channel characteristics of the low-frequency time code system, there is an urgent need for a highly robust carrier synchronization scheme that takes into account anti-interference, fast convergence, and frequency division adaptation.

[0005] The above content is only used to assist in understanding the technical solution of the present invention, and does not represent an admission that the above content is the prior art. Summary of the Invention

[0006] The object of the present invention is to provide a PID-based low-frequency time code Costas loop and carrier synchronization method, which can improve the speed, accuracy and robustness of carrier synchronization in the LFTC system.

[0007] The present invention provides a PID-based low-frequency time code Costas loop. The PID-based low-frequency time code Costas loop includes a Costas loop and at least one PID controller, and the Costas loop and the at least one PID controller are electrically connected; the Costas loop includes a first voltage-controlled oscillator, a first multiplier, a first low-pass filter, a second voltage-controlled oscillator, a second multiplier, a second low-pass filter, a phase discriminator and a loop filter; the output end of the first voltage-controlled oscillator is connected to the first input end of the first multiplier, the output end of the first multiplier is connected to the input end of the first low-pass filter, the output end of the first low-pass filter is connected to the first input end of the phase discriminator, the output end of the phase discriminator is connected to the input end of the loop filter, and the output end of the loop filter is connected to the first input end of the first voltage-controlled oscillator; the output end of the second voltage-controlled oscillator is connected to the first input end of the second multiplier, the output end of the second multiplier is connected to the input end of the second low-pass filter, the output end of the second low-pass filter is connected to the second input end of the phase discriminator, and the output end of the loop filter is also connected to the first input end of the second voltage-controlled oscillator; the second input end of the first voltage-controlled oscillator is connected to the second input end of the second voltage-controlled oscillator and is used as a signal input end; the output end of the phase discriminator is used as a signal output end.

[0008] The present invention also provides a carrier synchronization method applied to the above-mentioned PID-based low-frequency time code Costas loop, including: setting the initial values of the proportional term, integral term and differential term of the PID controller; dynamically adjusting the proportional term according to the signal-to-noise ratio and the initial value of the proportional term; dynamically adjusting the integral term according to the initial value of the integral term; dynamically adjusting the differential term according to the signal-to-noise ratio and the initial value of the differential term.

[0009] Implementing the PID-based low-frequency time code Costas loop and carrier synchronization method provided by the present invention has the following beneficial effects:

[0010] The present invention embeds a PID controller module into the error adjustment link of the Costas loop. According to the real-time signal-to-noise ratio (SNR) of the low-frequency time-code spread-spectrum communication system and the error output e(t) of the phase discriminator, the magnitudes of the proportional, integral, and differential terms are dynamically and adaptively adjusted to adapt to the time-varying channel conditions (SNR fluctuations, burst phase jitter) of the low-frequency time-code spread-spectrum (LFTC) system, quickly cancel the error and maintain the loop stability, significantly shorten the phase discrimination time, and improve the carrier synchronization speed and anti-interference ability. In different SNR scenarios, the carrier synchronization time of the present invention is shortened, and the carrier synchronization speed and efficiency are significantly improved; through the SNR and real-time error e(t)-driven PID parameter adaptive mechanism, the present invention realizes the automatic increase of the proportional gain at low SNR, the suppression of the integral gain at large errors, the activation of the differential term at high SNR, suppresses burst phase jitter, and takes into account the high-robust carrier synchronization of anti-interference, fast convergence, and frequency division adaptation, improving the speed, accuracy, and robustness of carrier synchronization in the LFTC system. Description of the Drawings

[0011] The present invention will be further described below in conjunction with the drawings and embodiments. In the drawings:

[0012] Figure 1 is a schematic diagram of the low-frequency time-code combined modulation structure provided by the present invention;

[0013] Figure 3 is a schematic block diagram of the Costas loop principle provided by the present invention;

[0014] Figure 4 is a schematic block diagram of the structure of the second-order loop filter provided by the present invention;

[0015] Figure 2 is a control structure diagram of the PID controller provided by the present invention;

[0016] Figure 5 is a schematic diagram of the Costas loop model before optimization provided by the present invention;

[0017] Figure 6 is a schematic block diagram of the principle of the low-frequency time-code Costas loop based on PID provided by the present invention;

[0018] Figure 7 is a schematic block diagram of the principle of another implementation of the low-frequency time-code Costas loop based on PID provided by the present invention;

[0019] Figure 8 is a schematic diagram of the output of the phase discriminator under ideal channel conditions provided by the present invention;

[0020] Figure 9 is a schematic diagram of the output waveform of the phase discriminator when the static frequency of the voltage-controlled oscillator is 102 Hz provided by the present invention;

[0021] Figure 10 It is a schematic diagram of the output waveform of the phase discriminator when the static frequency of the voltage-controlled oscillator provided by the present invention is 104 Hz;

[0022] Figure 11 It is a schematic diagram of the output waveform of the phase discriminator when the static frequency of the voltage-controlled oscillator provided by the present invention is 106 Hz;

[0023] Figure 12 It is a schematic diagram of the output waveform of the phase discriminator when the static frequency of the voltage-controlled oscillator provided by the present invention is 107 Hz. Detailed implementation manners

[0024] For a clearer understanding of the technical features, objectives, and effects of the present invention, the detailed implementation manners of the present invention will now be described in detail with reference to the accompanying drawings.

[0025] This embodiment provides a PID-based low-frequency time code Costas loop, which includes a Costas loop and at least one PID controller, and the Costas loop and the at least one PID controller are electrically connected; the Costas loop includes a first voltage-controlled oscillator, a first multiplier, a first low-pass filter, a second voltage-controlled oscillator, a second multiplier, a second low-pass filter, a phase discriminator, and a loop filter; the output end of the first voltage-controlled oscillator is connected to the first input end of the first multiplier, the output end of the first multiplier is connected to the input end of the first low-pass filter, the output end of the first low-pass filter is connected to the first input end of the phase discriminator, the output end of the phase discriminator is connected to the input end of the loop filter, and the output end of the loop filter is connected to the first input end of the first voltage-controlled oscillator; the output end of the second voltage-controlled oscillator is connected to the first input end of the second multiplier, the output end of the second multiplier is connected to the input end of the second low-pass filter, the output end of the second low-pass filter is connected to the second input end of the phase discriminator, and the output end of the loop filter is also connected to the first input end of the second voltage-controlled oscillator; the second input end of the first voltage-controlled oscillator is connected to the second input end of the second voltage-controlled oscillator and is used as a signal input end; the output end of the phase discriminator is used as a signal output end.

[0026] In an exemplary embodiment, the phase discriminator, the PID controller, and the loop filter are connected in series in sequence.

[0027] In an exemplary embodiment, a PID controller is connected in series between the first low-pass filter and the phase discriminator, and another PID controller is connected in series between the second low-pass filter and the phase discriminator.

[0028] This embodiment provides a carrier synchronization method applied to the above-mentioned PID-based low-frequency time code Costas loop, including: setting the initial values of the proportional term, integral term, and derivative term of the PID controller; dynamically adjusting the proportional term according to the signal-to-noise ratio and the initial value of the proportional term; dynamically adjusting the integral term according to the initial value of the integral term; and dynamically adjusting the derivative term according to the signal-to-noise ratio and the initial value of the derivative term.

[0029] In an exemplary embodiment, setting the initial values of the proportional term, integral term, and derivative term of the PID controller specifically means: setting the initial value of the proportional term of the PID controller to 3, setting the initial value of the integral term of the PID controller to 0.05, and setting the initial value of the derivative term of the PID controller to 0.01.

[0030] In an exemplary embodiment, dynamically adjusting the proportional term according to the signal-to-noise ratio and the initial value of the proportional term is as shown in the formula:

[0031]

[0032] where K P is the proportional term of the PID controller, K P0 is the initial value of the proportional term of the PID controller; SNR is the signal-to-noise ratio.

[0033] In an exemplary embodiment, dynamically adjusting the integral term according to the initial value of the integral term is as shown in the formula:

[0034]

[0035] where K I is the integral term of the PID controller, K I0 is the initial value of the integral term of the PID controller, and e(t) is the error output of the phase discriminator.

[0036] In an exemplary embodiment, dynamically adjusting the derivative term according to the signal-to-noise ratio and the initial value of the derivative term is as shown in the formula:

[0037] K D = K D0 tanhSNR,

[0038] where K D is the derivative term of the PID controller, K D0 is the initial value of the derivative term of the PID controller, and tanh represents the hyperbolic tangent function.

[0039] In some embodiments, the above carrier synchronization method can also be implemented in the following manner.

[0040] The main purpose of this embodiment is to overcome the defects of the traditional Costas loop carrier synchronization method in the existing low-frequency time code spread spectrum communication (LFTC) system, such as slow convergence speed, insufficient anti-phase jitter ability, and poor frequency division adaptability. A Costas loop carrier synchronization method based on PID optimization is proposed. Specifically, the PID controller module is embedded in the error adjustment link of the Costas loop (the PID controller is placed behind the phase detector and behind the low-pass filter respectively and compared). According to the real-time signal-to-noise ratio (SNR) of the low-frequency time code spread spectrum communication system and the error output e(t) of the phase detector, the sizes of the proportional (K p ), integral (K i ), and derivative (K d ) terms are dynamically and adaptively adjusted to adapt to the time-varying channel conditions (SNR fluctuations, burst phase jitters) of the LFTC system, quickly cancel the error and maintain the loop stability, significantly shorten the phase detection time, and improve the carrier synchronization speed and anti-interference ability.

[0041] The PID controller is a feedback controller widely used in industrial control systems. Its name comes from the combination of three control operations: proportional, integral, and derivative, which are combined in the way of generating control signals. As a feedback controller, the PID controller maintains the output through closed-loop operation, so that there is zero error between the process variable and the required output of the set point.

[0042] The proportional control part (P) adjusts the control output according to the current error (the difference between the set value and the actual value). The output is proportional to the error e(t). The larger the error, the larger the control output. It compares the expected value or set value with the actual value or the feedback process value, and multiplies the obtained error by the proportional constant to obtain the output. If the error value is zero, the output of this controller is zero. Although proportional control can quickly respond to errors, it may leave a steady-state error. To solve this problem, the integral control (I) eliminates the steady-state error by accumulating historical errors. Its output is proportional to the accumulated value of the error, which can effectively eliminate the steady-state error, but may cause the system response to slow down or overshoot. When a negative error occurs, the integral control reduces its output. It limits the response speed and affects the stability of the system. By reducing the integral gain K i to improve the response speed. The derivative control (D) is adjusted according to the rate of change of the error, which can predict the future error change, thereby improving the response speed and stability of the system and reducing the overshoot phenomenon. The error e(t) used in this embodiment is the phase difference V d output by the multiplication phase detector. The control structure of the PID controller is as Figure 2 shown.

[0043] This embodiment is based on a low-frequency time code spread-spectrum communication system. The Costas loop used in this system consists of four parts: a low-pass filter, a phase discriminator, a voltage-controlled oscillator, and a loop filter. The principle block diagram is as shown in Figure 3 the figure. The low-pass filter selects a Butterworth filter. Its function is to filter out the noise in the loop as much as possible, so that the filtering result can not only truly reflect the phase change of the input signal of the loop filter, but also prevent the voltage-controlled oscillator from being overly adjusted due to noise. The cut-off frequency of the passband of the low-pass filter is set to 110 Hz. The phase discriminator (phase detector) is a phase comparison device, mainly used to measure the difference between the feedback signal and the input signal. During the process of carrier synchronization, the output of the phase discriminator, that is, the phase difference V d will gradually tend to 0 from a non-zero value and stabilize around 0, indicating that the modulated signal and the local signal have completed synchronization. This embodiment uses a traditional multiplication phase discriminator. The voltage-controlled oscillator is used to generate a local carrier signal with a quiescent frequency of 102 Hz to track and synchronize the carrier of the received signal. The gain K d of the voltage-controlled oscillator is set to 5 Hz / V.

[0044] The theoretical working process of the Costas loop used in this embodiment is as follows:

[0045] Assume that the input modulated signal is m(t)cosω0t, then

[0046] V3 = m(t)cosω0t cos(ω0t + θ) = 1 / 2m(t)[cosθ + cos(2ω0t + θ)] (1)

[0047] V4 = m(t)sinω0t sin(ω0t + θ) = 1 / 2m(t)[sinθ + sin(2ω0t + θ)] (2)

[0048] The two outputs after passing through the low-pass filter are respectively:

[0049] V5 = 1 / 2m(t)cosθ (3)

[0050] V6 = 1 / 2m(t)sinθ (4)

[0051] This embodiment uses a multiplication phase discriminator

[0052] sin[2θ(t)] = V5V6 = θ (5)

[0053] The output of the phase discriminator is θ. When the loop is not locked, θ controls the frequency of the voltage-controlled oscillator. The phase of the sine wave output by the voltage-controlled oscillator is continuously adjusted in the direction of reducing the tracking error until the output θ of the phase discriminator tends to the stable value of 0, indicating that the output of the voltage-controlled oscillator has tracked the carrier frequency of the input signal and the carrier synchronization is completed.

[0054] The digital loop filter adopts a second-order digital loop filter. The typical structure of a second-order digital loop filter is as Figure 4 shown. Where Z -1 represents the unit time delay, and C1 and C2 are filter parameters, which are determined by the noise bandwidth, time period, and damping factor of the filter.

[0055] For the analog loop filter, the bilinear transformation method is used to transform the S domain to the digital domain. The theoretical process of analyzing the optimal digital second-order loop is as follows:

[0056] H(z) = {[4ξω n +(ω n T) 2 +2(ω n T) 2 Z -1 +(ω n T) 2 -(ξω n T) 2} / {[4+4ξω n T+(ω n T) 2 +[2(ω n T) 2 -8]Z -1 +[4-4ξω n T+(ω n T) 2 Z -2} (6)

[0057] In Equation (6), ω n is the natural angular frequency of the loop filter, ω n = 6Hz, the damping coefficient ξ is generally taken as 0.707, and T is the sampling time, taken as 0.001s.

[0058] The Z-domain transfer function K is:

[0059]

[0060] In Equation (15), C1 and C2 are the coefficients of the loop filter. The transfer function of the numerically controlled oscillator is:

[0061]

[0062] Then the closed-loop transfer function is:

[0063]

[0064] Compared with Equation (6), it can be obtained that:

[0065]

[0066] In formulas (10) and (11), K d w n = 8ξB L / 4ξ 2 +1, K d is the phase detector gain, and K0 is the voltage-controlled oscillator gain. Calculated from the above formulas, C1 in this embodiment is taken as 1 and C2 is taken as 0.01.

[0067] The LFTC carrier synchronization module uses a Costas phase-locked loop. The simulation model of the Costas phase-locked loop before optimization is as follows Figure 5 .

[0068] To shorten the phase detection time of the phase detector, that is, the time required to achieve carrier synchronization, a PID controller module is added to this Costas loop. Since there are two loops and there is a common branch between the two loops, consider placing the PID controller behind the low-pass filter and behind the multiplication phase detector respectively. First, manually tune the three initial parameters K P , K I , K D of K P0 , K I0 , K D0 under ideal channel conditions (SNR is infinite), and then dynamically adjust the parameters of the PID according to the following formulas. The formulas in this embodiment specifically include:

[0069] Proportional term dynamic adjustment: Through the formula:

[0070]

[0071] Enhance the error response strength at low SNR, suppress overshoot at high SNR, and balance the convergence speed and stability;

[0072] Integral term anti-saturation design: Through the formula:

[0073]

[0074] Dynamically scale the integral gain according to the error amplitude to avoid integral saturation and improve the steady-state accuracy;

[0075] Differential term smooth transition: Through the formula:

[0076] K D = K D0 tanh SNR,

[0077] Utilize the boundedness of the hyperbolic tangent function to suppress noise amplification at low SNR and enable full differentiation to suppress phase mutation at high SNR.

[0078] The following are the specific design ideas for each formula:

[0079] Proportional term K P Formula:

[0080]

[0081] Increase K at low SNR (noise-dominated) P to enhance the error response strength and accelerate the initial capture; decrease K at high SNR (signal pure) P to avoid overshoot and maintain loop stability. Use the reciprocal of SNR (1 / SNR) to characterize the noise pollution degree, and through linearly superposing the noise influence, implement a negative feedback mechanism of "the greater the noise, the more aggressive the control".

[0082] Integral term K I Formula:

[0083]

[0084] Shrink K when the error is large (|e(t)| >> 1) I to suppress integral saturation and prevent overshoot; enlarge K when the error is small (|e(t)| ≈ 0) I to improve the steady-state accuracy. Introduce the error amplitude e(t) as the denominator to construct a continuous conditional integral to avoid loop jitter caused by parameter mutation.

[0085] Derivative term K D Formula:

[0086] K D = K D0 tanh SNR,

[0087] At low SNR, tanh SNR ≈ 0, suppressing the derivative term to avoid noise amplification; at high SNR, tanh SNR ≈ 1, enabling the full differential gain to suppress phase mutation. Use the hyperbolic tangent function tanh to achieve a smooth gain transition, and its monotonic boundedness (output range [0,1]) ensures that the derivative term is controllable at any SNR.

[0088] Applied in the LFTC simulation system, set different signal-to-noise ratios and the quiescent frequency of the voltage-controlled oscillator, obtain the output waveform of the phase detector, and compare and analyze it with the output of the Costas loop phase detector without adding PID to judge the performance.

[0089] The Costas loop model optimized by adding a PID controller is as Figure 6 and Figure 7 . Figure 6 The shown is the optimized model with the PID controller placed after the multiplicative phase detector, Figure 7The optimized model shown places the PID controller after the low-pass filter.

[0090] Directly use the PID Controller module already integrated in Simulink. The key to using the PID controller lies in the P settings of the three parameters I , D , and P . I and D generate the response speed and strength. If it is too small, the response is slow; if it is too large, oscillations will occur. It is the basis for I and D . D eliminates the deviation and improves the accuracy when there are system errors and external forces. At the same time, it will also increase the response speed and cause overshoot. If it is too large, oscillations will occur.

[0091] Under the condition of an ideal channel (infinite SNR), manually tune the values of the three parameters of the PID control module. The adjustment order is: P > I > D . The adjustment goal is that the steady-state error approaches 0 and the system response is as fast as possible. First, fix I and D at 0, and slowly increase P from 1 until the system is stable. Each time the controller parameters are changed, observe the system output for a period of time until the closed-loop system reaches critical stability and the output produces equal-amplitude and equal-period continuous oscillations. Record P at this time. Fix P , set D = 0, that is, use the PI controller, gradually increase I from 0, and observe the system output for a period of time until the closed-loop system's suppression of disturbances reaches the best. After determining P and I , fix their values, add D , until the system output reaches stability. The initial parameters after tuning are set as P0 = 3; I0 = 0.05; D0 = 0.01. At this time, the output of the phase detector is as Figure 8 shown.

[0092] After determining the initial values, set the three parameters of the PID as variables and write code in the m file to make the three parameters of the PID adjust dynamically according to the signal-to-noise ratio and error output of the system. Conduct simulation verification under different channel conditions with signal-to-noise ratios (SNR) of 5 dB, 10 dB, and 20 dB respectively, and set the static frequencies of the voltage-controlled oscillator to 102 Hz, 104 Hz, 106 Hz, and 107 Hz respectively, and compare with the output of the Costas loop phase detector without PID.

[0093] The simulation results are as follows: When the static frequency of the voltage-controlled oscillator is 102 Hz, as Figure 9 shown is the output of the phase detector when the static frequency of the voltage-controlled oscillator is 102 Hz; when the static frequency of the voltage-controlled oscillator is 104 Hz, as Figure 10 shown is the output of the phase detector when the static frequency of the voltage-controlled oscillator is 104 Hz; when the static frequency of the voltage-controlled oscillator is 106 Hz, as Figure 11 shown is the output of the phase detector when the static frequency of the voltage-controlled oscillator is 106 Hz; when the static frequency of the voltage-controlled oscillator is 107 Hz, as Figure 12 shown is the output waveform of the phase detector when the static frequency of the voltage-controlled oscillator is 107 Hz.

[0094] To facilitate the analysis of the influence of the PID controller on the performance of the Costas loop under different signal-to-noise ratios and different frequency offsets, compare the relevant test results. Table 1 is the comparison table of the Costas loop synchronization performance test results at different VCO static frequencies when the signal-to-noise ratio is 5 dB, Table 2 is the comparison table of the Costas loop synchronization performance test results at different VCO static frequencies when the signal-to-noise ratio is 10 dB, and Table 3 is the comparison table of the Costas loop synchronization performance test results at different VCO static frequencies when the signal-to-noise ratio is 20 dB;

[0095] Table 1: Comparison Table of Costas Loop Synchronization Performance Test Results at Different VCO Static Frequencies when the Signal-to-Noise Ratio is 5 dB

[0096]

[0097] Table 2: Comparison Table of Costas Loop Synchronization Performance Test Results at Different VCO Static Frequencies when the Signal-to-Noise Ratio is 10 dB

[0098]

[0099] Table 3: Comparison Table of Costas Loop Synchronization Performance Test Results at Different VCO Static Frequencies when the Signal-to-Noise Ratio is 20 dB

[0100]

[0101] Based on the above result analysis, it can be seen that adding a PID controller to the traditional Costas loop can significantly shorten the time required for the output of the phase discriminator to reach stability, and the improvement in the phase discrimination speed is more than 30% in all cases; moreover, the larger the initial frequency offset, the more significant the effect of the PID controller. As can be seen from the data in the above table, when the initial frequency offset is +7Hz, the improvement in the phase discrimination speed is more than 80% in all cases, and the highest can reach 87.8%.

[0102] Therefore, the self-adaptive dynamic adjustment PID controller designed in the present invention can be applied to the LFTC system and significantly improve the speed, accuracy and robustness of carrier synchronization, providing an efficient and reliable solution for suppressing carrier synchronization in the carrier modulation system.

[0103] The embodiments of the present invention have been described above in conjunction with the accompanying drawings. However, the present invention is not limited to the above specific embodiments. The above specific embodiments are merely illustrative and not restrictive. Under the inspiration of the present invention, those of ordinary skill in the art can also make many forms without departing from the purpose of the present invention and the scope protected by the claims. All of these are within the protection scope of the present invention.

Claims

1. A PID-based low-frequency time code Costas loop, characterized in that, The PID-based low-frequency time code Costas loop includes a Costas loop and at least one PID controller, and the Costas loop and the at least one PID controller are electrically connected; the Costas loop includes a first voltage-controlled oscillator, a first multiplier, a first low-pass filter, a second voltage-controlled oscillator, a second multiplier, a second low-pass filter, a phase discriminator and a loop filter; the output end of the first voltage-controlled oscillator is connected to the first input end of the first multiplier, the output end of the first multiplier is connected to the input end of the first low-pass filter, the output end of the first low-pass filter is connected to the first input end of the phase discriminator, the output end of the phase discriminator is connected to the input end of the loop filter, and the output end of the loop filter is connected to the first input end of the first voltage-controlled oscillator; the output end of the second voltage-controlled oscillator is connected to the first input end of the second multiplier, the output end of the second multiplier is connected to the input end of the second low-pass filter, the output end of the second low-pass filter is connected to the second input end of the phase discriminator, and the output end of the loop filter is also connected to the first input end of the second voltage-controlled oscillator; the second input end of the first voltage-controlled oscillator is connected to the second input end of the second voltage-controlled oscillator and is used as a signal input end; the output end of the phase discriminator is used as a signal output end.

2. The PID-based low-frequency time code Costas loop according to claim 1, wherein The phase discriminator, the PID controller and the loop filter are connected in series in sequence.

3. The PID-based low-frequency time code Costas loop according to claim 1, characterized in that A PID controller is connected in series between the first low-pass filter and the phase discriminator, and another PID controller is connected in series between the second low-pass filter and the phase discriminator.

4. A carrier synchronization method for the PID-based low-frequency time code Costas loop according to any one of claims 1-3, characterized in that, It includes: Setting the initial values of the proportional term, integral term and differential term of the PID controller; Dynamically adjusting the proportional term according to the signal-to-noise ratio and the initial value of the proportional term; dynamically adjusting the integral term according to the initial value of the integral term; dynamically adjusting the differential term according to the signal-to-noise ratio and the initial value of the differential term.

5. The carrier synchronization method according to claim 4, wherein The setting of the initial values of the proportional term, integral term and differential term of the PID controller is specifically: setting the initial value of the proportional term of the PID controller to 3, setting the initial value of the integral term of the PID controller to 0.05, and setting the initial value of the differential term of the PID controller to 0.

01.

6. The carrier synchronization method according to claim 4, wherein The dynamic adjustment of the proportional term according to the signal-to-noise ratio and the initial value of the proportional term, as the formula: Among them, K P is the proportional term of the PID controller, and K P0 is the initial value of the proportional term of the PID controller; SNR is the signal-to-noise ratio.

7. The carrier synchronization method according to claim 4, wherein The dynamic adjustment of the integral term according to the initial value of the integral term, as the formula: Among them, K I is the integral term of the PID controller, and K I0 is the initial value of the integral term of the PID controller, and e(t) is the error output of the phase discriminator.

8. The carrier synchronization method according to claim 4, wherein The dynamic adjustment of the differential term according to the signal-to-noise ratio and the initial value of the differential term, as the formula: K D = K D0 tanh SNR, Among them, K D is the differential term of the PID controller, and K D0 is the initial value of the differential term of the PID controller. Tanh represents the hyperbolic tangent function.

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