Circuit design performance analysis method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a circuit design performance analysis method and device, electronic equipment and a storage medium, the performance analysis method comprises the steps that a constraint file used for performance analysis and a circuit design file are acquired, the constraint file comprises a plurality of constraint conditions, and the constraint conditions are used for determining a performance path in a plurality of paths of a circuit; according to the multiple constraint conditions, the design file is analyzed, a performance analysis directed graph is generated, the performance analysis directed graph at least comprises a starting point, an end point and at least one intermediate node of a performance path in the circuit, and the performance path is a path used for reflecting the performance of the circuit in multiple paths of the circuit; according to the performance analysis directed graph, the bandwidth efficiency of the circuit is calculated, and the bandwidth efficiency is used for representing the performance of circuit design. According to the method, the bandwidth efficiency of the circuit can be obtained through analysis according to the design file and the constraint file, higher accuracy is achieved compared with manual analysis, and a large amount of time does not need to be consumed compared with performance simulation.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a performance analysis method, apparatus, electronic device, and storage medium for circuit design. Background Art

[0002] Chip performance is a key chip metric, influenced by both system architecture and microarchitecture design. At the system architecture level, system-level performance analysis is typically considered during the initial stages of chip design. At the microarchitecture level, as chip design becomes increasingly complex with increasing demand, chip performance is often affected by the combined impact of multiple modules on the chip. The designs of these different modules often undergo numerous revisions, necessitating continuous theoretical and simulation analysis to determine whether the chip's overall performance meets the design's performance requirements.

[0003] In actual chip design, theoretical analysis is performed manually, typically based on design documents or register transfer level (RTL) code. This approach is inaccurate and prone to errors. For example, if the internal delay of a circuit module is modified, or the number of register slices between modules changes, these changes can easily be overlooked by the manual analyst, resulting in the analysis being out of sync with the real-time design. Therefore, theoretical analysis is typically used for rough estimates in the early stages of design and cannot be used as the basis for final performance analysis. Performance simulation can produce relatively accurate simulation results based on RTL code, such as obtaining information such as delay parameters. However, chip performance simulation is time-consuming, especially for large chips such as system-on-chip (SoC) chips, where a single performance simulation can take several days. After the chip design is modified, the performance simulation must be repeated, which is very time-consuming. Summary of the Invention

[0004] One or more embodiments of the present disclosure provide a performance analysis method, apparatus, electronic device, and storage medium for circuit design to solve the problem that manual analysis is inaccurate while performance simulation is time-consuming.

[0005] In a first aspect, at least one embodiment of the present disclosure provides a performance analysis method for circuit design, comprising: obtaining a constraint file for performance analysis and a design file of a circuit, wherein the constraint file includes multiple constraint conditions, and the constraint conditions are used to determine a performance path among multiple paths of the circuit; parsing the design file according to the multiple constraint conditions, and generating a performance analysis directed graph, wherein the performance analysis directed graph includes at least a starting point, an end point, and at least one intermediate node of a performance path in the circuit, and the performance path is a path among multiple paths of the circuit used to reflect the performance of the circuit; calculating the bandwidth efficiency of the circuit according to the performance analysis directed graph, and the bandwidth efficiency is used to characterize the performance of the circuit design.

[0006] Optionally, in the performance analysis method for circuit design provided according to at least one embodiment of the present disclosure, the multiple constraints include at least the starting point of the performance path, the end point of the performance path, the maximum transmission capacity of the performance path, and the clock of the performance path.

[0007] Optionally, in the performance analysis method of circuit design provided according to at least one embodiment of the present disclosure, the starting point defines the starting point of the performance path, which is the input and output port of the register or circuit module; the end point defines the end point of the performance path, which is the input and output port of the register or circuit module; the maximum transmission capacity defines the maximum transmission capacity that the performance path can support, and the maximum transmission capacity is a preset value or a parameter in the circuit design; the clock defines a hash table of clock cycles, the key of the hash table is the clock name, and the value of the hash table is the clock cycle.

[0008] Optionally, in a performance analysis method for circuit design provided according to at least one embodiment of the present disclosure, a design file is parsed according to multiple constraints and a performance analysis directed graph is generated, including: determining a performance path according to multiple constraints; abstracting the performance path to generate an abstract circuit directed graph, wherein the abstract circuit directed graph includes multiple nodes, the length between any two adjacent nodes in the multiple nodes is one clock cycle, and different clocks correspond to different clock cycle lengths; simplifying the abstract circuit directed graph to obtain a performance analysis directed graph.

[0009] Optionally, in the performance analysis method for circuit design provided according to at least one embodiment of the present disclosure, simplifying the abstract circuit directed graph includes: merging adjacent nodes without branches among multiple nodes to reduce the number of multiple nodes.

[0010] Optionally, in the performance analysis method of circuit design provided according to at least one embodiment of the present disclosure, the performance path is abstracted to generate an abstract circuit directed graph, including: determining the end point of the performance path based on the end point of the performance path in multiple constraints; from the end point of the performance path, reversely determining multiple nodes in the performance path until reaching the starting point of the performance path, where the multiple nodes are register nodes; and adding a transmission direction between any two connected nodes among the multiple nodes to generate an abstract circuit directed graph.

[0011] Optionally, in the performance analysis method for circuit design provided according to at least one embodiment of the present disclosure, a maximum path search algorithm is used to reversely determine multiple nodes in the performance path from the end point of the performance path until the starting point of the performance path is reached.

[0012] Optionally, in the performance analysis method for circuit design provided according to at least one embodiment of the present disclosure, the bandwidth efficiency of the circuit is calculated based on the performance analysis directed graph, including: calculating the bandwidth efficiency of the performance path based on the nodes and path delays between nodes in the performance analysis directed graph.

[0013] Optionally, in the performance analysis method of circuit design provided according to at least one embodiment of the present disclosure, the bandwidth efficiency of the performance path is calculated based on the path delay between nodes in the performance analysis directed graph, including: determining the branch path with the longest delay between the starting point and the end point of the performance path; and calculating the bandwidth efficiency of the performance path based on the maximum transmission capacity among multiple constraints and its corresponding operating frequency and the delay of the branch path with the longest delay.

[0014] Optionally, according to the performance analysis method of circuit design provided in at least one embodiment of the present disclosure, the method further includes: determining whether the circuit meets preset performance requirements based on bandwidth efficiency; when the circuit does not meet the preset performance requirements, increasing the cache capacity of the circuit to increase the corresponding maximum transmission capacity of the circuit.

[0015] Optionally, in the performance analysis method for circuit design provided according to at least one embodiment of the present disclosure, the design file includes a system-level design file or a register transfer-level design file.

[0016] In a second aspect, at least one embodiment of the present disclosure provides a performance analysis device for circuit design, comprising: a file acquisition module, configured to acquire a constraint file for performance analysis and a design file of a circuit, wherein the constraint file includes multiple constraint conditions, and the constraint conditions are used to determine a performance path among multiple paths of the circuit; a directed graph generation module, configured to parse the design file according to the multiple constraint conditions and generate a performance analysis directed graph, wherein the performance analysis directed graph includes at least a starting point, an end point and at least one intermediate node of the performance path in the circuit, and the performance path is a path among the multiple paths of the circuit used to reflect the performance of the circuit; a calculation module, configured to calculate the bandwidth efficiency of the circuit according to the performance analysis directed graph.

[0017] In a third aspect, at least one embodiment of the present disclosure provides an electronic device comprising: at least one processor and a memory; wherein a computer program is stored on the memory, and when the computer program is executed by at least one processor, any one of the methods in the above-mentioned first aspect is implemented.

[0018] In a fourth aspect, at least one embodiment of the present disclosure provides a computer-readable storage medium having computer-executable instructions stored thereon, wherein when the instructions are executed by a processor, the method of any one of the above-mentioned first aspects is implemented.

[0019] According to the embodiment of the present disclosure, a performance analysis method for circuit design, a performance analysis device for circuit design, an electronic device, and a storage medium are provided. The performance analysis method includes obtaining a constraint file for performance analysis and a design file of a circuit, wherein the constraint file includes multiple constraint conditions, and the constraint conditions are used to determine the performance path among multiple paths of the circuit; according to the multiple constraint conditions, the design file is parsed and a performance analysis directed graph is generated, wherein the performance analysis directed graph includes at least the starting point, the end point, and at least one intermediate node of the performance path in the circuit, and the performance path is a path among multiple paths of the circuit used to reflect the performance of the circuit; according to the performance analysis directed graph, the bandwidth efficiency of the circuit is calculated, and the bandwidth efficiency is used to characterize the performance of the circuit design. By executing the performance analysis method, the bandwidth efficiency of the circuit can be analyzed and obtained through the design file and the constraint file, which has higher accuracy than manual analysis and does not require a lot of time compared to performance simulation, and can improve analysis efficiency while ensuring analysis accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0021] Figure 1 A schematic diagram showing access delay in a system on chip provided according to an embodiment of the present disclosure is shown;

[0022] Figure 2A-2C A schematic diagram showing the relationship between maximum transmission capacity and bandwidth efficiency provided according to an embodiment of the present disclosure is shown;

[0023] Figure 3 A schematic diagram illustrating a performance analysis method for a circuit design provided according to an embodiment of the present disclosure is shown;

[0024] Figure 4A A schematic diagram of a performance path provided according to an embodiment of the present disclosure is shown;

[0025] Figure 4B Shown as Figure 4A Schematic diagram of the abstract circuit directed graph corresponding to the performance path shown;

[0026] Figure 4C A schematic diagram of a performance analysis directed graph provided according to an embodiment of the present disclosure is shown;

[0027] Figure 5A An example of a circuit module provided according to an embodiment of the present disclosure is shown;

[0028] Figure 5B Shown as Figure 5A Schematic diagram of the abstract circuit directed graph and performance analysis directed graph of the circuit module shown;

[0029] Figure 6 A schematic diagram of a performance analysis device for a circuit design provided according to an embodiment of the present disclosure is shown;

[0030] Figure 7 A schematic diagram of an electronic device provided according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0031] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present disclosure.

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless explicitly defined in this manner in the embodiments of the present disclosure.

[0033] The words "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Similarly, words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Flowcharts are used in the embodiments of the present disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the previous or subsequent steps are not necessarily performed in exact order. Instead, the various steps may be processed in reverse order or simultaneously. At the same time, other operations may be added to these processes, or one or more steps may be removed from these processes.

[0034] Two important factors in measuring chip performance are bandwidth and latency. Bandwidth refers to the amount of data that can be transmitted per unit time. Bandwidth is generally determined by bus width and operating frequency. For example, if the bus width is 64 bits and the operating frequency is 1 GHz, the corresponding theoretical bandwidth is 64 Gb / s. Latency refers to the time from initiating a request to receiving a response.

[0035] Figure 1 A schematic diagram illustrating access delay in a system on chip provided according to an embodiment of the present disclosure is shown.

[0036] like Figure 1 As shown, in a system on chip 100, host 1, host 2, and host 3 interact with the memory controller via the on-chip network to access dynamic random access memory (DRAM). Host 3 is connected to memory controller 1 via on-chip network 2, and memory controller 1 is connected to DRAM 1. Host 1 and host 2 are both connected to memory controller 2 via on-chip network 1 and on-chip network 2, and memory controller 2 is connected to DRAM 2. The on-chip network transmits data with other devices via register slices, for example, Figure 1The data transmission between the on-chip network 1 and the host 1 is carried out through the register slice 1, the data transmission between the on-chip network 1 and the on-chip network 2 is carried out through the register slice 2, and the data transmission between the on-chip network 2 and the memory controller 2 is carried out through the register slice 3. In addition, a register slice can also be set between the host 3, the memory controller 1 and the on-chip network 2, but it is not shown in FIG. Figure 1 Shown in.

[0037] Multiple hosts can access the memory through a complex on-chip network, such as Figure 1 As shown. The host here can be a central processing unit (CPU), a graphics processing unit (GPU) or a direct memory access (DMA), etc. Typical memory access operations include: the host selects a command from the command cache, initiates a request, and after passing through the on-chip network, reaches the memory controller. After the memory controller completes the access to the DRAM, it returns the response to the host. After receiving the response, the host clears the corresponding command in the command cache. The request here can be a read request, and the returned response is the read data. The request can also be a write request, and the returned response is a write response. For example Figure 1 In the example, if host 1 initiates a read request, the read request passes through network on chip 1 and network on chip 2 before reaching memory controller 2. Memory controller 2 reads data from DRAM 2, and the read data passes through network on chip 2 and network on chip 1 before returning to host 1. The delay from the host sending the request to receiving the returned response is called round-trip latency, as shown in Figure 1. Figure 1 The dotted line in FIG shows the round-trip delay path for host 1 to access DRAM 2.

[0038] The round-trip delay is mainly determined by the circuits on the access path. For every additional register on the circuit on the round-trip path, the delay will increase by one clock cycle corresponding to the register. In large SOC chips, the host and the destination to be accessed may be far apart and need to cross multiple modules, so the round-trip delay is very large. In addition, in order to solve the timing problem between different modules in large SOCs, register slices may be inserted between modules. These register slices will also increase the round-trip delay of the access path, such as Figure 1 Register slices between host 1 and on-chip network 1, between on-chip network 1 and on-chip network 2, and between on-chip network 2 and memory controller 2.

[0039] Affected by the round-trip delay and the size of the request buffer, the bandwidth on the data path may not reach the theoretical value (the theoretical value is the data width of the data path multiplied by the operating frequency). The ratio of actual bandwidth to theoretical bandwidth is called bandwidth efficiency. For example, in the example mentioned above, a 64-byte bus operates at a frequency of 1GHz, corresponding to a theoretical bandwidth of 64GB / s. When the actual bandwidth is only 56GB / s, the bandwidth efficiency is 87.5%. When the data width of the data path is fixed, the bandwidth efficiency can also be expressed by the effective transmission time within the unit time window on the data path. For example, if an average of 80ns is used to transmit data within 100ns, the bandwidth efficiency is 80%. Therefore, bandwidth efficiency is related to whether the system can send data continuously, and whether it can send data continuously is affected by the system delay and maximum transmission capacity. Maximum transmission capacity is also called outstanding capacity.

[0040] Figure 2A-2C A schematic diagram showing the relationship between maximum transmission capacity and bandwidth efficiency provided according to an embodiment of the present disclosure is shown.

[0041] Figure 2A-2C Taking the read request as an example, it is assumed that the round-trip delay of the host reading data is fixed at 7 clock cycles, and the host has continuous read requests to be sent and processed.

[0042] exist Figure 2A In the example, the host's Outstanding capability is 3 (corresponding to 3 command buffers), so it can send three consecutive read requests before receiving the first read data. For example, before receiving data A, it sends three consecutive read requests: A, B, and C. When the host receives data A, it can send the next read request: D. When the host receives data B, it can send the next read request: E, and so on. As can be seen, because the host's Outstanding capability is 3, the maximum number of outstanding requests issued is 3, resulting in discontinuous data being returned. Data is returned in only 3 of every 7 cycles, resulting in a bandwidth efficiency of only 3 / 7 = 42.86%.

[0043] Figure 2BIn the example, the host's Outstanding capability is 5 (corresponding to 5 command buffers), so it can send five consecutive read requests before receiving the first read data. For example, before receiving data A, it sends five consecutive read requests: A, B, C, D, and E. When the host receives data A, it can send the next read request: F. When the host receives data B, it can send the next read request: G, and so on. As can be seen, because the host's Outstanding capability is 5, the maximum number of outstanding requests is 5, resulting in discontinuous data being returned. Data is returned in only 5 of every 7 cycles, resulting in a bandwidth efficiency of only 5 / 7 = 71.43%.

[0044] Figure 2C In the example, the host's Outstanding capability is 7 (corresponding to 7 command buffers), so it can send 7 read requests in succession before receiving the first read data. For example, before receiving data A, 7 read requests A, B, C, D, E, F, and G are sent in succession. When the host receives the returned data A, it can continue to send the next read request H; when the host receives the returned data B, it can continue to send the next read request I, and so on. As you can see, due to the upgrade of the host's Outstanding capability, the host can send read requests continuously, and data can also be returned continuously, making the bandwidth efficiency reach 100%.

[0045] according to Figures 2A to 2C , the greater the Outstanding capability of the host, the higher the bandwidth efficiency and the better the performance. When the total duration corresponding to the Outstanding capability is equal to the round-trip delay of access, the theoretical bandwidth can reach its maximum. At this time, increasing the Outstanding capability will not further improve the performance. Since increasing the Outstanding capability means increasing the command cache of the host, which will increase the chip area, performance and area requirements need to be considered during design. The ideal situation is that the Outstanding capability can cover the round-trip delay of data access. The relationship between bandwidth efficiency, Outstanding (OSD) capability size and access round-trip delay L is shown in formula (1), where f is the operating clock frequency.

[0046]

[0047] Because the access round-trip delay L = the number of clock cycles of the round-trip delay D cycle / clock frequency f, formula (1) can be simplified to formula (2).

[0048]

[0049] Bandwidth efficiency is equal to the ratio of the outstanding capability to the number of cycles of the access round-trip delay. According to formulas (1) and (2), bandwidth efficiency can be maximized only when the outstanding capability is greater than or equal to the access round-trip delay. However, it is meaningless to set the outstanding capability value too large. It will not further improve the bandwidth efficiency and will increase the design area. Therefore, when designing a chip, the outstanding capability of different hosts, or the request cache size, needs to be adjusted according to the host's round-trip delay. However, when the host's access path passes through different modules, the internal designs of different modules vary greatly. Different levels of register slices may be inserted between different modules according to the timing conditions, making it difficult to calculate the host's access round-trip delay theoretically. When designing an actual chip, performance simulation based on the RTL code is required to obtain accurate delay. However, chip performance simulation is very time-consuming, especially for large SOC chips. A single simulation may take several days. When any module on the access path is modified or the register slices between modules are changed, performance simulation needs to be repeated.

[0050] Based on the above, current circuit performance analysis primarily involves theoretical analysis and performance simulation. Theoretical analysis involves manual analysis of access path latency, typically performed based on design documents or RTL code. Performance analysis is typically performed using dynamic simulation. Dynamic simulation involves developing performance test cases, setting up a performance simulation environment, and simulating the complete RTL of a circuit or chip. Dynamic simulation analyzes whether the access path latency of each host in the chip meets the host's Outstanding performance requirements.

[0051] However, the inventors of the present disclosure discovered the following technical problems:

[0052] Theoretical analysis suffers from low accuracy and is prone to errors. For example, if the delay within a chip module changes, or if register slices between modules vary, theoretical analysis can easily overlook these variations, making it impossible to synchronize theoretical analysis with the design in real time. Therefore, theoretical analysis is often used for rough estimates in the early stages of chip design and cannot be used as the final basis for performance analysis.

[0053] When the test cases are accurate, the results of dynamic performance simulation will be very accurate. However, dynamic simulation requires setting up a complex performance simulation environment and a significant amount of manpower to develop the test cases. Therefore, even after the RTL is ready, a significant amount of time and manpower is still required for preparation, and performance analysis results cannot be obtained in a timely manner. The completeness of the test cases determines the accuracy of the performance analysis results. For example, if the test cases do not cover the worst-case performance conditions, the performance analysis results will be optimistic and inconsistent with the final chip performance results. Dynamic simulation takes a long time and requires continuous iteration. For large SoC chips, it may take several days to obtain simulation results for a single test case. Even if a module in the RTL design is slightly modified, or if there are minor changes in the register slices between modules, performance simulation must be repeated. This consumes a lot of time.

[0054] Based on this, one or more embodiments of the present disclosure provide a circuit design performance analysis method, a circuit design performance analysis device, an electronic device, and a storage medium to solve the above technical problems.

[0055] At least one embodiment of the present disclosure provides a performance analysis method for circuit design, comprising: obtaining a constraint file for performance analysis and a design file of a circuit, wherein the constraint file includes multiple constraint conditions, and the constraint conditions are used to determine a performance path among multiple paths of the circuit; parsing the design file based on the multiple constraint conditions, and generating a performance analysis directed graph, wherein the performance analysis directed graph includes at least a starting point, an end point, and at least one intermediate node of a performance path in the circuit, and the performance path is a path among multiple paths of the circuit used to reflect the performance of the circuit; and calculating the bandwidth efficiency of the circuit based on the performance analysis directed graph, and the bandwidth efficiency is used to characterize the performance of the circuit design.

[0056] At least one embodiment of the present disclosure provides a performance analysis device for circuit design, comprising: a file acquisition module, configured to acquire a constraint file for performance analysis and a design file of a circuit, wherein the constraint file includes multiple constraint conditions, and the constraint conditions are used to determine a performance path among multiple paths of the circuit; a directed graph generation module, configured to parse the design file according to the multiple constraint conditions and generate a performance analysis directed graph, wherein the performance analysis directed graph includes at least a starting point, an end point, and at least one intermediate node of a performance path in the circuit, and the performance path is a path among the multiple paths of the circuit used to reflect the performance of the circuit; and a calculation module, configured to calculate the bandwidth efficiency of the circuit according to the performance analysis directed graph.

[0057] At least one embodiment of the present disclosure provides an electronic device, comprising: at least one processing device and a memory; wherein the memory stores a computer program, and when the computer program is executed by the at least one processing device, the performance analysis method of the circuit design described above is implemented.

[0058] At least one embodiment of the present disclosure provides a computer-readable storage medium having computer-executable instructions stored thereon, wherein when the instructions are executed by a processor, the performance analysis method of the circuit design described above is implemented.

[0059] The following will continue to introduce the embodiments of the present disclosure with reference to the accompanying drawings.

[0060] Figure 3 A schematic diagram of a performance analysis method for a circuit design provided according to an embodiment of the present disclosure is shown.

[0061] like Figure 3 As shown, the performance analysis method 300 of a circuit design includes the following steps:

[0062] Step S310 , obtaining a constraint file for performance analysis and a design file of a circuit, wherein the constraint file includes a plurality of constraint conditions, and the constraint conditions are used to determine a performance path among a plurality of paths of the circuit.

[0063] In this embodiment, the design file may come from a design database, and the design file may correspond to a SOC design, an RTL design, or a gate-level netlist. Optionally, the design file includes a system-level design file or a register transfer level design file. The constraint file is used to indicate the information of the performance path that needs to be analyzed, such as the starting point of the performance path, the end point of the performance path, the maximum transmission capacity, the clock, the black box path, the breakpoint, etc. The constraint condition corresponds to the information of the performance path, which can be used to determine the performance path among multiple paths of the circuit. The circuit in this embodiment includes a chip or a module in a chip. The performance path is a path that can reflect the performance of the circuit. For example, the performance path can be a predetermined path.

[0064] Optionally, the multiple constraints include at least a starting point of the performance path, an end point of the performance path, a maximum transmission capacity of the performance path, and a clock of the performance path. Optionally, the starting point defines the starting point of the performance path, which is an input / output port of a register or circuit module; the end point defines the end point of the performance path, which is an input / output port of a register or circuit module; the maximum transmission capacity defines the maximum transmission capacity that the performance path can support, which is a preset value or a parameter in the circuit design; and the clock defines a hash table of clock cycles, where the hash table keys are clock names and the hash table values are clock cycles.

[0065] Table 1 Example of the format of the constraint file

[0066]

[0067] Table 1 shows an example of the constraint file format. The variable is the constraint name, the description is the constraint definition, and the "Required" column in the last column indicates whether the corresponding constraint must exist. Using the performance path's start and end points, maximum transmission capacity, and clock, it's possible to determine which paths in the circuit meet the performance path requirements. Black-box paths and breakpoints help determine the maximum delay of the performance path.

[0068] In step S320, the design file is parsed according to multiple constraints, and a performance analysis directed graph is generated, wherein the performance analysis directed graph includes at least a starting point, an end point, and at least one intermediate node of a performance path in the circuit, and the performance path is a path among multiple paths of the circuit that is used to reflect the performance of the circuit.

[0069] After obtaining the constraint file and design file, the design file can be parsed according to the constraints to generate a performance analysis directed graph. For example, the performance analysis directed graph can reflect the delay between registers in the performance path. The nodes of the performance analysis directed graph represent registers, and each edge of the performance analysis directed graph represents a delay.

[0070] Optionally, the design file is parsed according to multiple constraints and a performance analysis directed graph is generated, including: determining a performance path according to the multiple constraints; abstracting the performance path to generate an abstract circuit directed graph, wherein the abstract circuit directed graph includes multiple nodes, the length between any two adjacent nodes in the multiple nodes is one clock cycle, and different clocks correspond to different clock cycle lengths; simplifying the abstract circuit directed graph to obtain a performance analysis directed graph.

[0071] Optionally, in the performance analysis method of circuit design provided according to at least one embodiment of the present disclosure, the performance path is abstracted to generate an abstract circuit directed graph, including: determining the end point of the performance path based on the end point of the performance path in multiple constraints; from the end point of the performance path, reversely determining multiple nodes in the performance path until reaching the starting point of the performance path, where the multiple nodes are register nodes; and adding a transmission direction between any two connected nodes among the multiple nodes to generate an abstract circuit directed graph.

[0072] When generating a performance analysis directed graph, a performance path can be determined based on multiple constraints. The performance path is a path in the circuit, such as Figure 4AAs shown. After determining the performance path, the performance path can be abstracted to generate an abstract circuit directed graph. For example, a depth-first search algorithm is used to obtain all registers from the end point of the performance path to the starting point of the performance path, and the registers are abstracted into nodes. The nodes are connected according to the direction of data transmission to form an abstract circuit directed graph. The abstract circuit directed graph can also be called a performance analysis abstract circuit (PAAC), which is an abstract form of the performance path. For example, Figure 4B A schematic diagram of an abstract circuit directed graph is shown. In the abstract circuit directed graph, in addition to representing registers, nodes can also be the starting point or end point of a performance path. That is, the nodes at both ends are the starting point and end point of the performance path, and the middle node is used to represent a register. The length between any two adjacent nodes in the abstract circuit directed graph is one clock cycle. It should be noted that different nodes may correspond to different clocks, so the length of the clock cycle of different clocks is different. Optionally, each node can also store the clock name of the register in the performance path.

[0073] Optionally, determining multiple nodes in the performance path in reverse from the end point of the performance path until reaching the starting point of the performance path is achieved by using a maximum path search algorithm.

[0074] Assume that the end point of the performance path is denoted by E, the starting point by S, the set of breakpoints by BP, and the black-box path hash table by BB. When using the maximum path search algorithm, first add a node E to the directed graph for the end point E, record its clock name, and obtain a list of driver nodes {X0,…,Xm} for node E, where m is an integer greater than or equal to 0. A driver node is a register or the input or output port of a module.

[0075] Then traverse {X0,…,Xm} and make the following judgments, including:

[0076] 1.1.1 If node Xi∈BP, then jump to Xi's driving node Xi+1, where i is an integer greater than or equal to 0 and less than or equal to m, and ∈ indicates belonging, otherwise jump to step 1.2;

[0077] 1.1.2 If a node Xi∈keys(BB), then take the value of BB{Xi} to obtain the starting point bs, period n, and clock name CLK of the black-box path, where Xi∈keys(BB) indicates that Xi belongs to the key of the black-box path hash table;

[0078] 1.1.2.1Continuously add n nodes and the clock name CLK corresponding to each node in the directed graph;

[0079] 1.1.2.2 Set Xi = bs, then skip to step 1.3;

[0080] 1.2 Add a node to the directed graph for node Xi (0≤i≤m) and record its clock name;

[0081] 1.3 If Xi = S, jump to Xi + 1 and restart the judgment process, otherwise jump to step 1.4;

[0082] 1.4 Obtain the list of driver nodes of node Xi and traverse the list of driver nodes of Xi according to the method of steps 1.1-1.3.

[0083] Figure 4A A schematic diagram illustrating a performance path provided according to an embodiment of the present disclosure is shown. Figure 4B Shown as Figure 4A Schematic diagram of the abstract circuit directed graph corresponding to the performance path shown.

[0084] like Figure 4A As shown, the performance path 400 includes five combinational logics 410-414 and eight registers 401-408. The combinational logics 410-414 do not affect the delay of the performance path 400, so they are not used as nodes when generating the abstract circuit directed graph.

[0085] According to the above method of generating an abstract circuit directed graph, the input port A is the starting point of the performance path, and the output port B is the end point of the performance path, which can be obtained as follows: Figure 4B The abstract circuit directed graph shown in Figure 4B In the example, nodes 401 to 408 correspond to Figure 4A Registers 401 to 408 are included in the performance path, where register 404 also serves as the end point of the performance path. The length between any two nodes is one clock cycle.

[0086] Use as Figure 4B The abstract circuit directed graph shown can already calculate the bandwidth effect of the circuit. However, since the abstract circuit directed graph usually has a large number of nodes, the calculation process is relatively complicated, and the calculation efficiency is not high.

[0087] Optionally, simplifying the abstract circuit directed graph includes: merging adjacent nodes without branches among the multiple nodes to reduce the number of the multiple nodes.

[0088] The abstract circuit directed graph can be simplified to produce a performance analysis directed graph with fewer nodes. Compared to the abstract circuit directed graph, the performance analysis directed graph retains only the starting point, end point, and some intermediate nodes. The performance analysis directed graph is also called a performance analysis graph (PAG). When simplifying the abstract circuit directed graph, some intermediate nodes can be merged to reduce the number of nodes. For example, nodes without branches can be merged, while nodes with branches are retained. Figure 4C A schematic diagram of a performance analysis directed graph provided according to an embodiment of the present disclosure is shown.

[0089] See also Figure 4B and Figure 4C , Figure 4B Nodes 403, 405, 406, 407, and 408 in the example are nodes without branches, while nodes 401 and 402 are nodes with branches. Therefore, nodes 401 and 402 can be retained, and nodes 403, 405, 406, 407, and 408 can be merged according to the path, retaining only the clock cycles. For example, in the path from node 401 to end point 404 via node 408, the length from node 401 to end point 404 is 2 clock cycles, so the simplified performance analysis directed graph is illustrated using only 2 clock cycles. In the path from node 402 to end point 404 via nodes 405-407, the length from node 402 to end point 404 is 4 clock cycles, so the simplified performance analysis directed graph is illustrated using only 2 clock cycles. There are 2 clock cycles in the path from node 402 to end point 404 via node 403, so the simplified performance analysis directed graph is illustrated using only 2 clock cycles.

[0090] In one implementation, when simplifying the abstract circuit directed graph, the end point of the performance path can be denoted as E, and the starting point of the performance path can be denoted as S. For the abstract circuit directed graph, each node is processed starting from the end point E until the starting point S. The processing method includes:

[0091] 2.1 Merge the nodes with out-degree ≤ 1 and in-degree ≤ 1 on the continuous paths in the directed graph of the abstract circuit. Out-degree and in-degree are the characteristics of the nodes in the directed graph, where in-degree refers to the number of edges pointing to a node, and out-degree refers to the number of edges starting from a node and pointing to other fixed points. For example, Figure 4B The out-degree of node 401 in is 2 and the in-degree is 1; Figure 4B The node 402 in has an in-degree of 1 and an out-degree of 2. The end point and the starting point here do not belong to the node to be merged. The out-degree is less than or equal to 1 and the in-degree is less than or equal to 1, which means that the node has at most one incoming edge and at most one outgoing edge. A continuous path requires that there are no breakpoints on the path. The merged nodes will become edges in the directed graph. For example, Figure 4B Node 408, node 403, and nodes 405-407 in will be merged into an edge with a length greater than 1 clock cycle. Figure 4C The length of the edge from node 401 to the end point is 2 clock cycles, the length of one edge from node 402 to the end point is 2 clock cycles, and the length of the other edge from node 402 to the end point is 4 clock cycles.

[0092] 2.2 Nodes that do not meet the above conditions (i.e., out-degree ≤ 1 and in-degree ≤ 1) are not merged, for example Figure 4C Nodes 401 and 402 in the dataset do not satisfy the out-degree ≤ 1 and in-degree ≤ 1, so nodes 401 and 402 are retained. The lengths of the edges between the retained nodes will change.

[0093] Figure 4B There is only one clock in the path, so the path delay = side length / clock frequency, that is, the number of clock cycles / clock frequency.

[0094] Step S330 : Calculate the bandwidth efficiency of the circuit based on the performance analysis directed graph. The bandwidth efficiency is used to characterize the performance of the circuit design.

[0095] Optionally, calculating the bandwidth efficiency of the circuit according to the performance analysis directed graph includes: calculating the bandwidth efficiency of the performance path according to the nodes and path delays between the nodes in the performance analysis directed graph.

[0096] In this embodiment, the bandwidth efficiency of a performance path is equal to the maximum transmission capacity of the performance path divided by the maximum path delay in the performance path. Figure 4C The performance analysis directed graph shown in Figure 1 has three paths from the starting point to the end point, and the corresponding delays are 3 clock cycles, 4 clock cycles, and 6 clock cycles respectively. Figure 4C The maximum transmission capacity of the performance path in the performance analysis directed graph shown is 3. It takes 3 clock cycles to fully send the 3 commands corresponding to the maximum transmission capacity. Therefore, the bandwidth efficiencies corresponding to the three paths are 3 / 3 = 100%, 3 / 4 = 75%, and 3 / 6 = 50%, respectively. Although the bandwidth efficiency of one of the three paths reaches 100%, the overall bandwidth efficiency of the circuit corresponding to Figure 4c is equal to 50%.

[0097] Optionally, the bandwidth efficiency of the performance path is calculated based on the path delay between nodes in the performance analysis directed graph, including: determining the branch path with the longest delay between the starting point and the end point of the performance path; and calculating the bandwidth efficiency of the performance path based on the maximum transmission capacity among multiple constraints and its corresponding operating frequency and the delay of the branch path with the longest delay.

[0098] In some cases, a performance analysis directed graph may have multiple clocks, so using clock cycles to represent the path delay between nodes is not accurate. To calculate bandwidth efficiency, you need to know the maximum transmission capacity, its corresponding operating frequency, and the maximum path delay of the performance path. For example, assuming the maximum path delay is 24ns and the maximum transmission capacity is 16 (corresponding to an operating frequency of 1GHz), the bandwidth efficiency is 16 / 1GHz / 24ns = 66.7%. The operating frequency in this example refers to the operating frequency of the command cache, and the number of entries in the command cache corresponds to the maximum transmission capacity.

[0099] According to an embodiment of the present disclosure, a performance analysis method for circuit design is provided. The performance analysis method includes obtaining a constraint file for performance analysis and a design file of the circuit, wherein the constraint file includes multiple constraint conditions, and the constraint conditions are used to determine the performance path among multiple paths of the circuit; parsing the design file according to the multiple constraint conditions and generating a performance analysis directed graph, wherein the performance analysis directed graph includes at least the starting point, the end point, and at least one intermediate node of the performance path in the circuit, and the performance path is a path among multiple paths of the circuit used to reflect the performance of the circuit; and calculating the bandwidth efficiency of the circuit according to the performance analysis directed graph, wherein the bandwidth efficiency is used to characterize the performance of the circuit design. By executing this performance analysis method, the bandwidth efficiency of the circuit can be analyzed and obtained through the design file and the constraint file, which has higher accuracy than manual analysis and does not require a lot of time. It can improve the analysis efficiency while ensuring the accuracy of the analysis.

[0100] The performance analysis method of the circuit design provided in accordance with the embodiment of the present disclosure only needs to obtain the design file and the constraint file to perform the analysis. It does not require a complex simulation environment, nor does it require the development of test cases. The analysis can be started in the early stage when the RTL code or file RTL is prepared, so that performance problems can be discovered early and labor costs can be saved. Static analysis is performed on the circuit, and the analysis speed is faster than dynamic simulation. When the module design or the register slice between modules changes, the analysis results can be quickly obtained even for the modified design, which can speed up the chip development cycle. In addition, the accuracy of the performance analysis is high. Since static analysis can always find the maximum delay of the path and obtain the bandwidth efficiency in the worst case, the accuracy of the performance analysis is only related to the design file and does not depend on the test case.

[0101] Optionally, according to the performance analysis method of circuit design provided in at least one embodiment of the present disclosure, the method further includes: determining whether the circuit meets preset performance requirements based on bandwidth efficiency; when the circuit does not meet the preset performance requirements, increasing the cache capacity of the circuit to increase the corresponding maximum transmission capacity of the circuit.

[0102] When bandwidth efficiency is obtained, it can be used to determine whether the circuit meets preset performance requirements, for example, whether the bandwidth efficiency is greater than a preset threshold, such as 80% or 100%. If the circuit does not meet the preset performance requirements, the circuit's cache capacity is increased to increase the circuit's maximum transmission capacity. In other words, by increasing the circuit's maximum transmission capacity, bandwidth efficiency is improved without changing the register design within the circuit.

[0103] Figure 5A An example of a circuit module provided according to an embodiment of the present disclosure is shown. Figure 5B Shown as Figure 5A Schematic diagram of the abstract circuit directed graph and performance analysis directed graph of the circuit module shown.

[0104] exist Figure 5A In the example, the top.buf submodule is a command buffer with 16 entries, corresponding to a maximum transfer capacity of 16. This means that a maximum of 16 consecutive requests can be issued before a response is received. The performance path to be analyzed starts at the output port req of the top.buf submodule, denoted as top.buf.req. The performance path ends at the input port resp of the top.buf submodule, denoted as top.buf.resp.

[0105] There are two clocks in the circuit module 500 , where the clock period of clock 1 (Clock 1) is 2.5 ns and the clock period of clock 2 (Clock 2) is 1 ns. In the figure, registers and black box paths operating at different clocks are marked in white and gray respectively.

[0106] There are two black box paths in circuit module 500. One black box path runs from input port In to output port Out of submodule inst, and the other black box path runs from output port outportA to input port inportB. Both black box paths operate on clock 2, with delay cycles of 3 and 2, respectively.

[0107] There is also a breakpoint in the circuit module 500 (located at register 11), and the paths starting from this breakpoint do not need to participate in the analysis of the target performance path, that is, Figure 5A Register 5 and input port inportC.

[0108] Assume that the constraints recorded in the corresponding constraint file include: the end point of the performance path is top.buf.resp, the starting point of the performance path is top.buf.req, the clocks include clock 1 and clock 2, black box path information, and breakpoint information.

[0109] After obtaining the constraint file and design file, you can get Figure 5BThe abstract circuit directed graph and performance analysis directed graph are shown in .

[0110] First, an abstract circuit directed graph is obtained according to the constraint file and the design file.

[0111] refer to Figure 5A First, we determine the driver node for the performance path's endpoint, top.buf.resp, as register 1. Register 1's clock is Clock 1, so we add a node E, which also represents the performance path's endpoint. Next, we determine register 1's driver node as register 2. Register 2 isn't in the breakpoint set or the black-box path, so we add node 501 and an edge. Register 2's clock is Clock 1, so node 501 records its clock as Clock 1.

[0112] Next, we determine the driver node for register 2. Register 2 has multiple driver nodes, including register 3 and register 11. Register 11 is in the breakpoint set, so we discard it. Register 3 is neither in the breakpoint set nor in the black-box path, so we add a node 502 and an edge for register 3. Register 3's clock is Clock 2, so node 502 records its clock as Clock 2.

[0113] Determine all the driving nodes of register 3 and find that the driving nodes of register 3 are the output port top.inst.Out of inst and register 4. Since top.inst.Out is in the black box path, some processing needs to be performed on the black box path.

[0114] The black-box path starts at top.inst.In, has a period of 3, and a clock of Clock 2. Therefore, we need to add three nodes to this black-box path: node 513, node 512, and node 511, all with a clock of Clock 2. We continue to identify the driver node of top.inst.In, finding that it is register 8. Register 8 is not in the breakpoint set or the black-box path. We add node 509 and an edge to it, and continue tracing back to register 8 and its upstream driver nodes until we reach the performance analysis starting point, top.buf.req. We then add node S to the performance analysis starting point, marking the end of the path.

[0115] Another driving node of register 3 is register 4. Register 4 is not in the breakpoint set and black box path. A node 503 and an edge are added to register 4. The driving nodes of register 4 and its upstream are determined and processed in a similar way until all paths are traversed. Finally, Figure 5BAbstract circuit directed graph 500a. Each edge in abstract circuit directed graph 500a is one clock cycle long. However, because there are two clocks, one clock cycle of clock 1 is 1 ns, and one clock cycle of clock 2 is 2.5 ns. The duration of an edge entering a node is the length of the clock cycle of the clock being input. For example, the duration of the edge from node 507 to node 506 is 2.5 ns, not 1 ns.

[0116] After obtaining the abstract circuit directed graph 500a, the abstract circuit directed graph 500a can be further simplified to obtain the performance analysis directed graph 500b. The simplification process starts from the performance path end point E. The simplification process is similar to that from the abstract circuit directed graph. Figure 4B Abstract Circuit Directed Figure 4C The difference is that the abstract circuit directed graph 500a involves two clocks, so here only the two clocks need to be converted. For example, the delay of a single clock cycle of clock 2 is 2.5 times that of clock 1, so it is only necessary to multiply the edge corresponding to clock 2 by 2.5 and remember to convert it to the length of the edge corresponding to clock 1. Continuing to refer to the abstract circuit directed graph 500a and the performance analysis directed graph 500b, the simplification process first merges the nodes according to the out-degree and in-degree conditions. Node 507, node 510, node 511, node 512, nodes 503-505, and node 501 are all merged, and node 508, node 509, node 506, node 513, and node 502 are retained. After the merger, the lengths of the edges between the retained nodes change accordingly.

[0117] After obtaining the performance analysis directed graph 500b, it can be determined that the maximum path delay between node S and node E is 24ns, while the maximum transmission capacity of the performance path is 16 (corresponding to an operating frequency of 1 GHz). The calculated bandwidth efficiency is 16 / 24 = 66.7%. The command cache in the top.buf submodule needs to be increased to 24 to achieve 100% bandwidth efficiency. After determining the bandwidth efficiency, the command cache in the top.buf submodule can be modified. For example, the number of command caches can be increased in the early stages of circuit design, allowing performance defects in the circuit to be discovered and corrected as early as possible.

[0118] At least one embodiment of the present disclosure further provides a performance analysis device for circuit design, comprising: a file acquisition module, configured to acquire a constraint file for performance analysis and a design file of a circuit, wherein the constraint file includes multiple constraint conditions, and the constraint conditions are used to determine a performance path among multiple paths of the circuit; a directed graph generation module, configured to parse the design file according to the multiple constraint conditions and generate a performance analysis directed graph, wherein the performance analysis directed graph includes at least a starting point, an end point and at least one intermediate node of a performance path in the circuit, and the performance path is a path among the multiple paths of the circuit used to reflect the performance of the circuit; and a calculation module, configured to calculate the bandwidth efficiency of the circuit according to the performance analysis directed graph.

[0119] Figure 6 A schematic diagram of a performance analysis device for a circuit design provided according to an embodiment of the present disclosure is shown.

[0120] like Figure 6 As shown, the circuit design performance analysis device 600 includes a file acquisition module 610, a directed graph generation module 620, and a calculation module 630. The file acquisition module 610 is connected to the directed graph generation module 620 and the calculation module 630. The directed graph generation module 620 is connected to the calculation module 630.

[0121] The file acquisition module 610 is configured to acquire a constraint file for performance analysis and a design file of a circuit, wherein the constraint file includes a plurality of constraint conditions, and the constraint conditions are used to determine a performance path among a plurality of paths of the circuit.

[0122] The directed graph generation module 620 is configured to parse the design file according to multiple constraints and generate a performance analysis directed graph, wherein the performance analysis directed graph includes at least the starting point, the end point and at least one intermediate node of the performance path in the circuit, and the performance path is a path among multiple paths of the circuit used to reflect the performance of the circuit.

[0123] The calculation module 630 is configured to calculate the bandwidth efficiency of the circuit according to the performance analysis directed graph.

[0124] The circuit design performance analysis device 600 provided in this embodiment can execute the performance analysis method in the above-mentioned method embodiment and achieve the same technical effect. For details, please refer to the implementation of the above-mentioned performance analysis method, which will not be expanded here. The circuit design performance analysis device 600 provided in this embodiment can be implemented as software, hardware, or a combination of software and hardware.

[0125] Optionally, in the performance analysis device for circuit design provided according to at least one embodiment of the present disclosure, the multiple constraints include at least the starting point of the performance path, the end point of the performance path, the maximum transmission capacity of the performance path, and the clock of the performance path.

[0126] Optionally, in the performance analysis device of the circuit design provided according to at least one embodiment of the present disclosure, the starting point defines the starting point of the performance path, which is the input and output port of the register or circuit module; the end point defines the end point of the performance path, which is the input and output port of the register or circuit module; the maximum transmission capacity defines the maximum transmission capacity that the performance path can support, and the maximum transmission capacity is a preset value or a parameter in the circuit design; the clock defines a hash table of clock cycles, the key of the hash table is the clock name, and the value of the hash table is the clock cycle.

[0127] Optionally, in the performance analysis device of the circuit design provided according to at least one embodiment of the present disclosure, the directed graph generation module 620 is further configured to determine a performance path based on multiple constraints; abstract the performance path to generate an abstract circuit directed graph, wherein the abstract circuit directed graph includes multiple nodes, and the length between any two adjacent nodes in the multiple nodes is one clock cycle, and different clocks correspond to different clock cycle lengths; simplify the abstract circuit directed graph to obtain a performance analysis directed graph.

[0128] Optionally, in the performance analysis device for circuit design provided according to at least one embodiment of the present disclosure, the directed graph generation module 620 is further configured to merge adjacent nodes without branches among the multiple nodes to reduce the number of the multiple nodes.

[0129] Optionally, in the performance analysis device for circuit design provided according to at least one embodiment of the present disclosure, the directed graph generation module 620 is further configured to determine the end point of the performance path based on the end point of the performance path in multiple constraints; from the end point of the performance path, reversely determine multiple nodes in the performance path until reaching the starting point of the performance path, where the multiple nodes are register nodes; and add a transmission direction between any two connected nodes among the multiple nodes to generate an abstract circuit directed graph.

[0130] Optionally, in the performance analysis device for circuit design provided according to at least one embodiment of the present disclosure, reversely determining multiple nodes in the performance path from the end point of the performance path until reaching the starting point of the performance path is achieved using a maximum path search algorithm.

[0131] Optionally, in the performance analysis device for circuit design provided according to at least one embodiment of the present disclosure, the calculation module 630 is further configured to calculate the bandwidth efficiency of the performance path based on the nodes and path delays between nodes in the performance analysis directed graph.

[0132] Optionally, in the performance analysis device of the circuit design provided according to at least one embodiment of the present disclosure, the calculation module 630 is also configured to determine the branch path with the longest delay between the starting point and the end point of the performance path; and calculate the bandwidth efficiency of the performance path based on the maximum transmission capacity among multiple constraints and the clock frequency of the branch path with the longest delay.

[0133] Optionally, the performance analysis device for circuit design provided according to at least one embodiment of the present disclosure further includes an adjustment module, which is configured to determine whether the circuit meets preset performance requirements based on bandwidth efficiency; when the circuit does not meet the preset performance requirements, increase the cache capacity of the circuit to increase the corresponding maximum transmission capacity of the circuit.

[0134] Optionally, in the performance analysis device for circuit design provided according to at least one embodiment of the present disclosure, the design file includes a system-level design file or a register transfer-level design file.

[0135] At least one embodiment of the present disclosure provides an electronic device, comprising: at least one processing device and a memory; wherein the memory stores a computer program, and when the computer program is executed by the at least one processing device, the above-mentioned performance analysis method is implemented.

[0136] Figure 7 A schematic diagram of an electronic device provided according to an embodiment of the present disclosure is shown.

[0137] For example, Figure 7 As shown, in some examples, the electronic device 700 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage device 708 into a random access memory (RAM) 703. For example, the processing device may include a performance analysis device for the circuit design of any embodiment of the present disclosure. Various programs and data required for the operation of the computer system are also stored in the RAM 703. The processor 701, ROM 702, and RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0138] For example, the following components may be connected to the I / O interface 705: an input device 706 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, and the like; an output device 707 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, and the like; a storage device 708 including, for example, a magnetic tape, a hard disk, and the like; and a communication device 709, which may also include, for example, a network interface card such as a LAN card or a modem. The communication device 709 may allow the electronic device 700 to communicate with other devices wirelessly or wired to exchange data, performing communication processing via a network such as the Internet. A drive 710 is also connected to the I / O interface 705 as needed. Removable media 711, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, and the like, is installed in the drive 710 as needed, so that computer programs read therefrom can be installed into the storage device 708 as needed.

[0139] For example, the electronic device 700 may further include a peripheral interface (not shown in the figure). The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 709 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular telephone network, a wireless local area network (LAN), and / or a metropolitan area network (MAN). The wireless communication may use any of a variety of communication standards, protocols, and technologies, including but not limited to Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.7a, IEEE 802.7b, IEEE 802.7g, and / or IEEE 802.7n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or short message service (SMS), or any other suitable communication protocol.

[0140] The electronic devices in the embodiments of the present disclosure may include but are not limited to mobile terminals such as chips, components of chips, mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 7 The electronic device shown is only an example and should not limit the functions and scope of use of the embodiments of the present disclosure.

[0141] For example, the electronic device 700 can be any device such as a mobile phone, tablet computer, laptop computer, e-book, game console, television, digital photo frame, navigator, server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure do not limit this.

[0142] Optionally, at least one embodiment of the present disclosure further provides a computer-readable storage medium having computer-executable instructions stored thereon, wherein when the instructions are executed by a processor, the above-mentioned performance analysis method 300 is implemented.

[0143] It should be noted that the computer-readable medium mentioned above in the present disclosure may be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In embodiments of the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, device, or device. In embodiments of the present disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium may be transmitted using any suitable medium, including but not limited to wires, optical cables, RF (radio frequency), etc., or any suitable combination thereof.

[0144] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0145] The basic principles of the present application have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, and effects mentioned in this application are merely illustrative and not restrictive, and it should not be assumed that these advantages, strengths, and effects are required of each embodiment of this application. In addition, the specific details disclosed above are merely illustrative and facilitating understanding, and are not restrictive. The above details do not limit this application to necessarily being implemented using the above specific details.

[0146] It is worth noting that the step flow charts and the above method descriptions in this application are only illustrative examples and are not intended to require or imply that the steps of each embodiment must be performed in the order given. Some steps can be performed in parallel, independently of each other, or in other appropriate orders. In addition, words such as "secondly," "then," "next," etc. are not intended to limit the order of the steps; these words are only used to guide the reader through the description of these methods.

[0147] The block diagrams of the devices, apparatuses, equipment, and systems described in this application are intended only as illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. It should also be noted that in the apparatuses and methods of this application, the components or steps may be decomposed and / or recombined. Such decompositions and / or recombinations shall be considered equivalents of this application.

[0148] In addition to the above non-limiting disclosure, the present disclosure also has the following points to be explained:

[0149] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0150] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0151] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A performance analysis method for circuit design, comprising: Obtaining a constraint file for performance analysis and a design file of a circuit, wherein the constraint file includes a plurality of constraint conditions, and the constraint conditions are used to determine a performance path among a plurality of paths of the circuit; parsing the design file according to the plurality of constraint conditions, and generating a performance analysis directed graph, wherein the performance analysis directed graph includes at least a starting point, an end point, and at least one intermediate node of a performance path in the circuit, and the performance path is a path among the plurality of paths of the circuit that is used to reflect the performance of the circuit; and The bandwidth efficiency of the circuit is calculated according to the performance analysis directed graph, and the bandwidth efficiency is used to characterize the performance of the circuit design.

2. The method according to claim 1, wherein The multiple constraint conditions include at least a starting point of the performance path, an end point of the performance path, a maximum transmission capacity of the performance path, and a clock of the performance path.

3. The method according to claim 2, wherein: The starting point defines the starting point of the performance path, which is an input / output port of a register or a circuit module; the end point defines the end point of the performance path, which is an input / output port of a register or a circuit module; The maximum transmission capacity defines the maximum transmission capacity that the performance path can support, and the maximum transmission capacity is a preset value or a parameter in the circuit design; the clock defines a hash table of clock cycles, the key of the hash table is the clock name, and the value of the hash table is the clock cycle.

4. The method according to claim 1, wherein The step of parsing the design file according to the plurality of constraints and generating a performance analysis directed graph includes: determining the performance path according to the plurality of constraints; Abstracting the performance path to generate an abstract circuit directed graph, wherein the abstract circuit directed graph includes a plurality of nodes, a length between any two adjacent nodes among the plurality of nodes is one clock cycle, and different clocks correspond to different clock cycle lengths; The abstract circuit directed graph is simplified to obtain the performance analysis directed graph.

5. The method according to claim 4, wherein Simplifying the abstract circuit directed graph includes: Adjacent nodes without branches among the multiple nodes are merged to reduce the number of the multiple nodes.

6. The method according to claim 4, wherein: The abstracting of the performance path to generate an abstract circuit directed graph includes: determining an end point of the performance path according to end points of the performance path in the plurality of constraints; From an end point of the performance path, reversely determining the plurality of nodes in the performance path until reaching a starting point of the performance path, wherein the plurality of nodes are register nodes; A transmission direction is added between any two connected nodes among the plurality of nodes to generate the abstract circuit directed graph.

7. The method according to claim 6, wherein: The step of reversely determining the multiple nodes in the performance path from the end point of the performance path until reaching the starting point of the performance path is achieved by using a maximum path search algorithm.

8. The method according to claim 1, wherein Calculating the bandwidth efficiency of the circuit according to the performance analysis directed graph includes: The bandwidth efficiency of the performance path is calculated based on the nodes and path delays between the nodes in the performance analysis directed graph.

9. The method according to claim 8, wherein Calculating the bandwidth efficiency of the performance path based on the path delays between nodes in the performance analysis directed graph includes: Determining a branch path with the longest delay between a starting point and an end point of the performance path; The bandwidth efficiency of the performance path is calculated according to the maximum transmission capacity and its corresponding operating frequency in the multiple constraints and the delay of the branch path with the longest delay.

10. The method according to claim 1, further comprising: determining, based on the bandwidth efficiency, whether the circuit meets a preset performance requirement; When the circuit does not meet the preset performance requirement, the cache capacity of the circuit is increased to increase the maximum transmission capacity corresponding to the circuit.

11. The method according to claim 1, wherein The design file includes a system-level design file or a register transfer-level design file.

12. A performance analysis device for a circuit design, comprising: a file acquisition module configured to acquire a constraint file for performance analysis and a design file of a circuit, wherein the constraint file includes a plurality of constraint conditions, and the constraint conditions are used to determine a performance path among a plurality of paths of the circuit; a directed graph generation module configured to parse the design file according to the plurality of constraints and generate a performance analysis directed graph, wherein the performance analysis directed graph includes at least a start point, an end point, and at least one intermediate node of a performance path in the circuit, the performance path being a path among a plurality of paths in the circuit that is used to reflect the performance of the circuit; and The calculation module is configured to calculate the bandwidth efficiency of the circuit according to the performance analysis directed graph.

13. An electronic device comprising: at least one processor and memory; The memory stores a computer program, and when the computer program is executed by the at least one processor, the method according to any one of claims 1 to 11 is implemented.

14. A computer-readable storage medium having computer-executable instructions stored thereon, wherein: When the instructions are executed by the processor, the method according to any one of claims 1 to 11 is implemented.

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