Data processing device and method, electronic equipment and storage medium

Abstract

The invention provides a data processing device, and relates to the technical field of artificial intelligence, in particular to the technical field of chips, large models and distributions. The device comprises a first processing unit configured to read at least one initial floating-point number from a first storage unit; according to the at least one initial floating-point number, at least one target floating-point number is obtained, the index bit of the target floating-point number comprises at least one first code and a second code, the first code comprises at least one preset value, and the first code is located at the target position of the index bit of the target floating-point number; the target position is at least one of a starting position and an ending position of an index bit of the target floating-point number; deleting a target code of the at least one target floating-point number to obtain at least one processed floating-point number, the target code being determined according to the at least one first code; and outputting at least one processed floating-point number. The invention further provides a data processing method, electronic equipment and a storage medium.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, and in particular to the fields of chips, large models, and distributed technology. More specifically, the present disclosure provides a data processing device, method, electronic device, and storage medium. Background Art

[0002] With the development of artificial intelligence technology, the application scenarios of large models are constantly increasing. During the training or inference process of large models, floating-point data can be used. Summary of the Invention

[0003] The present disclosure provides a data processing apparatus, method, device, and storage medium.

[0004] According to one aspect of the present disclosure, a data processing device is provided, the device including: a first storage unit configured to store at least one initial floating-point number; a first processing unit configured to: read the at least one initial floating-point number from the first storage unit; obtain at least one target floating-point number based on the at least one initial floating-point number, wherein the exponent bits of the target floating-point number include at least one first code and a second code, the first code includes at least one preset value, the first code is located at a target position of the exponent bits of the target floating-point number, and the target position is at least one of a starting position and an ending position of the exponent bits of the target floating-point number; delete the target code of the at least one target floating-point number to obtain at least one processed floating-point number, wherein the target code is determined based on the at least one first code; and output the at least one processed floating-point number.

[0005] According to another aspect of the present disclosure, a data processing device is provided, comprising: a second storage unit configured to receive at least one processed floating-point number, wherein the processed floating-point number comes from the device provided by the present disclosure; a second processing unit configured to: add a preset value to the exponent bits of the at least one processed floating-point number to obtain at least one target floating-point number; and obtain at least one initial floating-point number based on the at least one target floating-point number.

[0006] According to another aspect of the present disclosure, an electronic device is provided, including a data processing device provided by the present disclosure.

[0007] According to another aspect of the present disclosure, a data processing system is provided, including: two data processing devices provided by the present disclosure.

[0008] According to another aspect of the present disclosure, a data processing method is provided, the method comprising: obtaining at least one target floating-point number based on at least one initial floating-point number, wherein the exponent bits of the target floating-point number include at least one first code and a second code, the first code includes at least one preset value, and the first code is located at a target position of the exponent bits of the target floating-point number, the target position being at least one of a starting position and an ending position of the exponent bits of the target floating-point number; deleting a target code of the at least one target floating-point number to obtain at least one processed floating-point number, wherein the target code is determined based on the at least one first code; and outputting the at least one processed floating-point number.

[0009] According to another aspect of the present disclosure, a data processing method is provided, comprising: receiving at least one processed floating-point number, wherein the processed floating-point number comes from another method provided by the present disclosure; adding a preset value to an exponent bit of the at least one processed floating-point number to obtain at least one target floating-point number; and obtaining at least one initial floating-point number based on the at least one target floating-point number.

[0010] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method provided according to the present disclosure.

[0011] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided. The computer instructions are used to cause a computer to execute the method provided according to the present disclosure.

[0012] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, which implements the method provided according to the present disclosure when executed by a processor.

[0013] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0015] Figure 1 is a schematic diagram of encoding of brain floating point numbers according to one embodiment of the present disclosure;

[0016] Figure 2 is a schematic block diagram of a data processing device according to an embodiment of the present disclosure;

[0017] Figure 3 is a schematic diagram of an initial floating-point number according to an embodiment of the present disclosure;

[0018] Figure 4 is a schematic diagram of an initial floating-point number according to another embodiment of the present disclosure;

[0019] Figure 5A is a schematic diagram of an initial floating-point number according to an embodiment of the present disclosure;

[0020] Figure 5B is a schematic diagram of a target floating-point number according to one embodiment of the present disclosure;

[0021] Figure 6 is a schematic block diagram of a data processing device according to another embodiment of the present disclosure;

[0022] Figure 7 is a schematic block diagram of an electronic device according to an embodiment of the present disclosure;

[0023] Figure 8 is a schematic block diagram of a data processing system according to an embodiment of the present disclosure;

[0024] Figure 9 is a flow chart of a data processing method according to an embodiment of the present disclosure;

[0025] Figure 10 is a flowchart of a data processing method according to another embodiment of the present disclosure; and

[0026] Figure 11 is a block diagram of an electronic device to which a data processing method according to an embodiment of the present disclosure can be applied. DETAILED DESCRIPTION

[0027] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0028] Floating-point numbers are the opposite of fixed-point numbers. Fixed-point numbers in computers use a fixed-point format with a fixed decimal point, which is a manually set position. For example, with fixed-point integers, the decimal point can be placed at the end of the numeric digits. Another example is with fixed-point decimal numbers, where the most significant digit is placed after the decimal point. Due to computer word length limitations, when data with a wide range of values needs to be represented, it cannot be directly represented using fixed-point decimals or fixed-point integers.

[0029] Floating-point numbers can be composed of a mantissa and an exponent. The encoding rules for floating-point numbers include: the mantissa is a decimal, represented by an n+1-bit signed fixed-point decimal; the number of bits n+1 determines the precision of the floating-point number. The longer the mantissa, the higher the precision that can be represented. n is an integer greater than 0. The exponent must be an integer, represented by a k+1-bit signed fixed-point integer; the number of bits k+1 determines the numerical range represented by the floating-point number, that is, the data size or the actual position of the decimal point in the data; the exponent determines the positive or negative sign of the exponent. The longer the exponent, the larger the range that can be represented. k is an integer greater than 0

[0030] Neural network model processing of data can be divided into two phases: training and inference. During the training phase, the parameters of the neural network model are adjusted using a known dataset to obtain a trained neural network model. During the training phase, the data in the dataset must have high precision. Floating-point data can be used in the training phase of the neural network.

[0031] Floating point numbers can include single-precision floating point numbers (Float Point 32, FP32), tensor single-precision floating point numbers (TensorFloat 32, TF32), half-precision floating point numbers (Float Point 32, FP16), and brain floating point numbers (Brain FloatPoint 16, BF16).

[0032] Single-precision floating-point numbers and tensor single-precision floating-point numbers have higher precision. The bit width of these two types of floating-point numbers is 32 bits, which results in the amount of data accessed being about twice as high as that of half-precision floating-point numbers, and also requires more computing resources. When processing data of the single-precision floating-point type and tensor single-precision floating-point number type, the performance of artificial intelligence chips is poor. During the training phase, higher performance can be achieved if half-precision floating-point numbers or brain floating-point numbers are used. Fixed-point numbers (such as 4-bit fixed-point numbers or 8-bit fixed-point numbers) have a smaller bit width and lower precision, and can be used in the inference phase of neural network models. The following will take brain floating-point numbers as an example for further explanation.

[0033] Figure 1 Schematic diagram of encoding of floating-point numbers according to an embodiment of the present disclosure.

[0034] Floating point numbers can be represented in computers through encoding. The encoding of floating point numbers includes a sign bit (sign) 101, an exponent bit (exponent) 102, and a fraction bit (fraction) 103.

[0035] In some embodiments, the sign bit of the floating point number is 1 bit, the number of exponent bits can be 8 bits, and the number of mantissa bits is 7 bits.

[0036] The sign bit is used to indicate the sign of the floating point number. For example, 0 can indicate that the floating point number is positive, and 1 can indicate that the floating point number is negative. Figure 1 As shown, the 15th bit of the floating point number can be a sign bit.

[0037] The exponent bits can represent the range of floating point values. For example, the more exponent bits there are, the wider the range that can be represented. Figure 1 As shown, the 14th to 7th bits of the floating point number can be exponent bits.

[0038] The precision of the floating point number can be determined by the number of mantissa bits and the number of exponent bits. The more mantissa bits there are, the higher the precision of the floating point number. Figure 1 As shown, the 6th to 0th bits of the floating point number can be the mantissa bits.

[0039] The brain floating point number BF16 can be expressed as:

[0040] BF16=(-1) s *1.M*2 (E-127) (Formula 1)

[0041] M may be the value corresponding to the mantissa bit 103. E may be the value corresponding to the exponent bit 102. s may be the value of the sign bit.

[0042] These large models can be trained using floating-point numbers, helping to avoid data overflow and underflow. During large model training, intermediate model results and gradients can be transmitted using floating-point numbers. However, interconnection bandwidth between different AI chips is limited to 400 gigabytes (GB).

[0043] Therefore, in order to fully utilize the data transmission bandwidth, the present disclosure provides a data processing device, which will be described below.

[0044] Figure 2 is a schematic block diagram of a data processing device according to an embodiment of the present disclosure.

[0045] like Figure 2 As shown, the device 21 may include a first storage unit 211 and a first processing unit 212 .

[0046] The first storage unit 211 may be configured to store at least one initial floating point number. For example, the initial floating point number may be the aforementioned brain floating point number.

[0047] The first processing unit 212 can be configured to read at least one initial floating-point number. In the disclosed embodiment, the first processing unit can be a processor composed of multiple processing cores or a single processor core. The first processing unit 212 can read at least one initial floating-point number from the first storage unit 211.

[0048] The first processing unit 212 may also be configured to obtain at least one target floating-point number according to the at least one initial floating-point number.

[0049] In the embodiment of the present disclosure, at least one target floating-point number can be obtained in various ways based on at least one initial floating-point number. For example, the initial floating-point number can be used as the target floating-point number.

[0050] In the embodiment of the present disclosure, the target floating point number may also be a brain floating point number. The exponent bits of the target floating point number may include the 14th to 7th bits of the floating point number.

[0051] In the disclosed embodiment, the exponent bit of the target floating-point number includes at least one first encoding and a second encoding. The first encoding includes at least one preset value, and the first encoding is located at the target position of the exponent bit of the target floating-point number, and the target position is at least one of the starting position and the ending position of the exponent bit of the target floating-point number. For example, taking the first encoding of the target floating-point number as the 14th bit of the floating-point number as an example, the second encoding can be the 13th to the 7th bit of the floating-point number. Thus, the first encoding of the target floating-point number is located at the starting position of the exponent bit. It is understandable that the target position can include at least one bit of the exponent bit.

[0052] The first processing unit 212 can also be configured to delete the target encoding of at least one target floating-point number to obtain at least one processed floating-point number. In the disclosed embodiment, the target encoding is determined based on at least one first encoding. For example, taking the first encoding of the target floating-point number as the 14th bit of the floating-point number as an example, the first encoding can be used as the target encoding. The target encoding can be deleted from the target floating-point number to obtain the processed floating-point number. The processed floating-point number can include the sign bit and mantissa bits of the target floating-point number, and can also include bits 13 to 7 of the target floating-point number.

[0053] The first processing unit 212 may also be configured to output at least one processed floating-point number.

[0054] In the embodiment of the present disclosure, the processed floating-point number may be output to the first storage unit, or may be output to a storage unit of an external processing device, which is not limited in the present disclosure.

[0055] The disclosed embodiments reduce the number of exponent bits, making the data transmission bandwidth required for processed floating-point numbers smaller than that required for the original floating-point numbers. This reduces the amount of data required for floating-point number transmission, fully utilizes bandwidth resources, and improves data processing efficiency.

[0056] It can be understood that the above description uses the initial floating-point number as the target floating-point number as an example to illustrate the present disclosure, which will be further described below in conjunction with relevant embodiments.

[0057] Figure 3 is a schematic diagram of an initial floating-point number according to an embodiment of the present disclosure.

[0058] like Figure 3 As shown, the floating point number F31 may be an initial floating point number. The exponent bits of the floating point number F31 are "01111101". The floating point number F31 may be used as a target floating point number.

[0059] In the disclosed embodiment, at least one preset value at the start or end position of the exponent bit can be used as the first code. The preset value can be zero. For example, the 14th bit "0" of the floating-point number F31 is a preset value. The 13th bit "1" of the floating-point number F31 is not a preset value. Therefore, the 14th bit "0" of the floating-point number F31 can be used as the first code.

[0060] In the disclosed embodiment, the first position of the first non-zero value in the exponent bit can be determined. Based on the first position, multiple consecutive values are determined from the exponent bit as the second code. For example, the 13th bit "1" of the floating-point number F31 is a non-zero value. Therefore, the 13th bit to the 7th bit of the floating-point number F31, "1111101", can be used as the second code.

[0061] In the disclosed embodiment, the first encoding can be used as the target encoding. This target encoding can be deleted to obtain a processed floating-point number. For example, the 14th bit "0" of the floating-point number F31, which is the first encoding, can be deleted to obtain the processed floating-point number "011111011100001". Through the disclosed embodiment, the amount of data required to transmit floating-point numbers is reduced by at least 6.25%, helping to improve bandwidth utilization efficiency.

[0062] It can be understood that the present disclosure is described above in conjunction with one target floating-point number, but the present disclosure is not limited thereto. The target floating-point number may be multiple, as will be explained below.

[0063] Figure 4 is a schematic diagram of an initial floating-point number according to another embodiment of the present disclosure.

[0064] In some embodiments, at least one initial floating point number may be multiple. For example, the multiple initial floating point numbers may be 32 initial floating point numbers. 32 floating point numbers in which the 14th bit of the floating point number is all 0 and the 13th bit is all 1 may be used as the 32 initial floating point numbers. The 32 initial floating point numbers may include the above-mentioned floating point number F31 and the floating point number F32. Figure 4 The floating point number F42 is shown. The exponent bits of the floating point number F42 are "01011101". It can be understood that the number of the initial floating point numbers can be any value, and the present disclosure does not limit this.

[0065] In the embodiment of the present disclosure, multiple target floating-point numbers can be obtained based on multiple initial floating-point numbers. For example, the multiple initial floating-point numbers can be used as multiple target floating-point numbers. The floating-point number F31 and the floating-point number F42 can be used as the target floating-point numbers respectively.

[0066] The 14th bit "0" of the exponent of the floating-point number F42 is a preset value. The 13th bit "1" of the exponent of the floating-point number F42 is not a preset value. Therefore, the 14th bit "0" of the floating-point number F42 can be used as the first code. The 13th to 7th bits of the floating-point number F42, "1011101", can be used as the second code.

[0067] In the disclosed embodiment, multiple target codes are located at the same target position. For example, based on 32 initial floating-point numbers, 32 target floating-point numbers can be obtained. As described above, the 14th bit of these floating-point numbers is 0 and the 13th bit is 1. That is, the target codes of the 32 target floating-point numbers are all located at the starting position of the exponent bit.

[0068] In the disclosed embodiment, the target codes of multiple target floating-point numbers can be deleted to obtain multiple processed floating-point numbers. For example, by deleting the target code of the floating-point number F42, the processed floating-point number "010111011100001" can be obtained. Subsequently, multiple processed floating-point numbers can be output, as will be described below with reference to relevant embodiments.

[0069] In the embodiment of the present disclosure, the first processing unit may be further configured to perform the following operations to output at least one processed floating-point number: sending the at least one processed floating-point number and an identification value.

[0070] In the embodiment of the present disclosure, the identification value is used to indicate the number of preset values included in the first code.

[0071] For example, the identification value may be 1 bit. The identification value may be 1 or 0. An identification value of "1" may indicate that the number of preset values included in the target encoding of the corresponding floating-point number is 1. An identification value of "0" may indicate that the corresponding floating-point number is not compressed.

[0072] For example, taking the aforementioned 32 target floating-point numbers as an example, the identification value can be 1. The data volume of the 32 target floating-point numbers can be 32×16 bits. The data volume of the 32 processed floating-point numbers can be 32×15 bits. The data volume of the identification value can be 1 bit. Therefore, through the embodiments of the present disclosure, the amount of data required to transmit multiple floating-point numbers is reduced by at least 6.05%, which helps to improve bandwidth utilization efficiency.

[0073] It is understood that the above description of the present disclosure is based on an example in which the 14th bit of a floating point number is 0 and the 13th bit is 1. However, the present disclosure is not limited thereto, and the 14th to 8th bits of the floating point number may all be 0, as will be explained below.

[0074] In an embodiment of the present disclosure, 32 floating-point numbers whose 14th and 13th bits are both 0 and whose 12th bits are both 1 can be used as initial floating-point numbers. These initial floating-point numbers can be used as 32 target floating-point numbers. The first codes of these 32 target floating-point numbers can all be "00." This first code can be used as the target code. That is, the target codes of the 32 target floating-point numbers are all located at the beginning of the exponent bits. The target codes of the multiple target floating-point numbers are deleted to obtain processed floating-point numbers. Next, the multiple processed floating-point numbers and an identification value can be output. The identification value can be 2 bits. The identification value can be 10. The identification value "10" can indicate that the target code of the corresponding floating-point number includes 2 preset values. Therefore, the data volume of the 32 target floating-point numbers can be 32×16 bits. The data volume of the 32 processed floating-point numbers can be 32×14 bits. The data volume of the identification value can be 2 bits. Therefore, through the embodiment of the present disclosure, the amount of data required to transmit multiple floating-point numbers is reduced by at least 12.1%, which helps to improve bandwidth utilization efficiency.

[0075] It will be appreciated that the present disclosure is described above using an initial floating-point number as an example of a target floating-point number. However, the present disclosure is not limited thereto. Among the multiple initial floating-point numbers, there may be at least one floating-point number whose 14th bit is not a preset value. In this case, the initial floating-point number can be processed to obtain the target floating-point number, as will be described below.

[0076] In some embodiments, the first processing unit may be further configured to perform the following operations to obtain at least one target floating-point number based on the at least one initial floating-point number: determining a target value based on a compression parameter value and an initial value corresponding to an exponent bit of the initial floating-point number; and replacing the exponent bit of the initial floating-point number with an exponent bit corresponding to the target value to obtain the target floating-point number.

[0077] In the embodiment of the present disclosure, the compression parameter value (margin) can convert the initial value corresponding to the exponent bit of the initial floating-point number into a target numerical range.

[0078] In an embodiment of the present disclosure, an initial floating-point number having an initial value greater than or equal to a preset threshold may be used as the floating-point number to be converted. A target value may be determined based on a compression parameter value and the initial value corresponding to the exponent bit of the floating-point number to be converted. The target floating-point number may be obtained by replacing the exponent bit of the floating-point number to be converted with the exponent bit corresponding to the target value.

[0079] For example, taking the compression parameter value as a decimal value, if the initial value of the initial floating-point number is greater than 127 and less than 255, the compression parameter value can be 127. The corresponding target value range can be 0 to 127, and the data size of the values within the target value range can be less than or equal to 7 bits. It is understood that the compression parameter value, initial value, and target value can also be various types of values, such as octal or hexadecimal, and this disclosure is not limited to this.

[0080] For example, if the exponent bits of the initial floating-point number are "11111011," the initial value corresponding to the exponent bits "11111011" is 251. Based on the difference between the compression parameter value and the initial value, the target value "124" can be determined. The target floating-point number can be obtained by replacing the exponent bits of the initial floating-point number with the exponent bits "01111100" corresponding to the target value "124."

[0081] Taking the case where all 32 initial floating-point numbers are floating-point numbers to be converted as an example, after the 32 initial floating-point numbers are converted into target floating-point numbers using the compression parameter value "127", the 32 target floating-point numbers can be determined.

[0082] In an embodiment of the present disclosure, a first encoding of each of a plurality of target floating-point numbers can be obtained. Based on the plurality of first encodings, a plurality of target encodings can be determined. For a batch of a plurality of initial floating-point numbers, the target encodings of the different target floating-point numbers can include the same number of preset values. The target encodings of the 32 target floating-point numbers can be the 14th bit "0" of each floating-point number. Next, the target encodings of the 32 target floating-point numbers can be deleted to obtain 32 processed floating-point numbers.

[0083] In an embodiment of the present disclosure, the first processing unit is further configured to perform the following operations to output at least one processed floating point number: output at least one processed floating point number, an identification value, and a compression parameter value. The identification value is used to indicate the number of preset values included in the target encoding.

[0084] For example, the identification value may be 2 bits. An identification value of "01" may indicate that the number of preset values included in the target encoding of the corresponding floating-point number is 1.

[0085] For example, taking the 32 target floating-point numbers obtained from the floating-point numbers to be converted, the identification value can be 01. The data size of the 32 target floating-point numbers can be 32×16 bits. The data size of the 32 processed floating-point numbers can be 32×15 bits. The data size of the identification value can be 2 bits. The number of compression parameter values can be 7 bits. Thus, through the embodiments of the present disclosure, the data size required to transmit multiple floating-point numbers is reduced by at least 4.49%, which helps improve bandwidth utilization efficiency.

[0086] In another embodiment, taking the compression parameter value as a decimal value, if the initial value of the initial floating-point number is greater than 0 and less than or equal to 128, the compression parameter value may be 63. The corresponding target value range may be 0 to 63, and the data size of the values within the target value range may be less than or equal to 6 bits. It is understood that the compression parameter value may be determined based on the value range of the initial value.

[0087] It is understood that the above description of the present disclosure is based on an example in which the compression parameter value is 127. However, the present disclosure is not limited thereto, as will be described below.

[0088] Figure 5A is a schematic diagram of an initial floating-point number according to an embodiment of the present disclosure.

[0089] In some embodiments, at least one initial floating point number can be multiple. For example, the multiple initial floating point numbers can be 32 initial floating point numbers. 32 floating point numbers whose 14th bit of the floating point number is all 1 can be used as the initial floating point number. The 32 initial floating point numbers can include the following: Figure 5A The floating point number F53 is shown. The exponent bits of the floating point number F53 are "11111011".

[0090] Taking a decimal value as an example, if the initial value of the initial floating-point number is greater than 127 and less than 255, and the target value range is 0 to 63, the compression parameter value may be 191. The data size of the value within the target value range may be less than or equal to 6 bits.

[0091] like Figure 5A As shown, the exponent bits of floating-point number F53 are "11111011." The initial value corresponding to the exponent bits "11111011" is 251. Based on the difference between the compression parameter value and this initial value, the target value "60" can be determined. The target floating-point number can be obtained by replacing the exponent bits of the initial floating-point number with the exponent bits "001111 00" corresponding to the target value "60."

[0092] Figure 5B is a schematic diagram of a target floating-point number according to an embodiment of the present disclosure.

[0093] like Figure 5B As shown, the floating point number F54 can be a target floating point number obtained by the floating point number F53. The exponent bits of the floating point number F54 are "00111100".

[0094] Taking 32 initial floating-point numbers, all of which are floating-point numbers to be converted, as an example, after converting the 32 initial floating-point numbers into target floating-point numbers using the compression parameter value "191," the 32 target floating-point numbers can be determined. The target codes of the 32 target floating-point numbers can include the 14th bit "0" and the 13th bit "0" of each floating-point number. Next, the target codes "00" of the 32 target floating-point numbers can be deleted to obtain 32 processed floating-point numbers. The 32 processed floating-point numbers, an identification value, and a compression parameter value can be output. The identification value can be "10," indicating that the target code of the corresponding floating-point number includes 2 preset values. The data volume of the 32 target floating-point numbers can be 32×16 bits. The data volume of the 32 processed floating-point numbers can be 32×14 bits. The data volume of the identification value can be 2 bits. The number of compression parameter values can be 8 bits. Thus, through the embodiments of the present disclosure, the amount of data required to transmit multiple floating-point numbers is reduced by at least 10.55%, which helps to improve bandwidth utilization efficiency.

[0095] It is understood that the above description of the present disclosure is based on an example in which the compression parameter value is 191. However, the present disclosure is not limited thereto, as will be described below.

[0096] In some embodiments, at least one initial floating point number can be multiple. For example, the multiple initial floating point numbers can be 32 initial floating point numbers. 32 floating point numbers whose 14th bit of the floating point number is all 1 can be used as the initial floating point number. The 32 initial floating point numbers can include the following: Figure 5A The floating point number F53 is shown. The exponent bits of the floating point number F53 are "11111011".

[0097] Taking a decimal value as an example, if the initial value of the initial floating-point number is greater than 127 and less than 255, and the target value range is 0 to 31, the compression parameter value may be 223. The data size of the value within the target value range may be less than or equal to 5 bits.

[0098] like Figure 5A As shown, the exponent bits of floating-point number F53 are "11111011." The initial value corresponding to the exponent bits "11111011" is 251. Based on the difference between the compression parameter value and this initial value, the target value "28" can be determined. The target floating-point number can be obtained by replacing the exponent bits of the initial floating-point number with the exponent bits "00011100" corresponding to the target value "28."

[0099] Taking 32 initial floating-point numbers, all of which are floating-point numbers to be converted, as an example, after converting the 32 initial floating-point numbers into target floating-point numbers using the compression parameter value "223", the 32 target floating-point numbers can be determined. The target codes of the 32 target floating-point numbers can include the 14th bit "0", the 13th bit "0", and the 12th bit "0" of each floating-point number. Next, the target code "000" of the 32 target floating-point numbers can be deleted to obtain 32 processed floating-point numbers. The 32 processed floating-point numbers, the identification value, and the compression parameter value can be output. The identification value can be "11", which can indicate that the number of preset values included in the target code of the corresponding floating-point number is 3. The data volume of the 32 target floating-point numbers can be 32×16 bits. The data volume of the 32 processed floating-point numbers can be 32×13 bits. The data volume of the identification value can be 2 bits. The number of compression parameter values can be 8 bits. Therefore, through the embodiments of the present disclosure, the amount of data required to transmit multiple floating-point numbers is reduced by at least 16.80%, which helps to improve bandwidth utilization efficiency.

[0100] It can be understood that the above description is made in conjunction with some methods for the first processing unit to output the processed floating-point number. The following description will describe some methods for converting the processed floating-point number into the initial floating-point number.

[0101] Figure 6 is a schematic block diagram of a data processing device according to another embodiment of the present disclosure.

[0102] like Figure 6 As shown, the device 62 may include a second storage unit 621 and a second processing unit 622 .

[0103] The second storage unit 621 may be configured to store at least one processed floating point number. For example, the processed floating point number may be output by the first processing unit 211 of the device 21 .

[0104] The second processing unit 622 can be configured to add a preset value to the exponent bit of at least one processed floating-point number to obtain at least one target floating-point number. For example, the preset value can be a zero value. The device 51 and the device 62 can perform data transmission according to a preset protocol. Based on the protocol, the first encoding of the target floating-point number corresponding to the processed floating-point number can be the 14th bit of the floating-point number. Thus, the preset value can be added to the exponent bit of the processed floating-point number as the 14th bit of the floating-point number to obtain the target floating-point number.

[0105] The second processing unit 622 may also be configured to obtain at least one initial floating point number based on at least one target floating point number. For example, the target floating point number may be used as the initial floating point number. The initial floating point number may be the floating point number F31.

[0106] Through the embodiments of the present disclosure, the received processed floating-point numbers can be converted back to the original floating-point numbers while saving transmission bandwidth, and the data generated by the first processing unit can be used for efficient and accurate model training or inference.

[0107] It is understood that the present disclosure is described above with reference to a single processed floating-point number, but the present disclosure is not limited thereto, and the processed floating-point numbers may be multiple, as will be described below.

[0108] In some embodiments, the second storage unit is further configured to receive at least one processed floating-point number and an identification value. The identification value is used to indicate the number of preset values. For example, the identification value can be 1 bit. The identification value can be 1 or 0. The identification value "1" can indicate that the target encoding of the corresponding floating-point number includes 1 preset value. The identification value "0" can indicate that the corresponding floating-point number is not compressed. The multiple processed floating-point numbers can be 32 processed floating-point numbers. It is understood that the number of processed floating-point numbers can be any value and is not limited by this disclosure.

[0109] In some embodiments, the second processing unit is further configured to perform the following operations to add a preset value to the exponent bit of at least one processed floating point number: adding a preset value to the exponent bit of at least one processed floating point number according to the number of preset values indicated by the identification value.

[0110] For example, when the identification value is 1, a preset value can be added to the exponent bits of the multiple processed floating-point numbers as the 14th bit of the floating-point numbers to obtain multiple target floating-point numbers. Next, the multiple target floating-point numbers can be used as multiple initial floating-point numbers. The multiple initial floating-point numbers can include the floating-point number F42.

[0111] It is understood that the above description of the present disclosure uses the example of adding a preset value to the processed floating-point number as an example, but the present disclosure is not limited thereto, and multiple preset values can be added to the processed floating-point number, as will be explained below.

[0112] For example, the identification value may be 10, which may indicate that the preset value is two. When the identification value is 10, the two preset values may be added to the exponent bits of the processed floating-point number, respectively, as the 14th and 13th bits of the floating-point number, to obtain the target floating-point number. Subsequently, the target floating-point number may be used as the initial floating-point number.

[0113] It is understood that the present disclosure is described above using the target floating-point number as an example of the initial floating-point number, but the present disclosure is not limited thereto, and the target floating-point number can be processed to obtain the initial floating-point number, as will be described below.

[0114] In some embodiments, the second storage unit is further configured to store a compression parameter value.

[0115] In the embodiment of the present disclosure, the compression parameter value may convert the initial value corresponding to the exponent bit of the initial floating-point number into a target numerical range.

[0116] For example, taking the compression parameter value as a decimal value, when the initial value of the initial floating-point number is greater than 127 and less than 255, the compression parameter value may be 127. The corresponding target value range may be 0 to 127, and the data amount of the values within the target value range may be less than or equal to 7 bits.

[0117] In some embodiments, the second processing unit is further configured to perform the following operations to obtain at least one initial floating-point number based on the at least one target floating-point data: determining the initial value based on the compression parameter value and the target value corresponding to the exponent bit of the target floating-point number; and replacing the exponent bit of the target floating-point number with the exponent bit corresponding to the initial value to obtain the initial floating-point number.

[0118] In the embodiment of the present disclosure, when the initial floating point number is a brain floating point number BF16', the decimal value of the initial floating point number can be determined using the following formula:

[0119] BF16′=(-1) s *1.M*2 (E-127+margin) (Formula 4)

[0120] For example, if the target value is 124 and the exponent bits corresponding to the target value are "01111100," the initial value can be determined to be 251 based on the sum of the target value and the compression parameter value. The exponent bits corresponding to this initial value are "11111011." The target floating-point number can be obtained by replacing the exponent bits corresponding to the target floating-point number with the exponent bits corresponding to the initial value, "11111011."

[0121] For another example, in the case where there are multiple target floating-point numbers, after converting 32 target floating-point numbers into initial floating-point numbers using the compression parameter value "127", 32 initial floating-point numbers can be determined.

[0122] It is understood that the above description of the present disclosure is based on an example in which the compression parameter value is 127. However, the present disclosure is not limited thereto, as will be described below.

[0123] Taking a decimal value as an example, if the initial value of the initial floating-point number is greater than 127 and less than 255, and the target value range is 0 to 63, the compression parameter value may be 191. The data size of the value within the target value range may be less than or equal to 6 bits.

[0124] Taking the floating-point number F54 as an example, the target value is 60, and the exponent bits corresponding to the target value are "00111100." Based on the sum of the target value and the compression parameter value, the initial value can be determined to be 251. The exponent bits corresponding to this initial value are "11111011." Replacing the exponent bits corresponding to the target floating-point number with the exponent bits corresponding to the initial value, "11111011," yields the initial floating-point number. This initial floating-point number can be the floating-point number F53 described above.

[0125] It can be understood that the above description of the present disclosure is based on an example in which the compression parameter value is 191. However, the present disclosure is not limited thereto, as will be described below.

[0126] Taking a decimal value as an example, if the initial value of the initial floating-point number is greater than 127 and less than 255, and the target value range is 0 to 31, the compression parameter value may be 223. The data size of the value within the target value range may be less than or equal to 5 bits.

[0127] If the target value is 28 and the exponent bits corresponding to the target value are "00011100", the initial value can be determined to be 251 based on the sum of the target value and the compression parameter value. The exponent bits corresponding to this initial value are "11111011". Replacing the exponent bits corresponding to the target floating-point number with the exponent bits corresponding to the initial value, "11111011", yields the initial floating-point number. This initial floating-point number can be the aforementioned floating-point number F53.

[0128] It is understood that the present disclosure is described above in conjunction with brain floating-point numbers. However, the present disclosure is not limited thereto, and the initial floating-point number can be a variety of floating-point numbers, such as single-precision floating-point numbers, tensor single-precision floating-point numbers, and half-precision floating-point numbers.

[0129] It is understood that the above description of the present disclosure is based on an example in which the target position is a starting position, but the present disclosure is not limited thereto, and the target position may also include an ending position, which will be described below.

[0130] In another embodiment of the present disclosure, the first position of the first non-zero value in the exponent bit can be determined. The second position of the last non-zero value in the exponent bit can be determined. Based on the first position and the second position, at least one numerical value is determined from the exponent bit as the second code. For example, the 12th bit of the floating point number F54 is a non-zero value and can be used as the first position. The 9th bit of the floating point number F54 is a non-zero value and can be used as the second position. Based on the first position and the second position, the numerical value "1111" can be determined as the second code. Accordingly, based on the first position, the first code "00" including the 14th and 13th bits of the floating point number F54 can be determined. Based on the second position, the first code "00" including the 8th and 7th bits of the floating point number F54 can be determined.

[0131] In another embodiment of the present disclosure, the target encoding can be determined based on at least one first encoding. For example, the first encoding "00" including the 14th and 13th bits of the floating-point number F54 can be determined as the target encoding, or the first encoding "00" including the 8th and 7th bits of the floating-point number F54 can be determined as the target encoding. These two target encodings can be deleted to obtain the target floating-point number. The data volume of the target floating-point number can be 12 bits. Accordingly, in the case of using the two first encodings as the target encoding, the identification value can be 4 bits, the first two bits of the identification value can indicate the number of preset values in the target encoding at the starting position, and the last two bits of the identification value can indicate the number of preset values in the target encoding at the ending position. It can be understood that only the first encoding "00" including the 8th and 7th bits of the floating-point number F54 can be determined as the target encoding, and the present disclosure does not limit this.

[0132] It can be understood that the above description is of the data processing device of the present disclosure, and the following description will be of an electronic device and a system including the data processing device.

[0133] Figure 7 is a schematic block diagram of an electronic device according to an embodiment of the present disclosure.

[0134] like Figure 7 As shown, the device 700 may include a data processing device 71. The data processing device 71 may be the device 21 described above.

[0135] Figure 8 is a schematic block diagram of a data processing system according to an embodiment of the present disclosure.

[0136] like Figure 8 As shown, the system 8000 may include a data processing device 81 and a data processing device 82. The data processing device 81 may be the aforementioned device 21. The data processing device 82 may be the aforementioned device 62.

[0137] It can be understood that the above describes the device and system of the present disclosure, and the following will describe the method of the present disclosure.

[0138] Figure 9 is a flowchart of a data processing method according to an embodiment of the present disclosure.

[0139] like Figure 9 As shown, the method 910 may include operations S911 to S913.

[0140] In operation S911, at least one target floating-point number is obtained according to at least one initial floating-point number.

[0141] In an embodiment of the present disclosure, the exponent bit of the target floating-point number includes at least one first code and a second code, the first code includes at least one preset value, and the first code is located at a target position of the exponent bit of the target floating-point number, and the target position is at least one of the starting position and the ending position of the exponent bit of the target floating-point number.

[0142] In operation S912, a target code of at least one target floating-point number is deleted to obtain at least one processed floating-point number.

[0143] In the embodiment of the present disclosure, the target encoding is determined according to at least one first encoding.

[0144] In operation S913 , at least one processed floating-point number is output.

[0145] For example, the method 910 may be executed by the second processing unit 212 .

[0146] In some embodiments, the second code includes a plurality of consecutive numerical values, and the first value of the second code is a non-zero value.

[0147] In some embodiments, the preset value is zero.

[0148] In some embodiments, at least one target floating-point number is multiple, and the multiple target codes are located at the same target position.

[0149] In some embodiments, outputting at least one processed floating-point number includes: outputting at least one processed floating-point number and an identification value, wherein the identification value is used to indicate the number of preset values included in the target code.

[0150] In some embodiments, obtaining at least one target floating-point number based on at least one initial floating-point number includes determining a target value based on a compression parameter value and an initial value corresponding to an exponent bit of the initial floating-point number, and replacing the exponent bit of the initial floating-point number with an exponent bit corresponding to the target value to obtain the target floating-point number.

[0151] In some embodiments, outputting at least one processed floating-point number includes: outputting at least one processed floating-point number, an identification value, and a compression parameter value. The identification value is used to indicate the number of preset values included in the target encoding.

[0152] Figure 10 is a flowchart of a data processing method according to another embodiment of the present disclosure.

[0153] like Figure 10 As shown, the method 1020 may include operations S1020 to S1022.

[0154] In operation S1020 , at least one processed floating-point number is received.

[0155] In operation S1021, a preset value is added to an exponent bit of at least one processed floating point number to obtain at least one target floating point number.

[0156] In operation S1022 , at least one initial floating point number is obtained according to at least one target floating point number.

[0157] In the disclosed embodiment, the processed floating point number comes from method 910 .

[0158] For example, the method 1020 may be performed by the aforementioned device 62 .

[0159] In some embodiments, adding the preset value to the exponent bit of the at least one processed floating point number includes: adding the preset value to the exponent bit of the at least one processed floating point number according to the number of the preset values indicated by the identification value.

[0160] In some embodiments, obtaining at least one initial floating-point number based on at least one target floating-point data includes: determining the initial value based on a compression parameter value and a target value corresponding to an exponent bit of the target floating-point number; and replacing the exponent bit of the target floating-point number with the exponent bit corresponding to the initial value to obtain the initial floating-point number.

[0161] In the technical solutions disclosed herein, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0162] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0163] Figure 11 A schematic block diagram of an example electronic device 1100 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0164] like Figure 11As shown, the device 1100 includes a computing unit 1101, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 1102 or a computer program loaded from a storage unit 1108 into a random access memory (RAM) 1103. Various programs and data required for the operation of the device 1100 can also be stored in the RAM 1103. The computing unit 1101, the ROM 1102, and the RAM 1103 are connected to each other via a bus 1104. An input / output (I / O) interface 1105 is also connected to the bus 1104.

[0165] Various components in device 1100 are connected to I / O interface 1105, including an input unit 1106, such as a keyboard and mouse; an output unit 1107, such as various types of displays and speakers; a storage unit 1108, such as a magnetic disk and optical disk; and a communication unit 1109, such as a network card, a modem, a wireless communication transceiver, etc. Communication unit 1109 allows device 1100 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0166] The computing unit 1101 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 1101 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 1101 performs the various methods and processes described above, such as the data processing method. For example, in some embodiments, the data processing method can be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 1108. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 1100 via the ROM 1102 and / or the communication unit 1109. When the computer program is loaded into the RAM 1103 and executed by the computing unit 1101, one or more steps of the data processing method described above can be performed. Alternatively, in other embodiments, the computing unit 1101 can be configured to perform the data processing method by any other appropriate means (e.g., by means of firmware).

[0167] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0168] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0169] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0170] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) display or an LCD (liquid crystal display)) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0171] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0172] Computer systems may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The client and server relationship arises through computer programs running on the respective computers and having a client-server relationship to each other.

[0173] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not limited herein.

[0174] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A data processing device, comprising: a first storage unit configured to store at least one initial floating point number; The first processing unit is configured as follows: Read at least one of the initial floating-point numbers from the first storage unit; Obtaining at least one target floating-point number based on at least one of the initial floating-point numbers, wherein an exponent bit of the target floating-point number includes at least one first code and a second code, the first code includes at least one preset value, and the first code is located at a target position of the exponent bit of the target floating-point number, the target position being at least one of a starting position and an ending position of the exponent bit of the target floating-point number; deleting a target code of at least one of the target floating-point numbers to obtain at least one processed floating-point number, wherein the target code is determined based on at least one of the first codes; Output at least one processed floating-point number.

2. The device according to claim 1, wherein The second code includes a plurality of consecutive numerical values, and the first value of the second code is a non-zero value.

3. The device according to claim 1, wherein The preset value is zero.

4. The device according to claim 1, wherein At least one of the target floating-point numbers is multiple, and the multiple target codes are located at the same target position.

5. The device according to claim 1, wherein The first processing unit is further configured to perform the following operations to output at least one of the processed floating-point numbers: Output at least one of the processed floating-point numbers and an identification value, wherein the identification value is used to indicate the number of the preset values included in the target code.

6. The device according to claim 1 or 5, wherein: The first processing unit is further configured to perform the following operations to obtain at least one target floating-point number according to at least one of the initial floating-point numbers: determining a target value according to a compression parameter value and an initial value corresponding to an exponent bit of the initial floating-point number; The exponent bits of the initial floating-point number are replaced with exponent bits corresponding to the target value to obtain the target floating-point number.

7. The device according to claim 6, wherein The first processing unit is further configured to perform the following operations to output at least one of the processed floating-point numbers: Output at least one of the processed floating-point number, an identification value, and the compression parameter value, wherein the identification value is used to indicate the number of the preset values included in the target encoding.

8. A data processing device comprising: a second storage unit configured to receive at least one processed floating-point number, wherein the processed floating-point number comes from the apparatus according to any one of claims 1 to 7; The second processing unit is configured as follows: adding a preset value to an exponent bit of at least one of the processed floating-point numbers to obtain at least one target floating-point number; At least one initial floating-point number is obtained according to at least one target floating-point number.

9. The device according to claim 8, wherein The second storage unit is further configured to receive at least one processed floating point number and an identification value, wherein the identification value is used to indicate the number of the preset values.

10. The device according to claim 9, wherein The second processing unit is further configured to perform the following operations to add a preset value to an exponent bit of at least one of the processed floating-point numbers: The preset value is added to the exponent bits of at least one of the processed floating-point numbers according to the number of the preset values indicated by the identification value.

11. The device according to claim 8, wherein The second storage unit is further configured to store a compression parameter value.

12. The device according to claim 11, wherein The second processing unit is further configured to perform the following operations to obtain at least one initial floating-point number according to at least one target floating-point data: Determining an initial value according to the compression parameter value and a target value corresponding to an exponent bit of the target floating-point number; The exponent bit of the target floating-point number is replaced by the exponent bit corresponding to the initial value to obtain the initial floating-point number.

13. An electronic device comprising the data processing device according to any one of claims 1 to 7.

14. A data processing system, comprising the data processing apparatus according to any one of claims 1 to 7; and the data processing apparatus according to any one of claims 8 to 12.

15. A data processing method, comprising: At least one target floating-point number is obtained according to at least one initial floating-point number, wherein an exponent bit of the target floating-point number includes at least one first code and a second code, the first code includes at least one preset value, the first code is located at a target position of the exponent bit of the target floating-point number, and the target position is at least one of a starting position and an ending position of the exponent bit of the target floating-point number; deleting a target code of at least one of the target floating-point numbers to obtain at least one processed floating-point number, wherein the target code is determined based on at least one of the first codes; Output at least one processed floating-point number.

16. The method according to claim 15, wherein The second code includes a plurality of consecutive numerical values, and the first value of the second code is a non-zero value.

17. The method according to claim 15, wherein: The preset value is zero.

18. The method according to claim 15, wherein At least one of the target floating-point numbers is multiple, and the multiple target codes are located at the same target position.

19. The method according to claim 15, wherein Outputting at least one processed floating-point number comprises: Output at least one of the processed floating-point numbers and an identification value, wherein the identification value is used to indicate the number of the preset values included in the target code.

20. The method according to claim 15 or 19, wherein Obtaining at least one target floating-point number according to at least one initial floating-point number comprises: determining a target value according to a compression parameter value and an initial value corresponding to an exponent bit of the initial floating-point number; The exponent bits of the initial floating-point number are replaced with exponent bits corresponding to the target value to obtain the target floating-point number.

21. The method according to claim 20, wherein Outputting at least one processed floating-point number comprises: Output at least one of the processed floating-point number, an identification value, and the compression parameter value, wherein the identification value is used to indicate the number of the preset values included in the target encoding.

22. A data processing method, comprising: Receiving at least one processed floating point number, wherein the processed floating point number is obtained from the method according to any one of claims 15 to 21; adding a preset value to an exponent bit of at least one of the processed floating-point numbers to obtain at least one target floating-point number; At least one initial floating-point number is obtained according to at least one target floating-point number.

23. The method according to claim 22, wherein Adding a preset value to the exponent bit of at least one of the processed floating-point numbers comprises: The preset value is added to the exponent bits of at least one of the processed floating-point numbers according to the number of the preset values indicated by the identification value.

24. The method according to claim 22, wherein Obtaining at least one initial floating-point number according to at least one target floating-point data comprises: Determining an initial value according to a compression parameter value and a target value corresponding to an exponent bit of the target floating-point number; The exponent bit of the target floating-point number is replaced by the exponent bit corresponding to the initial value to obtain the initial floating-point number.

25. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 15 to 24.

26. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 15 to 24.

27. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 15 to 24.

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