Protection circuit

Abstract

The invention relates to a protection circuit. An electronic circuit is disclosed. The electronic circuit comprises: first and second circuit nodes (11, 12); a bipolar transistor (2) comprising an emitter region (21) connected to one of the first and second circuit nodes (11, 12), a collector region (22) connected to the other of the first and second circuit nodes (11, 12), and a base region (23); a trigger element (3) connected between the emitter region (21) and the base region (23) of the bipolar transistor (2); and an avalanche diode (4). The bipolar transistor (2) and the avalanche diode (3) are integrated in a semiconductor body (100) in which an emitter region (21) and a collector region (23) are spaced apart from each other in a lateral direction of the semiconductor body (100), and in which a base region (23) and a collector region (22) of the bipolar transistor (2) simultaneously form the avalanche diode (4).

Description

Technical Field

[0001] The present disclosure generally relates to a protection circuit, such as an electrostatic discharge (ESD) protection circuit. Background Art

[0002] Voltage or current pulses (spikes), such as those caused by electrostatic discharge (ESD) events or electrical overstress (EOS), can cause damage or reliability problems in semiconductor devices or in integrated circuits (ICs) that include several semiconductor devices. During an ESD event, charge is transferred from an object (such as a charged person, a charged cable, or charged manufacturing equipment) to a circuit node connected to the semiconductor device or IC in a short period of time. The voltage or current spike can damage or destroy the semiconductor device or IC. Damage induced by voltage or current spikes is, for example, the interruption of a connection wire by melting the connection wire; failure caused by burning of a hot semiconductor junction; or destruction or degradation of the gate oxide of a semiconductor device (such as a MOSFET (metal oxide field effect transistor) or an IGBT (insulated gate bipolar transistor)).

[0003] Various concepts are known for protecting semiconductor devices or ICs from voltage or current spikes caused by ESD events. According to one concept, a transistor (such as a MOSFET or IGBT) has its load path connected in parallel to the semiconductor device or IC to be protected. Furthermore, a control circuit is connected in parallel to the load path of the transistor and is configured to turn on the transistor when the voltage across the load path reaches a trigger voltage. In the on state, the transistor provides a low-ohmic current path for conducting the current generated by the ESD event.

[0004] There is a need for a protection circuit, such as an ESD protection circuit, which can be implemented in a space-saving manner and in which the trigger voltage can be easily adjusted by design. Summary of the Invention

[0005] One example relates to an electronic circuit. The electronic circuit includes: a first circuit node and a second circuit node; a bipolar transistor having an emitter region connected to one of the first and second circuit nodes, a collector region connected to the other of the first and second circuit nodes, and a base region; a trigger element connected between the emitter and base regions of the bipolar transistor; and an avalanche diode. The bipolar transistor and the avalanche diode are integrated into a semiconductor body, wherein the emitter and collector regions are separated from each other in a lateral direction of the semiconductor body, and wherein the base and collector regions of the bipolar transistor simultaneously form the avalanche diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following examples are explained with reference to the accompanying drawings. The accompanying drawings are used to illustrate certain principles and thus only illustrate aspects necessary for understanding these principles. The accompanying drawings are not necessarily drawn to scale. In the accompanying drawings, the same reference numerals indicate similar features.

[0007] Figure 1 A circuit diagram of a protection circuit including a bipolar transistor, an avalanche diode and a trigger element is shown;

[0008] Figure 2 schematically illustrates a vertical cross-sectional view of a section of a semiconductor body to illustrate one example for integrating a bipolar transistor and an avalanche diode in the semiconductor body;

[0009] Figure 3 and 4 shows different examples of alternative carriers on top of which bipolar transistors and avalanche diodes are formed in a semiconductor body 100 ;

[0010] Figure 5A and 5B A vertical cross-sectional view of a section of a semiconductor body is shown ( Figure 5A ) and top view ( Figure 5B ) to illustrate another example for integrating a bipolar transistor and an avalanche diode;

[0011] Figure 6 An example of a protection circuit in which the trigger element is implemented as a resistor is shown;

[0012] Figure 7 FIG. 1 shows an example of a protection circuit in which the trigger element is implemented as a diode arrangement;

[0013] Figure 8 illustrates an example of a protection circuit, wherein the trigger element is integrated in a polysilicon layer, the polysilicon layer being arranged over a first surface of the semiconductor body; and

[0014] Figure 9 A cross-sectional view of a polysilicon layer integrating a trigger element implemented as a diode is shown. DETAILED DESCRIPTION

[0015] In the following detailed description, reference is made to the accompanying drawings, which form a part of the description and show, for illustrative purposes, examples of how the invention may be used and implemented. It should be understood that the features of the various embodiments described herein may be combined with each other unless specifically indicated otherwise.

[0016] Figure 1 A circuit diagram of an electronic circuit according to one example is shown. More specifically, Figure 11 shows a circuit diagram of a protection circuit configured to clamp (limit) a voltage Vesd applied between a first circuit node 11 and a second circuit node 12 of the protection circuit. Figure 1 The protection circuit can be connected to any kind of electronic device or electronic circuit (not shown in the figure) to be protected from high voltage (especially high voltage caused by ESD events) Figure 1 For example, the electronic device to be protected may be a MOSFET. In this example, the protection circuit may be connected between the drain node and the source node, or between the gate node and the source node, of the MOSFET via the first circuit node 11 and the second circuit node 12.

[0017] Reference Figure 1 The protection circuit includes a bipolar transistor 2, a trigger element 3, and an avalanche diode 4. The bipolar transistor 2 includes an emitter node E, a collector node C, and a base node B. The collector-emitter path of the bipolar transistor 2 is an internal path of the bipolar transistor 2 between the emitter node E and the collector node C, and is connected between the first circuit node 11 and the second circuit node 12. To this end, Figure 1 In the example illustrated in , the emitter node E is connected to a first circuit node 11 and the collector node is connected to a second circuit node 12 of the protection circuit.

[0018] Reference Figure 1 , the trigger element 3 is connected between the emitter node E and the base node B of the bipolar transistor 2, and the avalanche diode 4 is connected between the base node B and the collector node C. In this way, the trigger element 3 and the avalanche diode 4 are connected in series between the first circuit node 11 and the second circuit node 12.

[0019] The protection circuit is configured to clamp (limit) a voltage Vesd applied between first circuit node 11 and second circuit node 12 so that a voltage level of voltage Vesd does not significantly exceed a predefined maximum voltage level. Voltage Vesd applied between first circuit node 11 and second circuit node 12 may be caused by an ESD event, and such voltage is hereinafter also referred to as an ESD voltage.

[0020] The maximum voltage level to which the ESD voltage Vesd is clamped (limited) is referred to below as the clamping voltage. The clamping voltage depends primarily on the breakdown voltage (avalanche voltage) of the avalanche diode 4. When the voltage level of the ESD voltage Vesd reaches the breakdown voltage of the avalanche diode 4, the avalanche diode 4 begins to conduct an avalanche current Iav. The avalanche current Iav causes a voltage drop Vtr across the trigger element 3. This voltage Vtr is referred to below as the trigger voltage. When the trigger voltage Vtr reaches the threshold voltage of the bipolar transistor 2, the bipolar transistor 2 turns on to provide a conduction current path in parallel with the series circuit including the trigger element 3 and the avalanche diode 4. The "threshold voltage" of the bipolar transistor 2 is the voltage level of the voltage (base-emitter voltage) between the base node B and the emitter node E, at which the bipolar transistor 2 turns on.

[0021] According to an example (such as Figure 1 ), the bipolar transistor is a PNP transistor. In this example, the threshold voltage is a negative voltage between the base node B and the emitter node E. According to one example, the bipolar transistor is a silicon-based bipolar transistor. In this example, the negative threshold voltage is approximately -0.7V, so that when the base-emitter voltage becomes lower than the negative threshold voltage, the bipolar transistor 2 turns on.

[0022] Figure 2 Schematically illustrates an example for integrating a bipolar transistor 2 and an avalanche diode 4 in a semiconductor body 100. More specifically, Figure 2 A schematic vertical cross-section of a section of a semiconductor body 100 is shown, integrating a bipolar transistor 2 and an avalanche diode 4. The trigger element 3 is only Figure 2 Examples of triggering elements 3 are explained further below in this context.

[0023] At least one region of the semiconductor body 100 integrating the bipolar transistor 2 and the avalanche diode 4 comprises a single-crystalline semiconductor material, such as, for example, silicon (Si) or silicon carbide (SiC).

[0024] Reference Figure 2 , bipolar transistor 2 includes an emitter region 21, a collector region 22, and a base region 23. Emitter region 21 is connected to or forms an emitter node E, collector region 22 is connected to or forms a collector node C, and base region 22 is connected to or forms a base node B.

[0025] Reference Figure 2 The emitter region 21 and the collector region 22 are separated from each other in a lateral direction of the semiconductor body 100. The lateral direction is a direction substantially parallel to the first surface 101 of the semiconductor body. The emitter region 21 and the collector region 22 are separated from each other by the base region 23.

[0026] In accordance with Figure 2 In the protection circuit of FIG. 2 , the base region 23 and the collector region 22 of the bipolar transistor 2 simultaneously form an avalanche diode 4. In a PNP bipolar transistor, for example, the base region 23 is an N-type region, and the collector region 22 is a P-type region, so that the base region 23 forms the cathode of the avalanche diode 4, and the collector region 22 forms the anode of the avalanche diode 4. For the purpose of illustration, the circuit symbol of the avalanche diode 4 formed by the base region 23 and the collector region 22 of the bipolar transistor 2 is also illustrated in FIG. Figure 2 In a PNP transistor, the emitter region 21 is a P-type region. In each case, the emitter region 21 and the collector region 22 have the same doping type.

[0027] Reference Figure 2 The collector region 22 may include a first region 221 and a second region 222, wherein the first region 221 is adjacent to the base region 23 and is arranged between the base region 23 and the second region 222. According to one example, the first region 221 has a lower doping concentration than the second region 222. According to one example, the doping concentration of the second region 222 is at least 10 times, at least 100 times, or at least 1000 times the doping concentration of the first region 221.

[0028] According to one example, from 1E14 cm -3 and 1E16 cm -3 The doping concentration of the first region 221 is selected between 1E17 cm -3 and 1E19 cm -3 The doping concentration of the second region 222 is selected between 1E19 and 2E19 cm. The doping concentrations of the base region 23 and the emitter region 21 can be selected from the same range as the doping concentration of the second region 222 of the collector region 22. It should be noted that each of the emitter region 21, the base region 23, and the second collector region 222 can have a (top) contact region (not shown) in a section adjacent to the first surface 101. The contact region can have a higher doping concentration than the rest of the corresponding region 21, 23, 222. These contact regions are used to provide ohmic contacts for the corresponding regions 21, 23, 222. From 1E19 cm -3 and 1E21 cm -3 The doping concentration of the contact region is selected in the range between .

[0029] according to Figure 2According to an example illustrated by dashed lines in FIG, the base region 23 includes a base region extension 231, which extends along a portion of the first region 221 in the direction of the second region 222 and is adjacent to a portion of the first collector region 221. The base region extension 231 may be adjacent to the second region 222 or may be separated from the second region 222. For example, the doping concentration of the base region extension 231 is lower than the doping concentration of the remaining portion of the base region 23 and is at 1E15 cm -3 and 1E18 cm -3 between.

[0030] With reference to the above, the avalanche diode 4 is formed between the base region 23 and the collector region 22. In the presence of the base region extension 231 and the first collector region 221, the base region extension 231 and the first collector region 221 form a portion of the avalanche diode 4. The base extension 231 and the first collector region 221 form a resurf structure in which a PN junction is formed between the base region extension 231 and the first collector region 221.

[0031] In accordance with Figure 2 In the protection circuit of FIG. 1 , the breakdown voltage of the avalanche diode 4 depends on the dimension d of the first region 221 in the lateral direction. This dimension of the first region 221 in the lateral direction of the semiconductor body 100 is equal to the distance between the base region 23 and the second region 222 of the collector region 22 in the lateral direction. At a given doping concentration of the base region 23, the first region 221, and the second region 222, the greater the distance d between the base region 23 and the second region 222, the higher the breakdown voltage of the avalanche diode 4. At approximately 2E16 cm -3 For example, when the distance d is about 10 micrometers (μm), the breakdown voltage is about 150 V. For example, when the distance d is about 15 μm, the breakdown voltage is about 200 V. Figure 2 In the protection circuit of FIG. 4 , the breakdown voltage of the avalanche diode 4 (and therefore, the clamping voltage of the protection circuit) can be easily adjusted by appropriately designing the distance between the base region 23 and the second region 222 of the collector region 22 .

[0032] According to one example, the breakdown voltage of the avalanche diode 4 is selected from between 30 V and 1000 V. In this example, the distance between the base region 23 and the second region 222 of the collector region 22 is selected from between 1 micrometer and 100 micrometers.

[0033] exist Figure 2In FIG, only the portion of the semiconductor body 100 comprising the emitter region 21, the collector region 22 and the base region 23 is illustrated. The semiconductor body 100 may comprise further portions, such as a portion 110 which provides mechanical stability for the semiconductor body 100. This stabilizing portion 110, also referred to below as a carrier portion, is illustrated in dashed lines in FIG. Figure 2 The carrier portion 110 can be implemented in various ways. Figure 3 and 4 Let's explain two different examples.

[0034] Reference Figure 3 The carrier portion 110 may include a semiconductor substrate 111 and an insulating layer 112 formed on the semiconductor substrate 111. The bipolar transistor 2 and the avalanche diode 4 are integrated in a semiconductor layer formed on the insulating layer 112. The semiconductor substrate 111, the insulating layer 112, and the semiconductor layer including the bipolar transistor 2 and the avalanche diode 4 may be formed of an SOI substrate.

[0035] according to Figure 4 In another example illustrated in FIG, the carrier portion 110 includes a semiconductor substrate 113. The semiconductor substrate 113 may have the same doping type as the emitter region 21 and the collector region 22. According to one example, the bipolar transistor 2 and the avalanche diode 4 are formed in an epitaxial layer formed on the semiconductor substrate 113. According to another example, the bipolar transistor 2 and the avalanche diode 4 are integrated into the substrate 113 and may be formed using at least one of an implantation and a diffusion process.

[0036] The semiconductor substrate 113 may have the same doping concentration or a lower doping concentration than the first region 221 of the collector region 22. Figure 2 An example of the doping concentration of the first collector region 221 is explained. According to one example, the collector node C is connected to the substrate 113 in an ohmic manner. This connection is schematically illustrated in FIG. Figure 4 middle.

[0037] according to Figure 5A and 5B In one example illustrated in FIG, in a horizontal plane of the semiconductor body 100 , the collector region 22 having the first region 221 and the second region 222 surrounds the emitter region 21 and the base region 23 in a ring-shaped manner. Figure 5A shows a vertical cross-sectional view of a semiconductor body 100, and Figure 5B Shown is a top view of the first surface 101 of the semiconductor body 100. In each lateral direction, the shortest distance between the base region 23 and the second region 222 of the collector region 22 is given by the distance d which defines the breakdown voltage of the avalanche diode.

[0038] Referring to the above, the trigger element 3 conducts the avalanche current Iav and generates a trigger voltage Vtr between the base node B and the emitter node E of the bipolar transistor 2 to turn on the bipolar transistor 2. The trigger element 3 can be implemented in various ways.

[0039] according to Figure 6 In one example illustrated in FIG, the trigger element is a resistor 3 connected between the first circuit node 11 and the base node B of the bipolar transistor 2. The resistance of the resistor 3 is selected so that the avalanche current Iav through the avalanche diode 4 generates a trigger voltage Vtr, so that the trigger voltage turns on the bipolar transistor 2.

[0040] according to Figure 7 In another example shown in FIG, the trigger element 3 is a diode device connected between the first circuit node 11 and the base node B of the bipolar transistor 2. The diode device includes at least one diode and may include several diodes connected in series. Figure 7 In the example illustrated in FIG, the anode node of the at least one diode is connected to the first circuit node 11, and the cathode node of the at least one diode is connected to the base node B of the bipolar transistor 2. The diode device forming the trigger element 3 and the bipolar transistor 2 are adapted to each other so that the forward voltage of the diode is high enough to turn on the bipolar transistor 2. The "forward voltage" is the voltage between the anode node and the cathode node of the diode when the diode is forward biased by the avalanche current Iav.

[0041] according to Figure 8 In one example shown in FIG, the trigger element 3 is formed in a polysilicon layer 7 formed above the first surface 101 of the semiconductor body 100. Figure 8 As shown in , a polysilicon layer 7 may be formed over the emitter region 21 of the bipolar transistor 2. In a vertical direction of the semiconductor body 100, the polysilicon layer 7 is separated from the first surface 101 of the semiconductor body 100 and isolated from the semiconductor body 100 by the insulating layer 5. The "vertical direction" of the semiconductor body 100 is a direction that is substantially perpendicular to the first surface 101.

[0042] According to one example, the polysilicon layer 7 is embedded in the insulating layer 5. The insulating layer 5 may include several insulating portions. According to one example, the insulating layer 5 includes a shallow trench isolation (STI) 51, and the polysilicon layer 7 is formed on the STI 51. This example is illustrated in FIG. Figure 8 The STI 51 causes a recess in the first surface 101 of the semiconductor body 100 , so that the first surface 101 can have surface sections at different vertical levels of the semiconductor body 100 .

[0043] Forming STI 51 may include an oxidation process in which a single crystalline portion of semiconductor body 100 is converted to oxide so that first surface 101 of semiconductor body 100 at the bottom of the STI is at a different level than the rest of first surface 101 .

[0044] However, forming the polysilicon layer 7 over the STI 51 is only an example. According to another example, a first portion of the insulating layer 5 is deposited on the first surface 101 of the semiconductor body, the polysilicon layer 7 is formed over this first portion of the insulating layer 5, and another portion of the insulating layer 5 is deposited so as to cover the polysilicon layer 7.

[0045] Reference Figure 8 The protection circuit may further include a first electrical contact 61 and a second electrical contact 62, both formed on the insulating layer 5. Each of the first and second contacts 61 and 62 comprises a conductive material, such as metal. The first contact 61 is connected to the first circuit node 11, or the first circuit node 11 forming the protection circuit, and the second contact 62 is connected to the second circuit node 12, or the second circuit node 12 forming the protection circuit. The first contact 61 is connected to the emitter region 21 of the bipolar transistor 2 via a first conductive via 63 extending from the emitter region 21 through the insulating layer 5 to the first contact 61. The second contact 62 is connected to the collector region 22 of the bipolar transistor via a second conductive via 64 extending from the collector region 22 through the insulating layer 5 to the second contact 62. More specifically, the second region 222 of the collector region 22 is connected to the second contact 62 via the second via 64.

[0046] As explained above, the trigger element 3 is connected between the first circuit node 11 and the base region 23 of the bipolar transistor 2. Figure 8 In the example illustrated in FIG, a first portion of the polysilicon layer 7 is connected to the first circuit node 11. To connect the first portion of the polysilicon layer 7 to the first contact 61, the first portion of the polysilicon layer 7 can be connected to the first via 63 via a first conductor 65. In addition, a second portion of the polysilicon layer 7 is connected to the base region 23 via a second conductor 66. Each of the first and second conductors 65, 66 includes a conductive material and can be formed within the insulating layer 5 in a conventional manner.

[0047] Within the polysilicon layer 7, the trigger element 3 is formed between a first portion connected to the first conductor 65 and a second portion connected to the second conductor 66. According to one example explained above, the trigger element 3 is a resistor. In this example, the resistance of the resistor depends on the doping concentration and size of the polysilicon layer 7. Therefore, by appropriately selecting the doping concentration of the polysilicon layer and appropriately designing the size of the polysilicon layer 7, the resistance of the resistor can be adjusted.

[0048] According to another example explained above, the trigger element 3 comprises a diode device. An example for realizing a diode device as the trigger element 3 in the polysilicon layer 7 is illustrated in FIG. Figure 9 middle.

[0049] Figure 9 Schematically illustrated is a vertical cross-section of a polysilicon layer 7 integrating a diode device 3 as a trigger element. In this example, the diode device 3 comprises a plurality of diodes connected in series.

[0050] exist Figure 9 In the example shown in FIG, the polysilicon layer 7 includes a plurality of first regions 71 having a first doping type and second regions 72 having a second doping type complementary to the first doping type. The first regions 71 and the second regions 72 are alternately arranged in the polysilicon layer. For example, the first regions 71 are P-type regions, and the second regions 72 are N-type regions.

[0051] Each pair including the first region 71 and the adjacent second region 72 forms a PN junction therebetween, so that each pair including the first region 71 and the adjacent second region 72 forms a diode 31, 32 of the diode device 3. The diodes 31, 32 include a first diode 31 and a second diode 32, wherein the first diode 31 and the second diode 32 are connected in anti-series. The circuit symbols of the first diode 31 and the second diode 32 are also shown in FIG. Figure 9 middle.

[0052] Reference Figure 9 Diode device 3 further includes short-circuit elements 73 formed on polysilicon layer 7. Each of these short-circuit elements shorts the PN junction of a corresponding second diode 32, thereby electrically operating a series circuit including first diode 31 within the diode device. The forward voltage of diode device 3 is determined by the sum of the forward voltages of first diodes 31 within the diode device.

[0053] Some of the aspects explained above are briefly summarized below with reference to numbered examples.

[0054] Example 1. An electronic circuit includes: a first circuit node and a second circuit node; a bipolar transistor including an emitter region connected to one of the first circuit node and the second circuit node, a collector region connected to the other of the first circuit node and the second circuit node, and a base region; a trigger element connected between the emitter region and the base region of the bipolar transistor; and an avalanche diode, wherein the bipolar transistor and the avalanche diode are integrated into a semiconductor body, wherein the emitter region and the collector region are separated from each other in a lateral direction of the semiconductor body, and wherein the base region and the collector region of the bipolar transistor simultaneously form the avalanche diode.

[0055] Example 2. The electronic circuit of Example 1, wherein the base region of the bipolar transistor is arranged between the emitter region and the collector region, wherein the collector region includes a first region adjacent to the base region and a second region separated from the base region by the first region, wherein the first region has a lower doping concentration than the second region.

[0056] Example 3. The electronic circuit of Example 2, wherein the distance between the base region and the second region of the collector region is selected from between 1 micrometer and 100 micrometers.

[0057] Example 4. The electronic circuit of any of Examples 1 to 3, wherein the base region surrounds the emitter region in a lateral plane of the semiconductor body, and wherein the collector region surrounds the base region in a lateral plane of the semiconductor body.

[0058] Example 5. The electronic circuit of any of Examples 1 to 4, wherein the trigger element comprises a resistor.

[0059] Example 6. The electronic circuit of any one of Examples 1 to 4, wherein the trigger element comprises a diode.

[0060] Example 7. The electronic circuit of any of Examples 1 to 6, wherein the trigger element is integrated in a polysilicon layer formed over the first surface of the semiconductor body.

[0061] Example 8. The electronic circuit of any of Examples 1 to 7, wherein the bipolar transistor is a PNP bipolar transistor.

[0062] Example 9. The electronic circuit of any one of Examples 1 to 8, wherein the breakdown voltage of the avalanche diode is between 30V and 1000V.

[0063] Example 10. The electronic circuit of any one of claims 2 to 9, wherein the base region comprises a base region extension extending along a portion of the first region in the direction of the second region of the collector region.

[0064] Example 11. The electronic circuit of claim 10, wherein the base region extension abuts the second region of the collector region.

[0065] Example 12. The electronic circuit of claim 10, wherein the base region extension is spaced apart from the second region of the collector region.

Claims

1. An electronic circuit comprising: A first circuit node and a second circuit node (11, 12); A bipolar transistor (2) comprising an emitter region (21) connected to one of the first and second circuit nodes (11, 12), a collector region (22) connected to the other of the first and second circuit nodes (11, 12), and a base region (23); a trigger element (3) connected between the emitter region (21) and the base region (23) of the bipolar transistor (2); and Avalanche diode (4), wherein the bipolar transistor (2) and the avalanche diode (3) are integrated in a semiconductor body (100), wherein the emitter region (21) and the collector region (23) are separated from each other in a lateral direction of the semiconductor body (100), and The base region (23) and the collector region (22) of the bipolar transistor (2) simultaneously form the avalanche diode (4).

2. The electronic circuit according to claim 1, wherein the base region (23) of the bipolar transistor (2) is arranged between the emitter region (21) and the collector region (22), wherein the collector region (22) includes a first region (221) adjacent to the base region (23) and a second region (222) separated from the base region (23) by the first region (221), Wherein, compared with the second region (222), the first region (221) has a lower doping concentration.

3. The electronic circuit according to claim 2, The distance between the base region (23) and the second region (222) of the collector region (22) is selected from between 1 micron and 100 microns.

4. The electronic circuit according to any one of claims 1 to 3, wherein in a lateral plane of the semiconductor body (100), the base region (23) surrounds the emitter region (21), and In the lateral plane of the semiconductor body (100), the collector region (22) surrounds the base region (23).

5. The electronic circuit according to any one of claims 1 to 4, The trigger element (3) comprises a resistor.

6. The electronic circuit according to any one of claims 1 to 4, The trigger element (3) comprises a diode.

7. An electronic circuit as claimed in any one of the preceding claims, The trigger element (3) is integrated in a polysilicon layer (7) formed above a first surface (101) of the semiconductor body (100).

8. An electronic circuit as claimed in any one of the preceding claims, The bipolar transistor (2) is a PNP bipolar transistor.

9. An electronic circuit as claimed in any one of the preceding claims, The breakdown voltage of the avalanche diode (4) is between 30V and 1000V.

10. The electronic circuit according to any one of claims 2 to 9, The base region (23) includes a base region extension portion (231), and the base region extension portion (231) extends along a portion of the first region (221) in the direction of the second region (222) of the collector region (22).

11. The electronic circuit according to claim 10, The base region extension (231) is adjacent to the second region (222) of the collector region (22).

12. The electronic circuit according to claim 10, The base region extension (231) is separated from the second region (222) of the collector region (22).

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