In-memory computing architecture compiling method and device, electronic equipment and system on chip

Abstract

The invention discloses an in-memory computing architecture compiling method and device, electronic equipment and a system on chip, and belongs to the technical field of in-memory computing. The method comprises the following steps: determining an initial iteration space of a polyhedral model according to a nested loop structure of a neural network operator in a compiling process; segmenting the initial iteration space into a plurality of sub-iteration spaces, and mapping iteration vectors in the plurality of sub-iteration spaces to a target base direction based on the target base transformation matrix to obtain an affine scheduling space; the method comprises the following steps: mapping an affine scheduling space to a plurality of macro units of an in-memory computing device to obtain a target mapping strategy, performing layout on memory access data corresponding to the affine scheduling space, and optimizing data handling operation of the memory access data according to a preset data handling cost function to obtain a target iteration space; and generating a compiled code according to the target iteration space. In this way, the data transmission overhead can be reduced, and the utilization rate of the macro-cell can be improved.

Description

Technical Field

[0001] The present application relates to the field of in-memory computing technology, and in particular to a method, device, electronic device, and system on chip for compiling an in-memory computing architecture. Background Art

[0002] With the rapid development of deep learning technology, computing resources and storage requirements have increased dramatically. In particular, the performance gap between processors and memory has become a bottleneck, impacting overall system performance. This gap, widening with the continued growth of data size and computational complexity, has become known as the "memory wall." Compute-in-Memory (CIM), an emerging computing paradigm, breaks through the limitations of the von Neumann architecture by embedding multiply-and-accumulate (MAC) operations directly into memory cells, eliminating the "memory wall" problem caused by frequent data movement.

[0003] Currently, a growing body of research is focusing on compiler design for in-memory computing architectures. However, related compiler optimization methods mostly target fixed-size standard convolution, point-by-point convolution operators, or depthwise operators, making them difficult to adapt to other types of operators. Furthermore, in-memory computing architectures face the unique rigidity of their array structures, resulting in low macrocell utilization when mapping convolution operators, impacting overall performance. Summary of the Invention

[0004] Embodiments of the present application provide a method, apparatus, device, and system-on-chip for compiling an in-memory computing architecture to at least solve the problem of low utilization of macro units in related in-memory computing.

[0005] In order to solve the above technical problems, this application is implemented as follows: In the first aspect, an embodiment of the present application provides an in-memory computing architecture compilation method, including: determining the initial iteration space of a polyhedron model based on the nested loop structure of a neural network operator during the compilation process; dividing the initial iteration space into multiple sub-iteration spaces, and mapping the iteration vectors in the multiple sub-iteration spaces to the target basis direction based on the target basis transformation matrix to obtain an affine scheduling space; obtaining a target mapping strategy by mapping the affine scheduling space to multiple macro units of an in-memory computing device, laying out the memory access data corresponding to the affine scheduling space, and optimizing the data transfer operation of the memory access data according to a preset data transfer cost function to obtain a target iteration space; generating compilation code based on the target iteration space.

[0006] In the second aspect, an embodiment of the present application provides an in-memory computing architecture compilation device, including: a space determination module, used to determine the initial iteration space of the polyhedron model according to the nested loop structure of the neural network operator in the compilation process; an affine scheduling module, used to divide the initial iteration space into multiple sub-iteration spaces, and map the iteration vectors in the multiple sub-iteration spaces to the target basis direction based on the target basis transformation matrix to obtain an affine scheduling space; a space optimization module, used to obtain a target mapping strategy by mapping the affine scheduling space to multiple macro units of an in-memory computing device, layout the memory access data corresponding to the affine scheduling space, and optimize the data handling operation of the memory access data according to a preset data handling cost function to obtain a target iteration space; a code compilation module, used to generate compilation code according to the target iteration space.

[0007] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the method described in the first aspect above are implemented.

[0008] In a fourth aspect, an embodiment of the present application provides a system on chip, which executes the method described in the first aspect above.

[0009] In a fifth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method described in the first aspect above are implemented.

[0010] In a sixth aspect, an embodiment of the present application provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer executes the steps of the method described in the first aspect above.

[0011] In an embodiment of the present application, an initial iteration space of a polyhedron model is determined based on a nested loop structure of a neural network operator during compilation. The initial iteration space is divided into multiple sub-iteration spaces, and iteration vectors in the multiple sub-iteration spaces are mapped to target basis directions based on a target basis transformation matrix to obtain an affine scheduling space. The affine scheduling space is mapped to multiple macrocells of an in-memory computing device to obtain a target mapping strategy, and memory access data corresponding to the affine scheduling space is laid out. The data transfer operation of the memory access data is optimized based on a preset data transfer cost function to obtain a target iteration space. Compiled code is generated based on the target iteration space. In this way, the initial iteration space of the polyhedron model can adapt to various types of neural network operators, improving the applicability of the method. The iteration vectors in the multiple sub-iteration spaces are mapped to target basis directions using the target basis transformation matrix, which can expose data reuse in non-basis directions in the operator iteration space to basis directions, thereby facilitating the mining of data reuse in the iteration space. Furthermore, by mapping the affine scheduling space to multiple macrocells and optimizing the data transfer process of the memory access data corresponding to the affine scheduling space, data transmission overhead can be reduced and macrocell utilization can be improved.

[0012] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0014] Figure 1 A schematic diagram of a process for compiling an in-memory computing architecture provided by an embodiment of the present application is shown; Figure 2 An example diagram of data reuse mining and macro unit mapping provided by an embodiment of the present application is shown; Figure 3 An example diagram of CIM array mapping provided by an embodiment of the present application is shown; Figure 4 A flowchart of the PolyCIM compilation method provided in an embodiment of the present application is shown; Figure 5 A schematic diagram of the structure of the in-memory computing architecture compilation device provided by an embodiment of the present application is shown; Figure 6 A schematic structural diagram of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0015] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0016] In this field, in-memory computing generally refers to a computing paradigm that performs calculations within memory cells. There are many ways to implement in-memory computing. The in-memory computing shown in the embodiments of this application specifically refers to a type of in-memory computing that uses macro cells to perform matrix-vector multiplication. In this method, matrix elements are stored in a memory array, and vectors are input along word lines. The input data is then multiplied with the data stored in the memory cells. Addition operations are performed on the bit lines based on Kirchhoff's laws or additional addition trees to obtain the final matrix-vector multiplication result. Each cell in the memory array can store one or more bits of data. If the weight data exceeds the capacity of a cell, the data is placed in adjacent cells on the same word line, and the adjacent results are combined using a shift-and-add unit to obtain the final result. If the width of the input data exceeds the bit width limit of each word line or the accuracy of the digital-to-analog converter, the input data is provided in a bit-serial manner over multiple cycles, and the shift-and-add unit is used to accumulate the data over multiple cycles to obtain the final result.

[0017] A memory array, along with peripheral facilities like adder trees and shift-accumulate units, forms a macrocell. Multiple macrocells form a CIM array (Compute-in-Memory), which is used to perform multiple matrix-vector multiplications simultaneously. The CIM array, along with components like the register file, scalar arithmetic unit (ALU), vector arithmetic unit (ALU), and local storage, form a computing core.

[0018] Current in-memory computing research focuses more on the design of macrocells and accelerators, often employing hand-crafted fixed dataflows that support only a few fixed operator loads. Dataflows are often fixed in the hardware or configurable via only a few simple registers. However, with the increasing complexity of deep learning algorithms and in-memory computing architectures, hand-crafted dataflows are exhibiting performance and cost disadvantages. Dataflows designed for specific hardware and algorithms are difficult to reuse in multiple scenarios, and frequent redesigns result in significant design and implementation costs, limiting the scope of in-memory computing architectures. Subtle differences in algorithmic load and hardware configuration can affect the effectiveness of the dataflow, making it difficult for rigid dataflow designs to achieve optimal performance and unleash the full potential of in-memory computing.

[0019] In recent years, researchers have begun to focus on compiler research for in-memory computing architectures. However, overall research is still in its early stages, and at least the following issues remain: a) In terms of applicability, related compilation optimization methods mainly perform mapping optimization on standard convolution operators, point-by-point convolution, depthwise convolution, or matrix multiplication operators, and have limited support for other types of neural network operators; b) In terms of performance, the relevant compilation optimization methods have not effectively solved the problem of low utilization caused by the rigid structure of macro units, resulting in poor performance on some operators and neural networks.

[0020] In response to the problems existing in the compilation process for the above-mentioned in-memory computing architecture, an embodiment of the present application provides a compilation method for an in-memory computing architecture. In this method, the initial iteration space of the polyhedron model is determined based on the nested loop structure of the neural network operator in the compilation process. The initial iteration space of the polyhedron model can adapt to various types of neural network operators, thereby improving the applicability of the method; the iteration vectors in multiple sub-iteration spaces are mapped to the target basis direction through the target basis transformation matrix, and the data reuse of the non-basis direction in the operator iteration space can be exposed to the basis direction, which is conducive to mining the data reuse in the iteration space, and then by mapping the affine scheduling space to multiple macro units and optimizing the data handling process of the memory access data corresponding to the affine scheduling space, the data transmission overhead can be reduced and the utilization rate of the macro units can be improved.

[0021] The aforementioned polyhedral model is an efficient program optimization technique primarily used to process program structures with nested loops. It abstracts the nested loops as polyhedra in a high-dimensional geometric space, enabling program parallelization and local optimization. Many classic compilation optimization algorithms and compilers based on the polyhedral model have had a significant impact on the compilation field.

[0022] To facilitate understanding of the embodiments of the present application, the relevant terms are explained as follows: (1) Iteration vector: An iteration vector of a statement S is a vector consisting of the index values ​​of all loops outside the statement.

[0023] (2) Statement instance: A statement instance S(i) of a statement S is an abstraction of an execution of the statement S, where i represents an iteration vector.

[0024] (3) Iteration Space: The set of all iteration vectors of a statement is called the iteration space of the statement, denoted as ,in, is the iteration vector, is an approximate affine function. The iteration space and nested loops can be transformed into each other. In nested loops, the lower and upper bounds of the loop subscripts at each level are pseudo-affine functions of the outer loop subscripts, which can be directly incorporated into the constraints of the iteration space. Using polyhedron scanning techniques, the iteration space can be restored to its nested loop form.

[0025] (4) Memory access relationship: The memory access relationship is the mapping from iteration space to data space: ; Given an iteration vector , the number of operands accessed can be obtained through the access relation: . The memory access relationship contains information about data dependency and data reuse. For example, the dependency relationship between different statements can be extracted from the memory access relationship through dependency analysis technology. The embodiment of the present application focuses on the data reuse relationship, that is, whether different statement instances share the same operand, thereby guiding the mapping of operators to CIM macro units.

[0026] (5) Scheduling: Scheduling is the mapping of iteration space to execution time , the schedule determines when each statement instance should be executed. Vector Represents a "timestamp." Different statement instances are executed in the order of the timestamp fields. Furthermore, if the dimensions in the timestamp are considered axes in the iteration space, scheduling can also be considered a transformation of the iteration space.

[0027] (6) Operator abstraction: use Describe an operator where D is the iteration space of the operator, These are the memory access relationships between input data, weight data, and output data. This abstraction can encompass various types of operators such as 1D convolution, 2D convolution, 3D convolution, depthwise convolution, grouped convolution, and dilated convolution.

[0028] Figure 1 A flow chart of an in-memory computing architecture compilation method provided by an embodiment of the present application is shown. As shown in the figure, the method 100 may include the following steps: Step 101: Determine the initial iteration space of the polyhedron model based on the nested loop structure of the neural network operator in the compilation process.

[0029] In this step, during the compilation process, the nested loop structure of the neural network operator is first obtained. The neural network operator can be a variety of operators such as 1D convolution, 2D convolution, 3D convolution, depth convolution, group convolution, dilated convolution, etc. In neural networks, the convolution operator is a basic and extremely core component, and is widely used in many computer vision tasks such as image recognition, target detection, and semantic segmentation. It can automatically extract local features of the image and capture feature information at different positions by sliding the convolution kernel on the image. It can effectively reduce the number of model parameters and reduce computational complexity. It can also retain the spatial structure information of the image, allowing the neural network to learn feature representations with translation invariance, thereby improving the model's ability to process and generalize image data.

[0030] For example, for a convolution operator, its nested loop includes input data, convolution kernel, and output data. The initial iteration space of the polyhedron model is determined based on the index values ​​of all loops in the outer layer of statement S in the nested loop structure.

[0031] In an exemplary embodiment, taking a 1D convolution as an example, it is assumed that the nested loop corresponding to the original 1D convolution is expressed as: foriin[0,2]; forjin[0,8]; forkin[0,3]; S: O[i,j]=I[j+k]*W[i,k] Define the operator as ,in, ; ; ; .

[0032] in, D S is the initial iteration space of the polyhedron model corresponding to the operator.

[0033] In this way, through the initial iteration space of the polyhedron model, diverse upper-layer neural network operators can be abstracted to facilitate subsequent analysis and transformation.

[0034] Step 102: Divide the initial iteration space into multiple sub-iteration spaces, and map the iteration vectors in the multiple sub-iteration spaces to the target basis direction based on the target basis transformation matrix to obtain an affine scheduling space.

[0035] In an exemplary embodiment, Figure 2As shown in (a) of the figure, taking the above 1D convolution as an example, the iterative vectors accessing the same input are arranged along the non-coordinate axis direction. The embodiment of the present application automatically analyzes the data reuse pattern of the operator and transforms the iterative space through pre-splitting scheduling and affine scheduling to mine the data reuse about the input. First, the j axis is split into two axes, j1 and j2, through pre-splitting scheduling, and the following is obtained: Figure 2 The two sub-iteration spaces shown in (b) in the figure are as follows. Here, the occurrence of subsequent empty calculations can be reduced by pre-splitting scheduling. Then, the affine transformation of the iteration space is performed through affine scheduling to obtain Figure 2 The affine scheduling space shown in (c) in FIG; The affine scheduling can arrange the iteration vectors of the reused input to a direction parallel to the basis vector.

[0036] The problem of low macro unit utilization is essentially because the data reuse in the base direction of the operator's iteration space is low, which leads to insufficient utilization of the macro unit when the base is mapped to the row or column of the macro unit that forces the reuse of data. Although there is data reuse in the non-base direction, the related Im2Col-like mapping strategy cannot utilize it. The embodiment of the present application exposes the data reuse in the non-base direction in the operator iteration space to the base direction through pre-splitting scheduling (or called loop blocking, loop splitting, etc.) and affine scheduling (or called loop tilting, etc.), and uses this non-base direction data reuse to find a mapping strategy that can maximize the utilization of the macro unit, so that it fits the rigid structure of the macro unit better and improves the utilization of the macro unit.

[0037] In a possible implementation, in step 102, the initial iteration space is divided into multiple sub-iteration spaces, including: An initial segmentation strategy set is obtained by factoring at least one dimension of the initial iteration space; a target segmentation strategy for each dimension is screened out from the initial segmentation strategy set, and a target segmentation strategy set for the initial iteration space is determined based on the target segmentation strategy for each dimension; and the initial iteration space is divided into multiple sub-iteration spaces based on each segmentation strategy in the target segmentation strategy set.

[0038] The above-mentioned step of selecting target segmentation strategies of each dimension from the initial segmentation strategy set includes at least one of the following: According to the segmentation restriction configuration information corresponding to each dimension, the target segmentation strategy is filtered from the initial segmentation strategy set; according to the upper limit of the number of segmentation layers of each dimension, the target segmentation strategy is filtered from the initial segmentation strategy set; according to the symmetry between the corresponding neural network parameters of each dimension, the target segmentation strategy is filtered from the initial segmentation strategy set.

[0039] In an exemplary embodiment, pre-slicing scheduling decomposes the dimensions of the iteration space, which can alleviate the shortcomings of subsequent affine scheduling and enhance its advantages, avoid the occurrence of macro units with extremely low utilization, and help improve the average macro unit utilization. The above-mentioned pre-slicing scheduling can include the following steps: Step 10211: Assume that the initial iteration space has n axes, and the length of each axis is ; Step 10212: For each axis s , construct an initial set of segmentation strategies based on factor decomposition: ; Step 10213: Filter the splitting strategy based on the splitting axis restriction; if the operator is configured to prohibit pre-splitting of axis i, then ; Step 10214: Filter the splitting strategy based on the upper limit of the splitting axis; if the operator is configured with an axis i The upper limit of the number of slices u i , then let In specific applications, for most operators, it is most appropriate to set the upper limit of the number of split layers to 2. A split number exceeding 2 will not lead to better results. In particular, for dilated convolution, setting the number of split layers to 3 can achieve better results. Step 10215: Screen the segmentation strategy based on symmetry; for example, for the Conv2d operator in the common convolutional neural network, H O and W O The dimensions are equal in size and their positions in the access relationship are symmetrical; H K and W K This symmetry also exists; assuming that ( H O , W O , H K , W K )The four axes are divided into two categories: t 1, t 2, t 3. t 4) and apply the subsequent scheduling process to obtain the optimal utilization r 1. It can be proved that H O , W O and HK , W K The segmentation strategies of are exchanged respectively, that is, the segmentation strategy ( t 2, t 1, t 4. t 3) and applying the subsequent scheduling process, we will get exactly the same optimal utilization r 1; Step 10216: Cartesian product of all axis segmentation strategy sets to obtain a complete segmentation strategy set ; Step 10217: According to F For each splitting strategy in , a splitting schedule is constructed and applied to the original iteration space and memory access relationship. The transformed result is used to continue the subsequent transformation.

[0040] In one possible implementation, in step 102, mapping the iteration vectors in the multiple sub-iteration spaces to the target basis directions based on the target basis transformation matrix to obtain an affine scheduling space includes: A reuse hyperplane is constructed, and the reuse hyperplane is used to represent the set of statement instances that reuse the same data elements in the sub-iteration space; based on the reuse hyperplane, a set of candidate basis vectors is determined, each candidate basis vector in the candidate basis vector set is parallel to the reuse hyperplane, and the number of statement instances corresponding to each candidate basis vector exceeds a preset number threshold; a target basis combination is selected from the candidate basis vector set, and a target basis transformation matrix is ​​determined based on the target basis combination; multiple sub-iteration spaces are mapped to the target basis direction based on the target basis transformation matrix to obtain an affine scheduling space.

[0041] In an exemplary embodiment, an affine transformation is performed on the iteration space to convert the data reuse in the non-basis reverse direction to the basis direction so that it can be mapped to the macro unit. The affine scheduling includes the following steps: Step 10221: construct a reuse hyperplane; This embodiment of the application uses the concept of reuse hyperplanes to represent data reuse. Each array access is associated with a set of reuse hyperplanes that describe the set of statement instances that reuse the same data elements in the iteration space. When array T is an m-dimensional array, its access relationship has the following form: ; At this time, a set of reused hyperplanes of the m-dimensional array T is defined as: ; in, yes nA constant. For any two statement instances to access the same element of array T, a necessary condition is that they are located within the same reuse hyperplane of the multi-dimensional array T.

[0042] Step 10222: Construct candidate basis direction constraints; Reuse direction constraints mean that the basis vectors should be parallel to the reuse hyperplane. In this way, the iteration vectors arranged along the direction of the new basis vectors will be located on the same reuse hyperplane, enabling them to share the same operands. For an n-dimensional iteration space D and an m-dimensional array T (with the array access index matrix being A), the basis vectors if and only if is satisfied, the vector b is parallel to the reuse hyperplane of array T, and the statement instances along the direction of b have the opportunity to reuse the same elements in array A.

[0043] [[ID=^{12}]]Step 10223: Construct candidate basis reuse degree constraints; Just satisfying the reuse direction constraints may still not enable actual data reuse. For example, there may be only 1 statement instance along the reuse direction. To solve this problem, it is necessary to further introduce reuse degree constraints. Given an n-dimensional iteration space D with a constant boundary, let the value range of its i-th dimension be , that is, along the i-th dimension, it contains statement instances, and the basis vector b that satisfies the reuse direction constraints. Then, the reuse degree of the iteration space D on the basis vector b is at least r if and only if ; Step 10224: Construct candidate basis set; The new basis needs to satisfy both the reuse direction constraints and the reuse direction constraints with a minimum reuse degree of 1 to ensure that there must be data reuse in the new basis direction. For this purpose, construct the following integer set: ; [[ID=^{30}]]As the candidate basis vector set. Among them, Ab = 0 is the reuse direction constraint, and -m < b < m is the reuse degree constraint. Using the Integer Set Library (ISL), the vector set that conforms to the above constraints can be quickly solved.

[0044] Step 10225: Screening of basis vector set based on vector direction; The candidate basis vector set B may contain a large number of vectors, resulting in a large scale for subsequent search steps. To reduce the search scale and maintain the search results, it is necessary to further trim the candidate basis vector set. In the candidate basis vector set, for the vector b, if there exists and , such that , then the vector Eliminate it from B. Because it will never appear in the same basis as b, and it will not be able to create a better result than b.

[0045] Step 10226: Construct candidate base combinations; Given a set of candidate basis vectors B, we need to select n linearly independent bases from them to form a basis combination to span the linear space. After obtaining all the selected cases, we filter them out: we filter out linearly dependent basis combinations and we filter out target basis combinations that are not reused for a particular operand.

[0046] Step 10227: Construct an affine schedule; For each target basis combination, construct an affine schedule for it. First, construct the basis transformation matrix , and then invert this matrix to obtain the coordinate transformation matrix The coordinate transformation matrix may contain fractions. To facilitate subsequent processing, each row of P needs to be converted to an integer. Assuming that all fractions are in their simplest form, for each row p i , multiplying it by the least common multiple of the denominators in that row: ; ; All elements of the coordinate transformation matrix can be converted to integers. It should be noted that this conversion does not destroy the scheduling results.

[0047] Finally, convert the coordinate transformation matrix into scheduling form: ; And apply it to the iteration space and memory access relationship to perform the transformation operation.

[0048] Step 103: By mapping the affine scheduling space to multiple macro units of the in-memory computing device, a target mapping strategy is obtained, the memory access data corresponding to the affine scheduling space is laid out, and the data transfer operation of the memory access data is optimized according to a preset data transfer cost function to obtain the target iteration space.

[0049] In this step, through the pre-splitting and affine scheduling steps described above, hidden data reuse is exposed in the base direction of the iteration space, facilitating further mapping to macrocells. Furthermore, by mapping the affine scheduling space to multiple macrocells in the in-memory computing device, a target mapping strategy is obtained. Data is then laid out in the affine scheduling space based on the target mapping strategy, and data transfer operations in the affine scheduling space are optimized according to a preset data transfer cost function to obtain the target iteration space.

[0050] In a possible implementation, in step 103, obtaining a target mapping strategy by mapping the affine scheduling space to multiple macro units includes: The affine scheduling space is mapped to the virtual macrocell; the virtual macrocell is divided according to the hardware parameters of the multiple macrocells in the in-memory computing device to obtain multiple groups of macrocell mapping strategies; the average macrocell utilization of each group of macrocell mapping strategies is determined; and the mapping strategy with the highest average macrocell utilization among the multiple groups of macrocell mapping strategies is determined as the target mapping strategy.

[0051] In this step, the mapping process of the affine scheduling space is divided into two steps: virtual mapping and physical mapping. Virtual mapping focuses on data reuse and maps the iteration space to a virtual infinite macro unit to ensure that the software's data reuse pattern matches the macro unit's data reuse pattern. Physical mapping further limits the macro unit size, "cutting" the iteration space mapped to the virtual macro unit into the actual macro unit size and mapping it to the physical macro unit. In terms of implementation, virtual mapping corresponds to a loop merge scheduling, and physical mapping corresponds to a loop block scheduling.

[0052] In an exemplary embodiment, Figure 2 As shown in (c), data reuse has been mined. Through further merging scheduling and post-splitting scheduling, the iteration space can fit the size of the macro unit and then be mapped to the macro unit. Through (3) merging scheduling, the i axis j i Axis is merged into q axis to reuse input, such as Figure 2 As shown in (d) in the figure. At the same time, the p-axis can reuse the output. Assuming that the target macro unit has a sufficiently large number of rows and columns, the mapping of the operator to the macro unit can be completed by binding q to the row dimension of the macro unit and p to the column dimension of the macro unit, as shown in Figure 2 However, when the macro unit size is smaller than the size of the p and q axes, the iteration space needs to be further divided through the post-division scheduling (4) to match the CIM array size, and the result is Figure 2 The result shown in (f) in the figure is shown in the figure. The final result of binding to the macro unit is as follows: Figure 2 As shown in (g).

[0053] The specific implementation steps of the above mapping process include: Step 10311: data reuse analysis and axis classification; Assume the current affine scheduling space is , whose boundaries are All axes are divided into three categories according to their data reuse types. Multiplexed input, q basis Multiplexed output, the remaining k=np-1 basis Does not participate in input or output data multiplexing.

[0054] Step 10312: Build a merge schedule; First define the coordinate merging function: ; Based on this operation, build a merge schedule:

[0055] This schedule is then applied to the operator. After the merge schedule, bases that reuse the same data are merged into a single base, which directly corresponds to the data reuse dimension in the macro unit. Assuming a sufficiently large virtual macro unit exists, the current iteration space can be directly and legally mapped into the macro unit.

[0056] Step 10313: Post-segmentation scheduling; The real macro unit has a size limit, and the iteration space exceeding this size cannot be directly mapped on it. Therefore, the macro unit size is further limited through the physical mapping process, and the iteration space mapped to the virtual macro unit is "cut" into the real macro unit size. Let the current iteration space be , and assuming that the number of rows of a macro unit is r and the number of columns is c, then the following post-segmentation scheduling is constructed: ; After this scheduling, the two innermost axes of the iteration space comply with both the data reuse constraint and the macrocell size and can be directly mapped to the macrocell. If the remaining axes are mapped to the time dimension, the operator mapping to a single macrocell is complete.

[0057] The data reuse mining and macrocell mapping process described above generates multiple sets of candidate mapping strategies. For each set of mapping strategies, the average macrocell utilization is calculated, and the target mapping strategy with the highest utilization is retained for subsequent compilation.

[0058] In specific applications, a CIM array usually contains multiple macro units, and there is no strict data reuse constraint between multiple macro units. The above process has mapped the iteration space to a single macro unit and regarded the remaining axis as the time axis. However, this cannot fully utilize the other macro units working in parallel on the chip. It is necessary to further convert part of the time axis into a space axis and map it between different macro units to fully utilize the computing power of multiple macro units on the chip, such as Figure 3 To achieve this goal, the embodiment of the present application adopts a heuristic strategy to implement CIM array mapping, and the CIM array mapping is generally divided into the following steps: Step 10321: Axis classification; The time axes in the affine scheduling space that are not mapped to the macro unit are classified into the following categories: (1) Reuse output axis: the iteration vectors arranged along this axis share output; (2) Reuse input axis: the iteration vectors arranged along this axis share input; (3) Reuse weight axis: the iteration vectors arranged along this axis share weight; (4) Non-reuse axis: the iteration vectors arranged along this axis do not share any operands or outputs. In most cases, these four categories can form a partition of the entire time axis set.

[0059] Step 10322: Axis sorting; The time axes are prioritized from high to low in the order of reused output axis -> reused input axis -> non-reused axis -> reused weight axis, and sorted. Categories with higher priorities are mapped to the multi-macrocell dimension first.

[0060] Step 10323: axis mapping; In descending order of priority, the time axis is included in the multi-macro unit dimension. Assume that the current included axis i and the remaining number of macro units is M. Find the maximum factor that can be included in the multi-macro unit of axis i If f max =1, it means that the macro unit has been used up, no further mapping is required, and the algorithm is exited; if f max =s i , then include the full i-axis into the multi-macro unit dimension and divide M by s i To reduce the number of currently available macro units and continue the mapping process of the next axis; if , then the i-axis is divided into a loop: ; The inner i i The axis is mapped to the multi-macrocell dimension, and the algorithm is stopped. Through the above algorithm process, the time axis can be mapped to the multi-macrocell dimension according to the arranged priority. In this way, multiple macrocells on the chip can be fully and efficiently utilized.

[0061] In one possible implementation, in step 103, the memory access data corresponding to the affine scheduling space is laid out, and the data transfer operation of the memory access data is optimized according to a preset data transfer cost function to obtain a target iteration space, including: The memory access data corresponding to the affine scheduling space is cyclically divided to obtain multiple subtasks; the data transfer cost function is determined based on the number of data transfers and the amount of data transferred; with the goal of minimizing the data transfer cost function, data layout is performed on multiple subtasks to obtain the optimized target iteration space.

[0062] In this step, when the original data layout is used directly (for example, for the input and output of a 2D convolution, the classic layouts are NCHW or NHWC), the discontinuous nature of data access during the calculation process will introduce a large number of small data movement instructions, which cannot effectively utilize memory bandwidth. This embodiment of the present application introduces the concept of iterative spatially aligned data layout (Domain-Aligned Data Layout), which rearranges data according to the order in which statement instances are accessed. This ensures that the data accessed by each data movement and CIM calculation is physically continuous.

[0063] Definition: Let the iteration space , whose n axes are i1,…,i n , where k axes dominate the array T:i p1 ,…,i pk , the current access relationship for array T is AccRel T If the array satisfy: ; Then it is called T align An iterative spatial alignment layout for T.

[0064] Based on the concept of iterative spatial alignment layout, the original data transfer process can be decoupled into two stages: the first stage is to convert the data from the original layout to the iterative spatial alignment layout before calculation; the second stage is to extract regular and continuous data from the iterative spatial alignment layout in real time during calculation to complete the calculation.

[0065] The data layout conversion in the first phase can be implemented through a variety of different methods, such as designing a data layout conversion program or designing a dedicated hardware conversion unit. The solution adopted in the embodiment of the present application is to generate a program based on C++ code from the data layout conversion logic and put it into the CPU outside the chip for implementation. The CIM architecture reads the converted data and performs calculations. Specifically, the conversion process includes the following steps: Step 10331: Obtain memory access relationship; Get the access relationship of the original array respectively The memory access relationship of the array after the iteration space alignment layout .

[0066] Step 10332: Generate abstract syntax tree; Using the Integer Set Library (ISL) tool, we perform a polyhedron scan of the iteration space D, generating an equivalent abstract syntax tree consisting of nested loops and conditional branches. By incorporating the loop subscript into the access relation, we can further derive the abstract syntax tree for computing the array access subscript.

[0067] Step 10333: C++ code generation; recursively traverse the abstract syntax tree to generate C++ code for data layout conversion.

[0068] Step 10334: Generate an executable program. The C++ code is further compiled into an executable program using the g++ compiler, and the program completes the data layout conversion process.

[0069] Although the iterative space alignment layout is relatively regular, the calculation process still involves a large amount of input and output data handling operations, which requires further memory access optimization to improve data locality and reduce data handling overhead. The basic idea of ​​optimization is to minimize data handling overhead through different loop segmentation, loop rearrangement and memory access level setting strategies. The embodiment of the present application uses mixed integer programming (MIP) to model and solve the data handling process. The steps are as follows: Step 10341: loop segmentation; Assume that the current iteration space has N axes (which can be understood as N layers of loops). After factoring and looping, the i-th axis is divided into m i After all N axes are decomposed, we get new axes, let the jth axis I j The length is S j .

[0070] Step 10342: Define a permutation matrix; Let matrix , used to represent the cyclic exchange scheduling to be done (i.e. subtasks): ; X i,j =1 means that the current j-th axis I j Swap to the position of the i-th axis. Obviously, X is a permutation matrix, which must satisfy that there is only one 1 element in each row and column, and all other positions are 0 elements. Therefore, the following constraints are added to X: ; Step 10343: define access information; Consider inserting operand T into the storage level local_buffer. Let vector , used to characterize the axes that dominate the operand I and their sizes. All elements in A are constants, satisfying ; Step 10344: define the memory access hierarchy; Let vector , used to express the level at which the operand I will loop through the local_buffer. The loop access at level i can be expressed as and To this end, L must satisfy the following conditions: ; Step 10345: Construct storage size constraints; Considering the size B occupied by operand I on the local bufffer, it can be expressed as ; The independent variable is in the exponential position. Taking the logarithm of both sides of the equation gives ; Assume the size of the local buffer is B max , we can restrict the use of the local buffer by adding the following constraints: ; Step 10346: Modeling the number of data transfers Considering the number of data transfers of operand I on the local bufffer, it can be expressed as: ; Taking the logarithm of both sides, we get ; Step 10347: Data handling volume modeling; Consider the total amount of data carried by operand I on the local buffer is ; Taking the logarithm of both sides, we get ; Step 10348: Objective function construction Use a similar method to get the Traf of other operands at different memory levels. Add them directly as the objective function: ; Step 10349: Solve; The objective function and the constraints contain multiplication of independent variables, which is nonlinear. i,j and L iThey are all 0-1 variables and are small in scale, so they can be solved quickly using the Gurobi solver.

[0071] Step 103410: rewrite the intermediate representation; Perform loop swaps based on X, insert memory access information at corresponding locations based on L, and generate data handling instructions during code generation.

[0072] In this way, by decoupling the original data transfer problem and solving it separately, the complexity of the problem can be reduced; by solving the optimal data transfer process through MIP, the performance of in-memory computing can be improved.

[0073] Step 104: Generate compiled code according to the target iteration space.

[0074] In this step, the result of the above-mentioned iteration space optimization, that is, the target iteration space, is output in an executable form so that the optimization strategy can be implemented and executed on the target hardware.

[0075] In one possible implementation, in step 104, generating compiled code according to the target iteration space includes: Perform a polyhedron scan on the target iteration space to generate an abstract syntax tree; recursively traverse the abstract syntax tree to generate compiled code for the domain-specific language.

[0076] In this step, ISL performs a polyhedron scan of the iteration space, identifying key information such as data dependencies and loop execution order. Based on this information, an Abstract Syntax Tree (AST) is generated. All branches of the AST are recursively traversed to generate compiled code for the Domain-Specific Language (DSL). The backend compiler then compiles the DSL into instructions.

[0077] In an exemplary embodiment, Figure 4 As shown, during the compilation process, neural network operators are defined, and operator definitions and in-memory computing device (CIM) configuration information are input. Data reuse is then mined through pre-slicing and affine scheduling, and macrocell mapping is performed through merge scheduling and post-slicing scheduling. CIM array mapping and data handling optimization are then performed, and finally compiled code is generated. This approach reduces data transmission overhead and improves macrocell utilization.

[0078] Figure 5 The schematic diagram of the structure of the in-memory computing architecture compilation device provided by the embodiment of the present application is shown. The in-memory computing architecture compilation device can implement the following Figure 1 In the embodiment shown, all or part of the content, the in-memory computing architecture compilation device 500 includes: A space determination module 510 is used to determine the initial iteration space of the polyhedron model according to the nested loop structure of the neural network operator during the compilation process; An affine scheduling module 520 is configured to divide the initial iteration space into a plurality of sub-iteration spaces, and map the iteration vectors in the plurality of sub-iteration spaces to target basis directions based on a target basis transformation matrix to obtain an affine scheduling space; A space optimization module 530 is configured to map the affine scheduling space to multiple macro units of an in-memory computing device to obtain a target mapping strategy, lay out memory access data corresponding to the affine scheduling space, and optimize data transfer operations of the memory access data according to a preset data transfer cost function to obtain a target iteration space. The code compiling module 540 is configured to generate compiled code according to the target iteration space.

[0079] In a possible implementation, the affine scheduling module 520, when used to divide the initial iteration space into a plurality of sub-iteration spaces, is specifically configured to: Obtaining an initial segmentation strategy set by factoring at least one dimension of the initial iteration space; Filtering target segmentation strategies of various dimensions from the initial segmentation strategy set, and determining the target segmentation strategy set of the initial iteration space according to the target segmentation strategies of various dimensions; According to each segmentation strategy in the target segmentation strategy set, the initial iteration space is divided into a plurality of sub-iteration spaces.

[0080] In a possible implementation, the affine scheduling module 520, when used to filter out the target segmentation strategies of each dimension from the initial segmentation strategy set, is specifically used to: Filtering a target segmentation strategy from the initial segmentation strategy set according to the segmentation restriction configuration information corresponding to each dimension; Filtering a target segmentation strategy from the initial segmentation strategy set according to the upper limit of the number of segmentation layers of each dimension; According to the symmetry between the corresponding neural network parameters of each dimension, the target segmentation strategy is screened from the initial segmentation strategy set.

[0081] In one possible implementation, the affine scheduling module 520, when used to map the iteration vectors in the multiple sub-iteration spaces to the target basis direction based on the target basis transformation matrix to obtain the affine scheduling space, is specifically used to: Constructing a reuse hyperplane, where the reuse hyperplane is used to represent a set of statement instances that reuse the same data elements in the sub-iteration space; Determine a set of candidate basis vectors based on the reused hyperplane, wherein each candidate basis vector in the set of candidate basis vectors is parallel to the reused hyperplane, and the number of sentence instances corresponding to each candidate basis vector exceeds a preset threshold value; Selecting a target basis combination from the candidate basis vector set, and determining a target basis transformation matrix according to the target basis combination; The multiple sub-iteration spaces are mapped to the target basis direction according to the target basis transformation matrix to obtain an affine scheduling space.

[0082] In one possible implementation, the space optimization module 530, when used to map the affine scheduling space to multiple macro units of the in-memory computing device to obtain a target mapping strategy, is specifically configured to: Mapping the affine scheduling space to virtual macrocells; Dividing the virtual macrocell according to hardware parameters of a plurality of macrocells in the in-memory computing device to obtain a plurality of groups of macrocell mapping strategies; determining an average macrocell utilization for each set of macrocell mapping strategies; The mapping strategy with the highest average macrocell utilization rate among the multiple groups of macrocell mapping strategies is determined as the target mapping strategy.

[0083] In one possible implementation, the space optimization module 530, when used to layout the memory access data corresponding to the affine scheduling space and optimize the data transfer operation of the memory access data according to a preset data transfer cost function to obtain the target iteration space, is specifically configured to: Circularly dividing the memory access data corresponding to the affine scheduling space to obtain multiple subtasks; Determine the transport cost function based on the number of data transports and the amount of data transported; With the goal of minimizing the data handling cost function, data layout is performed on the multiple subtasks to obtain an optimized target iteration space.

[0084] An embodiment of the present application provides an in-memory computing architecture compilation device, including a space determination module, an affine scheduling module, a space optimization module and a code compilation module; the space determination module determines the initial iteration space of the polyhedron model according to the nested loop structure of the neural network operator in the compilation process; the affine scheduling module divides the initial iteration space into multiple sub-iteration spaces, and maps the iteration vectors in the multiple sub-iteration spaces to the target basis direction based on the target basis transformation matrix to obtain an affine scheduling space; the space optimization module obtains a target mapping strategy by mapping the affine scheduling space to multiple macro units of an in-memory computing device, layouts the memory access data corresponding to the affine scheduling space, and optimizes the data transfer operation of the memory access data according to a preset data transfer cost function to obtain a target iteration space; the code compilation module generates compilation code according to the target iteration space. In this way, the initial iteration space of the polyhedron model can adapt to various types of neural network operators, improve the applicability of the method, and map the iteration vectors in multiple sub-iteration spaces to the target basis direction through the target basis transformation matrix. The data reuse of the non-basis direction in the operator iteration space can be exposed to the basis direction, which is conducive to mining the data reuse in the iteration space. Furthermore, by mapping the affine scheduling space to multiple macro units and optimizing the data handling process of the memory access data corresponding to the affine scheduling space, the data transmission overhead can be reduced and the utilization rate of the macro units can be improved.

[0085] Figure 6 A schematic diagram of the hardware structure of an electronic device that implements the embodiments of the present application is shown. Referring to this figure, at the hardware level, electronic device 600 includes a processor 610, and optionally includes an internal bus 620, a network interface 630, and a memory 640. The memory 640 may include a memory 641, such as a high-speed random-access memory (RAM), and may also include a non-volatile memory 642, such as at least one disk storage device. Of course, the electronic device may also include hardware required for other services.

[0086] The processor 610, network interface 630, and memory can be interconnected via an internal bus 620. This internal bus 620 can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus. Such buses can be classified as address buses, data buses, control buses, and the like. For ease of illustration, the figure uses only one bidirectional arrow, but this does not imply that there is only one bus or only one type of bus.

[0087] The memory 640 stores programs. Specifically, the programs may include program codes, which include computer operating instructions. The memory 640 may include a memory 641 and a non-volatile memory 642, and provides instructions and data to the processor 610.

[0088] The processor 610 reads the corresponding computer program from the non-volatile memory 642 into the memory and then runs it, forming a device for locating the target user at the logical level. The processor 610 executes the program stored in the memory and specifically performs the following: Figure 1 The methods disclosed in the illustrated embodiments implement the functions and beneficial effects of the various methods described in the foregoing method embodiments, which will not be described in detail here.

[0089] The above application Figure 1The methods disclosed in the illustrated embodiments can be applied to or implemented by processor 610. Processor 610 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be performed by hardware integrated logic circuits or software instructions within processor 610. The processor 610 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The methods, steps, and logic block diagrams disclosed in the embodiments of this application can be implemented or executed. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly executed by a hardware decoding processor or by a combination of hardware and software modules within the decoding processor. The software module can be located in a storage medium well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0090] The computer device can also execute the methods described in the above method embodiments and realize the functions and beneficial effects of the methods described in the above method embodiments, which will not be repeated here.

[0091] Of course, in addition to software implementation, the electronic device of this application does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc. That is to say, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic devices.

[0092] An embodiment of the present application also proposes a system on chip, which executes the above-mentioned in-memory computing architecture compilation method.

[0093] The embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, which, when executed by an electronic device including multiple application programs, enables the electronic device to execute Figure 1The methods disclosed in the illustrated embodiments implement the functions and beneficial effects of the various methods described in the foregoing method embodiments, which will not be described in detail here.

[0094] The computer-readable storage medium includes a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0095] Furthermore, an embodiment of the present application provides a computer program product, comprising a computer program stored on a non-transitory computer-readable storage medium, wherein the computer program comprises program instructions. When the program instructions are executed by a computer, the following process is implemented: Figure 1 The methods disclosed in the illustrated embodiments implement the functions and beneficial effects of the various methods described in the foregoing method embodiments, which will not be described in detail here.

[0096] The embodiments of the present application can be applied to various electronic device collaboration or interconnection scenarios, including: collaboration and interconnection between mobile phones and laptops / tablets; collaboration and interconnection between mobile terminals and smart TVs / displays; collaboration and interconnection between mobile phones or tablets and in-car entertainment systems; collaboration and interconnection between mobile terminals and smart conference systems, etc., thereby meeting the diverse needs of users in scenarios such as smart homes, smart offices, and smart travel.

[0097] In short, the above description is only a preferred embodiment of the present application and does not limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

[0098] The systems, devices, modules, or units described in the above embodiments may be implemented by computer chips or entities, or by products having certain functions. A typical implementation device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smartphone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0099] Computer-readable media includes permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media (transitory media), such as modulated data signals and carrier waves.

[0100] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0101] The various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the description of the method embodiments.

Claims

1. A method for compiling an in-memory computing architecture, characterized in that: include: Determine the initial iteration space of the polyhedron model based on the nested loop structure of the neural network operator during the compilation process; The initial iteration space is divided into a plurality of sub-iteration spaces, and the iteration vectors in the plurality of sub-iteration spaces are mapped to the target basis direction based on the target basis transformation matrix to obtain an affine scheduling space; A target mapping strategy is obtained by mapping the affine scheduling space to a plurality of macro units of an in-memory computing device, laying out memory access data corresponding to the affine scheduling space, and optimizing data transfer operations of the memory access data according to a preset data transfer cost function to obtain a target iteration space; Generate compiled code according to the target iteration space.

2. The method according to claim 1, characterized in that The step of dividing the initial iteration space into a plurality of sub-iteration spaces comprises: Obtaining an initial segmentation strategy set by factoring at least one dimension of the initial iteration space; Filtering target segmentation strategies of various dimensions from the initial segmentation strategy set, and determining the target segmentation strategy set of the initial iteration space according to the target segmentation strategies of various dimensions; According to each segmentation strategy in the target segmentation strategy set, the initial iteration space is divided into a plurality of sub-iteration spaces.

3. The method according to claim 2, characterized in that The step of selecting target segmentation strategies for each dimension from the initial segmentation strategy set includes at least one of the following: Filtering a target segmentation strategy from the initial segmentation strategy set according to the segmentation restriction configuration information corresponding to each dimension; Filtering a target segmentation strategy from the initial segmentation strategy set according to the upper limit of the number of segmentation layers of each dimension; According to the symmetry between the corresponding neural network parameters of each dimension, the target segmentation strategy is screened from the initial segmentation strategy set.

4. The method according to claim 1, wherein The step of mapping the iteration vectors in the plurality of sub-iteration spaces to the target basis direction based on the target basis transformation matrix to obtain an affine scheduling space includes: Constructing a reuse hyperplane, where the reuse hyperplane is used to represent a set of statement instances that reuse the same data elements in the sub-iteration space; Determine a set of candidate basis vectors based on the reused hyperplane, wherein each candidate basis vector in the set of candidate basis vectors is parallel to the reused hyperplane, and the number of sentence instances corresponding to each candidate basis vector exceeds a preset threshold value; Selecting a target basis combination from the candidate basis vector set, and determining a target basis transformation matrix according to the target basis combination; The multiple sub-iteration spaces are mapped to the target basis direction according to the target basis transformation matrix to obtain an affine scheduling space.

5. The method according to claim 1, wherein The obtaining of a target mapping strategy by mapping the affine scheduling space to a plurality of macro units of an in-memory computing device includes: Mapping the affine scheduling space to virtual macrocells; Dividing the virtual macrocell according to hardware parameters of a plurality of macrocells in the in-memory computing device to obtain a plurality of groups of macrocell mapping strategies; determining an average macrocell utilization for each set of macrocell mapping strategies; The mapping strategy with the highest average macrocell utilization rate among the multiple groups of macrocell mapping strategies is determined as the target mapping strategy.

6. The method according to claim 1, characterized in that The step of laying out the memory access data corresponding to the affine scheduling space and optimizing the data handling operation of the memory access data according to a preset data handling cost function to obtain a target iteration space includes: Circularly dividing the memory access data corresponding to the affine scheduling space to obtain multiple subtasks; Determine the transport cost function based on the number of data transports and the amount of data transported; With the goal of minimizing the data handling cost function, data layout is performed on the multiple subtasks to obtain an optimized target iteration space.

7. The method according to any one of claims 1 to 6, characterized in that Generating compiled code according to the target iteration space includes: Performing a polyhedron scan on the target iteration space to generate an abstract syntax tree; The abstract syntax tree is recursively traversed to generate compiled code in a domain-specific language.

8. An in-memory computing architecture compilation device, characterized in that: include: A space determination module is used to determine the initial iteration space of the polyhedron model according to the nested loop structure of the neural network operator in the compilation process; An affine scheduling module is used to divide the initial iteration space into multiple sub-iteration spaces, and map the iteration vectors in the multiple sub-iteration spaces to the target basis direction based on the target basis transformation matrix to obtain an affine scheduling space; a space optimization module, configured to obtain a target mapping strategy by mapping the affine scheduling space to a plurality of macro units of an in-memory computing device, layout memory access data corresponding to the affine scheduling space, and optimize data transfer operations of the memory access data according to a preset data transfer cost function to obtain a target iteration space; A code compilation module is used to generate compiled code according to the target iteration space.

9. An electronic device, characterized in that: The electronic device includes a processor and a memory, wherein the memory stores programs or instructions that can be run on the processor, and when the programs or instructions are executed by the processor, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A system on chip, characterized in that: The method according to any one of claims 1 to 7 is performed.

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