Preparation method of nanoscale contact resistance test structure and nanoscale contact resistance test structure
By forming a channel in the surface silicon of the substrate and forming a vertical contact surface between the sidewall of the contact hole and the channel, combined with chemical mechanical polishing, the problem of current crowding effect at the nanoscale is solved, and the precise preparation and testing of the nanoscale contact resistance test structure is achieved.
Patent Information
- Application Number
- CN202510709613.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-29
- Publication Date
- 2025-09-12
AI Technical Summary
At the nanoscale, the current crowding effect causes carriers to abnormally aggregate at contact edges or interface defects, forming a non-uniform current density distribution, which affects the conduction characteristics and reliability of the device. Existing technologies make it difficult to accurately extract the specific contact resistivity.
A channel is formed by doping and activating the surface silicon of the substrate, etching to form a contact hole and forming a vertical contact surface between the sidewall and the channel, and then performing metal deposition and chemical mechanical polishing to generate a nanoscale contact resistance test structure.
It achieves uniform current distribution, reduces the impact of process fluctuations, and improves the accuracy of contact resistance testing and the performance and reliability of devices.
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Figure CN120637252A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to a preparation method of a nanoscale contact resistance test structure and the nanoscale contact resistance test structure. Background Art
[0002] The specific contact resistivity of semiconductor devices is a core parameter for measuring the quality of ohmic contacts, and its accurate extraction is crucial for device design and process optimization.
[0003] The extraction methods of related technologies rely on the assumption of uniform current distribution at the macroscale. However, at the nanoscale, the current crowding effect causes carriers to abnormally aggregate at the contact edge or interface defects, forming a non-uniform current density distribution, triggering a serious current crowding effect, significantly increasing the specific contact resistivity, and thus affecting the device's conduction characteristics and reliability. Summary of the Invention
[0004] In view of the above problems, the present disclosure provides a method for preparing a nanoscale contact resistance test structure and a nanoscale contact resistance test structure.
[0005] According to a first aspect of the present disclosure, a method for preparing a nanoscale contact resistance test structure is provided, which is characterized in that the method includes: doping and activating the surface silicon of a substrate to form a channel; etching the channel to form a contact hole, and forming a vertical contact surface between the sidewall of the contact hole and the channel; depositing metal on the surface where the contact hole is formed to generate a metal layer; chemically mechanically polishing the metal layer to remove the metal layer outside the contact hole to obtain a polished metal layer; and etching the polished metal layer into a test pad to obtain a nanoscale contact resistance test structure.
[0006] According to an embodiment of the present disclosure, metal deposition is performed on a surface where a contact hole is formed to generate a metal layer, including: performing metal deposition treatment on the surface where the contact hole is formed to generate a metal film at least on the bottom and sidewalls of the contact hole; performing silicidation annealing treatment on the metal film to generate a silicide layer; and performing metal deposition treatment on the surface of the silicide layer to generate a metal layer.
[0007] According to an embodiment of the present disclosure, the metal layer includes at least one of Ti, Ni, Mo, or Co.
[0008] According to an embodiment of the present disclosure, etching the channel to form a contact hole includes: depositing a semiconductor dielectric on the channel to generate a dielectric layer; and etching the channel and the dielectric layer to form the contact hole.
[0009] According to an embodiment of the present disclosure, the semiconductor medium includes at least one of SiO 2 or Si 3 N 4 .
[0010] According to an embodiment of the present disclosure, the test pad is etched on the polished metal layer to obtain a nanoscale contact resistance test structure, including: performing metal deposition processing on the polished metal layer to generate a target metal layer; and etching the test pad on the target metal layer to obtain a nanoscale contact resistance test structure.
[0011] According to an embodiment of the present disclosure, metal deposition is performed on the polished metal layer to generate a target metal layer, including: depositing a semiconductor medium on the polished metal layer and etching it to form a groove on the metal layer; and performing metal deposition processing on the surface of the groove and the surface of the semiconductor medium to generate the target metal layer.
[0012] According to an embodiment of the present disclosure, the type of the substrate includes SOI, and the surface silicon layer includes a silicon cap layer.
[0013] According to an embodiment of the present disclosure, a substrate is doped and activated to form a channel, which includes: uniformly doping a surface silicon layer of the substrate with a dopant, wherein the dopant includes impurity atoms.
[0014] A second aspect of the present disclosure provides a nanoscale contact resistance test structure, which is prepared by the above method.
[0015] According to the embodiments of the present disclosure, the surface silicon of the substrate is doped and activated to form a channel; the channel is etched to form a contact hole, and a vertical contact surface is formed between the sidewall of the contact hole and the channel; metal is deposited on the surface formed with the contact hole to generate a metal layer; the metal layer is chemically and mechanically polished to remove the metal layer outside the contact hole to obtain a polished metal layer; the polished metal layer is etched with a test pad to obtain a nanoscale contact resistance test structure. Since a vertical contact surface is formed between the sidewall of the contact hole and the channel, the problem of abnormal carrier aggregation at the contact edge or interface defect in the related art, resulting in non-uniform current density distribution, is avoided, and uniform current distribution is achieved; since the metal layer is chemically and mechanically polished, the preparation and testing of the nanoscale contact resistance test structure is achieved, reducing the impact of process fluctuations. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:
[0017] Figure 1 A flow chart schematically illustrates a method for preparing a nanoscale contact resistance test structure according to an embodiment of the present disclosure;
[0018] Figure 2A A schematic diagram of a current flow of a nanoscale contact resistance test structure according to an embodiment of the present disclosure is shown;
[0019] Figure 2B Schematically shows a cross-sectional view of a nanoscale contact resistance test structure according to an embodiment of the present disclosure;
[0020] Figure 3 Schematically shows a schematic diagram of a substrate according to an embodiment of the present disclosure;
[0021] Figure 4 A schematic diagram of a channel according to an embodiment of the present disclosure is schematically shown.
[0022] Figure 5 A schematic diagram of a contact hole according to an embodiment of the present disclosure is schematically shown;
[0023] Figure 6 A schematic diagram schematically illustrates a metal layer grown on the surface of a contact hole according to an embodiment of the present disclosure;
[0024] Figure 7 A schematic diagram schematically illustrates silicide grown on the surface of a contact hole according to an embodiment of the present disclosure;
[0025] Figure 8 Schematic diagram showing a metal layer grown on a silicide surface according to an embodiment of the present disclosure;
[0026] Figure 9 Schematically shows a schematic diagram of a metal layer after polishing according to an embodiment of the present disclosure;
[0027] Figure 10 Schematically shows a schematic diagram of a groove according to an embodiment of the present disclosure;
[0028] Figure 11 Schematically shows a schematic diagram of a target metal layer according to an embodiment of the present disclosure;
[0029] Figure 12 A schematic diagram of a nanoscale contact resistance test structure according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION
[0030] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.
[0031] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0032] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.
[0033] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).
[0034] The actual current distribution in contact resistance test structures of related technologies is non-uniform, closely related to its transmission length. As the planar contact holes continue to decrease in size, the current crowding effect becomes increasingly prominent. This non-uniform current distribution and current crowding effect lead to even more inaccurate contact resistance extraction. Furthermore, the extremely small contact holes and spacing in nano-contact resistance test structures place extremely stringent requirements on the accuracy of the error.
[0035] An embodiment of the present disclosure provides a method for preparing a nanoscale contact resistance test structure, comprising: doping and activating the surface silicon of a substrate to form a channel; etching the channel to form a contact hole, with the sidewall of the contact hole forming a vertical contact surface with the channel; depositing metal on the surface having the contact hole to form a metal layer; chemically and mechanically polishing the metal layer to remove the metal layer outside the contact hole to obtain a polished metal layer; and etching the polished metal layer for test pads to obtain a nanoscale contact resistance test structure. The present disclosure also provides a nanoscale contact resistance test structure.
[0036] Figure 1 The flowchart of the method for preparing the nanoscale contact resistance test structure according to an embodiment of the present disclosure is schematically shown.
[0037] like Figure 1 As shown, the method for preparing the nano-scale contact resistance test structure of this embodiment includes operations S110 to S150.
[0038] In operation S110 , a surface silicon layer of the substrate is doped and activated to form a channel.
[0039] According to an embodiment of the present disclosure, the surface silicon of the substrate is doped and activated. The purpose of doping is to introduce impurity atoms into the semiconductor substrate, thereby changing its electrical properties, such as forming n-type or p-type regions, optimizing resistivity, etc.
[0040] According to the embodiments of the present disclosure, dopants are introduced into the substrate and activated to provide a background doping environment for the formation of a channel. Further, a voltage is applied to induce a conductive channel on the substrate surface.
[0041] In operation S120 , the trench is etched to form a contact hole, and a vertical contact surface is formed between the sidewall of the contact hole and the trench.
[0042] According to the embodiments of the present disclosure, the depth of doping is controlled and thus the size of the vertical contact surface is controlled, thereby improving the accuracy of nanoscale contact resistance testing.
[0043] According to the embodiments of the present disclosure, the contact holes collect current through the vertical contact surface, achieving uniform current distribution at the nanometer scale, fundamentally avoiding the current crowding effect, and accurately characterizing the resistance characteristics of the real silicide contact.
[0044] In operation S130 , metal deposition is performed on the surface where the contact hole is formed to generate a metal layer.
[0045] According to an embodiment of the present disclosure, a metal layer is used to transmit current in a nanoscale contact resistance test structure, and the contact resistivity is calculated by measuring the resistance between metals with different spacings.
[0046] According to the embodiments of the present disclosure, the conductivity of the metal layer ensures that current can stably flow through the nanoscale contact resistance test structure, thereby achieving accurate resistance measurement.
[0047] In operation S140 , chemical mechanical polishing is performed on the metal layer to remove the metal layer outside the contact hole to obtain a polished metal layer.
[0048] According to the embodiments of the present disclosure, a metal layer is flattened by chemical mechanical polishing to solve the influence of deviation, wherein the deviation is caused by the higher requirements for overlay of contact holes and spacing at nanometer scale.
[0049] In operation S150 , the polished metal layer is etched to form a test pad to obtain a nanoscale contact resistance test structure.
[0050] According to an embodiment of the present disclosure, test pad etching (PAD etching) is a process of forming a pad (Pad) for external circuit connection on a polished metal layer through photolithography and etching processes, wherein the pad is a key structure for extracting electrical characteristics such as current and voltage of a nanoscale contact resistance test structure.
[0051] According to an embodiment of the present disclosure, during the test pad etching process, the pattern of the pad is transferred to the photoresist using photolithography technology, and then the metal portion not covered by the photoresist is removed by etching.
[0052] Figure 2A A schematic diagram of a current flow of a nanoscale contact resistance test structure according to an embodiment of the present disclosure is shown; Figure 2B A cross-sectional view of a nanoscale contact resistance test structure according to an embodiment of the present disclosure is schematically shown.
[0053] According to the embodiments of the present disclosure, Figure 2A As shown, the current is transmitted in the channel and collected by the metal layer deposited on the surface of the contact hole. Figure 2A The schematic diagram of the metal layer and channel of the nanoscale contact resistance test structure in the cross section (a) is shown in FIG. Figure 2B According to an embodiment of the present disclosure, taking the nanoscale contact resistance test structure based on the Transmission Line Model (TLM) as an example, if the current is uniform, the contact resistivity is expressed as 𝝆=𝑹 c ×𝑨 eff , where the current is collected vertically and uniformly through the sidewall of the contact hole, and the contact area is determined by the contact width w and the channel thickness t. Specifically, the contact area =w*t, that is ), is the contact resistance.
[0054] According to an embodiment of the present disclosure, the above-mentioned method for preparing the nanoscale contact resistance test structure is not only applicable to preparing the nanoscale contact resistance test structure of TLM, but also applicable to the nanoscale contact resistance test structure of rectangular transmission line model (RTLM) and circular transmission line model (CTLM).
[0055] According to the embodiments of the present disclosure, the surface silicon of the substrate is doped and activated to form a channel; the channel is etched to form a contact hole, and a vertical contact surface is formed between the sidewall of the contact hole and the channel; metal is deposited on the surface formed with the contact hole to generate a metal layer; the metal layer is chemically and mechanically polished to remove the metal layer outside the contact hole to obtain a polished metal layer; the polished metal layer is etched with a test pad to obtain a nanoscale contact resistance test structure. Since a vertical contact surface is formed between the sidewall of the contact hole and the channel, the problem of abnormal carrier aggregation at the contact edge or interface defect in the related art, resulting in non-uniform current density distribution, is avoided, and uniform current distribution is achieved; since the metal layer is chemically and mechanically polished, the preparation and testing of the nanoscale contact resistance test structure is achieved, reducing the impact of process fluctuations.
[0056] According to an embodiment of the present disclosure, the type of the substrate includes SOI, and the surface silicon layer includes a silicon cap layer.
[0057] According to the embodiments of the present disclosure, for SOI substrates, it is suitable for high-performance, high-frequency, high-power and high-voltage applications, can significantly reduce parasitic effects, and improve device performance and reliability.
[0058] Figure 3 A schematic diagram of a substrate according to an embodiment of the present disclosure is schematically shown.
[0059] like Figure 3 As shown, the substrate includes silicon and silicon oxide.
[0060] According to an embodiment of the present disclosure, a substrate is doped and activated to form a channel, which includes: uniformly doping a surface silicon layer of the substrate with a dopant, wherein the dopant includes impurity atoms.
[0061] According to the embodiments of the present disclosure, the substrate is doped and activated by accelerating the impurity atoms of the dopant to high energy and directly injecting them into the surface of the substrate, or by diffusing the impurity atoms of the dopant to the surface of the substrate and allowing them to enter the interior of the substrate through thermal diffusion. Those skilled in the art can select the doping method according to actual needs.
[0062] Figure 4 A schematic diagram of a channel according to an embodiment of the present disclosure is schematically shown.
[0063] like Figure 4 As shown, after the substrate is doped and activated, a channel layer is formed on the silicon oxide.
[0064] According to an embodiment of the present disclosure, etching the channel to form a contact hole includes: depositing a semiconductor dielectric on the channel to generate a dielectric layer; and etching the channel and the dielectric layer to form the contact hole.
[0065] According to an embodiment of the present disclosure, the semiconductor medium includes at least one of SiO 2 or Si 3 N 4 .
[0066] According to an embodiment of the present disclosure, during the etching process, the semiconductor medium can be used as an etching mask to define the etching area and prevent a portion of the channel surface from being physically or chemically damaged.
[0067] According to the embodiments of the present disclosure, the dielectric layer can be selected according to actual needs and is not limited here.
[0068] Figure 5 A schematic diagram of a contact hole according to an embodiment of the present disclosure is schematically shown.
[0069] like Figure 5 As shown, the channel and the dielectric layer are etched to form a contact hole.
[0070] According to an embodiment of the present disclosure, metal deposition is performed on a surface where a contact hole is formed to generate a metal layer, including: performing metal deposition treatment on the surface where the contact hole is formed to generate a metal film at least on the bottom and sidewalls of the contact hole; performing silicidation annealing treatment on the metal film to generate a silicide layer; and performing metal deposition treatment on the surface of the silicide layer to generate a metal layer.
[0071] According to an embodiment of the present disclosure, the metal layer includes at least one of Ti, Ni, Mo, or Co.
[0072] According to the embodiments of the present disclosure, the annealing time and annealing temperature of the silicidation annealing are not limited here. The annealing time and temperature are related to the type and thickness of the metal. Those skilled in the art can select appropriate annealing temperature and time according to different metal conditions.
[0073] According to an embodiment of the present disclosure, a silicide layer is first generated on the surface where contact holes are formed, thereby reducing the resistance loss during current transmission, thereby improving the performance of the nanoscale contact resistance test structure. At the same time, the resistivity of the silicide layer obtained based on the silicidation annealing of the metal layer is usually lower than that of pure metal or semiconductor, which allows current to pass more smoothly.
[0074] Figure 6 A schematic diagram schematically illustrates a metal layer grown on the surface of a contact hole according to an embodiment of the present disclosure; Figure 7 The figure schematically shows a schematic diagram of silicide grown on the surface of a contact hole according to an embodiment of the present disclosure.
[0075] like Figure 6 As shown, metal deposition is performed on the surface where the contact hole is formed, and then a silicidation annealing process is performed to obtain the following Figure 7 The silicide layer shown.
[0076] Figure 8Schematic diagram showing a metal layer grown on a silicide surface according to an embodiment of the present disclosure; Figure 9 A schematic diagram of a polished metal layer according to an embodiment of the present disclosure is schematically shown.
[0077] like Figure 8 As shown, metal deposition is performed on the surface where the contact holes are formed to generate a metal layer, and then as shown in FIG. Figure 9 As shown, the metal layer is subjected to chemical mechanical polishing to obtain a polished metal layer.
[0078] According to an embodiment of the present disclosure, the test pad is etched on the polished metal layer to obtain a nanoscale contact resistance test structure, including: performing metal deposition processing on the polished metal layer to generate a target metal layer; and etching the test pad on the target metal layer to obtain a nanoscale contact resistance test structure.
[0079] According to an embodiment of the present disclosure, a metal deposition process is performed on the polished metal layer, and a target metal layer is first generated on the polished metal layer to facilitate subsequent test pad etching.
[0080] According to an embodiment of the present disclosure, a test pad is etched on a target metal layer to form a pad for external circuit connection on the target metal layer, thereby completing the preparation of a nanoscale contact resistance test structure.
[0081] According to an embodiment of the present disclosure, metal deposition is performed on the polished metal layer to generate a target metal layer, including: depositing a semiconductor medium on the polished metal layer and etching it to form a groove on the metal layer; and performing metal deposition processing on the surface of the groove and the surface of the semiconductor medium to generate the target metal layer.
[0082] According to an embodiment of the present disclosure, grooves are formed on the surface of the polished metal layer to optimize the contact resistance, thereby improving the performance and integration of the nanoscale contact resistance test structure.
[0083] According to an embodiment of the present disclosure, metal deposition is further performed on the surface of the groove and the surface of the semiconductor medium to facilitate subsequent etching of the test pad.
[0084] Figure 10 Schematically shows a schematic diagram of a groove according to an embodiment of the present disclosure; Figure 11 Schematically shows a schematic diagram of a target metal layer according to an embodiment of the present disclosure; Figure 12 A schematic diagram of a nanoscale contact resistance test structure according to an embodiment of the present disclosure is schematically shown.
[0085] The semiconductor dielectric is deposited on the polished metal layer to obtain Figure 10The semiconductor medium shown is further subjected to metal deposition processing to obtain Figure 11 The target metal layer shown in FIG. 1 is then subjected to PAD etching to form a pad for connecting an external circuit. Figure 12 Nanoscale contact resistance test structure shown.
[0086] A second aspect of the present disclosure provides a nanoscale contact resistance test structure, which is prepared by the above method.
[0087] Contact resistance test structure such as Figure 12 As shown, it includes silicon, silicon oxide, channel, silicide, dielectric layer and metal layer.
[0088] According to the embodiments of the present disclosure, the surface silicon of the substrate is doped and activated to form a channel; the channel is etched to form a contact hole, and a vertical contact surface is formed between the sidewall of the contact hole and the channel; metal is deposited on the surface formed with the contact hole to generate a metal layer; the metal layer is chemically and mechanically polished to remove the metal layer outside the contact hole to obtain a polished metal layer; the polished metal layer is etched with a test pad to obtain a nanoscale contact resistance test structure. Since a vertical contact surface is formed between the sidewall of the contact hole and the channel, the problem of abnormal carrier aggregation at the contact edge or interface defect in the related art, resulting in non-uniform current density distribution, is avoided, and uniform current distribution is achieved; since the metal layer is chemically and mechanically polished, the preparation and testing of the nanoscale contact resistance test structure is achieved, reducing the impact of process fluctuations.
[0089] Those skilled in the art will appreciate that the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in the present disclosure. In particular, the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways without departing from the spirit and teachings of the present disclosure. All such combinations and / or couplings fall within the scope of the present disclosure.
[0090] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.
Claims
1. A method for preparing a nanoscale contact resistance test structure, characterized in that: The method comprises: Doping and activating the surface silicon of the substrate to form a channel; Etching the trench to form a contact hole, wherein a vertical contact surface is formed between a sidewall of the contact hole and the trench; performing metal deposition on the surface where the contact hole is formed to generate a metal layer; performing chemical mechanical polishing on the metal layer to remove the metal layer outside the contact hole to obtain a polished metal layer; The polished metal layer is etched to form a test pad to obtain a nanoscale contact resistance test structure.
2. The method according to claim 1, characterized in that The step of depositing metal on the surface where the contact hole is formed to generate a metal layer comprises: performing a metal deposition process on the surface where the contact hole is formed, so as to form a metal film at least on the bottom and sidewalls of the contact hole; performing a silicidation annealing process on the metal film to form a silicide layer; A metal deposition process is performed on the surface of the silicide layer to generate the metal layer.
3. The method according to claim 1, characterized in that The metal layer includes at least one of Ti, Ni, Mo or Co.
4. The method according to claim 1, wherein The etching of the channel to form a contact hole comprises: Depositing a semiconductor dielectric on the channel to form a dielectric layer; The channel and the dielectric layer are etched to form the contact hole.
5. The method according to claim 4, characterized in that The semiconductor medium includes at least one of SiO2 or Si3N4.
6. The method according to claim 4, characterized in that The step of etching the test pad on the polished metal layer to obtain a contact resistance test structure includes: performing a metal deposition process on the polished metal layer to generate a target metal layer; The target metal layer is subjected to test pad etching to obtain the contact resistance test structure.
7. The method according to claim 6, characterized in that Depositing metal on the polished metal layer to generate a target metal layer comprises: Depositing the semiconductor medium on the polished metal layer and etching it to form a groove on the metal layer; A metal deposition process is performed on the surface of the groove and the surface of the semiconductor medium to generate the target metal layer.
8. The method according to claim 1, characterized in that The type of the substrate includes SOI, and the surface silicon layer includes a silicon cap layer.
9. The method according to claim 1, characterized in that The step of performing doping activation on the substrate to form a channel includes: The surface silicon of the substrate is uniformly doped with a dopant, wherein the dopant includes impurity atoms.
10. A nanoscale contact resistance test structure, characterized in that: The contact resistance test structure is prepared by the method according to any one of claims 1 to 9.