ESD electrostatic surge protection structure and method

Abstract

The present application relates to the special protection technology of electronic components, and proposes an ESD static surge protection structure and method, which comprises a plurality of I / O pins, a detection circuit, a transient voltage suppressor and a discharge channel. The I / O pin is connected with the detection circuit and is used for input signal. The detection circuit is used for analyzing ESD static event or surge event, and inputs the transient voltage suppressor and the discharge channel. The transient voltage suppressor comprises a side TSV path and a center TSV path. The detection circuit comprises a voltage sensor and a current sensor. The voltage sensor is connected with a first comparator and an amplitude detector respectively. The first comparator is used for monitoring the voltage slope of the input signal of the I / O pin. The current sensor is connected with a second comparator. The second comparator is used for monitoring the pulse energy and pulse duration of the input signal of the plurality of I / O pins. Through the multi-parameter dynamic analysis of the voltage slope, pulse width, voltage peak value and pulse energy, accurate event recognition and classification protection are realized.

Description

Technical Field

[0001] This invention relates to dedicated protection technologies for electronic components, and more particularly to an ESD surge protection structure and method. Background Technology

[0002] The continuous shrinking of integrated circuit (IC) process nodes and the increasing miniaturization of device dimensions have significantly increased the sensitivity of chips to transient voltage events such as electrostatic discharge (ESD) and surges. In practical applications, these high-energy, short-duration transient interferences can cause permanent damage to the internal circuitry of the chip, affecting system stability and reliability. Therefore, incorporating efficient electrostatic surge protection structures into IC design has become an indispensable and critical step.

[0003] Traditional ESD protection schemes typically employ diodes, MOS transistors, or silicon controlled rectifiers (SCRs) as discharge paths. Their primary goal is to quickly conduct upon the occurrence of an ESD event, discharging the transient current to ground and thus protecting downstream circuitry. However, these structures often have limited response speeds and lack differentiated handling capabilities for different types of transient events (such as ESD or surge), making them prone to false triggering or insufficient response. Furthermore, traditional ESD protection devices may introduce significant parasitic capacitances in high-frequency signal paths, affecting signal integrity, especially noticeable in high-speed I / O interfaces.

[0004] On the other hand, surge events are characterized by long duration and high energy, and are commonly seen during lightning strikes or power switching. Traditional ESD protection structures are unable to withstand their continuous energy impact, leading to protection failure or even device burnout.

[0005] Therefore, there is a lack of existing protection structures that can identify and dynamically respond to ESD and surge events, especially in high-speed signal paths, to achieve low parasitic capacitance, high response speed, and high energy carrying capacity. Summary of the Invention

[0006] In summary, this invention proposes an ESD surge protection structure and method, aiming to solve the problem of identifying and dynamically responding to ESD and surge events, and to achieve rapid response and precise protection against different types of transient events.

[0007] The technical solution of this invention is implemented as follows:

[0008] An ESD surge protection structure includes multiple I / O pins, a detection circuit, a transient voltage suppressor, and a discharge channel, characterized in that...

[0009] The I / O pins are connected to the detection circuit and used to input signals;

[0010] The detection circuit is used to analyze ESD (electrostatic discharge) events or surge events and inputs them to a transient voltage suppressor and a discharge channel. The transient voltage suppressor includes a side path TSV and a center path TSV.

[0011] in,

[0012] The detection circuit includes a voltage sensor and a current sensor. The voltage sensor is connected to a first comparator and an amplitude detector, respectively. The first comparator is used to monitor the voltage slope of the signal input from the I / O pin.

[0013] The current sensor is connected to a second comparator, which monitors the pulse energy and pulse duration of signals input from multiple I / O pins.

[0014] The voltage slope, pulse energy, and pulse duration are input into the event analysis unit. If the voltage slope exceeds the set threshold, it is determined to be an ESD event, and the side-circuit TSV path is activated.

[0015] If the pulse duration exceeds the set threshold, it is determined to be a surge event, and the central TSV path is activated.

[0016] It should be noted that,

[0017] If the voltage slope is ≤1V / ns, it is directly determined to be a harmless noise event;

[0018] If the voltage slope is >1V / ns and the pulse duration is less than or equal to 500ns, it is directly determined as an ESD electrostatic event, and the side-circuit TSV path is turned on.

[0019] If the voltage slope is >1V / ns and the pulse duration is >500ns, the pulse energy assessment stage is performed. If the pulse energy exceeds 5mJ, it is determined to be a surge event, and the central TSV path is activated. If the pulse energy is less than 5mJ, it is determined to be a transient interference.

[0020] It should be noted that the diameter of the side path TSV is 20μm×200μm, the aspect ratio is 10:1, and it is composed of polysilicon filling, TiN barrier layer and SiO2 insulating layer.

[0021] It should be noted that the central TSV path has a diameter of 80μm×400μm and a depth-to-width ratio of 5:1, and is composed of copper filler, TaN barrier layer and air gap insulation layer.

[0022] It should be noted that the transient voltage suppressor also includes a TVS diode, which is connected to the side TSV path and the center TSV path respectively. The TVS diode includes a P+ anode, an N+ cathode and an epitaxial layer.

[0023] It should be noted that the TVS diode includes a highly doped P++ substrate, on which a first epitaxial layer P++ isolation region is formed, and an N+ region is formed by a buried layer on the P++ isolation region, and then an N- type epitaxial layer is formed by a second epitaxial process.

[0024] It should be noted that the P++ isolation region is used as the P-type region of the TVS diode and is connected to the highly doped P++ substrate, forming an N+ region on the surface of the P-type region, thus constituting an avalanche diode with low breakdown voltage.

[0025] It should be noted that highly doped P+ and N+ regions are formed on the N-type epitaxial layer, wherein the P+ / N- / N++ structure forms a PIN-type low-capacitance diode D2; and the N+ / N- / P++ structure forms a NIP-type low-capacitance diode D1.

[0026] It should be noted that the detection circuit also includes a temperature sensor and a thermal management unit. The temperature sensor is connected to the event analysis unit via the thermal management unit and is used for overheat protection and temperature monitoring.

[0027] An ESD surge protection method, comprising the ESD surge protection structure as described in claim 1, characterized in that it further comprises the following steps:

[0028] Step 1: Detect the voltage and current in the circuit respectively, and perform transient high voltage protection and transient overcurrent protection;

[0029] Step 2: Capture the peak voltage of the input signal in real time and calculate the voltage slope of the input signal from multiple I / O pins;

[0030] Step 3: Monitor the pulse width of the input signals from multiple I / O pins 11 and calculate the pulse energy;

[0031] Step 4: The voltage slope and pulse energy input event analysis unit analyzes the specific event, and the path control unit controls the corresponding path to be turned on;

[0032] Step 5: The temperature sensor is connected to the event analysis unit via the thermal management unit to monitor the temperature for overheat protection and to implement predictive protection when the temperature exceeds the threshold.

[0033] The ESD surge protection structure and method of this invention have the following advantages:

[0034] 1. Accurate event identification and classification protection: Through multi-parameter dynamic analysis of voltage slope (dV / dt), pulse width, voltage peak value and pulse energy, nanosecond-level event determination is achieved.

[0035] 2. Dual-path collaborative discharge mechanism: The side TSV path adopts a polycrystalline silicon filled + TiN barrier layer structure, which has high resistance but extremely fast response to cope with ESD electrostatic events; the central TSV path adopts copper filled + Ta barrier layer + air gap insulation, which has low resistance and can carry continuous large current to cope with surge / lightning impact. The path control unit conducts the optimal path in real time according to the event type, taking into account both speed and current carrying capacity.

[0036] 3. TVS diodes adopt a double epitaxial layer structure, forming an avalanche diode + low capacitance diodes D1 / D2 through doping control. The breakdown voltage can be customized, saving area and reducing manufacturing costs. Attached Figure Description

[0037] Figure 1 This is a structural block diagram of the ESD surge protection structure of the present invention;

[0038] Figure 2 This is a structural block diagram of the ESD surge protection structure of the present invention;

[0039] Figure 3 This is a block diagram of the detection circuit of the present invention;

[0040] Figure 4 This is a logic block diagram of the detection circuit of the present invention;

[0041] Figure 5 This is a structural block diagram of the transient voltage suppressor of the present invention;

[0042] Figure 6 This is a structural block diagram of the transient voltage suppressor of the present invention;

[0043] Figure 7 This is a schematic diagram of the structure of the TVS diode of the present invention;

[0044] Figure 8 This is a flowchart of the ESD surge protection method of the present invention;

[0045] The reference numerals in the attached figures are as follows: ESD surge protection structure 100, I / O pin 11, detection circuit 12, voltage sensor 121, first comparator 123, amplitude detector 124, current sensor 122, second comparator 125, event analysis unit 126, path control unit 127, temperature sensor 128, thermal management unit 129, transient voltage suppressor 13, side TSV path 131, center TSV path 132, TVS diode 133, and discharge channel 14. Implementation

[0046] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0047] Example 1

[0048] refer to Figures 1 to 2 As shown, this invention proposes an ESD surge protection structure 100 for protecting the fine structures in integrated circuits (ICs). Under normal operating conditions, it does not interfere with circuit operation; in the event of an electrostatic discharge or surge event, it quickly conducts to discharge the transient large current to ground; after the discharge ends, it automatically returns to a high-resistance state, ensuring the system continues to operate normally.

[0049] In one embodiment, the ESD surge protection structure 100 includes multiple I / O pins 11, a detection circuit 12, a transient voltage suppressor 13, and a discharge channel 14. The multiple I / O pins 11 are connected to the detection circuit 12 for input signals. The detection circuit 12 analyzes ESD electrostatic events or surge events and inputs the signals to the transient voltage suppressor 13 and the discharge channel 14 for suppression and protection.

[0050] In one embodiment, reference Figure 3 As shown, the detection circuit 12 includes a voltage sensor 121 and a current sensor 122. The voltage sensor 121 is connected to a first comparator 123 and an amplitude detector 124. The first comparator 123 monitors the voltage slope of the input signals from multiple I / O pins 11, denoted as dV / dt. The amplitude detector 124 captures the voltage peak value of the input signals in real time. This accurately identifies the intensity of transient events within nanoseconds, providing key parameters for event classification. The current sensor 122 is connected to a second comparator 125, which monitors the pulse energy and pulse duration of the input signals from multiple I / O pins.

[0051] The first comparator 123, amplitude detector 124, and second comparator 125 input the acquired parameters to the event analysis unit 126 and the path control unit 127. The transient voltage suppressor 13 includes a side TSV path 131 and a center TSV path 132. If the voltage slope exceeds a set threshold, it is determined to be an ESD event, and the side TSV path is activated; if the pulse duration exceeds a set threshold, it is determined to be a surge event, and the center TSV path is activated.

[0052] It should be noted that the reference Figure 4 As shown, the specific working principle of the event analysis unit 126 is as follows:

[0053] First, the voltage slope in the circuit is monitored in real time. If the voltage slope is ≤1V / ns, it is directly identified as a relatively harmless noise event. If the voltage slope is >1V / ns, the system further analyzes its pulse width. If the pulse duration is less than or equal to 500ns, it is directly identified as an ESD event, and the side TSV path is activated. If the voltage slope is >1V / ns and the pulse width is >500ns, which is a slower event, a pulse energy assessment phase is performed. These events may manifest as surges caused by lightning strikes or power switching. If the pulse energy exceeds 5mJ, it is identified as a surge event, and the center TSV path is activated. If the pulse energy is less than 5mJ, it is identified as transient interference, and "no operation" is selected to avoid frequent actions affecting stability.

[0054] Event analysis unit 126 achieves rapid and accurate identification and differentiated protection against different types of transient threats by precisely matching characteristic parameters such as voltage slope, pulse width, and pulse energy at each level. By dynamically selecting the optimal discharge path, it can provide both extremely fast response to ESD and effective handling of continuous high-energy surge impacts, while minimizing interference with normal operation, significantly improving reliability and robustness.

[0055] In one embodiment, refer to Figures 5 to 6 As shown, the transient voltage suppressor 13 also includes a TVS diode 133, which is connected to the discharge channel 14 via a side TSV path 131 and a central TSV path 132. The TVS diode 133 includes a P+ anode, an N+ cathode, and an epitaxial layer. When external static electricity or a surge enters the signal terminal, the TVS diode, as the first-stage response unit, is the first to activate. The epitaxial layer between its P+ anode and N+ cathode undergoes avalanche breakdown or Zener breakdown under high voltage, instantly changing from a high-resistance state to a low-resistance conducting state, and then is guided into the discharge channel 14 via the side TSV path 131 or the central TSV path 132.

[0056] Specifically, the path control unit 127 is used to control whether the side TSV path 131 and the central TSV path 132 are conductive. If the event analysis unit 126 determines it to be an ESD electrostatic event, the path control unit 127 controls the side TSV path 131 to be conductive and the central TSV path 132 to be closed; if the event analysis unit 126 determines it to be a surge event, the path control unit 127 controls the central TSV path 132 to be conductive and the side TSV path 131 to be closed. The side TSV path 131 has a diameter of 20μm × 200μm and an aspect ratio of 10:1. It is filled with polysilicon, a TiN barrier layer, and a SiO2 insulating layer, exhibiting high resistance but fast response. The central TSV path 132 has a diameter of 80μm × 400μm and an aspect ratio of 5:1. It is filled with copper, a TaN barrier layer, and an air gap insulating layer, exhibiting low resistance and the ability to carry large currents.

[0057] In one embodiment, refer to Figure 7 As shown, improvements were made to the fabrication process of the TVS diode 133. First, a first epitaxial layer (P++ region) was grown on a highly doped P++ substrate. Then, a buried layer process was performed to form the N+ region. Next, a second epitaxial process was performed to grow an N-type epitaxial layer. The second epitaxial layer differed from the first; it was a high-resistivity N-type epitaxial layer.

[0058] Further adjustments were made to the TVS diode and the low-capacitance diodes D1 and D2. The P++ isolation region can be used as the P-type region of the TVS diode and is connected to the highly doped P++ substrate, forming an N+ region on the surface of the P-type region, thus constituting a low-breakdown-voltage avalanche diode. By adjusting the doping concentration, the reverse breakdown voltage of the TVS diode can be controlled.

[0059] Highly doped P+ and N+ regions are formed on the N-type epitaxial layer: the P+ / N- / N++ structure forms a PIN-type low-capacitance diode D2; while the N+ / N- / P++ structure forms a NIP-type low-capacitance diode D1.

[0060] This involves growing an N-type epitaxial layer on top of a P-type epitaxial layer, adjusting the doping type through methods such as ion implantation, and simultaneously forming a TVS protection device and low-capacitance diodes D1 and D2, thereby achieving a low-cost, low-parasitic-capacitance, and high-performance solution.

[0061] Example 2

[0062] Based on the above embodiments, referring to Figures 1 to 8 As shown, this embodiment also proposes an ESD surge protection method, including:

[0063] Step 1: Detect the voltage and current in the circuit respectively, and perform transient high voltage protection and transient overcurrent protection;

[0064] Step 2: Capture the peak voltage of the input signal in real time and calculate the voltage slope of the input signals from multiple I / O pins; detecting the voltage slope is the core parameter for identifying ESD events. A typical characteristic of ESD events is an extremely short voltage rise time, resulting in a large voltage slope.

[0065] Furthermore, the voltage slope is expressed as dV / dt, and the calculation formula is as follows:

[0066]

[0067] in, Indicates time Voltage value at time, Indicates time Voltage value at time, It represents the amount of voltage change. , Indicates the change over time. .

[0068] Discrete calculations are performed, and the difference approximation is used as follows:

[0069]

[0070] in, This represents the voltage at the nth sampling point. Indicates the sampling period. Real-time, stable, and low-noise differential calculations can be performed on a nanosecond timescale and applied to high-speed ESD event discrimination, enabling extremely rapid capture of the steep leading edge of ESD events.

[0071] Step 3: Monitor the pulse duration of the input signals from multiple I / O pins 11 and calculate the pulse energy. The formula for calculating the pulse energy is as follows:

[0072]

[0073] in, Indicates pulse energy. Indicates instantaneous power. Indicates instantaneous voltage. This represents instantaneous current.

[0074] Its effect lies in quantifying the destructive potential of transient events, such as lightning strikes and power switching. While the rise time of surge events may be slower than that of ESD events, their long duration and accumulated energy are enormous. Simply relying on pulse width may not be sufficient to distinguish between high-energy dangerous surges and low-energy harmless transients. Combining the pulse duration monitored in Step 3 with the generated pulse energy provides accurate parameters for determining surge events requiring high current discharge capacity. For example, pulse energy less than 5mJ can avoid false triggering of low-energy events and improve system stability.

[0075] Step 4: The voltage slope and pulse energy input event analysis unit 126 analyzes the specific event, and the path control unit 127 controls the corresponding path to conduct, realizing hierarchical judgment and avoiding misjudgment of a single parameter.

[0076] If the voltage slope exceeds a set threshold and the pulse duration does not exceed a set threshold, it is determined to be an ESD electrostatic event, and the side TSV path is activated; if the voltage slope exceeds a set threshold and the pulse duration exceeds a set threshold, it is determined to be a surge event, and the center TSV path is activated.

[0077] In this embodiment, the corresponding path is controlled based on the event analysis results.

[0078] In response to ESD events, the fast-response TSV path on the side discharges current in a very short time, protecting sensitive circuits from nanosecond-level high-voltage surges. However, while the side TSV path has high resistance, its current-carrying capacity is limited.

[0079] In response to surge events, the central TSV path, with its low on-resistance and high current-carrying capacity, can withstand long-term high-current discharge, preventing the device from burning out due to overheating.

[0080] For harmless events, such as low-energy events, the "no operation" option is selected to minimize the impact on normal circuit operation and improve system stability and robustness.

[0081] Preferably, it also includes, Step 5: Refer to Figure 3 As shown, the temperature sensor 128 is connected to the event analysis unit 126 via the thermal management unit 129, and is used to monitor the temperature for overheat protection and implement predictive protection when the temperature exceeds the threshold.

[0082] A temperature prediction model is established, and the calculation formula is as follows:

[0083]

[0084] in, Indicates real-time junction temperature. Indicates ambient temperature. Indicates power loss. Indicates thermal resistance. When <125℃, no response; when <140℃, dynamic derating is implemented; when 140℃ < <150℃, forced derating; when >150℃, shut off immediately; when If the temperature exceeds 175℃, a fuse will be used for isolation.

[0085] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An ESD surge protection structure, comprising multiple I / O pins, a detection circuit, a transient voltage suppressor, and a discharge channel, characterized in that, The I / O pins are connected to the detection circuit and used to input signals; The detection circuit is used to analyze ESD (electrostatic discharge) events or surge events and inputs them to a transient voltage suppressor and a discharge channel. The transient voltage suppressor includes a side path TSV and a center path TSV. in, The detection circuit includes a voltage sensor and a current sensor. The voltage sensor is connected to a first comparator and an amplitude detector, respectively. The first comparator is used to monitor the voltage slope of the signal input from the I / O pin. The current sensor is connected to a second comparator, which monitors the pulse energy and pulse duration of signals input from multiple I / O pins. The voltage slope, pulse energy, and pulse duration are input into the event analysis unit. If the voltage slope exceeds the set threshold, it is determined to be an ESD event, and the side-circuit TSV path is activated. If the pulse duration exceeds a set threshold, it is determined to be a surge event, and the central TSV path is activated. If the pulse duration is less than or equal to 500 ns, it is directly determined as an ESD electrostatic event, and the side TSV path is turned on; if the voltage slope is >1V / ns and the pulse width is >500ns, which is a slower event, the pulse energy assessment stage is carried out; if the pulse energy exceeds 5mJ, it is determined as a surge event, and the center TSV path is turned on; if the pulse energy is less than 5mJ, it is determined as transient interference.

2. The ESD surge protection structure according to claim 1, characterized in that, If the voltage slope is ≤1V / ns, it is directly determined to be a harmless noise event; If the voltage slope is >1V / ns and the pulse duration is less than or equal to 500ns, it is directly determined as an ESD electrostatic event, and the side-circuit TSV path is turned on. If the voltage slope is >1V / ns and the pulse duration is >500ns, the pulse energy assessment stage is performed. If the pulse energy exceeds 5mJ, it is determined to be a surge event, and the central TSV path is activated. If the pulse energy is less than 5mJ, it is determined to be a transient interference.

3. The ESD surge protection structure according to claim 1, characterized in that, The side path TSV has a diameter of 20μm×200μm and an aspect ratio of 10:

1. It is composed of polysilicon filling, a TiN barrier layer and a SiO2 insulating layer.

4. The ESD surge protection structure according to claim 1, characterized in that, The central TSV path has a diameter of 80μm×400μm and a depth-to-width ratio of 5:

1. It is composed of copper filler, TaN barrier layer and air gap insulation layer.

5. The ESD surge protection structure according to claim 1, characterized in that, The transient voltage suppressor also includes a TVS diode, which is connected to the side TSV path and the center TSV path respectively. The TVS diode includes a P+ anode, an N+ cathode and an epitaxial layer.

6. The ESD surge protection structure according to claim 5, characterized in that, The TVS diode includes a highly doped P++ substrate, on which a first epitaxial layer P++ isolation region is formed, and an N+ region is formed by a buried layer on the P++ isolation region, and an N- type epitaxial layer is formed by a second epitaxial process.

7. The ESD surge protection structure according to claim 6, characterized in that, The P++ isolation region serves as the P-type region of the TVS diode and is connected to the highly doped P++ substrate. An N+ region is formed on the surface of the P-type region, constituting an avalanche diode with low breakdown voltage.

8. The ESD surge protection structure according to claim 7, characterized in that, Highly doped P+ and N+ regions are formed on the N-type epitaxial layer, wherein the P+ / N- / N++ structure forms a PIN-type low-capacitance diode D2; and the N+ / N- / P++ structure forms a NIP-type low-capacitance diode D1.

9. The ESD surge protection structure according to claim 1, characterized in that, The detection circuit also includes a temperature sensor and a thermal management unit, wherein the temperature sensor is connected to the event analysis unit via the thermal management unit and is used for overheat protection monitoring temperature.

10. An ESD surge protection method, comprising the ESD surge protection structure as described in claim 1, characterized in that, It also includes the following steps: Step 1: Detect the voltage and current in the circuit respectively, and perform transient high voltage protection and transient overcurrent protection; Step 2: Capture the peak voltage of the input signal in real time and calculate the voltage slope of the input signal from multiple I / O pins; Step 3: Monitor the pulse width of the input signals from multiple I / O pins and calculate the pulse energy; Step 4: Input the voltage slope, pulse energy, and pulse duration into the event analysis unit to analyze the specific event, and the path control unit controls the corresponding path to be turned on; Step 5: The temperature sensor is connected to the event analysis unit via the thermal management unit to monitor the temperature for overheat protection and to implement predictive protection when the temperature exceeds the threshold.

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